INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF40245B buffers Octal bus transceiver with 3-state outputs Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF40245B buffers Octal bus transceiver with 3-state outputs DESCRIPTION PINNING The HEF40245B is an octal bus transmitter/receiver designed for 8-line asynchronous, 2-way data communication between data buses. It features output stages with high current output capability suitable for driving highly capacitive loads. The direction input (DR) controls transmission of data from bus A to bus B, or bus B to bus A, depending on its logic level. The 3-state outputs are controlled by the enable input EO. A HIGH on EO causes the outputs to assume a high impedance OFF-state. The device also features hysteresis on all inputs to improve noise immunity. A0 to A7 data input/output B0 to B7 data input/output DR direction input EO output enable input (active LOW) HEF40245BP(N): 20-lead DIL; plastic (SOT146-1) HEF40245BD(F): 20-lead DIL; ceramic (cerdip) (SOT152) HEF40245BT(D): 20-lead SO; plastic (SOT163-1) ( ): Package Designator North America Schmitt-trigger action in the inputs makes the circuit highly tolerant to slower input rise and fall times. The HEF40245B is pin and functionally compatible with the TTL ‘245’ device. Fig.2 Logic diagram; for functional diagram see Fig.3. FAMILY DATA, IDD LIMITS category buffers See Family Specifications. Fig.1 Pinning diagram. January 1995 2 Philips Semiconductors Product specification HEF40245B buffers Octal bus transceiver with 3-state outputs FUNCTION TABLE INPUTS INPUTS/OUTPUTS EO DR An Bn L L A=B input L H input B=A H X Z Z Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial Z = high impedance OFF-state (1) P-channel MOS transistor conducting. (2) P-channel MOS transistor and bipolar n-p-n transistor conducting. Fig.4 Typical output source current characteristic. Fig.3 Functional diagram. January 1995 Fig.5 3 Schematic diagram of output stage. Philips Semiconductors Product specification HEF40245B buffers Octal bus transceiver with 3-state outputs RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) See Family Specifications, except for: D.C. current into any input ± II max. 10 mA D.C. source or sink current into any output ± IO max. 25 mA D.C. current into the supply terminals ±I max. 100 mA DC CHARACTERISTICS VSS = 0 V VDD V VOH V VOL V Tamb (°C) SYMBOL −40 MIN. Output current HIGH Output current HIGH Output current LOW Hysteresis 5 4,6 10 9,5 15 13,5 5 3,6 10 8,4 15 13,2 −IOH + 25 MAX. MIN. 5 0,4 10 0,5 15 1,5 voltage 10 15 MAX. 0,6 1,2 0,45 mA 1,5 3,0 1,1 mA 15,5 mA 15 50 9,3 10 24 10,7 mA 14,4 15 46 15,0 mA 19,5 20 62 19,8 mA 2,3 9,5 7,6 30,0 25 5 (any input) MIN. 0,75 2,9 IOL MAX. 1,85 14,5 −IOH TYP. + 85 VH 5,4 1,75 17 mA 5,50 45 mA 19,0 mA 220 mV 250 mV 320 mV 3-state input/output leakage current 15 − IOZ(1) 1,6 pins An or Bn Note 1. Relevant output in OFF-state; An at VSS or VDD; Bn at VSS or VDD. January 1995 4 − − 1,6 − 12 µA Philips Semiconductors Product specification HEF40245B buffers Octal bus transceiver with 3-state outputs AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL TYPICAL EXTRAPOLATION FORMULA MIN. TYP. MAX. Propagation delays An → Bn HIGH to LOW 5 10 tPHL 15 An → Bn LOW to HIGH 5 10 tPLH 15 Output transition times HIGH to LOW LOW to HIGH 5 95 190 ns 83 ns + (0,24 ns/pF) CL 40 80 ns 35 ns + (0,10 ns/pF) CL 30 60 ns 26 ns + (0,07 ns/pF) CL 85 170 ns 82 ns + (0,06 ns/pF) CL 40 80 ns 38 ns + (0,03 ns/pF) CL 30 60 ns 29 ns + (0,02 ns/pF) CL 40 80 ns 20 40 ns 15 15 30 ns 5 30 60 ns 20 40 ns 15 15 30 ns 5 100 200 ns 50 100 ns 10 10 tTHL tTLH see Fig.6 3-state propagation delays Output disable times EO → An, Bn HIGH LOW 10 tPHZ 15 40 80 ns 5 100 200 ns 60 120 ns 15 50 100 ns 5 100 200 ns 10 tPLZ Output enable times EO → An, Bn HIGH LOW 10 tPZH 45 90 ns 15 35 70 ns 5 115 230 ns 55 110 ns 45 90 ns 10 tPZL 15 ALL BUFFERS SWITCHING VDD V Dynamic power 5 dissipation per package (P) TYPICAL FORMULA FOR P (µW) 4 250 fi + ∑ (foCL) × VDD2 10 17 000 fi + ∑ (foCL) × VDD 2 15 46 000 fi + ∑ (foCL) × VDD 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 5 Philips Semiconductors Product specification Octal bus transceiver with 3-state outputs tTLH − − − − tTHL Fig.6 Output transition times as a function of the load capacitance. January 1995 6 HEF40245B buffers