LINER LTC4265 8-port poe/poe pse controller Datasheet

LTC4290/LTC4271
8-Port PoE/PoE+
PSE Controller
FEATURES
DESCRIPTION
Eight Independent PSE Channels
n Compliant with IEEE 802.3at Type 1 and 2
n Chipset Provides Electrical Isolation
Reduced BOM Cost
Eliminates up to 6 High Speed Opto-Couplers
Eliminates Isolated 3.3V Power Supply
n Low Power Dissipation
0.25Ω Sense Resistance Per Channel
n Very High Reliability 4-Point PD Detection
2-Point Forced Voltage
2-Point Forced Current
n V
EE and VPORT Monitoring
n 1 Second Rolling I
PORT Averaging
n Supports 2-Pair and 4-Pair Output Power
n 1MHz I2C Compatible Serial Control Interface
n Available In a 40-Lead 6mm × 6mm (LTC4290)
and 24-Lead 4mm × 4mm (LTC4271) QFN Package
The LTC®4290/LTC4271 chipset is an 8-port power sourcing equipment (PSE) controller designed for use in IEEE
802.3at Type 1 and Type 2 (high power) compliant Power
over Ethernet (PoE) systems. Transformer-isolated communication protocol replaces expensive opto-couplers
and complex isolated 3.3V supply resulting in significant
BOM cost savings. The LTC4290/LTC4271 chipset delivers
lowest-in-industry heat dissipation by utilizing low-RDS(ON)
external MOSFETs and 0.25Ω sense resistors.
n
Advanced power management features include per-port 12bit current monitoring ADCs, DAC-programmable current
limit, and versatile fast shut-down of preselected ports.
Advanced power management host software is available
under a no-cost license. PD discovery uses a proprietary
dual-mode 4-point detection mechanism ensuring excellent immunity from false PD detection. Midspan PSEs
are supported with 2-event classification and a 2 second
backoff timer. The LTC4290/LTC4271 includes an I2C serial
interface operable up to 1MHz.
APPLICATIONS
n
n
PoE PSE Switches/Routers
PoE PSE Midspans
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
and LTPoE++ is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
3.3V
NO ISOLATION
REQUIRED ON
I2C INTERFACE
0.1µF
XIO0
VDD33
GP0
GP1
CPD
MID
RESET
MSD
AUTO
INT
3.3V
•
•
100Ω
SCL
SDAIN
SDAOUT
AD0
AD1
AD2
AD3
AD6 DGND
PORTn
S1B
GATEn
–54V
100Ω
CNA
0.25Ω
SENSEn
LTC4290
0.22µF
100V
DPA
DPD
100Ω
3.3V
•
•
100Ω
100Ω
100Ω
GATE1
0.25Ω
DNA
SENSE1
CAP2 VEE VSSK AGND
CAP1
0.1µF
–54V
>47µF
1µF SYSTEM
BULK CAP
–54V
S1B
PORT1
OUT1
–54V
DND
2nF 2kV
S1B
100Ω
CND
1µF
0.22µF
100V
OUTn
CPA
100Ω
LTC4271
XIO1
S1B
–54V
+
–54V
429071 TA01a
429071f
1
LTC4290/LTC4271
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 4)
(Note 1)
LTC4290
Supply Voltages
AGND – VEE............................................ –0.3V to 80V
VSSK (Note 7)...................... VEE – 0.3V to VEE + 0.3V
Digital Pins
XIOn .................................. VEE – 0.3V to CAP2 + 0.3V
Analog Pins
SENSEn, GATEn, OUTn ......... VEE – 0.3V to VEE + 80V
CAP2 (Note 13) ........................ VEE –0.3V to VEE + 5V
CPA, CNA, DPA, DNA...............VEE – 0.3V to VEE + 0.3
Operating Ambient Temperature Range
LTC4290I..............................................–40°C to 85°C
Junction Temperature (Note 2)............................. 125°C
Storage Temperature Range................... –65°C to 150°C
LTC4271
Supply Voltages
VDD – DGND.......................................... –0.3V to 3.6V
Digital Pins
SCL, SDAIN, SDAOUT, INT, RESET, MSD, ADn, AUTO,
MID, GPn .........................DGND – 0.3V to VDD + 0.3V
Analog Pins
CAP1 (Note 13)............................–0.3V to DGND + 2V
CPD, CND, DPD, DND.......DGND – 0.3V to VDD + 0.3V
Operating Ambient Temperature Range
LTC4271I..............................................–40°C to 85°C
Junction Temperature (Note 2)............................. 125°C
Storage Temperature Range................... –65°C to 150°C
429071f
2
LTC4290/LTC4271
PIN CONFIGURATION
LTC4271
28 OUT8
GATE2 4
27 GATE7
OUT2 5
41
VSSK
CAP2 6
CAP1
24 23 22 21 20 19
29 GATE8
OUT1 3
VDD33
30 VEE
GATE1 2
AUTO
MSD
40 39 38 37 36 35 34 33 32 31
VEE 1
GP1
NC
TOP VIEW
NC
VEE
NC
NC
DNA
DPA
CNA
CPA
VEE
TOP VIEW
GP0
LTC4290
AD0 1
18 SCL
AD1 2
17 SDAIN
26 OUT7
AD2 3
25 AGND
AD3 4
16 SDAOUT
25
DGND
15 INT
24 GATE6
AD6 5
14 RESET
OUT3 8
23 OUT6
MID 6
13 DNC
GATE4 9
22 GATE5
VDD33
DND
9 10 11 12
DPD
NC
XIO1
SENSE8
SENSE7
SENSE6
SENSE5
SENSE4
SENSE3
SENSE2
XIO0
SENSE1
11 12 13 14 15 16 17 18 19 20
8
CPD
7
21 OUT5
OUT4 10
CND
GATE3 7
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
TJMAX = 125°C, θJC = 4°C/W
EXPOSED PAD (PIN 25) IS DGND, MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJC = 2°C/W
EXPOSED PAD (PIN 41) IS VSSK, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
LTC4271IUF#PBF
LTC4271IUF#TRPBF
4271
24-Lead (4mm × 4mm) Plastic QFN
LTC4290BIUJ#PBF
LTC4290BIUJ#TRPBF
LTC4290BUJ
40-Lead (6mm × 6mm) Plastic QFN
MAX PWR TEMPERATURE RANGE
–40°C to 85°C
25.5W
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
429071f
3
LTC4290/LTC4271
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 & 4)
SYMBOL PARAMETER
VEE
VDD
Main PoE Supply Voltage
CONDITIONS
MIN
AGND – VEE
For IEEE Type 1 Compliant Output
For IEEE Type 2 Compliant Output
l
l
TYP
45
51
MAX
UNITS
57
57
V
V
Undervoltage Lock-Out
AGND – VEE
l
20
25
30
V
VDD Supply Voltage
VDD – DGND
l
3.0
3.3
3.6
V
Undervoltage Lock-Out
VDD – DGND
2.7
V
VCAP1
Internal Regulator Supply Voltage
VCAP1 – DGND
1.84
V
VCAP2
Internal Regulator Supply Voltage
VCAP2 – VEE
4.3
V
IEE
VEE Supply Current
(AGND – VEE) = 55V
l
REE
VEE Supply Resistance
VEE < 15V
l
IDD
VDD Supply Current
(VDD – DGND) = 3.3V
l
Detection Current – Forced Current
First Point, AGND – VOUTn = 9V
Second Point, AGND – VOUTn = 3.5V
l
l
Detection Voltage – Forced Voltage
AGND – VOUTn, 5µA ≤ IOUTn ≤ 500µA
First Point
Second Point
l
l
Detection Current Compliance
AGND – VOUTn = 0V
Detection Voltage Compliance
Detection Voltage Slew Rate
9
15
mA
12
kΩ
10
15
mA
220
143
240
160
260
180
µA
µA
7
3
8
4
9
5
V
V
l
0.8
0.9
AGND – VOUTn, Open Port
l
10.4
AGND – VOUTn, CPORT = 0.15µF
l
Detection
VOC
12
mA
V
0.01
V/µs
Min. Valid Signature Resistance
l
15.5
17
18.5
kΩ
Max. Valid Signature Resistance
l
27.5
29.7
32
kΩ
Classification
VCLASS
VMARK
Classification Voltage
AGND – VOUTn, 0mA ≤ IOUTn ≤ 50mA
l
16.0
Classification Current Compliance
VOUTn = AGND
l
53
61
20.5
67
mA
V
Classification Threshold Current
Class 0-1
Class 1-2
Class 2-3
Class 3-4
Class 4-Overcurrent
l
l
l
l
l
5.5
13.5
21.5
31.5
45.2
6.5
14.5
23
33
48
7.5
15.5
24.5
34.9
50.8
mA
mA
mA
mA
mA
Classification Mark State Voltage
AGND – VOUTn, 0.1mA ≤ ICLASS ≤ 5mA
l
7.5
9
10
V
Mark State Current Compliance
VOUTn = AGND
l
53
61
67
mA
Port Off, VGATEn = VEE + 5V
Port Off, VGATEn = VEE + 1V
l
l
0.4
0.08
0.12
Gate Driver
GATE Pin Pull-Down Current
mA
mA
GATE Pin Fast Pull-Down Current
VGATEn = VEE + 5V
GATE Pin On Voltage
VGATEn – VEE, IGATEn = 1µA
l
8
30
12
14
mA
V
Power Good Threshold Voltage
VOUTn – VEE
l
2
2.4
2.8
V
OUT Pin Pull-Up Resistance to AGND
0V ≤ (AGND – VOUT) ≤ 5V
l
300
500
700
kΩ
Output Voltage Sense
VPG
429071f
4
LTC4290/LTC4271
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 & 4)
SYMBOL PARAMETER
VCUT
VLIM
Overcurrent Sense Voltage
CONDITIONS
MIN
TYP
MAX
UNITS
VSENSEn – VEE,
hpen = 0Fh, cutn = D4h
hpen = 0Fh, cutn = E2h (Note 12)
l
l
89
152
94
159
99
168
mV
mV
Overcurrent Sense in AUTO Pin Mode
Class 0, Class 3
Class 1
Class 2
Class 4
l
l
l
l
89
26
49
152
94
28
52
159
99
30
55
168
mV
mV
mV
mV
Active Current Limit in 802.3af Compliant Mode
VSENSEn – VEE, hpen = 0Fh, limn = 80h,
(AGND – VEE) = 55V
VEE < VOUT < AGND – 29V
AGND – VOUT = 0V (Note 12)
l
l
102
25
106
112
50
mV
mV
hpen = 0Fh, limn = C0h,
(AGND – VEE) = 55V
VOUT – VEE = 0 – 10V
VEE + 23V < VOUT < AGND – 29V
AGND – VOUT = 0V (Note 12)
l
l
l
204
102
25
212
106
225
115
50
mV
mV
mV
VEE < VOUT < AGND – 10V,
(AGND – VEE) = 55V
Class 0 to Class 3
Class 4
l
l
102
204
106
212
112
225
mV
mV
Active Current Limit in High Power Mode
Active Current Limit in AUTO Pin Mode
VMIN
DC Disconnect Sense Voltage
VSENSE – VEE, rdis Bit = 0
VSENSE – VEE, rdis Bit = 1 (Note 12)
l
l
2.6
1.3
3.8
1.9
4.9
2.45
mV
mV
VSC
Short-Circuit Sense
VSENSEn – VEE – VLIM (Note 12)
rdis Bit = 0
rdis Bit = 1
l
l
125
70
200
100
255
125
mV
mV
Port Current Readback
Resolution
No Missing Codes, Reported as 14 Bits
LSB Weight
VSENSEn – VEE
12
Conversion Period
Bits
30.518
µV/LSB
25.1
ms/
Convert
Port Voltage Readback
Resolution
No Missing Codes, Reported as 14 Bits
LSB Weight
VSENSEn – VEE
12
Bits
5.8350
mV/LSB
Digital Interface
VILD
VIHD
Digital Input Low Voltage
ADn, RESET, MSD, GPn, AUTO, MID
(Note 6)
l
0.8
V
I2C Input Low Voltage
SCL, SDAIN (Note 6)
l
1.0
V
Digital Input High Voltage
(Note 6)
l
Digital Output Voltage Low
ISDAOUT = 3mA, IINT = 3mA
ISDAOUT = 5mA, IINT = 5mA
l
l
Internal Pull Up to VDD
ADn, RESET, MSD, GPn
50
kΩ
Internal Pull Down To DGND
AUTO, MID
50
kΩ
2.2
V
0.4
0.7
V
V
429071f
5
LTC4290/LTC4271
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 & 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
XIO
VOLX
XIO Digital Output Low
VXIOn – VEE, IXIOn = 5mA
l
VOHX
XIO Digital Output High
VXIOn – VEE, IXIOn = 100µA
l
0.7
XIO Digital Input Low Voltage
VXIOn – VEE
l
XIO Digital Input High Voltage
VXIOn – VEE
l
Internal Pull Up to CAP2
XIO0, XIO1
50
kΩ
3.5
V
V
0.8
3.4
V
V
PSE Timing Characteristics
tDET
Detection Time
Beginning To End of Detection (Note 7)
220
ms
tCLE
Class Event Duration
(Note 7)
12
ms
tCLEON
Class Event Turn On Duration
CPORT = 0.6µF (Note 7)
tME
Mark Event Duration
(Note 7, Note 11)
tMEL
Last Mark Event Duration
(Note 7, Note 11)
l
tPON
Power On Delay in AUTO Pin Mode
From End of Valid Detect to Application of
Power to Port (Note 7)
l
Turn-On Rise Time
(AGND – VOUT): 10% to 90% of (AGND VEE) CPORT = 0.15µF (Note 7)
l
0.1
l
16
ms
22
ms
60
15
ms
8.6
24
ms
µs
Turn-On Ramp Rate
CPORT = 0.15µF (Note 7)
l
10
V/µs
tTOCL
Turn-On Class Transition
CPORT = 0.15µF (Note 7)
l
0.1
ms
tED
Fault Delay
From ICUT or ILIM Fault to Next Detect
(Note 7)
l
1.0
1.1
Midspan Mode Detection Backoff
RPORT = 15.5kΩ (Note 7)
l
2.3
2.5
2.7
s
Power Removal Detection Delay
From Power Removal After tDIS to Next
Detect (Note 7)
l
1.0
1.3
2.5
s
tSTART
Maximum Current Limit Duration During Port
Start-Up
(Note 7)
l
52
59
66
ms
tCUT
Maximum Overcurrent Duration After Port StartUp
(Note 7)
l
52
59
66
ms
Maximum Overcurrent Duty Cycle
(Note 7)
l
5.8
6.3
6.7
%
Maximum Current Limit Duration After Port Start- tLIM = 1 (Note 7, Note 12)
Up – tLIM Enabled
l
10
12
14
ms
Maximum Current Limit Duration After Port Start- tLIM = 0 (Note 7, Note 12)
Up – tLIM as tCUT
l
52
59
66
ms
tMPS
Maintain Power Signature (MPS) Pulse Width
Sensitivity
Current Pulse Width to Reset Disconnect
Timer (Note 7, Note 8)
l
1.6
3.6
ms
tDIS
Maintain Power Signature (MPS) Dropout Time
(Note 7, Note 5)
l
320
350
380
ms
6.5
µs
2
3
s
tLIM
tMSD
s
Masked Shut Down Delay
(Note 7)
I2C Watchdog Timer Duration
(Note 7)
l
1.5
Minimum Pulse Width for Masked Shut Down
(Note 7)
l
3
µs
Minimum Pulse Width for RESET
(Note 7)
l
4.5
µs
429071f
6
LTC4290/LTC4271
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 & 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I2C Timing
fSCLK
Clock Frequency
(Note 7)
l
1
t1
Bus Free Time
Figure 5 (Notes 7, 9)
l
480
ns
t2
Start Hold Time
Figure 5 (Notes 7, 9)
l
240
ns
t3
SCL Low Time
Figure 5 (Notes 7, 9)
l
480
ns
t4
SCL High Time
Figure 5 (Notes 7, 9)
l
240
ns
t5
SDAIN Data Hold Time
Figure 5 (Notes 7, 9)
l
60
ns
t5
Data Clock to SDAOUT Valid
Figure 5 (Notes 7, 9)
l
130
MHz
ns
t6
Data Set-Up Time
Figure 5 (Notes 7, 9)
l
80
ns
t7
Start Set-Up Time
Figure 5 (Notes 7, 9)
l
240
ns
t8
Stop Set-Up Time
Figure 5 (Notes 7, 9)
l
240
ns
tr
SCL, SDAIN Rise Time
Figure 5 (Notes 7, 9)
l
120
ns
tf
SCL, SDAIN Fall Time
Figure 5 (Notes 7, 9)
l
60
ns
Fault Present to INT Pin Low
(Notes 7, 9, 10)
l
150
ns
Stop Condition to INT Pin Low
(Notes 7, 9, 10)
l
1.5
µs
ARA to INT Pin High Time
(Notes 7, 9)
l
1.5
µs
SCL Fall to ACK Low
(Notes 7, 9)
l
130
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. With the exception of (VDD –
DGND), exposure to any Absolute Maximum Rating condition for extended
periods may affect device reliability and lifetime.
Note 2: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 140ºC when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative.
Note 4: The LTC4290 operates with a negative supply voltage (with respect
to AGND). To avoid confusion, voltages in this data sheet are referred to in
terms of absolute magnitude.
Note 5: tDIS is the same as tMPDO defined by IEEE 802.3
Note 6: The LTC4271 digital interface operates with respect to DGND. All
logic levels are measured with respect to DGND.
Note 7: Guaranteed by design, not subject to test.
Note 8: The IEEE 802.3 specification allows a PD to present its
Maintain Power Signature (MPS) on an intermittent basis without being
disconnected. In order to stay powered, the PD must present the MPS for
tMPS within any tMPDO time window.
Note 9: Values Measured at VILD and VIHD
Note 10: If a fault condition occurs during an I2C transaction, the INT pin
will not be pulled down until a stop condition is present on the I2C bus.
Note 11: Load characteristics of the LTC4290 during Mark: 7V < (AGND –
VOUTn) < 10V or IOUT < 50µA.
Note 12: See the LTC4271 Software Programming documentation for
information on serial bus usage and device configuration and status
registers.
Note 13: Do not source or sink current from CAP1 and CAP2.
429071f
7
LTC4290/LTC4271
TYPICAL PERFORMANCE CHARACTERISTICS
802.3af Power On Sequence in
AUTO Pin Mode
0
802.3at Power On Sequence in
AUTO Pin Mode
0
AGND
FORCED VOLTAGE
DETECTION
–30
802.3af
CLASSIFICATION
VEE = –55V
CLASS 3 PD
POWER ON
VEE
FORCED CURRENT
DETECTION
–20
FORCED VOLTAGE
DETECTION
–30
–40
–50
VEE = –55V
CLASS 4 PD
802.3at
CLASSIFICATION
POWER ON
VEE
0mA
GATE VOLTAGE
10V/DIV
VEE
DETECT WITH 60Hz NOISE
NORMAL DETECT
POWER ON
429071 G03
Classification Transient Response
to 40mA Load Step
40mA
PORT
CURRENT
20mA/DIV
0mA
VEE = –54V
425mA
CURRENT LIMIT
VDD = 3.3V
VEE = –54V
–2
PORT
VOLTAGE
1V/DIV
–20V
FET ON
–4
–6
–8
–10
–12
–14
–16
–18
429071 G05
50µs/DIV
5ms/DIV
Classification Current Compliance
0
LOAD FULLY CHARGED
FOLDBACK
802.3af
CLASSIFICATION
50ms/DIV
CLASSIFICATION VOLTAGE (V)
AGND
PORT CURRENT
200mA/DIV
FORCED CURRENT
DETECTION
–15
429071 G02
Powering Up into a 180µF Load
VEE
–10
–25
429071 G01
PORT VOLTAGE
20V/DIV
–5
50ms/DIV
50ms/DIV
FORCED VOLTAGE
DETECTION
AGND
–20
–60
–60
PORT OFF
0
PORT VOLTAGE (V)
PORT VOLTAGE (V)
PORT VOLTAGE (V)
FORCED CURRENT
DETECTION
–20
–50
5
AGND
–10
–10
–40
Power On Sequence with 10VPP
60Hz Noise
–20
0
10
20
30
40
50
60
CLASSIFICATION CURRENT (mA)
429071 G04
429071 G06
VDD Supply Current vs Voltage
IDD SUPPLY CURRENT (mA)
9.0
6.0
0.0
VEE Supply Current vs Voltage
8.5
12.0
3.0
9.0
85°C
25°C
–40
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
VDD SUPPLY VOLTAGE (V)
429071 G07
IEE SUPPLY CURRENT (mA)
15.0
70
8.0
7.5
7.0
6.5
6.0
–60
85°C
25°C
–40
–50
–40
–30
VEE SUPPLY VOLTAGE (V)
–20
429071 G08
429071f
8
LTC4290/LTC4271
TYPICAL PERFORMANCE CHARACTERISTICS
802.3at ILIM Threshold
vs Temperature
208
832
204
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
162
648
160
640
158
632
156
624
154
616
152
–40 –20
816
100 120
656
0
20 40 60 80
TEMPERATURE (°C)
DC Disconnect Threshold
vs Temperature
802.3at Current Limit Foldback
PORT 1
REG 47h = E2h
RSENSE = 0.25Ω
7
1.50
6
0
20 40 60 80
TEMPERATURE (°C)
ILIM (mA)
1.75
700
150
500
125
400
100
300
75
200
50
100
25
–45
–36
–27
–18
VOUTn (V)
INT and SDAOUT Pull Down
Voltage vs Load Current
0
0
MOSFET Gate Drive With Fast
Pull Down
3.0
GND
VDD = 3.3V
VEE = –54V
PORT
VOLTAGE
20V/DIV
2.5
PULLDOWN VOLTAGE (V)
–9
429071 G12
429071 G11
2.0
VEE
1.5
FAST PULL DOWN
GATE
VOLTAGE
10V/DIV VEE
1.0
PORT
CURRENT
500mA/DIV 0mA
0.5
0.0
175
600
0
–54
5
100 120
200
VLIM (mV)
8
225
PORT 1
REG 48h = C0h
RSENSE = 0.25Ω
800
9
2.00
1.25
–40 –20
900
10
IMIN (mA)
VMIN (mV)
2.25
608
100 120
429071 G10
429071 G09
2.50
ICUT (mA)
848
ILIM (mA)
212
664
PORT 1
REG 47h = E2h
164 R
SENSE = 0.25Ω
864
216
VLIM (mV)
166
880
PORT 1
REG 48h = C0h
RSENSE = 0.25Ω
VCUT (mV)
220
802.3at ICUT Threshold
vs Temperature
0
10
20
30
40
LOAD CURRENT (mA)
50
60
50Ω
FAULT
APPLIED
CURRENT LIMIT
50Ω FAULT REMOVED
100µs/DIV
429071 G14
429071 G13
429071f
9
LTC4290/LTC4271
TEST TIMING DIAGRAMS
CLASSIFICATION
tDET
FORCED-CURRENT
VPORTn
FORCEDVOLTAGE
tME
0V
tMEL
VOC
VMARK
15.5V
VCLASS
20.5V
tCLE
tCLE
PD
CONNECTED
tCLEON
tPON
VEE
INT
429071 F01
Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-auto Modes
VLIM
VCUT
VSENSEn TO VEE
0V
tSTART, tCUT
INT
429071 F02
Figure 2. Current Limit Timing
VSENSEn
TO VEE
VMIN
INT
tMPS
tDIS
429071 F03
Figure 3. DC Disconnect Timing
429071f
10
LTC4290/LTC4271
TEST TIMING DIAGRAMS
VGATEn
VEE
tMSD
MSD
429071 F04
Figure 4. Shut Down Delay Timing
t3
tr
t4
tf
SCL
t2
t5
t6
t7
t8
SDA
t1
429071 F05
Figure 5. I2C Interface Timing
429071f
11
LTC4290/LTC4271
I2C TIMING DIAGRAMS
SCL
SDA
AD6
1
0
AD3 AD2 AD1 AD0 R/W ACK A7
START BY
MASTER
A6
A5
A4
A3
A2
ACK BY
SLAVE
FRAME 1
SERIAL BUS ADDRESS BYTE
A1
A0 ACK D7
D6
D5
D4
D3
D2
ACK BY
SLAVE
D1
D0
ACK
STOP BY
MASTER
ACK BY
SLAVE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 3
DATA BYTE
429071 F06
Figure 6. Writing to a Register
SCL
SDA
AD6
1
0
AD3 AD2 AD1 AD0 R/W ACK A7
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
A6
ACK BY
SLAVE
A5
A4
A3
A2
A1
A0 ACK
ACK BY
SLAVE
FRAME 2
REGISTER ADDRESS BYTE
AD6
1
0
AD3 AD2 AD1 AD0 R/W ACK D7
REPEATED
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
D6
D5
D4
D3
ACK BY
SLAVE
D2
D1
D0 ACK
NO ACK BY
MASTER
FRAME 2
DATA BYTE
STOP BY
MASTER
429071 F07
Figure 7. Reading from a Register
429071f
12
LTC4290/LTC4271
I2C TIMING DIAGRAMS
SCL
SDA
AD6
1
0
AD3 AD2 AD1 AD0 R/W ACK D7
START BY
MASTER
D6
D5
D4
D3
ACK BY
SLAVE
D2
D1
D0 ACK
STOP BY
MASTER
NO ACK BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE
429071 F08
Figure 8. Reading the Interrupt Register (Short Form)
SCL
SDA
0
0
0
1
1
0
0
R/W ACK AD6
START BY
MASTER
1
ACK BY
SLAVE
FRAME 1
ALERT RESPONSE ADDRESS BYTE
0
AD3 AD2 AD1 AD0
1
NO ACK BY
MASTER
FRAME 2
SERIAL BUS ADDRESS BYTE
ACK
STOP BY
MASTER
429071 F09
Figure 9. Reading from Alert Response Address
429071f
13
LTC4290/LTC4271
PIN FUNCTIONS
LTC4290
VEE (Pins 1, 30, 33, 40): Main PoE Supply Input. Connect to a –45V to –57V supply, relative to AGND. Voltage
depends on PSE type (Type 1 or Type 2).
GATEn (Pins 2, 4, 7, 9, 22, 24, 27, 29): Port n Gate Drive.
GATEn should be connected to the gate of the external
MOSFET for port n. When the MOSFET is turned on, the
gate voltage is driven to 12V (typ) above VEE. During a
current limit condition, the voltage at GATEn will be reduced to maintain constant current through the external
MOSFET. If the fault timer expires, GATEn is pulled down,
turning the MOSFET off and recording a port fault event.
If the port is unused, float the GATEn pin.
OUTn (Pins 3, 5, 8, 10, 21, 23, 26, 28): Port n Output
Voltage Monitor. OUTn should be connected to the output
port. A current limit foldback circuit limits the power dissipation in the external MOSFET by reducing the current
limit threshold when the drain-to-source voltage exceeds
10V. The port n Power Good bit is set when the voltage
from OUTn to VEE drops below 2.4V (typ). A 500k resistor
is connected internally from OUTn to AGND when the port
is idle. If the port is unused, the OUTn pin must be floated.
CAP2 (Pin 6): Analog Internal 4.3V Power Supply Bypass
Capacitor. Connect 0.1µF ceramic cap to VEE.
XIO0 (Pin 11): General Purpose Digital Input Output. Logic
signal between VEE and VEE + 4.3V. Internal pull up.
SENSEn (Pins 12, 13, 14, 15, 16, 17, 18, 19): Port n
Current Sense Input. SENSEn monitors the external MOSFET current via a 0.5Ω or 0.25Ω sense resistor between
SENSEn and VEE. Whenever the voltage across the sense
resistor exceeds the overcurrent detection threshold VCUT,
the current limit fault timer counts up. If the voltage across
the sense resistor reaches the current limit threshold VLIM,
the GATEn pin voltage is lowered to maintain constant current in the external MOSFET. See Applications Information
for further details. If the port is unused, the SENSEn pin
must be tied to VEE.
AGND (Pin 25): Analog Ground. Connect AGND to the
return for the VEE supply.
DNA (Pin 36): Data Transceiver Negative Input Output
(Analog). Connect to DND through a data transformer.
DPA (Pin 37): Data Transceiver Positive Input Output
(Analog). Connect to DPD through a data transformer.
CNA (Pin 38): Clock Transceiver Negative Input Output
(Analog). Connect to CND through a data transformer.
CPA (Pin 39): Clock Transceiver Positive Input Output
(Analog). Connect to CPD through a data transformer.
VSSK (Exposed Pad Pin 41): Kelvin Sense to VEE. Connect
to sense resistor common node. Do not connect directly
to VEE plane. See Layout Guide.
Common Pins
NC, DNC (LTC4271 Pins 7,13; LTC4290 Pins 31, 32, 34,
35): All pins identified with “NC” or “DNC” must be left
unconnected.
LTC4271
AD0 (Pin 1): Address Bit 0. Tie the address pins high or low
to set the starting I2C serial address to which the LTC4271
responds. The chip will respond to this address plus the
next two incremental addresses. The base address of the
first four ports will be (A610A3A2A1A0)b. The second and
third groups of four ports will respond at the next two
logical addresses. Internally pulled up to VDD.
AD1 (Pin 2): Address Bit 1. See AD0.
AD2 (Pin 3): Address Bit 2. See AD0.
AD3 (Pin 4): Address Bit 3. See AD0.
AD6 (Pin 5): Address Bit 6. See AD0.
MID (Pin 6): Midspan Mode Input. When high, the LTC4271
acts as a midspan device. Internally pulled down to DGND.
CPD (Pin 8): Clock Transceiver Positive Input Output
(Digital). Connect to CPA through a data transformer.
XIO1 (Pin 20): General Purpose Digital Input Output. Logic
signal between VEE and VEE + 4.3V. Internal pull up.
429071f
14
LTC4290/LTC4271
PIN FUNCTIONS
CND (Pin 9): Clock Transceiver Negative Input Output
(Digital). Connect to CNA through a data transformer.
DPD (Pin 10): Data Transceiver Positive Input Output
(Digital). Connect to DPA through a data transformer.
DND (Pin 11): Data Transceiver Negative Input Output
(Digital). Connect to DNA through a data transformer.
VDD33 (Pins 12, 20): VDD IO Power Supply. Connect to
a 3.3V power supply relative to DGND. VDD33 must be
bypassed to DGND near the LTC4271 with at least a 0.1μF
capacitor.
RESET (Pin 14): Reset Input, Active Low. When the RESET
pin is low, the LTC4290/LTC4271 is held inactive with all
ports off and all internal registers reset to their power-up
states. When RESET is pulled high, the LTC4271 begins
normal operation. RESET can be connected to an external capacitor or RC network to provide a power turn-on
delay. Internal filtering of the RESET pin prevents glitches
less than 1μs wide from resetting the LTC4290/LTC4271.
Internally pulled up to VDD.
INT (Pin 15): Interrupt Output, Open Drain. INT will pull low
when any one of several events occur in the LTC4271. It will
return to a high impedance state when bits 6 or 7 are set
in the Reset PB register (1Ah). The INT signal can be used
to generate an interrupt to the host processor, eliminating
the need for continuous software polling. Individual INT
events can be disabled using the INT Mask register (01h).
See LTC4271 Software Programming documentation for
more information. The INT pin is only updated between
I2C transactions.
SDAOUT (Pin 16): Serial Data Output, Open Drain Data
Output for the I2C Serial Interface Bus. The LTC4271 uses
two pins to implement the bidirectional SDA function to
simplify optoisolation of the I2C bus. To implement a standard bidirectional SDA pin, tie SDAOUT and SDAIN together.
See Applications Information for more information.
SDAIN (Pin 17): Serial Data Input. High impedance data
input for the I2C serial interface bus. The LTC4271 uses two
pins to implement the bidirectional SDA function to simplify
optoisolation of the I2C bus. To implement a standard
bidirectional SDA pin, tie SDAOUT and SDAIN together.
See Applications Information for more information.
SCL (Pin 18): Serial Clock Input. High impedance clock
input for the I2C serial interface bus. The SCL pin should
be connected directly to the I2C SCL bus line. SCL must
be tied high if the I2C serial interface bus is not used.
CAP1 (Pin 19): Core Power Supply Bypass Capacitor. Connect a 1µF Bypass capacitance to DGND for the internal
1.8V regulator. Do not use other capacitor values.
AUTO (Pin 21): AUTO Pin Mode Input. AUTO pin mode
allows the LTC4271 to detect and power up a PD even if
there is no host controller present on the I2C bus. The
AUTO pin determines the state of the internal registers
when the LTC4271 is reset or comes out of VDD UVLO
(see LTC4271 Software Programming documentation). The
states of these register bits can subsequently be changed
via the I2C interface. Internally pulled down to DGND. Must
be tied locally to either VDD or DGND.
GP1 (Pin 22): General Purpose Digital Input Output for
customer applications. Referenced to DGND.
GP0 (Pin 23): General Purpose Digital Input Output for
customer applications. Referenced to DGND.
MSD (Pin 24): Maskable Shutdown Input. Active low. When
pulled low, all ports that have their corresponding mask
bit set in the mconfig register (17h) will be reset. Internal
filtering of the MSD pin prevents glitches less than 1μs
wide from resetting ports. The MSD Pin Mode register can
configure the MSD pin polarity. Internally pulled up to VDD.
DGND (Exposed Pad Pin 25): Digital Ground. DGND should
be connected to the return from the VDD supply.
429071f
15
LTC4290/LTC4271
APPLICATIONS INFORMATION
OVERVIEW
LTC4290/LTC4271 Product Overview
Power over Ethernet, or PoE, is a standard protocol for
sending DC power over copper Ethernet data wiring. The
IEEE group that administers the 802.3 Ethernet data standards added PoE powering capability in 2003. This original
PoE spec, known as 802.3af, allowed for 48V DC power at
up to 13W. This initial specification was widely popular, but
13W was not adequate for some requirements. In 2009,
the IEEE released a new standard, known as 802.3at or
PoE+, increasing the voltage and current requirements to
provide 25W of power.
The LTC4290/LTC4271 is a fourth generation 8-port PSE
controller that implements eight PSE ports in either an
endpoint or midspan design. Virtually all necessary circuitry
is included to implement an IEEE 802.3at compliant PSE
design, requiring only an external power MOSFET and sense
resistor per channel; these minimize power loss compared
to alternative designs with onboard MOSFETs and increase
system reliability in the event a single channel fails.
The IEEE standard also defines PoE terminology. A device
that provides power to the network is known as a PSE, or
power sourcing equipment, while a device that draws power
from the network is known as a PD, or powered device.
PSEs come in two types: Endpoints (typically network
switches or routers), which provide data and power; and
Midspans, which provide power but pass through data.
Midspans are typically used to add PoE capability to existing
non-PoE networks. PDs are typically IP phones, wireless
access points, security cameras, and similar devices.
PSE
RJ45
4
DGND
3.3V
INTERRUPT
I2C
1µF
100V
X7R
–48V
The LTC4290/LTC4271 chipset implements a proprietary
isolation scheme for inter-chip communication. This
architecture dramatically reduces BOM cost by replacing
expensive opto-isolators and isolated power supplies with
a single low-cost transformer.
LTC4290/LTC4271 is a fully IEEE-compliant Type 2 PSE
supporting autonomous detection, classification and
powering of Type 1 and Type 2 PDs.
CAT 5
20Ω MAX
ROUNDTRIP
0.05µF MAX
5
GND
SMAJ58A
The LTC4290/LTC4271 offers advanced fourth generation
PSE features, including per-port current monitoring, VEE
monitoring, port current policing, one second current
averaging and four general purpose input/output pins.
AGND
VDD33
1/8
INT
LTC4290/
SCL
LTC4271
SDAIN
SDAOUT
VEE
SENSE GATE OUT
0.25Ω
S1B
PD
RJ45
4
5
1N4002
×4
SPARE PAIR
0.22µF
100V
X7R
1
1
Tx
DATA PAIR
3
2
3
Rx
0.1µF
Tx
6
DATA PAIR
6
5µF ≤ CIN
≤ 300µF
SMAJ58A
58V
Rx
2
1N4002
×4
GND
RCLASS
S1B
PWRGD
LTC4265
7
7
8
8
–48VIN
–48VOUT
DC/DC
CONVERTER
+
VOUT
–
SPARE PAIR
429071 F10
Figure 10. Power over Ethernet System Diagram
429071f
16
LTC4290/LTC4271
APPLICATIONS INFORMATION
PoE BASICS
Common Ethernet data connections consist of two or four
twisted pairs of copper wire (commonly known as CAT-5
cable), transformer-coupled at each end to avoid ground
loops. PoE systems take advantage of this coupling arrangement by applying voltage between the center-taps
of the data transformers to transmit power from the PSE
to the PD without affecting data transmission. Figure 10
shows a high level PoE system schematic.
To avoid damaging legacy data equipment that does not
expect to see DC voltage, the PoE spec defines a protocol
that determines when the PSE may apply and remove
power. Valid PDs are required to have a specific 25k common mode resistance at their input. When such a PD is
connected to the cable, the PSE detects this signature
resistance and turns on the power. When the PD is later
disconnected, the PSE senses the open circuit and turns
power off. The PSE also turns off power in the event of a
current fault or short circuit.
When a PD is detected, the PSE optionally looks for a
classification signature that tells the PSE the maximum
power the PD will draw. The PSE can use this information
to allocate power among several ports, to police the current
consumption of the PD, or to reject a PD that will draw more
power than the PSE has available. The classification step
is optional; if a PSE chooses not to classify a PD, it must
assume that the PD is a 13W (full 802.3af power) device.
New in 802.3at
The newer 802.3at standard supersedes 802.3af and brings
several new features:
• A PD may draw as much as 25.5W. Such PDs (and the
PSEs that support them) are known as Type 2. Older
13W 802.3af equipment is classified as Type 1. Type 1
PDs will work with all PSEs; Type 2 PDs may require
Type 2 PSEs to work properly. The LTC4290/LTC4271
is designed to work in both Type 1 and Type 2 PSE designs, and also supports non-standard configurations
at higher power levels.
• The Classification protocol is expanded to allow Type 2
PSEs to detect Type 2 PDs, and to allow Type 2 PDs to
determine if they are connected to a Type 2 PSE. Two
versions of the new Classification protocol are available: an expanded version of the 802.3af Class Pulse
protocol, and an alternate method integrated with the
existing LLDP protocol (using the Ethernet data path).
The LTC4290/LTC4271 fully supports the new Class
Pulse protocol and is also compatible with the LLDP
protocol (which is implemented in the data communications layer, not in the PoE circuitry).
• Fault protection current levels and timing are adjusted
to reduce peak power in the MOSFET during a fault; this
allows the new 25.5W power levels to be reached using
the same MOSFETs as older 13W designs.
BACKWARD COMPATIBILITY
The LTC4290/LTC4271 chipset is designed to be backward
compatible with the LTC4266, operating in Type 2 mode,
without software changes; only minor layout changes
are required to implement a fully compliant IEEE 802.3at
design.
Some LTC4266 registers have been obsoleted in the
LTC4290/LTC4271 chipset. The obsoleted registers are not
required for 802.3at compliant PSE operation. For more
details about software differences between the LTC4266
and LTC4290/LTC4271, refer to the LTC4271 Software
Programming document.
Operation with high power mode disabled is obsoleted in
the LTC4290/LTC4271 chipset. All operations previously
available in low power mode are fully implemented as a
subset of the high power mode capabilities.
429071f
17
LTC4290/LTC4271
APPLICATIONS INFORMATION
OPERATING MODES
The LTC4290/LTC4271 includes eight independent ports,
each of which can operate in one of four modes: manual,
semi-auto, AUTO pin, or shutdown.
Table 1. Operating Modes
MODE
AUTO OPMD DETECT/
PIN
CLASS
POWER-UP
AUTOMATIC
ICUT/ILIM
ASSIGNMENT
AUTO Pin
1
11b
Enabled
at Reset
Automatically
Yes
Reserved
0
11b
N/A
N/A
N/A
Semi-auto
0
10b
Host
Enabled
Upon
Request
No
Manual
0
01b
Once
Upon
Request
Upon
Request
No
Shutdown
0
00b
Disabled
Disabled
No
In manual mode, the port waits for instructions from the
host system before taking any action. It runs a single
detection or classification cycle when commanded to by
the host, and reports the result in its Port Status register.
The host system can command the port to turn on or off
the power at any time.
In semi-auto mode, the port repeatedly attempts to detect
and classify any PD attached to it. It reports the status of
these attempts back to the host, and waits for a command
from the host before turning on power to the port. The
host must enable detection (and optionally classification)
for the port before detection will start.
AUTO pin mode operates the same as semi-auto mode
except it will automatically turn on the power to the port if
detection is successful. AUTO pin mode will autonomously
set the ICUT and ILIM values based on the class result. This
operational mode is only valid if the AUTO pin is high at
reset or power-up and remains high during operation.
In shutdown mode, the port is disabled and will not detect
or power a PD.
Regardless of which mode it is in, the LTC4290/LTC4271
will remove power automatically from any port that generates a current limit fault. It will also automatically remove
power from any port that generates a disconnect event if
disconnect detection is enabled. The host controller may
also command the port to remove power at any time.
Reset and the AUTO/MID Pins
The initial LTC4290/LTC4271 configuration depends on
the state of the AUTO and MID pins during reset. Reset
occurs at power-up, or whenever the RESET pin is pulled
low or the global Reset All bit is set. Changing the state of
AUTO or MID after power-up will not properly change the
port behavior of the LTC4290/LTC4271 until a reset occurs.
Although typically used with a host controller, the LTC4290/
LTC4271 can also be used in a standalone mode with no
connection to the serial interface. If there is no host present, the AUTO pin must be tied high so that, at reset, all
ports will be configured to operate automatically. Each port
will detect and classify repeatedly until a PD is discovered,
set ICUT and ILIM according to the classification results,
apply power to valid PDs, and remove power when a PD
is disconnected.
Table 2 shows the ICUT and ILIM values that will be automatically set in standalone (AUTO pin) mode, based on
the discovered class.
Table 2. ICUT and ILIM Values in Standalone Mode
CLASS
ICUT
ILIM
Class 1
112mA
425mA
Class 2
206mA
425mA
Class 3 or 0
375mA
425mA
Class 4
638mA
850mA
The automatic setting of ICUT and ILIM values only occurs
if the LTC4290/LTC4271 is reset with the AUTO pin high.
If the standalone application is a midspan, the MID pin must
be tied high to enable correct midspan detection timing.
429071f
18
LTC4290/LTC4271
APPLICATIONS INFORMATION
DETECTION
Detection Overview
To avoid damaging network devices that were not designed
to tolerate DC voltage, a PSE must determine whether the
connected device is a real PD before applying power. The
IEEE specification requires that a valid PD have a commonmode resistance of 25k ±5% at any port voltage below 10V.
The PSE must accept resistances that fall between 19k and
26.5k, and it must reject resistances above 33k or below
15k (shaded regions in Figure 11). The PSE may choose to
accept or reject resistances in the undefined areas between
the must-accept and must-reject ranges. In particular, the
PSE must reject standard computer network ports, many
of which have 150Ω common-mode termination resistors
that will be damaged if power is applied to them (the black
region at the left of Figure 11).
RESISTANCE 0Ω
PD
10k
20k
150Ω (NIC)
PSE
15k
30k
23.75k
26.25k
19k
26.5k
ing currents are measured and subtracted. Both methods
must report valid resistances for the port to report a valid
detection. PD signature resistances between 17k and 29k
(typically) are detected as valid and reported as Detect
Good in the corresponding Port Status register. Values
outside this range, including open and short circuits, are
also reported. If the port measures less than 1V at the
first forced-current test, the detection cycle will abort and
Short Circuit will be reported. Table 3 shows the possible
detection results.
Table 3. Detection Status
MEASURED PD SIGNATURE
DETECTION RESULT
Incomplete or Not Yet Tested
Detect Status Unknown
< 2.4k
Short Circuit
Capacitance > 2.7µF
CPD too High
2.4k < RPD < 17k
RSIG too Low
17k < RPD < 29k
Detect Good
> 29k
RSIG too High
> 50k
Open Circuit
Voltage > 10V
Port Voltage Outside Detect Range
33k
429071 F11
Figure 11. IEEE 802.3af Signature Resistance Ranges
4-Point Detection
The LTC4290/LTC4271 uses a 4-point detection method to
discover PDs. False-positive detections are minimized by
checking for signature resistance with both forced-current
and forced-voltage measurements.
Initially, two test currents are forced onto the port (via the
OUTn pin) and the resulting voltages are measured. The
detection circuitry subtracts the two V-I points to determine
the resistive slope while removing offset caused by series
diodes or leakage at the port (see Figure 12). If the forcedcurrent detection yields a valid signature resistance, two
test voltages are then forced onto the port and the result-
CURRENT (µA)
275
25kΩ SLOPE
165
VALID PD
0V-2V
OFFSET
FIRST
DETECTION
POINT
SECOND
DETECTION
POINT
VOLTAGE
429071 F12
Figure 12. PD Detection
429071f
19
LTC4290/LTC4271
APPLICATIONS INFORMATION
More on Operating Modes
Detection of Legacy PDs
The port’s operating mode determines when the LTC4290/
LTC4271 runs a detection cycle. In manual mode, the port
will idle until the host orders a detect cycle. It will then
run detection, report the results, and return to idle to wait
for another command.
Proprietary PDs that predate the original IEEE 802.3af standard are commonly referred to today as legacy devices. One
type of legacy PD uses a large common mode capacitance
(>10μF) as the detection signature. Note that PDs in this
range of capacitance are defined as invalid, so a PSE that
detects legacy PDs is technically noncompliant with the
IEEE spec. The LTC4290/LTC4271 can be configured to
detect this type of legacy PD. Legacy detection is disabled
by default, but can be manually enabled on a per-port basis.
When enabled, the port will report Detect Good when it
sees either a valid IEEE PD or a high-capacitance legacy
PD. With legacy mode disabled, only valid IEEE PDs will
be recognized.
In semi-auto mode, the LTC4290/LTC4271 autonomously
polls a port for PDs, but it will not apply power until commanded to do so by the host. The Port Status register is
updated at the end of each detection cycle.
If a valid signature resistance is detected and classification
is enabled, the port will classify the PD and report that
result as well. The port will then wait for at least 100ms (or
2 seconds if midspan mode is enabled), and will repeat the
detection cycle to ensure that the data in the Port Status
register is up-to-date.
If the port is in semi-auto mode and high power operation is enabled, the port will not turn on in response to
a power-on command unless the current detect result is
detect good. Any other detect result will generate a tSTART
fault if a power-on command is received. In high power
mode the port must be placed in manual mode to force a
port on regardless of detect outcome.
Behavior in AUTO pin mode is similar to semi-auto; however,
after detect good is reported and the port is classified (if
classification is enabled), it is automatically powered on
without further intervention. In standalone (AUTO pin)
mode, the ICUT and ILIM thresholds are automatically set;
see the Reset and the AUTO/MID Pins section for more
information.
The signature detection circuitry is disabled when the port
is initially powered up with the AUTO pin low, in shutdown
mode, or when the corresponding Detect Enable bit is
cleared.
CLASSIFICATION
802.3af Classification
A PD may optionally present a classification signature to
the PSE to indicate the maximum power it will draw while
operating. The IEEE specification defines this signature
as a constant current draw when the PSE port voltage is
in the VCLASS range (between 15.5V and 20.5V), with the
current level indicating one of 5 possible PD classes. Figure
13 shows a typical PD load line, starting with the slope of
the 25k signature resistor below 10V, then transitioning to
the classification signature current (in this case, Class 3)
in the VCLASS range. Table 4 shows the possible classification values.
Table 4. 802.3af and 802.3at Classification Values
CLASS
RESULT
Class 0
No Class Signature Present; Treat Like Class 3
Class 1
3W
Class 2
7W
Class 3
13W
Class 4
25.5W (Type 2)
429071f
20
LTC4290/LTC4271
APPLICATIONS INFORMATION
If classification is enabled, the port will classify the PD
immediately after a successful detection cycle in semi-auto
or AUTO pin modes, or when commanded to in manual
mode. It measures the PD classification signature by applying 18V for 12ms (both values typical) to the port via
the OUTn pin and measuring the resulting current; it then
reports the discovered class in the Port Status register.
If the LTC4290/LTC4271 is in AUTO pin mode, it will additionally use the classification result to set the ICUT and
ILIM thresholds. See the Reset and the AUTO/MID Pin
section for more information.
The classification circuitry is disabled when the port is
initially powered up with the AUTO pin low, in shutdown
mode, or when the corresponding Class Enable bit is
cleared.
60
PSE LOAD LINE
OVER
CURRENT
50
CURRENT (mA)
48mA
40
CLASS 4
30
CLASS 3
23mA
20
TYPICAL
CLASS 3
PD LOAD
LINE
10
0
33mA
0
5
CLASS 2
CLASS 1
CLASS 0
10
15
VOLTAGE (VCLASS)
14.5mA
6.5mA
The second 802.3at classification method, known as
2-event classification or ping-pong, is supported by
the LTC4290/LTC4271. A Type 2 PD that is requesting
more than 13W will indicate Class 4 during normal
802.3af classification. If the LTC4290/LTC4271 sees
Class 4, it forces the port to a specified lower voltage
(called the mark voltage, typically 9V), pauses briefly, and
then re-runs classification to verify the Class 4 reading
(Figure 1). It also sets a bit in the High Power Status register
to indicate that it ran the second classification cycle. The
second cycle alerts the PD that it is connected to a Type
2 PSE which can supply Type 2 power levels.
2-event ping-pong classification is enabled by setting a bit
in the port’s High Power Mode register. Note that a pingpong enabled port only runs the second classification cycle
when it detects a Class 4 device; if the first cycle returns
Class 0 to 3, the port determines it is connected to a Type 1
PD and does not run the second classification cycle.
Invalid Type 2 Class Combinations
25
20
path. LLDP classification requires the PSE to power the
PD as a standard 802.3af (Type 1) device. It then waits for
the host to perform LLDP communication with the PD and
update the PSE port data. The LTC4290/LTC4271 supports
changing the ILIM and ICUT levels on the fly, allowing the
host to complete LLDP classification.
429071 F13
Figure 13. PD Classification
802.3at 2-Event Classification
The 802.3at specification defines two methods of classifying a Type 2 PD. LTC4290/LTC4271 parts support 802.3at
2-event classification.
One method adds extra fields to the Ethernet LLDP data
protocol; although the LTC4290/LTC4271 is compatible
with this classification method, it cannot perform classification directly since it doesn’t have access to the data
The 802.3at specification defines a Type 2 PD class signature as two consecutive Class 4 results; a Class 4 followed
by a Class 0-3 is not a valid signature. In AUTO pin mode,
the LTC4290/LTC4271 will power a detected PD regardless
of the classification results, with one exception: if the PD
presents an invalid Type 2 signature (Class 4 followed by
Class 0 to 3), the LTC4290/LTC4271 will not provide power
and will restart the detection process. To aid in diagnosis,
the Port Status register will always report the results of the
last class pulse, so an invalid Class 4–Class 2 combination
would report a second class pulse was run in the High
Power Status register (which implies that the first cycle
found class 4), and Class 2 in the Port Status register.
429071f
21
LTC4290/LTC4271
APPLICATIONS INFORMATION
POWER CONTROL
The primary function of the LTC4290/LTC4271 is to control the delivery of power to the PSE port. It does this by
controlling the gate drive voltage of an external power
MOSFET while monitoring the current via an external sense
resistor and the output voltage at the OUT pin. This circuitry
serves to couple the raw VEE input supply to the port in
a controlled manner that satisfies the PDs power needs
while minimizing both power dissipation in the MOSFET
and disturbances on the VEE backplane.
Inrush Control
Once the command has been given to turn on a port, the
LTC4290/LTC4271 ramps up the GATE pin of that port’s
external MOSFET in a controlled manner. Under normal
power-up circumstances, the MOSFET gate will rise until
the port current reaches the inrush current limit level
(typically 425mA), at which point the GATE pin will be
servoed to maintain the specified IINRUSH current. During
this inrush period, a timer (tSTART) runs. When output
charging is complete, the port current will fall and the GATE
pin will be allowed to continue rising to fully enhance the
MOSFET and minimize its on-resistance. The final VGS is
nominally 12V. The inrush period is maintained until the
tSTART timer expires. At this time if the inrush current limit
level is still exceeded, the port will be turned back off and
a tSTART fault reported.
Current Limit
Each LTC4290/LTC4271 port includes two current limiting
thresholds (ICUT and ILIM), each with a corresponding
timer (tCUT and tLIM). Setting the ICUT and ILIM thresholds
depends on several factors: the class of the PD, the voltage of the main supply (VEE), the type of PSE (Type 1 or
Type 2), the sense resistor (0.5Ω or 0.25Ω), the SOA of
the MOSFET, and whether or not the system is required
to enforce class current levels.
Per the IEEE specification, the LTC4290/LTC4271 will allow the port current to exceed ICUT for a limited period of
time before removing power from the port, whereas it will
actively control the MOSFET gate drive to keep the port
current below ILIM. The port does not take any action to
limit the current when only the ICUT threshold is exceeded,
but does start the tCUT timer. If the current drops below
the ICUT current threshold before its timer expires, the
tCUT timer counts back down, but at 1/16 the rate that it
counts up. If the tCUT timer reaches 60ms (typical) the
port is turned off and the port tCUT fault is set. This allows
the current limit circuitry to tolerate intermittent overload
signals with duty cycles below about 6%; longer duty cycle
overloads will turn the port off.
The ILIM current limiting circuit is always enabled and actively limiting port current. The tLIM timer is enabled only
when the tLIM Enable bit is set. This allows tLIM to be set
to a shorter value than tCUT to provide more aggressive
MOSFET protection and turn off a port before MOSFET
damage can occur. The tLIM timer starts when the ILIM
threshold is exceeded. When the tLIM timer reaches 12ms
(typical) the port is turned off and the port tLIM fault is
set. When the tLIM Enable bit is disabled tLIM behaviors
are tracked by the tCUT timer, which counts up during both
ILIM and ICUT events.
ICUT is typically set to a lower value than ILIM to allow the
port to tolerate minor faults without current limiting.
Per the IEEE specification, the LTC4290/LTC4271 will automatically set ILIM to 425mA (shown in bold in Table 5)
during inrush at port turn-on, and then switch to the
programmed ILIM setting once inrush has completed. To
maintain IEEE compliance, ILIM should be kept at 425mA
for all Type 1 PDs, and 850mA if a Type 2 PD is detected.
ILIM is automatically reset to 425mA when a port turns off.
429071f
22
LTC4290/LTC4271
APPLICATIONS INFORMATION
Table 5. Example Current Limit Settings
INTERNAL REGISTER SETTING (hex)
ILIM (mA)
RSENSE = 0.5Ω
53
88
106
08
159
89
213
80
266
8A
319
09
372
8B
425
00
478
8E
531
92
584
CB
RSENSE = 0.25Ω
88
08
89
80
8A
638
10
90
744
D2
9A
850
40
C0
956
4A
CA
1063
50
D0
1169
5A
DA
1275
60
E0
1488
52
49
1700
40
1913
4A
2125
50
2338
5A
2550
60
2975
52
ILIM Foldback
The LTC4290/LTC4271 features a two-stage foldback circuit
that reduces the port current if the port voltage falls below
the normal operating voltage. This keeps MOSFET power
dissipation at safe levels for typical 802.3af MOSFETs,
even at extended 802.3at power levels. Current limit and
foldback behavior are programmable on a per-port basis.
Table 5 gives examples of recommended ILIM register
settings.
The LTC4290/LTC4271 will support current levels well
beyond the maximum values in the 802.3at specification.
The shaded areas in Table 5 indicate settings that may
require a larger external MOSFET, additional heat sinking,
or setting tLIM Enable.
MOSFET Fault Detection
LTC4290/LTC4271 PSE ports are designed to tolerate
significant levels of abuse, but in extreme cases it is possible for the external MOSFET to be damaged. A failed
MOSFET may short source to drain, which will make the
port appear to be on when it should be off; this condition
may also cause the sense resistor to fuse open, turning
off the port but causing the LTC4290 SENSE pin to rise
to an abnormally high voltage. A failed MOSFET may also
short from gate to drain, causing the LTC4290 GATE pin
to rise to an abnormally high voltage. The LTC4290 OUT,
SENSE and GATE pins are designed to tolerate up to 80V
faults without damage.
If the LTC4290/LTC4271 sees any of these conditions for
more than 180μs, it disables all port functionality, reduces
the gate drive pull-down current for the port and reports
a FET Bad fault. This is typically a permanent fault, but
the host can attempt to recover by resetting the port, or
by resetting the entire chip if a port reset fails to clear the
fault. If the MOSFET is in fact bad, the fault will quickly
return, and the port will disable itself again. The remaining
ports of the LTC4290/LTC4271 are unaffected.
An open or missing MOSFET will not trigger a FET Bad
fault, but will cause a tSTART fault if the LTC4290/LTC4271
attempts to turn on the port.
Port Current Readback
The LTC4290/LTC4271 measures the current at each port
with an internal A/D converter. Port data is only valid when
the port power is on and reads zero at all other times. The
converter has two modes:
• 100ms mode: Samples are taken continuously and the
measured value is updated every 100ms
• 1s mode: Samples are taken continuously; a moving 1
second average is updated every 100ms
429071f
23
LTC4290/LTC4271
APPLICATIONS INFORMATION
Port Current Policing
Masked Shutdown
The LTC4290/LTC4271 can augment tCUT current monitoring with a policing function to track the one second current
averages. A port violating the user-specified Port Police
Threshold will be shut off with both a tCUT and Police event
recorded. A port current Police event can be differentiated
from a port tCUT violation by reading both events bits; both
bits are set for a Police violation while only the tCUT bit is
set for tCUT timer violations.
The LTC4290/LTC4271 provides a low latency port shedding feature to quickly reduce the system load when
required. By allowing a pre-determined set of ports to
be turned off, the current on an overloaded main power
supply can be reduced rapidly while keeping high priority
devices powered. Each port can be configured to high or
low priority; all low-priority ports will shut down within
6.5μs after the MSD pin is pulled low, high priority ports
will remain powered. If a port is turned off via MSD, the
corresponding Detection and Classification Enable bits are
cleared, so the port will remain off until the host explicitly
re-enables detection.
Port Voltage Readback
The LTC4290/LTC4271 measures the output voltage at each
port with an internal A/D converter. Port data is only valid
when the port power is on and reads zero at all other times.
Disconnect
The LTC4290/LTC4271 monitors powered ports to ensure
the PD continues to draw the minimum specified current. A
disconnect timer counts up whenever port current is below
7.5mA (typ), indicating that the PD has been disconnected.
If the tDIS timer expires, the port will be turned off and the
disconnect bit in the fault event register will be set. If the
current returns before the tDIS timer runs out, the timer
resets. As long as the PD exceeds the minimum current
level more often than tDIS, it will remain powered.
Although not recommended, the DC disconnect feature
can be disabled by clearing the corresponding enable bits.
Note that this defeats the protection mechanisms built
into the IEEE specification, since a powered port will stay
powered after the PD is removed. If the still-powered port
is subsequently connected to a non-PoE data device, the
device may be damaged.
The LTC4290/LTC4271 does not include AC disconnect
circuitry, but includes AC Disconnect Enable bits to maintain compatibility with the LTC4259A. If the AC Disconnect
Enable bits are set, DC disconnect will be used.
In the LTC4290/LTC4271 chipset the active level of MSD
is register configurable as active high or low. The default
is LTC4266-compatible active low behavior.
VEE Readback
The LTC4290/LTC4271 measures the VEE voltage with an
internal 12-bit A/D converter.
General Purpose IO
Two sets of general purpose IO pins are available in the
LTC4290/LTC4271 chipset. The first set of general purpose
IO are GP1 and GP0. These fully bidirectional IO are 3.3V
CMOS IO on the LTC4271 chip.
The second set of general purpose IO pins are XIO1 and
XIO0. These fully bidirectional IO are 4.3V CMOS IO on
the LTC4290 chip.
Code Download
LTC4271 firmware is field-upgradable by downloading
and executing RAM images. RAM images are volatile
and must be re-downloaded after each VDD power cycle,
but will remain valid during reset and VEE power events.
Contact Linear Technology for code download procedures
and RAM images.
429071f
24
LTC4290/LTC4271
APPLICATIONS INFORMATION
SERIAL DIGITAL INTERFACE
I2C ADDRESS
The LTC4290/LTC4271 requires both the VDD and VEE supply rails to be present for the serial interface to function.
0100001
AD0
AD1
AD2
AD3
AD6
SCL
SDAIN
SDAOUT
QUAD 0
0100000 3.3V
0100111
QUAD 1
QUAD 0
AD0
AD1
AD2
AD3
AD6
LTC4271
QUAD 1
LTC4271
Overview
The LTC4290/LTC4271 communicates with the host using a standard SMBus/I2C 2-wire interface. The LTC4290/
LTC4271 is a slave-only device, and communicates with
the host master using the standard SMBus protocols.
Interrupts are signaled to the host via the INT pin. The
Timing Diagrams (Figures 5 through 9) show typical
communication waveforms and their timing relationships.
More information about the SMBus data protocols can be
found at www.smbus.org.
I2C ADDRESS
0101000
SCL
SDAIN
SDAOUT
429071 F14
SCL
SDA
Figure 14. Example I2C Bus Addressing
Bus Addressing
The LTC4290/LTC4271’s primary 7-bit serial bus address
is A610A3A2A1A0b, with bit 6 controlled by AD6 and the
lower four bits set by the AD3-AD0 pins; this allows up to
16 LTC4290/LTC4271s, on a single bus. Sixteen LTC4290/
LTC4271 are equivalent to 32 quad PSEs or 128 ports. All
LTC4290/LTC4271s also respond to the broadcast address
0110000b, allowing the host to write the same command
(typically configuration commands) to multiple LTC4290/
LTC4271s in a single transaction. If the LTC4290/LTC4271
is asserting the INT pin, it will also respond to the alert
response address (0001100b) per the SMBus specification.
Interrupts and SMBAlert
Each LTC4290/LTC4271 is logically composed of two quads
of four ports each. Each quad occupies separate, contiguous I2C addresses. The AD6, AD3-0 pins set the address
of the base quad while the second quad is consecutively
numbered. I2C addresses outside of the x10xxxxb range
are considered illegal and will not respond. Each internal
quad is independent of the other quad, with the exception
of writes to the Chip Reset, MSD Inversion and General
Purpose Input Output registers. These registers are global
in nature and will affect all quads.
For information on serial bus usage and device configuration and status, refer to the LTC4271 Software Programming documentation.
Most LTC4290/LTC4271 port events can be configured
to trigger an interrupt, asserting the INT pin and alerting
the host to the event. This removes the need for the host
to poll the LTC4290/LTC4271, minimizing serial bus traffic and conserving host CPU cycles. Multiple LTC4290/
LTC4271s can share a common INT line, with the host
using the SMBAlert protocol (ARA) to determine which
LTC4290/LTC4271 caused an interrupt.
Register Description
ISOLATION REQUIREMENTS
IEEE 802.3 Ethernet specifications require that network
segments (including PoE circuitry) be electrically isolated
from the chassis ground of each network interface device.
However, network segments are not required to be isolated
from each other, provided that the segments are connected
to devices residing within a single building on a single
power distribution system.
429071f
25
LTC4290/LTC4271
APPLICATIONS INFORMATION
For simple devices such as small PoE switches, the isolation requirement can be met by using an isolated main
power supply for the entire device. This strategy can be
used if the device has no electrically conducting ports
other than twisted-pair Ethernet. In this case, the SDAIN
and SDAOUT pins can be tied together and will act as a
standard I2C/SMBus SDA pin.
If the device is part of a larger system, contains additional
external non-Ethernet ports, or must be referenced to
protective ground for some other reason, the Power over
Ethernet subsystem must be electrically isolated from the
rest of the system.
The LTC4290/LTC4271 chipset simplifies PSE isolation by
allowing the LTC4271 chip to reside on the non-isolated
side. There it can receive power from the main logic supply and connect directly to the I2C/SMBus bus. Isolation
between the LTC4271 and LTC4290 is implemented using
a proprietary transformer-based communication protocol.
Additional details are provided in the Serial Bus Isolation
section of this data sheet.
EXTERNAL COMPONENT SELECTION
Power Supplies and Bypassing
The LTC4290/LTC4271 requires two supply voltages to
operate. VDD requires 3.3V (nominally) relative to DGND.
VEE requires a negative voltage of between –45V and
–57V for Type 1 PSEs or –51V to –57V for Type 2 PSEs,
relative to AGND.
Digital Power Supply
VDD provides digital power for the LTC4271 processor,
and draws a maximum of 15mA. A ceramic decoupling
cap of at least 0.1μF should be placed from VDD to DGND,
as close as practical to each LTC4271 chip. A 1.8V core
voltage supply is generated internally and requires a 1µF
ceramic decoupling cap between the CAP1 pin and DGND.
In the LTC4290/LTC4271, VDD should be delivered by the
host controller’s non-isolated 3.3V supply. To maintain
required isolation AGND and DGND must not be connected in any way.
Main PoE Power Supply
VEE is the main isolated PoE supply that provides power
to the PDs. Because it supplies a relatively large amount
of power and is subject to significant current transients,
it requires more design care than a simple logic supply.
For minimum IR loss and best system efficiency, set VEE
near maximum amplitude (57V), leaving enough margin
to account for transient over or undershoot, temperature
drift, and the line regulation specifications of the particular
power supply used.
Bypass capacitance between AGND and VEE is very important for reliable operation. If a short circuit occurs at
one of the output ports it can take as long as 1μs for the
LTC4290 to begin regulating the current. During this time
the current is limited only by the small impedances in the
circuit and a high current spike typically occurs, causing a
voltage transient on the VEE supply and possibly causing
the LTC4290/LTC4271 to reset due to a UVLO fault. A 1μF,
100V X7R capacitor placed near the VEE pin along with an
electrolytic bulk capacitor of at least 47µF is recommended
to minimize spurious resets.
Serial Bus Isolation
The LTC4290/LTC4271 chipset uses transformers to isolate
the LTC4271 from the LTC4290. In this case, the SDAIN
and SDAOUT pins can be shorted to each other and tied
directly to the I2C/SMBus bus. The transformers should
be 10BASE-T or 10/100BASE-T with a 1:1 turns ratio. It
is important that the selected transformers do not have
common-mode chokes. These transformers typically
provide 1500V of isolation between the LTC4271 and the
LTC4290. For proper operation strict layout guidelines
must be met.
429071f
26
LTC4290/LTC4271
APPLICATIONS INFORMATION
3.3V
NO ISOLATION
REQUIRED ON
I2C INTERFACE
0.1µF
XIO0
VDD33
GP0
GP1
100Ω
3.3V
•
•
100Ω
SCL
SDAIN
SDAOUT
AD0
AD1
AD2
AD3
AD6
CPA
CPD
MID
RESET
MSD
AUTO
INT
0.25Ω
SENSEn
CNA
•
•
100Ω
LTC4290
100Ω
0.22µF
100V
100Ω
S1B
GATE1
CAP2 VEE
2nF, 2kV
S1B
PORT1
DNA
T2
–54V
OUT1
–54V
CAP1
1µF
S1B
DPA
3.3V
DGND
PORTn
GATEn
–54V
T1
100Ω
S1B
100Ω
DPD
DND
0.22µF
100V
OUTn
100Ω
CND
LTC4271
XIO1
VSSK
AGND SENSE1
0.1µF
1µF
–54V
0.25Ω
>47µF
SYSTEM
BULK CAP
–54V
+
–54V
429071 F15
Figure 15. LTC4290/LTC4271 Proprietary Isolation
External MOSFET
Careful selection of the power MOSFET is critical to system
reliability. LTC recommends either Fairchild IRFM120A,
FDT3612, FDMC3612 or Philips PHT6NQ10T for their
proven reliability in Type 1 and Type 2 PSE applications.
SOA curves are not a reliable specification for MOSFET
selection. Contact LTC Applications before using a MOSFET
other than one of these recommended parts.
Sense Resistor
The LTC4290/LTC4271 is designed to use 0.25Ω current
sense resistors to reduce power dissipation. Four commonly available 1Ω resistors (sized according to power
dissipation) can be used in parallel in place of a single
0.25Ω resistor. In order to meet the ICUT and ILIM accuracy
required by the IEEE specification, the sense resistors
should have ±1% tolerance or better, and no more than
±200ppm/°C temperature coefficient. In addition, the sense
resistors must meet strict layout guidelines.
Port Output Cap
Each port requires a 0.22μF cap across its outputs to keep
the LTC4290 stable while in current limit during startup or
overload. Common ceramic capacitors often have significant voltage coefficients; this means the capacitance is
reduced as the applied voltage increases. To minimize this
problem, X7R ceramic capacitors rated for at least 100V
are recommended and must be located close to the PSE.
429071f
27
LTC4290/LTC4271
APPLICATIONS INFORMATION
ESD/Cable Discharge Protection
LAYOUT GUIDELINES
Ethernet ports can be subject to significant ESD events
when long data cables, each potentially charged to thousands of volts, are plugged into the low impedance of the
RJ45 jack. To protect against damage, each port requires a
pair of clamp diodes; one to AGND and one to VEE (Figure
16). An additional surge suppressor is required for each
LTC4290 chip from VEE to AGND. The diodes at the ports
steer harmful surges into the supply rails, where they are
absorbed by the surge suppressor and the VEE bypass
capacitance. The surge suppressor has the additional
benefit of protecting the LTC4290 from transients on the
VEE supply.
Strict adherence to board layout, parts placement and
routing guidelines is critical for optimal current reading accuracy, IEEE compliance, system robustness, and
thermal dissipation. Refer to the DC1842A Demo Board
as a layout reference. Contact LTC Applications to obtain
a full set of layout guidelines, example layouts and BOMs.
S1B diodes work well as port clamp diodes, and an
SMAJ58A or equivalent is recommended for the VEE surge
suppressor.
0.22µF
AGND
S1B
PORTn
OUTn
SMAJ58A
LTC4290
0.1µF
GATEn
S1B
SENSEn
VEE
–54V
0.25Ω
429071 F16
Figure 16. LTC4290 Discharge Protection
429071f
28
1µF
DND
CND
DPD
CPD
0.1µF
DGND CAP1
VDD33
GP0
GP1
MID
RESET
MSD
AUTO
INT
LTC4271
SCL
SDAIN
SDAOUT
AD0
AD1
AD2
AD3
AD6
3.3V
100Ω
3.3V
100Ω
100Ω
3.3V
100Ω
1µF
T3
T2
•
•
2nF 2000V
SMAJ58A
•
•
1µF
–54V
–54V
OUT1
GATE1
SENSE1
–54V
+
(NETWORK
PHYSICAL
LAYER
CHIP)
•
•
•
–54V
ISOLATED
ISOLATED
GND
•
PHY
RS
S1B
0.22µF
100V
X7R
T1
S1B
•
•
•
•
0.25Ω, 1% FDMC3612
0.1µF
>47µF
SYSTEM
BULK CAP
1µF
100V
X7R
DNA
AGND
CAP2 VEE VSSK
CNA
DPA
OUT8
GATE8
SENSE8
XIO1
LTC4290
XIO0
CPA
•
•
•
•
Complete 8-Port PSE
0.01µF
200V
75Ω
0.01µF
200V
75Ω
429071 TA02
RJ45
0.01µF
CONNECTOR
200V
1
2
0.01µF
3
200V
75Ω
4
5
6
0.01µF
200V 7
8
0.01µF
200V
75Ω
2
1
2
3
4
5
6
7
8
RJ45
CONNECTOR
1
7
8
LTC4290/LTC4271
TYPICAL APPLICATION
429071f
29
LTC4290/LTC4271
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 0.05
4.50 0.05
2.45 0.05
3.10 0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 0.10
(4 SIDES)
R = 0.115
TYP
0.75 0.05
PIN 1
TOP MARK
(NOTE 6)
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 x 45º CHAMFER
23 24
0.40 0.10
1
2
2.45 0.10
(4-SIDES)
(UF24) QFN 0105
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION
(WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
0.25 0.05
0.50 BSC
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
429071f
30
LTC4290/LTC4271
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
0.70 0.05
6.50 0.05
5.10 0.05
4.42 0.05
4.50 0.05
(4 SIDES)
4.42 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 0.10
(4 SIDES)
0.75 0.05
R = 0.10
TYP
R = 0.115
TYP
39 40
0.40 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
4.50 REF
(4-SIDES)
4.42 0.10
2
PIN 1 NOTCH
R = 0.45 OR
0.35 x 45º
CHAMFER
4.42 0.10
(UJ40) QFN REV Ø 0406
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
429071f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC4290/LTC4271
TYPICAL APPLICATION
Complete 8-Port PSE
3.3V 0.1µF
1µF
7
VDD33
GP0
GP1
MID
RESET
MSD
AUTO
INT
LTC4271
SCL
SDAIN
SDAOUT
AD0
AD1
AD2
AD3
AD6
XIO0
CPA
CPD
100Ω
3.3V
•
•
100Ω
100Ω
3.3V
•
LTC4290
CNA
DPA
•
100Ω
RJ45
CONNECTOR
1µF
100V
X7R
SMAJ58A
S1B
•
0.1µF
T1
•
>47µF
SYSTEM
BULK CAP
+
•
(NETWORK
PHYSICAL
LAYER
CHIP)
•
–54V
•
0.01µF
200V
75Ω
•
•
•
ISOLATED
GND
PHY
•
–54V
ISOLATED
2nF 2000V
•
•
1µF
RS
DNA
AGND
CAP2 VEE VSSK
2
0.22µF
100V
X7R
0.25Ω, 1% FDMC3612
1µF
DGND CAP1
S1B
OUT1
GATE1
SENSE1
–54V
T3
DND
1
OUT8
GATE8
SENSE8
–54V
T2
CND
DPD
XIO1
8
0.01µF
200V
75Ω
RJ45
0.01µF
CONNECTOR
200V
1
2
0.01µF
3
200V
75Ω
4
5
6
0.01µF
200V 7
8
1
2
3
4
5
6
7
8
0.01µF
200V
75Ω
•
429071 TA03
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PART NUMBER
DESCRIPTION
COMMENTS
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500kHz, Aux Support
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Single IEEE 802.3at PoE PSE Controller
With Programmable ICUT/ILIM, 2-Event Classification, and Port Current and Voltage Monitoring
LTC4278
IEEE 802.3af PD Interface With Integrated
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429071f
32 Linear Technology Corporation
LT 0812 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2012