Hitachi HM628128DLTS-7UL 1 m sram (128-kword x 8-bit) Datasheet

HM628128D Series
1 M SRAM (128-kword × 8-bit)
ADE-203-996 (Z)
Preliminary, Rev. 0.0
Jan. 20, 1999
Description
The Hitachi HM628128D Series is 1-Mbit static RAM organized 131,072-kword × 8-bit. HM628128D
Series has realized higher density, higher performance and low power consumption by employing HiCMOS process technology. The HM628128D Series offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It has package variations of standard 32-pin plastic DIP,
standard 32-pin plastic SOP and standard 32-pin plastic TSOPI.
Features
• Single 5 V supply: 5 V ± 10%
• Access time: 55 ns/70 ns (max)
• Power dissipation
 Active: 30 mW/MHz (typ)
 Standby: 10 µW (typ)
• Completely static memory.
 No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
 Three state output
• Directly TTL compatible all inputs
• Battery backup operation
 2 chip selection for battery backup
HM628128D Series
Ordering Information
Type No.
Access time
Package
HM628128DLP-5
HM628128DLP-7
55 ns
70 ns
600-mil 32-pin plastic DIP (DP-32)
HM628128DLP-5SL
HM628128DLP-7SL
55 ns
70 ns
HM628128DLP-5UL
HM628128DLP-7UL
55 ns
70 ns
HM628128DLFP-5
HM628128DLFP-7
55 ns
70 ns
HM628128DLFP-5SL
HM628128DLFP-7SL
55 ns
70 ns
HM628128DLFP-5UL
HM628128DLFP-7UL
55 ns
70 ns
HM628128DLTS-5
HM628128DLTS-7
55 ns
70 ns
HM628128DLTS-5SL
HM628128DLTS-7SL
55 ns
70 ns
HM628128DLTS-5UL
HM628128DLTS-7UL
55 ns
70 ns
HM628128DLT-5
HM628128DLT-7
55 ns
70 ns
HM628128DLT-5SL
HM628128DLT-7SL
55 ns
70 ns
HM628128DLT-5UL
HM628128DLT-7UL
55 ns
70 ns
HM628128DLR-5
HM628128DLR-7
55 ns
70 ns
HM628128DLR-5SL
HM628128DLR-7SL
55 ns
70 ns
HM628128DLR-5UL
HM628128DLR-7UL
55 ns
70 ns
2
525-mil 32-pin plastic SOP (FP-32D)
8 × 13.4 mm 32-pin plastic TSOP I (TFP-32DC)
Normal-bend type 8 × 20 mm 32-pin plastic TSOP I (TFP-32D)
Reverse-bend type 8 × 20 mm 32-pin plastic TSOP I (TFP-32DR)
HM628128D Series
Pin Arrangement
32-pin DIP/SOP
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-pin TSOP (Normal Type TSOP)
VCC
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
(Top view)
A11
A9
A8
A13
WE
CS2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
A3
(Top view)
32-pin TSOP (Reverse Type TSOP)
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
WE
CS2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
(Top View)
Pin Description
Pin name
Function
A0 to A16
Address input
I/O0 to I/O7
Data input/output
CS1
Chip select 1
CS2
Chip select 2
WE
Write enable
OE
Output enable
VCC
Power supply
VSS
Ground
NC
No connection
3
HM628128D Series
Block Diagram
LSB
A12
VCC
A7
VSS
A6
A5
A4
A3
Row
decoder
•
•
•
•
•
Memory matrix
512 x 2,048
A2
A1
A0
A10
MSB
I/O0
•
•
Column I/O
•
•
Input
data
control
Column decoder
I/O7
LSB
A14 A16 A15 A13 A8 A9 A11
•
•
CS1
CS2
Timing pulse generator
WE
OE
4
Read/Write control
MSB
HM628128D Series
Operation Table
CS1
CS2
WE
OE
I/O
Operation
H
H
×
×
High-Z
Standby
L
L
×
×
High-Z
Standby
L
L
×
×
High-Z
Standby
L
H
H
L
Dout
Read
L
H
L
H
Din
Write
L
H
L
L
Din
Write
L
H
H
H
High-Z
Output disable
Note: H: V IH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Power supply voltage relative to V SS
VCC
–0.5 to +7.0
1
V
2
Terminal voltage on any pin relative to V SS
VT
–0.5* to V CC + 0.3*
V
Power dissipation
PT
1.0
W
Storage temperature range
Tstg
–55 to +125
°C
Storage temperature range under bias
Tbias
–20 to +85
°C
Notes: 1. VT min: –1.5 V for pulse half-width ≤ 30 ns
2. Maximum voltage is +7.0 V
DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
4.5
5.0
5.5
V
VSS
0
0
0
V
Input high voltage
VIH
2.2
—
VCC + 0.3
V
Input low voltage
VIL
–0.3
—
0.8
V
Ambient temperature range
Ta
–20
—
+70
°C
Note:
Note
1
1. VIL min: –1.5 V for pulse half-width ≤ 30 ns
5
HM628128D Series
DC Characteristics
Parameter
Symbol
Min
Typ*1
Max
Unit
Test conditions
Input leakage current
|ILI|
—
—
1
µA
Vin = VSS to V CC
Output leakage current
|ILO |
—
—
1
µA
CS1 = VIH or CS2 = VIL or
OE = VIH or WE = VIL,
V I/O = VSS to V CC
Operating current
I CC
—
—
15
mA
CS1 = VIL, CS2 = VIH,
others = VIH/VIL, I I/O = 0 mA
Average operating current
I CC1
—
—
60
mA
Min cycle, duty = 100%
I I/O = 0 mA, CS1 = VIL, CS2
= VIH, Others = VIH/VIL
I CC2
—
6
20
mA
Cycle time = 1 µs,
duty = 100%,
I I/O = 0 mA, CS1 ≤ 0.2 V,
CS2 ≥ V CC – 0.2 V,
VIH ≥ V CC – 0.2 V,
VIL ≤ 0.2 V
I SB
—
—
2
mA
(1) CS1 = VIH, CS2 = VIH, or
(2) CS2 = VIL
I SB1*2
—
2
100
µA
0 V ≤ Vin
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS1 ≥ V CC – 0.2 V,
CS2 ≥ V CC – 0.2 V
I SB1*3
—
2
50
µA
4
—
1
20
µA
Standby current
I SB1*
Output high voltage
VOH
2.4
—
—
V
I OH = –1 mA
Output low voltage
VOL
—
—
0.4
V
I OL = 2.1 mA
Notes: 1.
2.
3.
4.
Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading, and not guaranteed.
This characteristics is guaranteed only for L version.
This characteristics is guaranteed only for L-SL version.
This characteristics is guaranteed only for L-UL version.
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter
Symbol
Typ
Max
Unit
Test conditions
Note
Input capacitance
Cin
—
8
pF
Vin = 0 V
1
Input/output capacitance
CI/O
—
10
pF
VI/O = 0 V
1
Note:
6
1. This parameter is sampled and not 100% tested.
HM628128D Series
AC Characteristics (Ta = –20 to +70°C, VCC = 5.0 V ± 10%, unless otherwise noted.)
Test Conditions
•
•
•
•
•
Input pulse levels: VIL = 0.8 V, VIH = 2.4 V
Input rise and fall time: 5 ns
Input timing reference levels: 1.5 V
Output timing reference level: 1.5 V
Output load: 1 TTL Gate+ CL (100 pF) (HM628128D-7)
1 TTL Gate+ CL (50 pF) (HM628128D-5)
(Including scope and jig)
Read Cycle
HM628128D
-5
-7
Parameter
Symbol
Min
Max
Min
Max
Unit
Read cycle time
t RC
55
—
70
—
ns
Address access time
t AA
—
55
—
70
ns
Chip select access time
t ACS1
—
55
—
70
ns
t ACS2
—
55
—
70
ns
Output enable to output valid
t OE
—
30
—
35
ns
Output hold from address change
t OH
10
—
10
—
ns
Chip selection to output in low-Z
t CLZ1
10
—
10
—
ns
2, 3
t CLZ2
10
—
10
—
ns
2, 3
Output enable to output in low-Z
t OLZ
5
—
5
—
ns
2, 3
Chip deselection to output in high-Z
t CHZ1
0
20
0
25
ns
1, 2, 3
t CHZ2
0
20
0
25
ns
1, 2, 3
t OHZ
0
20
0
25
ns
1, 2, 3
Output disable to output in high-Z
Notes
7
HM628128D Series
Write Cycle
HM628128D
-5
-7
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
t WC
55
—
70
—
ns
Address valid to end of write
t AW
50
—
60
—
ns
Chip selection to end of write
t CW
50
—
60
—
ns
5
Write pulse width
t WP
40
—
50
—
ns
4, 13
Address setup time
t AS
0
—
0
—
ns
6
Write recovery time
t WR
0
—
0
—
ns
7
Data to write time overlap
t DW
20
—
25
—
ns
Data hold from write time
t DH
0
—
0
—
ns
Output active from output in high-Z
t OW
5
—
5
—
ns
2
Output disable to output in high-Z
t OHZ
0
20
0
25
ns
1, 2, 8
WE to output in high-Z
t WHZ
0
20
0
25
ns
1, 2, 8
Notes: 1. t CHZ, tOHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, t HZ max is less than tLZ min both for a given
device and from device to device.
4. A write occurs during the overlap (tWP) of a low CS1, a high CS2, and a low WE. A write begins
at the later transition of CS1 going low, CS2 going high, or WE going low. A write ends at the
earlier transition of CS1 going high, CS2 going low, or WE going high. tWP is measured from the
beginning of write to the end of write.
5. t CW is measured from CS1 going low or CS2 going high to the end of write.
6. t AS is measured from the address valid to the beginning of write.
7. t WR is measured from the earlier of WE or CS1 going high or CS2 going low to the end of write
cycle.
8. During this period, I/O pins are in the output state; therefore, the input signals of the opposite
phase to the outputs must not be applied.
9. If the CS1 goes low or CS2 going high simultaneously with WE going low or after WE going low,
the output remain in a high impedance state.
10. Dout is the same phase of the write data of this write cycle.
11. Dout is the read data of next address.
12. If CS1 is low and CS2 high during this period, I/O pins are in the output state. Therefore, the
input signals of the opposite phase to the outputs must not be applied to them.
13. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of
data bus contention. t WP ≥ tDW min + tWHZ max
8
HM628128D Series
Timing Waveforms
Read Cycle (WE = VIH)
tRC
Address
Valid address
tAA
CS1
tACS1
tCLZ1
tCHZ1
CS2
tACS2
tCLZ2
tCHZ2
OE
tOE
tOLZ
Dout
High impedance
tOHZ
tOH
Valid data
9
HM628128D Series
Write Cycle (1) (OE Clock)
tWC
Valid address
Address
tAW
OE
tCW
CS1
tWR
*9
CS2
tWP
tAS
WE
tOHZ
High impedance
Dout
tDW
Din
10
tDH
Valid data
HM628128D Series
Write Cycle (2) (OE = VIL )
tWC
Address
Valid address
tCW
tWR
CS1
*9
CS2
tAW
tWP
WE
tOH
tAS
tOW
tWHZ
*10
Dout
*11
High impedance
tDW
tDH
*12
Din
Valid data
11
HM628128D Series
Low VCC Data Retention Characteristics (Ta = –20 to +70°C)
Parameter
Symbol
Min
Typ* 5
Max
Unit
Test conditions*4
VCC for data retention
VDR
2.0
—
—
V
Vin ≥ 0V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ V CC – 0.2 V
CS1 ≥ V CC – 0.2 V
Data retention current
I CCDR*1
—
1.0
50
µA
VCC = 3.0 V, Vin ≥ 0 V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ V CC – 0.2 V,
CS1 ≥ V CC – 0.2 V
I CCDR*2
—
1.0
15
µA
3
—
0.5
10
µA
—
—
ns
—
—
ns
I CCDR*
Chip deselect to data retention time
Operation recovery time
t CDR
tR
0
t RC*
6
See retention waveform
This characteristic is guaranteed only for L-version, 20 µA max. at Ta = –20 to +40°C.
This characteristic is guaranteed only for L-SL-version, 3 µA max. at Ta = –20 to +40°C.
This characteristic is guaranteed only for L-UL-version, 1 µA max. at Ta = –20 to +40°C.
CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state.
If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The
other input levels (address, WE, OE, I/O) can be in the high impedance state.
5. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
6. t RC = read cycle time.
Notes: 1.
2.
3.
4.
Low V CC Data Retention Timing Waveform (1) (CS1 Controlled)
tCDR
Data retention mode
VCC
4.5 V
2.2 V
VDR
CS1
0V
12
CS1 ≥ VCC – 0.2 V
tR
HM628128D Series
Low V CC Data Retention Timing Waveform (2) (CS2 Controlled)
tCDR
Data retention mode
tR
VCC
4.5 V
CS2
VDR
0.8 V
0 V ≤ CS2 ≤ 0.2 V
0V
13
HM628128D Series
Package Dimensions
HM628128DLP Series (DP-32)
Unit: mm
41.90
42.50 Max
17
13.4
13.7 Max
32
16
5.08 Max
1.20
2.30 Max
2.54 ± 0.25
0.48 ± 0.10
0.51 Min
2.54 Min
1
15.24
+ 0.11
0.25 – 0.05
0° – 15°
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
14
DP-32
—
Conforms
5.1 g
HM628128D Series
HM628128DLFP Series (FP-32D)
Unit: mm
20.45
20.95 Max
17
11.30
32
1
1.27
*0.40 ± 0.08
0.38 ± 0.06
0.10
0.15 M
*Dimension including the plating thickness
Base material dimension
0.12
0.15 +– 0.10
1.00 Max
*0.22 ± 0.05
0.20 ± 0.04
3.00 Max
16
14.14 ± 0.30
1.42
0° – 8°
0.80 ± 0.20
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-32D
Conforms
—
1.3 g
15
HM628128D Series
HM628128DLTS Series (TFP-32DC)
Unit: mm
8.00
8.20 Max
17
1
16
11.80
32
0.50
0.22 ± 0.08
0.20 ± 0.06
0.08 M
0.80
13.40 ± 0.30
0.43 Max
Dimension including the plating thickness
Base material dimension
16
0.50 ± 0.10
+0.07
0.13 –0.08
0.10
0.17 ± 0.05
0.15 ± 0.04
1.20 Max
0° – 5°
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TFP-32DC
—
—
0.23 g
HM628128D Series
HM628128DLT Series (TFP-32D)
8.00
8.20 Max
Unit: mm
17
1
16
0.50
18.40
32
0.22 ± 0.08
0.20 ± 0.06
0.80
0.08 M
20.00 ± 0.20
Dimension including the plating thickness
Base material dimension
0.13 ± 0.05
0.10
0° – 5°
0.17 ± 0.05
0.125 ± 0.04
1.20 Max
0.45 Max
0.50 ± 0.10
Hitachi Code
JEDEC Code
EIAJ Code
Weight (reference value)
TFP-32D
MO-142BD
SC-664
0.39 g
17
HM628128D Series
HM628128DLR Series (TFP-32DR)
8.00
8.20 Max
32
18.40
17
Unit: mm
1
1.20 Max
0.22 ± 0.08
0.08 M
0.20 ± 0.06
0.45 Max
0.10
Dimension including the plating thickness
Base material dimension
18
0.80
20.00 ± 0.20
0.13 ± 0.05
0.50
0.17 ± 0.05
0.125 ± 0.04
16
0° – 5° 0.50 ± 0.10
Hitachi Code
JEDEC Code
EIAJ Code
Weight (reference value)
TFP-32DR
MO-142BD
SC-664
0.39 g
HM628128D Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
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For further information write to:
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Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
19
HM628128D Series
Revision Record
Rev.
Date
Contents of Modification
0.0
Jan. 20, 1999
Initial issue
20
Drawn by
Approved by