TI OPA692 Triple, wideband, fixed gain video buffer amplifier with disable Datasheet

OPA3692
OPA
369
2
SBOS228E – FEBRUARY 2002 – REVISED DECEMBER 2008
www.ti.com
Triple, Wideband, Fixed Gain
Video BUFFER AMPLIFIER With Disable
FEATURES
APPLICATIONS
● FLEXIBLE SUPPLY RANGE:
+5V to +12V Single Supply
±2.5V to ±6V Dual Supplies
● INTERNALLY FIXED GAIN: +2 or ±1
● HIGH BANDWIDTH (G = +2): 225MHz
● LOW SUPPLY CURRENT: 5.1mA/ch
● LOW DISABLED CURRENT: 150µA/ch
● HIGH OUTPUT CURRENT: 190mA
● OUTPUT VOLTAGE SWING: ±4.0V
● IMPROVED HIGH-FREQUENCY PINOUT
●
●
●
●
●
●
●
RGB VIDEO LINE DRIVERS
MULTIPLE LINE VIDEO DAs
PORTABLE INSTRUMENTS
ADC BUFFERS
ACTIVE FILTERS
WIDEBAND DIFFERENTIAL RECEIVERS
IMPROVED UPGRADE TO OPA3682
OPA3692 RELATED PRODUCTS
SINGLES
DUALS
TRIPLES
DESCRIPTION
Voltage-Feedback
OPA690
OPA2690
OPA3690
Current-Feedback
OPA691
OPA2691
OPA3691
The OPA3692 provides an easy-to-use, broadband fixed
gain, triple buffer amplifier. Depending on the external
connections, the internal resistor network may be used to
provide either a fixed gain of +2 video buffer, or a gain of +1
or –1 voltage buffer. Operating on a very low 5.1mA/ch
supply current, the OPA3692 offers a slew rate and output
power normally associated with a much higher supply current. A new output stage architecture delivers high output
current with minimal headroom and crossover distortion.
This gives exceptional single-supply operation. Using a
single +5V supply, the OPA3692 can deliver a 1V to 4V
output swing with over 120mA drive current and > 200MHz
bandwidth. This combination of features makes the OPA3692
an ideal RGB line driver or single-supply, triple Analog-toDigital Converter (ADC) input driver.
Fixed Gain
OPA692
—
OPA3682
The low 5.1mA/ch supply current of the OPA3692 is precisely
trimmed at +25°C. This trim, along with low drift over temperature, ensures lower maximum supply current than competing
products that report only a room temperature nominal supply
current. System power can be further reduced by using the
optional disable control pin. Leaving this disable pin open, or
holding it HIGH, gives normal operation. If pulled LOW, the
OPA3692 supply current drops to less than 150µA/ch while
the output goes into a high-impedance state. This feature
may be used for power savings.
VR
1/3
OPA3692
75.0Ω
75.0Ω
75Ω Cable
RG-59
402Ω
VG
402Ω
1/3
OPA3692
75.0Ω
75.0Ω
75Ω Cable
RG-59
402Ω
VB
402Ω
1/3
OPA3692
75.0Ω
75.0Ω
75Ω Cable
RG-59
402Ω
402Ω
RGB Line Driver
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2002-2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
Power Supply ............................................................................... ±6.5VDC
Internal Power Dissipation(2) ............................ See Thermal Information
Differential Input Voltage(3) ............................................................... ±1.2V
Input Voltage Range ............................................................................ ±VS
Storage Temperature Range: D, DBQ ........................... –65°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
Junction Temperature (TJ ) ........................................................... +175°C
ESD Resistance: HBM .................................................................... 2000V
CDM .................................................................... 1500V
MM ........................................................................ 200V
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. (2) Packages must be derated based on specified θJA.
Maximum TJ must be observed. (3) Noninverting input to internal inverting node.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
OPA3692
"
OPA3692
"
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
SO-16
D
–40°C to +85°C
OPA3692
"
"
"
"
SSOP-16
DBQ
–40°C to +85°C
OPA3692
"
"
"
"
OPA3692ID
OPA3692IDR
OPA3692IDBQT
OPA3692IDBQR
Rails, 48
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 2500
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.
PIN CONFIGURATION
Top View
SSOP, SO
OPA3692
402Ω
402Ω
–IN A
1
16 DIS A
+IN A
2
15 +VS
DIS B
3
402Ω
14 OUT A
402Ω
–IN B
4
13 –VS
+IN B
5
12 OUT B
DIS C
6
402Ω
11 +VS
402Ω
–IN C
7
10 OUT C
+IN C
8
9
–VS
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
G = +2 (–IN grounded) and RL = 100Ω (see Figure 1 for AC performance only), unless otherwise noted.
OPA3692ID, OPA3692IDBQ
MIN/MAX OVER TEMPERATURE(1)
TYP
PARAMETER
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth (VO < 0.5VPP)
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
Rise-and-Fall Time
2
CONDITIONS
+25°C
G = +1
G = +2
G = –1
G = +2, VO < 0.5VPP
VO < 0.5Vp-p
G = +2, VO = 5VPP
G = +2, 4V Step
G = +2, VO = 0.5V Step
G = +2, VO = 5V Step
280
225
220
120
0.2
220
2000
1.6
1.9
+25°C
0°C to
70°C
–40°C to
+85°C
185
180
170
40
1
35
1.5
30
2
1400
1375
1350
UNITS
MIN/
MAX
TEST
LEVEL(2 )
MHz
MHz
MHz
MHz
dB
MHz
V/µs
ns
ns
typ
min
typ
min
max
typ
min
typ
typ
C
B
C
B
B
C
B
C
C
OPA3692
www.ti.com
SBOS228E
ELECTRICAL CHARACTERISTICS: VS = ±5V (Cont.)
Boldface limits are tested at +25°C.
G = +2 (–IN grounded) and RL = 100Ω (see Figure 1 for AC performance only), unless otherwise noted.
OPA3692ID, OPA3692IDBQ
MIN/MAX OVER TEMPERATURE(1)
TYP
PARAMETER
AC PERFORMANCE (Cont.)
Settling Time to 0.02%
0.1%
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Noninverting Input Current Noise
Inverting Input Current Noise (Internal)
Differential Gain
Differential Phase
Channel-to-Channel Crosstalk
DC PERFORMANCE(3)
Gain Error
Internal RF and RG
Maximum
Minimum
Average Drift
Input Offset Voltage
Average Offset Voltage Drift
Noninverting Input Bias Current
Average Noninverting Input Bias Current Drift
Inverting Input Bias Current
Average Inverting Input Bias Current Drift
CONDITIONS
+25°C
G = +2, VO = 2V Step
G = +2, VO = 2V Step
G = +2, f = 5MHz, VO = 2VPP
RL = 100Ω
RL ≥ 500Ω
RL = 100Ω
RL ≥ 500Ω
f > 1MHz
f > 1MHz
f > 1MHz
NTSC, RL = 150Ω
NTSC, RL = 37.5Ω
NTSC, RL = 150Ω
NTSC, RL = 37.5Ω
f = 5MHz, Input Referred, All Hostile
12
8
–69
–79
–76
–94
1.7
12
15
0.07
0.17
0.02
0.07
–82
G = +1
G = +2
G = –1
±0.2
±0.3
±0.2
Current Output, Sourcing
Sinking
Short-Circuit Current
Closed-Loop Output Impedance
DISABLE/POWER DOWN (DIS Pin)
Power-Down Supply Current (+VS)
Disable Time
Enable Time
Off Isolation
Output Capacitance in Disable
Turn-On Glitch
Turn-Off Glitch
Enable Voltage
Disable Voltage
Control Pin Input Bias Current
POWER SUPPLY
Specified Operating Voltage
Maximum Operating Voltage Range
Maximum Quiescent Current (3 Channels)
Minimum Quiescent Current (3 Channels)
Power-Supply Rejection Ratio (–PSRR)
TEMPERATURE RANGE
Specification: D, DBQ
Thermal Resistance, θJA
D
SO-16
DBQ SSOP-16
0°C to
70°C
–40°C to
+85°C
UNITS
MIN/
MAX
TEST
LEVEL(2 )
ns
ns
typ
typ
C
C
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
%
%
deg
deg
dBc
max
max
max
max
max
max
max
typ
typ
typ
typ
typ
B
B
B
B
B
B
B
C
C
C
C
C
–62
–70
–72
–87
2.5
14
17
–59
–67
–70
–82
2.9
15
18
–57
–65
–68
–78
3.1
15
19
±1.5
±1.6
±1.6
±1.7
±1.7
%
%
%
typ
max
max
C
A
B
±0.8
457
347
0.13
±3
+15
+35
±5
±25
462
342
0.13
±3.7
±12
+43
–300
±30
±90
464
340
0.13
±4.3
±20
+45
–300
±40
±200
Ω
Ω
%/°C
mV
µV/°C
µA
nA/°C
µA
nA°C
max
min
max
max
max
max
max
max
max
A
A
B
A
B
A
B
A
B
±3.5
100 || 2
±3.4
±3.3
±3.2
V
kΩ || pF
min
typ
B
C
±4.0
±3.9
+190
–190
±250
0.12
±3.8
±3.7
+160
–160
±3.7
±3.6
+140
–140
±3.6
±3.3
+100
–100
V
V
mA
mA
mA
Ω
min
min
min
min
typ
typ
A
A
A
A
C
C
–900
–1050
–1200
3.5
1.7
130
3.6
1.6
150
3.7
1.5
160
µA
µs
ns
dB
pF
mV
mV
V
V
µA
max
typ
typ
typ
typ
typ
typ
min
max
max
A
C
C
C
C
C
C
A
A
A
±6
±6
16.8
13.2
50
±6
17.4
12.75
49
V
V
mA
mA
dB
typ
max
max
min
min
C
A
A
A
A
–40 to +85
°C
typ
C
100
100
°C/W
°C/W
typ
typ
C
C
402
402
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
INPUT
Common-Mode Input Range
Noninverting Input Impedance
OUTPUT
Voltage Output Swing
+25°C
No Load
100Ω Load
G = +2, f = 100kHz
VDIS = 0, All Channels
VIN = +1VDC
VIN = +1VDC
G = +2, 5MHz
–450
1
25
74
4
±50
±20
3.3
1.8
75
G = +2, RL = 150Ω, VIN = 0V
G = +2, RL = 150Ω, VIN = 0V
VDIS = 0, Each Channel
±5
VS = ±5V
VS = ±5V
Input Referred
15.3
15.3
58
±1.5
15.9
14.7
52
NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +15°C at
high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by
characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode voltage.
OPA3692
SBOS228E
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3
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
G = +2 (–IN grounded though 0.1µF) and RL = 100Ω to VS /2 (see Figure 2 for AC performance only), unless otherwise noted.
OPA3692ID, OPA3692IDBQ
MIN/MAX OVER TEMPERATURE(1)
TYP
PARAMETER
AC PERFORMANCE (see Figure 2)
Small-Signal Bandwidth (VO < 0.5VPP)
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
Rise-and-Fall Time
Settling Time to 0.02%
0.1%
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Noninverting Input Current Noise
Inverting Input Current Noise
DC PERFORMANCE(3)
Gain Error
Internal RF and RG
Minimum
Maximum
Average Drift
Input Offset Voltage
Average Offset Voltage Drift
Noninverting Input Bias Current
Average Noninverting Input Bias Current Drift
Inverting Input Bias Current
Average Inverting Input Bias Current Drift
INPUT
Least Positive Input Voltage
Most Positive Input Voltage
Noninverting Input Impedance
OUTPUT
Most Positive Output Voltage
Least Positive Output Voltage
Current Output, Sourcing
Sinking
Short-Circuit Current
Output Impedance
DISABLE/POWER DOWN (DIS Pin)
Power-Down Supply Current (+VS)
Off Isolation
Output Capacitance in Disable
Turn-On Glitch
Turn-Off Glitch
Enable Voltage
Disable Voltage
Control Pin Input Bias Current (DIS)
POWER SUPPLY
Specified Single-Supply Operating Voltage
Maximum Single-Supply Operating Voltage
Maximum Quiescent Current (3 Channels)
Minimum Quiescent Current (3 Channels)
Power-Supply Rejection Ratio (+PSRR)
TEMPERATURE RANGE
Specification: D, DBQ
Thermal Resistance, θJA
D
SO-16
DBQ SSOP-16
+25°C
0°C to
70°C
–40°C to
+85°C
168
160
140
40
1
30
2.5
25
3
600
575
550
–66
–73
–72
–77
1.7
12
15
–58
–65
–68
–72
2.5
14
17
–57
–63
–67
–70
2.9
15
18
±0.2
±0.3
±0.2
±1.5
±1.5
±0.8
457
347
0.13
±3.5
+20
+40
±5
±20
1.5
3.5
100 || 2
UNITS
MIN/
MAX
TEST
LEVEL(2 )
MHz
MHz
MHz
MHz
dB
MHz
V/µs
ns
ns
ns
ns
typ
min
typ
min
max
typ
min
typ
typ
typ
typ
C
B
C
B
B
C
B
C
C
C
C
–56
–62
–65
–69
3.1
15
19
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
max
max
max
max
max
max
max
B
B
B
B
B
B
B
±1.6
±1.6
±1.7
±1.7
%
%
%
typ
max
max
C
A
B
462
342
0.13
±4.1
±12
+46
–250
±25
±112
464
340
0.13
±4.8
±20
+56
–250
±35
±200
Ω
Ω
%/°C
mV
µV/°C
µA
nA/°C
µA
nA°C
min
max
max
max
max
max
max
max
max
B
B
B
A
B
A
B
A
B
1.6
3.4
1.7
3.3
1.8
3.2
V
V
kΩ || pF
max
min
typ
B
B
C
4.0
3.9
1.0
1.1
+160
–160
±250
0.12
3.8
3.7
1.2
1.3
+120
–120
3.7
3.6
1.3
1.4
+100
–100
3.5
3.4
1.5
1.6
+80
–80
V
V
V
V
mA
mA
mA
Ω
min
min
max
max
min
min
typ
typ
A
A
A
A
A
A
C
C
–450
65
4
±50
±20
3.3
1.8
75
–900
–1050
–1200
3.5
1.7
130
3.6
1.6
150
3.7
1.5
160
µA
dB
pF
mV
mV
V
V
µA
max
typ
typ
typ
typ
min
max
typ
A
C
C
B
B
A
A
C
12
14.4
12.3
12
15.3
11.4
12
15.9
11.0
V
V
mA
mA
dB
typ
max
max
min
typ
C
A
A
A
C
–40 to +85
°C
typ
C
100
100
°C/W
°C/W
typ
typ
C
C
CONDITIONS
+25°C
G = +1
G = +2
G = –1
G = +2, VO < 0.5VPP
VO < 0.5VPP
G = +2, VO = 2VPP
G = +2, 2V Step
G = +2, VO = 0.5V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
G = +2, f = 5MHz, VO = 2VPP
RL = 100Ω to VS /2
RL ≥ 500Ω to VS /2
RL = 100Ω to VS /2
RL ≥ 500Ω to VS /2
f > 1MHz
f > 1MHz
f > 1MHz
240
190
195
90
0.2
210
830
2.0
2.3
14
10
G = +1
G = +2
G = –1
402
402
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
No Load
RL = 100Ω
No Load
RL = 100Ω
G = +2, f = 100kHz
VDIS = 0, All Channels
G = +2, 5MHz
G = +2, RL = 150Ω, VIN = 2.5V
G = +2, RL = 150Ω, VIN = 2.5V
VDIS = 0, Each Channel
5
VS = +5V
VS = +5V
Input Referred
13.5
13.5
62
NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +15°C at
high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by
characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode voltage.
4
OPA3692
www.ti.com
SBOS228E
TYPICAL CHARACTERISTICS: VS = ±5V
TA = +25°C, G = +2 (–In grounded), and RL = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
1
7
VO = 1Vp-p
G = +1
6
–1
VO = 2Vp-p
G = –1
–2
Gain (1dB/div)
Normalized Gain (1dB/div)
0
–3
–4
–5
5
4
VO = 4Vp-p
G = +2
–6
3
VO = 7Vp-p
–7
2
–8
0
250MHz
0
500MHz
125MHz
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
4
VO = 0.5Vp-p
G = +2
300
VO = 5Vp-p
G = +2
3
Output Voltage (1V/div)
Output Voltage (100mV/div)
400
200
100
0
–100
–200
2
1
0
–1
–2
–3
–300
–4
–400
Time (5ns/div)
Time (5ns/div)
COMPOSITE VIDEO dG/dP
0.20
Video In
DIS
DISABLED FEEDTHROUGH vs FREQUENCY
–50
+5V
0.18
Video Loads
No Pull-Down
With 1.3kΩ Pull-Down
–5V
–60
dG
Optional
1.3kΩ
Pull-Down
0.12
Feedthrough (dB)
0.14
VDIS = 0
–55
1/3
OPA3692
0.16
dG/dP (%/°)
250MHz
Frequency (25MHz/div)
Frequency (50MHz/div)
dG
0.10
0.08
dP
0.06
–65
–70
–75
–80
–85
0.04
dP
–90
0.02
0
–95
1
2
3
0.5
4
10
100
Frequency (MHz)
Number of 150Ω Loads
OPA3692
SBOS228E
1
www.ti.com
5
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = +25°C, G = +2 (–In grounded), and RL = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs SUPPLY VOLTAGE
–60
–50
VO = 2Vp-p
f = 5MHz
VO = 2Vp-p
RL = 100Ω
f = 5MHz
–55
–70
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–65
2nd-Harmonic
–75
–80
3rd-Harmonic
–85
–90
–95
–60
2nd-Harmonic
–65
–70
–75
–80
3rd-Harmonic
–85
–100
–90
100
1000
2.0
2.5
3.0
Load Resistance (Ω)
4.5
5.0
5.5
6.0
–65
VO = 2Vp-p
RL = 100Ω
dBc = dB Below Carrier
RL = 100Ω
f = 5MHz
–60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
4.0
HARMONIC DISTORTION vs OUTPUT VOLTAGE
HARMONIC DISTORTION vs FREQUENCY (G = +2)
–50
2nd-Harmonic
–70
–80
3rd-Harmonic
–90
–100
2nd-Harmonic
–70
–75
3rd-Harmonic
–80
–85
0.1
1
10
0.1
20
HARMONIC DISTORTION vs FREQUENCY (G = –1)
–50
HARMONIC DISTORTION vs FREQUENCY (G = +1)
VO = 2Vp-p
RL = 100Ω
dBc = dB Below Carrier
Harmonic Distortion (dBc)
–60
2nd-Harmonic
–70
–80
3rd-Harmonic
–90
5
–50
VO = 2Vp-p
RL = 100Ω
dBc = dB Below Carrier
1
Output Voltage Swing (Vp-p)
Frequency (MHz)
Harmonic Distortion (dBc)
3.5
Supply Voltage (±VS)
–60
–70
3rd-Harmonic
–80
–90
2nd-Harmonic
–100
–100
0.1
1
10
20
0.1
Frequency (MHz)
6
1
10
20
Frequency (MHz)
OPA3692
www.ti.com
SBOS228E
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = +25°C, G = +2 (–In grounded), and RL = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted.
2-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
INPUT VOLTAGE AND CURRENT NOISE DENSITY
–30
3rd-Order Spurious Level (dBc)
Inverting Input Current Noise (15pA/√Hz)
10
Noninverting Current Noise (12pA/√Hz)
Voltage Noise (1.7nV/√Hz)
1
dBc = dB below carriers
50MHz
–40
–50
–60
20MHz
–70
10MHz
–80
Load Power at Matched 50Ω Load
–90
100
1k
10k
100k
1M
10M
–8
–6
–4
Frequency (Hz)
RECOMMENDED RS vs CAPACITIVE LOAD
Normalized Gain to Capacitive Load (dB)
50
RS (Ω)
40
30
20
10
0
10
2
4
6
8
10
100
9
CL = 10pF
6
3
CL = 47pF
0
CL = 22pF
–3
VIN
1/3
OPA3692
402Ω
–6
CL = 100pF
RS
VO
CL
1kΩ
402Ω
1kΩ is optional.
–9
1k
0
125MHz
Capacitive Load (pF)
250MHz
Frequency (25MHz/div)
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
10
65
250
Sourcing Output Current
60
Supply Current (2mA/div)
+PSRR
55
PSRR (dB)
0
FREQUENCY RESPONSE vs CAPACITIVE LOAD
60
1
–2
Single-Tone Load Power (dBm)
–PSRR
50
45
40
35
30
8
200
Sinking Output Current
6
150
4
100
Quiescent Supply Current
(1 Channel)
2
50
Output Current (50mA/div)
Current Noise (pA/√Hz)
Voltage Noise (nV/√Hz)
100
25
0
20
1k
10k
100k
1M
10M
100M
–25
0
25
50
75
100
125
Ambient Temperature (°C)
Frequency (Hz)
OPA3692
SBOS228E
0
–50
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7
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = +25°C, G = +2 (–In grounded), and RL = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted.
TYPICAL DC DRIFT OVER TEMPERATURE
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
Output Current Limited
VO (V)
2
1
25Ω
Load Line
0
–1
50Ω Load Line
–2
100Ω Load Line
1W Internal
Power Limit
Single Channel
–3
–4
Output Current Limit
0
50
30
1
20
0.5
10
Inverting Input Bias Current
0
0
–0.5
–10
Input Offset Voltage
–1
–20
–1.5
–30
–2
–5
–300 –250 –200 –150 –100 –50
1.5
–40
–50
100 150 200 250 300
–25
0
25
50
75
100
125
Ambient Temperature (°C)
IO (mA)
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
DISABLE/ENABLE GLITCH
6.0
0
2.0
1.6
Output Voltage
0.8
0.4
VIN = +1V
0
VDIS
Output Voltage (10mV/div)
Output Voltage (400mV/div)
2.0
6.0
VDIS (2V/div)
4.0
VDIS
1.2
0
30
20
Output Voltage
VIN = 0V
10
0
–10
–20
Time (20ns/div)
ALL HOSTILE CROSSTALK
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
–55
10
–60
–65
1/3
OPA3692
ZO
–5V 402Ω
2 Channels Driving
Input Referred
Crosstalk to
Inactive Channel
–70
Crosstalk (dB)
Output Impedance (Ω)
+5V
1
4.0
2.0
Time (200ns/div)
50Ω
Input Bias Currents (µA)
3
40
Noninverting Input Bias Current
Input Offset Voltage (mV)
1W Internal
Power Limit
Single Channel
4
2
VDIS (2V/div)
5
–75
–80
–85
402Ω
–90
–95
0.1
–100
10k
100k
1M
10M
0.3
100M
8
1
10
100
Frequency (MHz)
Frequency (Hz)
OPA3692
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SBOS228E
TYPICAL CHARACTERISTICS: VS = +5V
TA = +25°C, G = +2 (–In grounded), and RL = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted.
LARGE-SIGNAL FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY RESPONSE
1
7
VO = 0.5Vp-p
0
6
Normalized Gain (1dB/div)
G = +1
–1
Gain (1dB/div)
5
–2
G = –1
–3
–4
–5
3
2
–6
G = +2
1
–7
RL = 100Ω to 2.5V
–8
0
0
250MHz
0
500MHz
125MHz
LARGE-SIGNAL PULSE RESPONSE
SMALL-SIGNAL PULSE RESPONSE
4.1
2.9
Output Voltage (400mV/div)
G = +2
VO = 0.5Vp-p
2.8
2.7
2.6
2.5
2.4
2.3
G = +2
VO = 2Vp-p
3.7
3.3
2.9
2.5
2.1
1.7
1.3
2.2
0.9
2.1
Time (5ns/div)
Time (5ns/div)
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
9
60
6
Normalized Gain to
Capacitive Load (dB)
70
50
RS (Ω)
250MHz
Frequency (25MHz/div)
Frequency (50MHz/div)
Output Voltage (100mV/div)
VO = 2Vp-p
VO = 1Vp-p
4
40
30
20
CL = 10pF
CL = 22pF
3
CL = 47pF
0
+5V
–3
0.1µF
50Ω Source
VIN
0.1µF
57.6Ω
10
–6
0
–9
+
6.8µF
806Ω
806Ω
1/3
OPA3692
VO
CL = 100pF
Dis
100Ω VS/2
402Ω
402Ω
(1kΩ is optional)
0.1µF
1
10
100
1k
0
Capacitive Load (pF)
OPA3692
SBOS228E
125MHz
250MHz
Frequency (25MHz/div)
www.ti.com
9
TYPICAL CHARACTERISTICS: VS = +5V (Cont.)
TA = +25°C, G = +2 (–In grounded), and RL = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted.
HARMONIC DISTORTION vs FREQUENCY
HARMONIC DISTORTION vs LOAD RESISTANCE
–60
–50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
VO = 2Vp-p
f = 5MHz
–65
2nd-Harmonic
–70
3rd-Harmonic
–75
–80
2nd-Harmonic
–70
–80
3rd-Harmonic
0.1
1k
1
Frequency (MHz)
HARMONIC DISTORTION vs OUTPUT VOLTAGE
2-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
–30
3rd-Order Spurious Level (dBc)
RL = 100Ω to 2.5V
f = 5MHz
–65
2nd-Harmonic
–70
–75
3rd-Harmonic
–80
1
2
50MHz
–40
–45
–50
–55
20MHz
–60
–65
10MHz
–70
–75
Load Power at Matched 50Ω Load
–14
3
20
dBc = dB Below Carriers
–35
–80
0.1
10
Load Resistance (Ω)
–60
Harmonic Distortion (dBc)
–60
–90
100
–12
–10
–8
–6
–4
–2
0
2
Single-Tone Load Power (dBm)
Output Voltage Swing (Vp-p)
10
VO = 2Vp-p
RL = 100Ω to 2.5V
OPA3692
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SBOS228E
APPLICATIONS INFORMATION
WIDEBAND BUFFER OPERATION
The OPA3692 gives the exceptional AC performance of a
wideband, current-feedback op amp with a highly linear,
high-power output stage. It features internal RF and RG
resistors that make it easy to select a gain of +2, +1, or
–1 without external resistors. Requiring only 5.1mA/ch quiescent current, the OPA3692 swings to within 1V of either
supply rail and delivers in excess of 160mA at room temperature. This low output headroom requirement, along with
supply voltage independent biasing, gives remarkable +5V
single-supply operation. The OPA3692 will deliver greater
than 200MHz bandwidth driving a 2Vp-p output into 100Ω on
a +5V single supply. Previous boosted output stage amplifiers have typically suffered from very poor crossover distortion as the output current goes through zero. The OPA3692
achieves a comparable power gain with much better linearity.
Figure 1 shows the DC-coupled, gain of +2, dual powersupply circuit configuration used as the basis of the ±5V
Electrical and Typical Characteristics. For test purposes, the
input impedance is set to 50Ω with a resistor to ground and
the output impedance is set to 50Ω with a series output
resistor. Voltage swings reported in the specifications are
taken directly at the input and output pins while load powers
(dBm) are defined at a matched 50Ω load. For the circuit of
Figure 1, the total effective load will be 100Ω || 804Ω = 89Ω.
The disable control line (DIS) is typically left open to ensure
normal amplifier operation. In addition to the usual powersupply decoupling capacitors to ground, a 0.1µF capacitor
can be included between the two power-supply pins. This
optional capacitor typically improves the 2nd-harmonic distortion performance by 3dB to 6dB.
Figure 2 shows the AC-coupled, gain of +2, single-supply
circuit configuration used as the basis of the +5V Electrical and
Typical Characteristics. Though not a rail-to-rail design, the
OPA3692 requires minimal input and output voltage headroom
compared to other very wideband, current-feedback op amps.
It will deliver a 3Vp-p output swing on a single +5V supply with
greater than 150MHz bandwidth. The key requirement of
broadband single-supply operation is to maintain input and
output signal swings within the usable voltage ranges at both
the input and the output. The circuit in Figure 2 establishes an
input midpoint bias using a simple resistive divider from the
+5V supply (two 806Ω resistors). The input signal is then ACcoupled into this midpoint voltage bias. The input voltage can
swing to within 1.5V of either supply pin, giving a 2Vp-p input
signal range centered between the supply pins. The input
impedance matching resistor (57.6Ω) used for testing is adjusted to give a 50Ω input match when the parallel combination
of the biasing divider network is included. The gain resistor
(RG) is AC-coupled, giving the circuit a DC gain of +1, which
puts the input DC bias voltage (2.5V) on the output as well.
Again, on a single +5V supply, the output voltage can swing to
within 1V of either supply pin while delivering more than 120mA
output current. A demanding 100Ω load to a midpoint bias is
used in this characterization circuit. The new output stage used
in the OPA3692 can deliver large bipolar output currents into
this midpoint load with minimal crossover distortion, as shown
by the +5V supply, 3rd-harmonic distortion plots. Although
Figure 2 shows a single +5V operation, this same circuit is
suitable for applications up to a single +12V supply.
+VS
+5V
0.1µF
50Ω Source
6.8µF
806Ω
0.1µF
DIS
VIN
57.6Ω
+
1/3
OPA3692
806Ω
VO
100Ω
VS/2
RF
402Ω
+5V
DIS
RG
402Ω
+
0.1µF
50Ω Source
6.8µF
0.1µF
VIN
50Ω
1/3
OPA3692
50Ω
50Ω Load
FIGURE 2. AC-Coupled, G = +2, Single-Supply Specification
and Test Circuit.
RF
402Ω
VIDEO RGB AMPLIFIER
The front page shows an RGB amplifier based on the
OPA3692. The package pinout supports a signal flow-through
printed circuit board (PCB). The internal resistors simplify the
PCB even more, while maintaining good gain accuracy. For
systems that need to conserve power, the total supply current
for the disabled OPA3692 is only 450µA.
RG
402Ω
0.1µF
+
6.8µF
–5V
FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit.
This triple op amp could also be used to drive triple video ADCs
to digitize component video.
OPA3692
SBOS228E
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11
HIGH-SPEED INSTRUMENTATION AMPLIFIER
7
Figure 3 shows an instrumentation amplifier based on the
OPA3692. The offset matching between inputs makes this an
attractive input stage for this application. The differential-tosingle-ended gain for this circuit is 2.0V/V. The inputs are high
impedance, with only 1pF to ground at each input. The loads
on the OPA3692 outputs are equal for the best harmonic
distortion possible.
6
5
Gain (dB)
4
3
2
1
0
–1
20log
–2
VOUT
|V1 – V2|
–3
1
10
100
400
Frequency (MHz)
V1
1/3
OPA3692
402Ω
200Ω
200Ω
FIGURE 4. High-Speed Instrumentation Amplifier Response.
402Ω
MULTIPLEXED CONVERTER DRIVER
1/3
OPA3692
402Ω
402Ω
1/3
OPA3692
402Ω
The converter driver in Figure 5 multiplexes among the three
input signals. The OPA3692s enable and disable times
support multiplexing among video signals. The make-beforebreak disable characteristic of the OPA3692 ensures that the
output is always under control. To avoid large switching
glitches, switch during the sync or retrace portions of the
video signal—the two inputs should be almost equal at these
times. The output is always under control, so the switching
glitches for two 0V inputs are < 20mV. With standard
video signals levels at the inputs, the maximum differential
voltage across the disabled inputs will not exceed the ±1.2V
maximum rating.
VOUT
402Ω
V2
FIGURE 3. High-Speed Instrumentation Amplifier.
As shown in Figure 4, the OPA3692 used as an instrumentation amplifier has a 240MHz, –3dB bandwidth. This plot has
been made for a 1Vp-p output signal using a low-impedance
differential input source.
V1
The output resistors isolate the outputs from each other
when switching between channels. The feedback network of
the disabled channels forms part of the load seen by the
enabled amplifier, attenuating the signal slightly.
100Ω
1/3
OPA3692
4.99kΩ
402Ω
V2
0.1µF
402Ω
100Ω
1/3
OPA3692
402Ω
0.1µF
4.99kΩ
REFT
+3.5V
0.1µF
REFB
+1.5V
+In
402Ω
ADS826
10-Bit
60MSPS
100pF
–In
CM
V3
100Ω
1/3
OPA3692
402Ω
402Ω
0.1µF
Selection
Logic
FIGURE 5. Multiplexed Converter Driver.
12
OPA3692
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SBOS228E
LOW-PASS FILTER
The demonstration fixtures can be requested at the Texas
Instruments web site at (www.ti.com) through the OPA3692
product folder.
The circuit in Figure 6 realizes a 7th-order Butterworth lowpass filter with a –3dB bandwidth of 20MHz. This filter is based
on the KRC active filter topology, which uses an amplifier with
the fixed gain ≥ 1. The OPA3692 makes a good amplifier for
this type of filter. The component values have been adjusted
to compensate for the parasitic effects of the op amp.
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and RF
amplifier circuits where parasitic capacitance and inductance
can have a major effect on circuit performance. A SPICE
model for the OPA692 is available through the Texas Instruments web site at www.ti.com. Use three of these models to
simulate the OPA3692. These models do a good job of
predicting small-signal AC and transient performance under
a wide variety of operating conditions. They do not do as well
in predicting the harmonic distortion or dG/dP characteristics.
These models do not attempt to distinguish between the
package types in their small-signal AC performance.
DESIGN-IN TOOLS
DEMONSTRATION FIXTURES
Two PCBs are available to assist in the initial evaluation of
circuit performance using the OPA3692 in its two package
options. Both of these are offered free of charge as
unpopulated PCBs, delivered with a user's guide. The summary information for these fixtures is shown in
Table I.
PRODUCT
PACKAGE
ORDERING
NUMBER
LITERATURE
NUMBER
OPA3692IDBQ
OPA3692ID
SSOP-16
SO-16
DEM-OPA-SSOP-3B
DEM-OPA-SO-3A
SBOU006
SBOU007
TABLE I. OPA3692 Demonstration Boards.
120pF
47.5Ω
49.9Ω
56pF
110Ω
VIN
220pF
124Ω
82pF
255Ω
1/3
OPA3692
1/3
OPA3692
22pF
402Ω
402Ω
402Ω
402Ω
(open)
180pF
48.7Ω
7TH-ORDER BUTTERWORTH
FILTER RESPONSE
95.3Ω
20
–0
1/3
OPA3692
68pF
VOUT
Gain (dB)
–20
402Ω
–40
–60
402Ω
–80
(open)
–100
1
3
10
30
100
300
1000
Frequency (MHz)
FIGURE 6. 7th-Order Butterworth Filter.
OPA3692
SBOS228E
www.ti.com
13
OPERATING SUGGESTIONS
DRIVING CAPACITIVE LOADS
GAIN SETTING
Setting the gain with the OPA3692 is very easy. For a gain
of +2, ground the –IN pin and drive the +IN pin with the
signal. For a gain of +1, leave the –IN pin open and drive the
+IN pin with the signal. For a gain of –1, ground the +IN pin
and drive the –IN pin with the signal. As the internal resistor
values (not their ratios) change significantly over temperature and process, external resistors should not be used to
modify the gain.
OUTPUT CURRENT AND VOLTAGE
The OPA3692 provides output voltage and current capabilities that are unsurpassed in a low-cost monolithic op amp.
Under no-load conditions at 25°C, the output voltage typically
swings closer than 1V to either supply rail; the tested swing
limit is within 1.2V of either rail. Into a 15Ω load (the minimum
tested load), it is tested to deliver more than ±160mA.
The specifications described previously, though familiar in
the industry, consider voltage and current limits separately. In
many applications, it is the voltage • current, or V-I product,
which is more relevant to circuit operation. Refer to the
Output Voltage and Current Limitations plot in the Typical
Characteristics. The X- and Y-axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA3692 output drive capabilities, noting
that the graph is bounded by a safe operating area of 1W
maximum internal power dissipation. Superimposing resistor
load lines onto the plot shows that the OPA3692 can drive
±2.5V into 25Ω or ±3.5V into 50Ω without exceeding the
output capabilities or the 1W dissipation limit. A 100Ω load
line (the standard test circuit load) shows the full ±3.9V
output swing capability, as shown in the Electrical Characteristics.
The minimum specified output voltage and current overtemperature are set by worst-case simulations at the cold
temperature extreme. Only at cold start-up does the output
current and voltage decrease to the numbers shown in the
Electrical Characteristic tables. As the output transistors
deliver power, their junction temperatures increase, decreasing their VBEs (increasing the available output voltage swing)
and increasing their current gains (increasing the available
output current). In steady-state operation, the available output voltage and current is always greater than that shown in
the over-temperature specifications because the output stage
junction temperatures are higher than the minimum specified
operating ambient.
To protect the output stage from accidental shorts to ground
and the power supplies, output short-circuit protection is
included in the OPA3692. This circuit acts to limit the maximum source or sink current to approximately 250mA.
14
One of the most demanding, but yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC—including additional
external capacitance that may be recommended to improve
ADC linearity. A high-speed amplifier like the OPA3692 can be
very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on
the output pin. When the amplifier open-loop output resistance
is considered, this capacitive load introduces an additional
pole in the signal path that can decrease the phase margin.
Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the
simplest and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series isolation
resistor between the amplifier output and the capacitive load.
This does not eliminate the pole from the loop response, but
rather shifts it and adds a zero at a higher frequency. The
additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability.
The Typical Characteristics show the recommended RS versus capacitive load and the resulting frequency response at
the load. Parasitic capacitive loads greater than 2pF can begin
to degrade the performance of the OPA3692. Long PCB
traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA3692 output pin
(see the Board Layout Guidelines section).
DISTORTION PERFORMANCE
The OPA3692 provides good distortion performance into a
100Ω load on ±5V supplies. Relative to alternative solutions, it
provides exceptional performance into lighter loads and/or
operating on a single +5V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the
2nd-harmonic dominates the distortion with a negligible 3rdharmonic component. Focusing then on the 2nd-harmonic,
increasing the load impedance improves distortion directly.
Remember that the total load includes the feedback network in
the noninverting configuration (see Figure 1); this is the sum
RF + RG, whereas in the inverting configuration, it is just RF.
Also, providing an additional supply decoupling capacitor (0.1µF)
between the supply pins (for bipolar operation) improves the
2nd-order distortion slightly (3dB to 6dB).
In most op amps, increasing the output voltage swing increases
harmonic distortion directly. The Typical Characteristics show the
2nd-harmonic increasing at a little less than the expected 2X rate
while the 3rd-harmonic increases at a little less than the expected
3X rate. Where the test power doubles, the 2nd-harmonic
increases only by less than the expected 6dB, whereas the 3rd-
OPA3692
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SBOS228E
harmonic increases by less than the expected 12dB. This also
shows up in the 2-tone, 3rd-order intermodulation spurious (IM3)
response curves. The 3rd-order spurious levels are extremely
low at low output power levels. The output stage continues to
hold them low even as the fundamental power reaches very high
levels. As the Typical Characteristics show, the spurious
intermodulation powers do not increase as predicted by a
traditional intercept model. As the fundamental power level
increases, the dynamic range does not decrease significantly.
For two tones centered at 20MHz, with 10dBm/tone into a
matched 50Ω load (that is, 2Vp-p for each tone at the load, which
requires 8Vp-p for the overall 2-tone envelope at the output pin),
the Typical Characteristics show a 58dBc difference between the
test-tone power and the 3rd-order intermodulation spurious
levels. This exceptional performance improves further when
operating at lower frequencies.
NOISE PERFORMANCE
The OPA3692 offers an excellent balance between voltage
and current noise terms to achieve low output noise. The
inverting current noise (15pA/√Hz) is significantly lower than
earlier solutions while the input voltage noise (1.7nV/√Hz) is
lower than most unity-gain stable, wideband, voltage-feedback
op amps. This low input voltage noise was achieved at the
price of higher noninverting input current noise (12pA/√Hz). As
long as the AC source impedance looking out of the
noninverting node is less than 100Ω, this current noise will not
contribute significantly to the total output noise. The op amp
input voltage noise and the two input current noise terms
combine to give low output noise under a wide variety of
operating conditions. Figure 7 shows the op amp noise analysis model with all the noise terms included. In this model, all
noise terms are taken to be noise voltage or current density
terms in either nV/√Hz or pA/√Hz.
ENI
RS
EO
OPA3692
IBN
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 1 shows the general form for the output
noise voltage using the terms shown in Figure 7.
(1)
2
2
EO =  ENI2 + (IBNR S ) + 4kTRS  NG2 + (IBIRF ) + 4kTRFNG
Dividing this expression by the noise gain (NG = (1+RF/RG))
gives the equivalent input-referred spot noise voltage at the
noninverting input as shown in Equation 2.
(2)
2
4kTRF
2
I R 
EN = ENI2 + (IBNR S ) + 4kTRS +  BI F  +
 NG 
NG
Evaluating these two equations for the OPA3692 circuit and
component values shown in Figure 1 gives a total output spot
noise voltage of 8nV/√Hz and a total equivalent input spot
noise voltage of 4nV/√Hz. This total input-referred spot noise
voltage is higher than the 1.7nV/√Hz specification for the op
amp voltage noise alone. This reflects the noise added to the
output by the inverting current noise times the feedback
resistor. This inverting node current noise is modeled as
internal to the OPA3692 with RF set internally as well.
DC ACCURACY
The OPA3692 provides exceptional bandwidth in high gains,
giving fast pulse settling but only moderate DC accuracy. The
Electrical Characteristics show an input offset voltage comparable to high-speed voltage-feedback amplifiers. However,
the two input bias currents are somewhat higher and are
unmatched. Bias current cancellation techniques do not
reduce the output DC offset for OPA3692. As the two input
bias currents are unrelated in both magnitude and polarity,
matching the source impedance looking out of each input to
reduce their error contribution to the output is ineffective.
Evaluating the configuration of Figure 1, using worst-case
+25°C input offset voltage and the two input bias currents,
gives a worst-case output offset range equal to:
±(NG • VOS(MAX)) + (IBN • RS/2 • NG) ± (IBI • RF)
ERS
4kT
RG
where NG = noninverting signal gain
RF
√4kTRS
= ±(2 • 3mV) + (35µA • 25Ω • 2) ± (402Ω • 25µA)
RG
IBI
√4kTRF
4kT = 1.6E –20J
at 290°K
= ±6mV + 1.75mV ± 10.05mV
= –14.3mV → +17.8mV
Minimizing the resistance seen by the noninverting input will
give the best DC offset performance.
FIGURE 7. Noise Model.
OPA3692
SBOS228E
www.ti.com
15
DISABLE OPERATION
The OPA3692 provides an optional disable feature that can
be used either to reduce system power or to implement a
simple channel multiplexing operation. If the DIS control pin
is left unconnected, the OPA3692 operates normally. To
disable, the control pin must be asserted LOW. Figure 8
shows a simplified internal circuit for the disable control
feature.
+VS
15kΩ
VDIS
Due to the high output power capability of the OPA3692,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction temperature
will set the maximum allowed internal power dissipation as
described following. In no case should the maximum junction
temperature be allowed to exceed 175°C.
110kΩ
IS
Control
–VS
FIGURE 8. Simplified Disable Control Circuit.
In normal operation, base current to Q1 is provided through the
110kΩ resistor while the emitter current through the 15kΩ
resistor sets up a voltage drop that is inadequate to turn on the
two diodes in the Q1 emitter. As VDIS is pulled LOW, additional
current is pulled through the 15kΩ resistor, eventually turning
on these two diodes (≈ 75µA). At this point, any additional
current pulled out of VDIS goes through those diodes holding
the emitter-base voltage of Q1 at approximately 0V. This shuts
off the collector current out of Q1, turning the amplifier off. The
supply current in the disable mode is only what is required to
operate the circuit of Figure 8. Additional circuitry ensures that
turn-on time occurs faster than turn-off time (make-beforebreak).
When disabled, the output and input nodes go to a highimpedance state. If the OPA3692 is operating in a gain of +1,
this shows a very high impedance (2pF || 1MΩ) at the output
and exceptional signal isolation. If operating at a gain of +2, the
total feedback network resistance (RF + RG) will appear as the
impedance looking back into the output, but the circuit will still
show very high forward and reverse isolation. If configured as
an inverting amplifier, the input and output will be connected
through the feedback network resistance (RF + RG) giving
relatively poor input to output isolation.
16
The transition edge rate (dV/dt) of the DIS control line
influences this glitch. For the curve, Disable/Enable Glitch,
shown in the Typical Characteristics, the edge rate was
reduced until no further reduction in glitch amplitude was
observed. This approximately 1V/ns maximum slew rate can
be achieved by adding a simple RC filter into the V DIS pin
from a higher speed logic line. If extremely fast transition
logic is used, a 2kΩ series resistor between the logic gate
and the DIS input pin provides adequate bandlimiting using
just the parasitic input capacitance on the DIS pin while still
ensuring an adequate logic level swing.
THERMAL ANALYSIS
Q1
25kΩ
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Typical
Characteristics show these glitches for the circuit of Figure 1
with the input signal set to 0V. The glitch waveform at the
output pin is plotted along with the DIS pin voltage.
Operating junction temperature (TJ) is given by TA + PD • θJA.
The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output
stage (PDL) to deliver load power. Quiescent power is simply
the specified no-load supply current times the total supply
voltage across the part. PDL depends on the required output
signal and load but, for a grounded resistive load, be at a
maximum when the output is fixed at a voltage equal to
1/2 of either supply voltage (for equal bipolar supplies). Under
this condition PDL = VS2/(4 • RL), where RL includes feedback
network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using an
OPA3692 in the circuit of Figure 1 operating at the maximum
specified ambient temperature of +85°C with all three outputs
driving a grounded 100Ω load to +2.5V:
PD = 10V • 17.4mA + 3 (52/(4 • (100Ω || 804Ω)) = 384mW
Maximum TJ = +85°C + (0.384W • 100°C/W) = 123.4°C
This worst-case condition is within the maximum junction
temperature. Normally, this extreme case is not encountered.
Careful attention to internal power dissipation is required.
OPA3692
www.ti.com
SBOS228E
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency amplifier like the OPA3692 requires careful attention to board
layout parasitics and external component types. Recommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output pin can cause instability: on the noninverting input, it
can react with the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all of the
ground and power planes around those pins. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.
b) Minimize the distance (< 0.25") from the power-supply
pins to high frequency 0.1µF decoupling capacitors. At
the device pins, the ground and power plane layout should
not be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections (on pins 9, 11, 13, and 15) should always be
decoupled with these capacitors. An optional supply
decoupling capacitor across the two power supplies (for
bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors,
effective at lower frequency, should also be used on the main
supply pins. These may be placed somewhat farther from the
device and may be shared among several devices in the
same area of the PCB.
c) Careful selection and placement of external components will preserve the high-frequency performance of
the OPA3692. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a tighter
overall layout. Metal-film and carbon composition, axiallyleaded resistors can also provide good high-frequency performance. Again, keep their leads and PCB trace length as
short as possible. Never use wirewound type resistors in a
high-frequency application. Other network components, such
as noninverting input termination resistors, should also be
placed close to the package.
d) Connections to other wideband devices on the board
may be made with short direct traces or through onboard transmission lines. For short connections, consider
the trace and the input to the next device as a lumped
capacitive load. Relatively wide traces (50mils to 100mils)
should be used, preferably with ground and power planes
opened up around them. Estimate the total capacitive load
and set RS from the plot of recommended RS versus Capacitive Load. Low parasitic capacitive loads (< 5pF) may not
need an RS because the OPA3692 is nominally compensated to operate with a 2pF parasitic load. If a long trace is
required, and the 6dB signal loss intrinsic to a doublyterminated transmission line is acceptable, implement a
matched impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a
higher impedance environment will improve distortion as
shown in the Distortion versus Load plots. With a characteristic board trace impedance defined based on board material
and trace dimensions, a matching series resistor into the
trace from the output of the OPA3692 is used as well as a
terminating shunt resistor at the input of the destination
device. Remember also that the terminating impedance will
be the parallel combination of the shunt resistor and the input
impedance of the destination device; this total effective
impedance should be set to match the trace impedance. The
high output voltage and current capability of the OPA3692
allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt
terminations. If the 6dB attenuation of a doubly-terminated
transmission line is unacceptable, a long trace can be seriesterminated at the source end only. Treat the trace as a
capacitive load in this case and set the series resistor value
as shown in the plot of RS versus Capacitive Load. This will
not preserve signal integrity as well as a doubly-terminated
line. If the input impedance of the destination device is low,
there will be some signal attenuation due to the voltage
divider formed by the series output into the terminating
impedance.
e) Socketing a high-speed part like the OPA3692 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA3692
onto the board.
INPUT AND ESD PROTECTION
The OPA3692 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins have limited ESD protection using internal diodes to the power supplies as shown in
Figure 9.
+V CC
External
Pin
–V CC
FIGURE 9. Internal ESD Protection.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (for example, in systems with ±15V
supply parts driving into the OPA3692), current-limiting series resistors should be added into the two inputs. Keep
these resistor values as low as possible since high values
degrade both noise performance and frequency response.
OPA3692
SBOS228E
Internal
Circuitry
www.ti.com
17
Revision History
DATE
REVISION
PAGE
12/08
E
2
6/06
D
SECTION
DESCRIPTION
Absolute Maximum Ratings Changed minimum Storage Temperature Range from −40°C to −65°C.
13
Design-In Tools
18
Applications Information
Demonstration fixture numbers changed.
Added Revision History table.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
18
OPA3692
www.ti.com
SBOS228E
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
OPA3692ID
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA3692
OPA3692IDBQR
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
3692
OPA3692IDBQRG4
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
3692
OPA3692IDBQT
ACTIVE
SSOP
DBQ
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
3692
OPA3692IDBQTG4
ACTIVE
SSOP
DBQ
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
3692
OPA3692IDG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA3692
OPA3692IDR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA3692
OPA3692IDRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA3692
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
OPA3692IDBQR
SSOP
DBQ
16
OPA3692IDBQT
SSOP
DBQ
OPA3692IDR
SOIC
D
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
5.2
2.1
8.0
12.0
Q1
2500
330.0
12.4
6.4
16
250
180.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA3692IDBQR
SSOP
DBQ
16
2500
367.0
367.0
35.0
OPA3692IDBQT
SSOP
DBQ
16
250
210.0
185.0
35.0
OPA3692IDR
SOIC
D
16
2500
367.0
367.0
38.0
Pack Materials-Page 2
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