TI HD3SS3412RUAR 4-channel high-performance differential switch Datasheet

HD3SS3412
www.ti.com
SLAS828A – FEBRUARY 2012 – REVISED FEBRUARY 2012
4-Channel High-Performance Differential Switch
1
B1+
B1C0+
NC
Top View
RUA
Package
GND
VDD
A1+
C0C1+
A1NC
C1VDD
SEL
GND
B2+
A2+
B2-
A2-
B3+
VDD
GND
B3C2+
GND
Pad
A3+
C2-
GND
21
VDD
22
18
21
C3+
C3-
17
22
A3GND
38
39
42
B0+
B0-
18
Desktop and Notebook PCs
Server/Storage Area Networks
PCI Express Backplanes
Shared I/O Ports
A0+
A0-
17
•
•
•
•
38
39
APPLICATIONS
GND
1
•
•
•
42
•
•
Compatible with Multiple Interface Standards
Operating up to 12Gbps Including PCI Express
Gen III and USB 3.0
Wide –3dB Differential BW of over 8GHz
Excellent Dynamic Characteristics (at 4GHz)
– Crosstalk = –35dB
– Off Isolation = –19dB
– Insertion Loss = –1.5dB
– Return Loss = –11dB
VDD Operating Range 3.3 V ±10%
Small 3.5 mm x 9.0 mm, 42-Pin TQFN Package
Common Industry Standard Pinout
NC
GND
•
GND
FEATURES
1
GND
VDD
Check for Samples: HD3SS3412
Figure 1. HD3SS3412 Pinout & Switch Flow
Through Routing
DESCRIPTION
The HD3SS3412 is a high-speed passive switch capable of switching four differential channels, including
applications such as two full PCI Express x1 lanes from one source to one of two target locations in a PC/server
application. With its bidirectional capability the HD3SS3412 will also support applications that allow connections
between one target and two source devices, such as a shared peripheral between two platforms. The
HD3SS3412 has a single control line (SEL Pin) which can be used to control the signal path between Port A and
either Port B or Port C.
The HD3SS3412 is offered in an industry standard 42-pin QFN package available in a common footprint shared
by several other vendors. The device is specified to operate from a single supply voltage of 3.3V over the full
industrial temperature range of –40°C to 85ºC
The HD3SS3412 is a generic 4-CH high speed mux/demux type of switch that can be used for routing highspeed signals between two different locations on a circuit board. Although it was designed specifically to address
PCI Express Gen III applications, the HD3SS3412 will also support several other high-speed data protocols with
a differential amplitude of <1800mVpp and a common mode voltage of <2.0V, as with USB 3.0 and DisplayPort
1.2. The device’s one select input (SEL) pin can easily be controlled by an available GPIO pin within a system or
from a micro-controller.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2012 , Texas Instruments Incorporated
HD3SS3412
SLAS828A – FEBRUARY 2012 – REVISED FEBRUARY 2012
www.ti.com
ORDERING INFORMATION (1)
(1)
PART NUMBER
PART MARKING
PACKAGE
HD3SS3412RUAR
HD3SS3412
42-pin RUA Reel (Large)
HD3SS3412RUAT
HD3SS3412
42-pin RUA Reel (Small)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com
Table 1. HD3SS3412 Control Logic
CONTROL PIN (SEL)
PORT A TO PORT B CONNECTION STATUS
PORT A TO PORT C CONNECTION STATUS
L (Default State)
Connected
Disconnected
H
Disconnected
Connected
FUNCTIONAL DIAGRAM
VDD
MUX 0
B0+
B0C0+
C0-
A0+
A0SEL
SEL
100kO
C1+
C1-
SEL
MUX 1
B1+
B1-
A1+
A1-
SEL
C2+
C2-
MUX 2
B2+
B2A2+
A2-
C3+
C3-
MUX 3
SEL
B3+
B3-
A3+
A3-
GND
PIN FUNCTIONS
PIN
PIN NAME
I/O
DESCRIPTION
2
3
A0+
A0–
I/O
Port A, Channel 0, High Speed Positive Signal
Port A, Channel 0, High Speed Negative Signal
6
7
A1+
A1–
I/O
Port A, Channel 1, High Speed Positive Signal
Port A, Channel 1, High Speed Negative Signal
SWITCH PORT A
2
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PIN FUNCTIONS (continued)
PIN
PIN NAME
11
12
A2+
A2–
I/O
I/O
Port A, Channel 2, High Speed Positive Signal
Port A, Channel 2, High Speed Negative Signal
DESCRIPTION
15
16
A3+
A3–
I/O
Port A, Channel 3, High Speed Positive Signal
Port A, Channel 3, High Speed Negative Signal
38
37
B0+
B0–
I/O
Port B, Channel 0, High Speed Positive Signal
lPort B, Channel 0, High Speed Negative Signal
36
35
B1+
B1–
I/O
Port B, Channel 1, High Speed Positive Signal
Port B, Channel 1, High Speed Negative Signal
29
28
B2+
B2–
I/O
Port B, Channel 2, High Speed Positive Signal
Port B, Channel 2, High Speed Negative Signal
27
26
B3+
B3–
I/O
Port B, Channel 3, High Speed Positive Signal
Port B, Channel 3, High Speed Negative Signal
34
33
C0+
C0–
I/O
Port C, Channel 0, High Speed Positive Signal
Port C, Channel 0, High Speed Negative Signal
32
31
C1+
C1–
I/O
Port C, Channel 1, High Speed Positive Signal
Port C, Channel 1, High Speed Negative Signal
25
24
C2+
C2–
I/O
Port C, Channel 2, High Speed Positive Signal
Port C, Channel 2, High Speed Negative Signal
23
22
C3+
C3–
I/O
Port C, Channel 3, High Speed Positive Signal
Port C, Channel 3, High Speed Negative Signal
9
SEL
I
5, 13, 20, 30, 40
VDD
Supply
Positive power supply voltage
1, 4, 10, 14, 17,
19, 21, 39, 41, Center
Pad
GND
Supply
Negative power supply voltage
8, 18, 42
NC
SWITCH PORT B
SWITCH PORT C
CONTROL, SUPPLY, AND NO CONNECT
Select between port B or port C. Internally tied to GND via 100kΩ resistor
Electrically not connected
Table 2. MUX Pin Connections (1)
PORT A CHANNEL
(1)
PORT B OR PORT C CHANNEL
CONNECTED TO PORT A CHANNEL
SEL = L
SEL = H
A0+
B0+
C0+
A0–
B0–
C0–
A1+
B1+
C1+
A1–
B1–
C1–
A2+
B2+
C2+
A2–
B2–
C2–
A3+
B3+
C3+
A3–
B3–
C3–
The HD3SS3412 can tolerate polarity inversions for all differential signals on Ports A, B and C. Care
should be taken to ensure the same polarity is maintained on Port A vs. Port B/C.
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HD3SS3412
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HD3SS3412
Chipset
Memory/GPU
Hub
Port B
x2
Port C
x2
Port B
x2
Port C
x2
x8
x16
HD3SS3412
Chipset
I/O Hub
HD3SS3412
iGPU
GPIO
Port B
x2
Port C
x2
x8 Graphics Card Slot
Port A
x2
x16 Graphics Card Slot
Microprocessor
HD3SS3412
TYPICAL APPLICATION
Port B
x2
Port C
x2
SEL Pins
ABSOLUTE MAXIMUM RATINGS (1) (2)
Over operating free-air temperature range (unless otherwise noted)
VALUE
Supply voltage range (VDD)
Voltage range
Electrostatic discharge
(1)
(2)
(3)
(4)
MIN
MAX
Absolute minimum/maximum supply voltage range
–0.5
4
Differential I/O
–0.5
4
Control pin (SEL)
–0.5
VDD+0.5
Human body model (3)
±4,000
Charged-device model (4)
±1,500
UNIT
V
V
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC/ESDA JS-001-2011
Tested in accordance with JEDEC JESD22 C101-E
THERMAL INFORMATION
THERMAL METRIC (1)
HD3SS3412
42-PIN TQFN (RUA)
θJA
Junction-to-ambient thermal resistance
53.8
θJCtop
Junction-to-case (top) thermal resistance
38.2
θJCbot
Junction-to-case (bottom) thermal resistance
21.9
θJB
Junction-to-board thermal resistance
27.4
ψJT
Junction-to-top characterization parameter
5.6
ψJB
Junction-to-board characterization parameter
Device Power Dissipation (PD)
(1)
4
UNITS
°C/W
27.3
15.5 (Typ)
21.6 (Max)
mW
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLAS828A – FEBRUARY 2012 – REVISED FEBRUARY 2012
RECOMMENDED OPERATING CONDITIONS
Typical values for all parameters are at VDD = 3.3V and TA = 25°C. (Temperature limits are specified by design)
MIN
TYP
3.3
MAX
UNIT
VDD
Supply voltage
3.0
3.6
V
VIH
Input high voltage (SEL Pin)
2.0
VDD
V
VIL
Input low voltage (SEL Pin)
–0.1
0.8
V
VI/O_Diff
Differential voltage (differential pins) Switch I/O diff voltage
0
1.8
VPP
VI/O_CM
Common voltage (differential pins)
Switch I/O common mode voltage
0
2.0
TA
Operating free-air temperature
Ambient temperature
–40
85
V
o
C
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DEVICE PARAMETERS
IIH
Input High Voltage (SEL)
VDD = 3.6 V; VIN = VDD
95
µA
IIL
Input Low Voltage (SEL)
VDD = 3.6 V; VIN = GND
1
µA
ILK
Leakage Current (Differential
I/O pins)
VDD = 3.6 V; VIN = 0 V; VOUT = 2 V
(ILK On OPEN outputs) [Ports B and C]
130
µA
VDD = 3.6 V, VIN = 2 V; VOUT = 0 V
(ILK On OPEN outputs) [Port A]
4
IDD
Supply Current
VDD = 3.6 V; SEL = VDD/GND; Outputs Floating
4.7
CON
Outputs ON Capacitance
VIN = 0 V; Outputs Open; Switch ON
1.5
COFF
Outputs OFF Capacitance
VIN = 0 V; Outputs Open, Switch OFF
1
RON
Output ON resistance
VDD = 3.3 V; VCM = 0.5 V to 1.5 V ; IO = –8 mA
5
On resistance match between
channels
ΔRON
RFLAT_ON
6
mA
pF
pF
8
Ω
VDD = 3.3 V ; –0.35 V ≤ VIN ≤ 1.2 V; IO = –8 mA
2
Ω
On resistance match between
pairs of the same channel
VDD = 3.3 V; –0.35 V ≤ VIN ≤ 1.2 V; IO = –8 mA
0.7
Ω
On resistance flatness
(RON(MAX) – RON(MAIN)
VDD = 3.3 V; –0.35 V ≤ VIN ≤ 1.2 V
1.15
Ω
85
ps
DEVICE PARAMETERS (Continued) RSC and RLOAD = 50Ω and CL = 50 pF unless otherwise noted
tPD
Switch propagation delay
SEL-to-switch Ton
SEL-to-switch Toff
TSKEW_Inter
Inter-pair output skew (CHCH)
Rsc and RLOAD = 50Ω
Rsc and RLOAD = 50Ω
70
250
70
250
Rsc and RLOAD = 50Ω
TSKEW_Intra Intra-pair output skew (bit-bit)
RL
XTALK
OIRR
IL
BW
Differential return loss (VCM = f = 0.3 MHz
0V)
f = 2500 MHz
Also see typical plots section
f = 4000 MHz
ns
20
ps
8
ps
–28
–12
dB
–11
Differential Crosstalk(VCM =
0V)
Also see typical plots section
f = 0.3 MHz
–90
f = 2500 MHz
–39
f = 4000 MHz
–35
Differential Off-Isolation(VCM
= 0V)
Also see typical plots section
f = 0.3 MHz
–75
f = 2500 MHz
–22
f = 4000 MHz
–19
Differential Insertion Loss
(VCM = 0V)
Also see typical plots section
f = 0.3 MHz
–0.5
f = 2500 MHz
–1.1
f = 4000 MHz
–1.5
Band Width
At –3 dB
8
dB
dB
dB
GHz
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TEST TIMING DIAGRAMS
Select to Switch Output On (TON) and Off (TOFF)
50%
SEL
90%
VOUT
10%
Toff
Ton
Figure 2. Switch On/Off Timing Diagram
Propagation Delay and Skew
VDD
RSC = 50W
An+
RSC = 50W
HD3SS3412
Bn+/Cn+
RL = 50W
An-
Bn-/CnRL = 50W
SEL
VDD
VIN+
50%
50%
50%
50%
0V
VDD
VIN-
0V
VDD
VOUT+
50%
50%
50%
50%
0V
VDD
VOUT+
0V
tP1
tP1
TSKEWInter = Difference between tPD for any two pairs of outputs
TSKEWIntra = Difference between tP1 and tP2 of same pair
Figure 3. Propagation Delay Timing Diagram and Test Setup
6
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SLAS828A – FEBRUARY 2012 – REVISED FEBRUARY 2012
TYPICAL PERFORMANCE PLOTS
0
m1
5
m2 m3
m1
freq=300.0kHz
freq=300.0kHz
dB(SDD21)=-0.491
m4
-2
-5
m2
freq= 2.514GHz
dB(SDD21)=-1.221
-6
-8
dB(SDD11)
-4
dB(SDD21)
m5
freq= 329.0kHz
dB(SDD11)=-28.545
0
m3
freq= 3.985GHz
dB(SDD21)=-1.536
-10
-12
-14
-15
m7
freq= 3.985GHz
dB(SDD11)=-11.177
-20
-25
m5
-30
2E10
1E10
1E9
1E8
1E7
1E6
2E10
1E10
1E9
1E8
1E7
1E6
m4
freq= 8.331GHz
dB(SDD21)=-2.998
freq, Hz
freq, Hz
Figure 4. Differential Insertion Loss
-20
Figure 5. Differential Return Loss
0
m1
freq=300.0kHz
dB(SDD21)=-97.081
-40
m2
freq=2.514GHz
dB(SDD21)=-39.567
-60
-80
m3
freq=3.985GHz
dB(SDD21)=-34.786
m1
-100
m1
freq=300.0kHz
dB(SDD21)=-74.449
m2 m3
-20
dB(SDD21)
m3
m2
dB(SDD21)
m6
freq= 2.514GHz
dB(SDD11)=-13.842
m7
m6
-10
m2
freq=2.514GHz
dB(SDD21)=-22.000
-40
-60
m1
m3
freq=3.985GHz
dB(SDD21)=-18.935
-80
-100
2E10
1E10
1E9
1E8
1E7
2E10
1E10
1E9
1E8
1E7
1E6
1E6
-120
freq, Hz
freq, Hz
Figure 6. Differential Crosstalk
Figure 7. Differential Off Isolation
SOURCE EYE DIAGRAM
A
3.1 Inches Rogers
Microstrip
Oscilloscope
10Gbps PRBS 2 7- 1
Vi=0.8Vpp ; Vcm =0V
Figure 8. Source Eye Diagram Test Setup
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TYPICAL PERFORMANCE PLOTS (continued)
Figure 9. 10Gbps Source Eye Diagram at A: VID = 800mVpp; 27-1 PRBS; VCM=0V
A
1.4 Inches
Rogers
Microstrip
1.7 Inches
Rogers
Microstrip
7
10Gbps PRBS 2 - 1
Vi=0.8Vpp ; Vcm =0V
Oscilloscope
Figure 10. Output Eye Diagram Test Setup
8
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TYPICAL PERFORMANCE PLOTS (continued)
Figure 11. 10Gbps Output Eye Diagram at A: VID = 800mVpp; 27-1 PRBS; VCM= 0V; VDD= 3.3v; SEL= 0V
CROSS TALK MEASUREMENT SETUP
Network
Analyzer
P2
P1
VDD
A0+
B0+
100 W
A0B0HD3SS3412
SEL
A1+
B1+
100 W
A1B1-
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TYPICAL PERFORMANCE PLOTS (continued)
OFF ISOLATION MEASUREMENT SETUP
Network
Analyzer
P2
P1
VDD
A0+
B0+
A0-
100 W
B0-
HD3SS3412
SEL
B1+
B1-
10
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SLAS828A – FEBRUARY 2012 – REVISED FEBRUARY 2012
REVISION HISTORY
NOTE: Page numbers of current version may differ from previous versions.
Changes from Original (February 2012 ) to Revision A
Page
•
Changed Differential BW Feature bullet from "7.5GHZ" to "8GHz" ...................................................................................... 1
•
Changed Dynamic Characteristics Feature sub-bullet from "Isolation" to "Off Isolation" ..................................................... 1
•
Changed Dynamic Characteristics sub-bullet Return Loss from "-9dB" to "-11dB" ............................................................. 1
•
Deleted Dynamic Characteristics sub-bullet "Max Intra-Pair (Bit-Bit) Skew" ........................................................................ 1
•
Changed ESD, Human body model, MAX voltage from "±2000" to "±4,000" in Absolute Maximum Ratings table ............. 4
•
Deleted ESD, Machine model spec from Absolute Maximum Ratings table ........................................................................ 4
•
Changed ILK spec (Diff I/O pins) MAX value from "4 µA" to "130 µA" and added [Ports B and C] and [Port A] to
Conditions statements. ......................................................................................................................................................... 5
•
Changed tPD spec MAX delay from "50" ps to "85" ps in Device Parameters table ............................................................. 5
•
Changed SEL-to-switch Ton and Toff spec TYP values from "175" ns to "70" ns; in the Device Parameters table .............. 5
•
Changed TSKEW_Inter and TSKEW_Intra spec MAX values from "5 ps" and "4 ps" respectively, to "20 ps" and "8 ps"
respectively, in Electrical Characteristics table. .................................................................................................................... 5
•
Changed RL spec TYP value from "–25" and "–9" dB to "–28" and "–11" dB for f=0.3 MHz and f=4000 MHz,
respectively, in Electrical Characteristics table. .................................................................................................................... 5
•
Changed OIRR spec TYP value from "–70" to "–75" dB for f=0.3 MHz, in Electrical Characteristics table. .......................... 5
•
Changed BW spec TYP value from "7.5" GHz to "8" GHz in Electrical Characteristics table. ............................................. 5
•
Changed graphic image for Figure 4. ................................................................................................................................... 7
•
Changed graphic image for Figure 5 .................................................................................................................................... 7
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Feb-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
HD3SS3412RUAR
ACTIVE
WQFN
RUA
42
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-2-260C-1 YEAR
HD3SS3412RUAT
ACTIVE
WQFN
RUA
42
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-May-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
HD3SS3412RUAR
WQFN
RUA
42
3000
330.0
16.4
3.8
9.3
1.0
8.0
16.0
Q1
HD3SS3412RUAT
WQFN
RUA
42
250
180.0
16.4
3.8
9.3
1.0
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-May-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
HD3SS3412RUAR
WQFN
RUA
42
3000
346.0
346.0
33.0
HD3SS3412RUAT
WQFN
RUA
42
250
210.0
185.0
35.0
Pack Materials-Page 2
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