ON FDMF301155 Smart power stage (sps) module Datasheet

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FDMF301155 – Smart Power Stage (SPS) Module
Features
 Supports PS4 Mode for IMVP-8
 Ultra-Compact 5 mm x 5 mm PQFN Copper-Clip
Package with Flip Chip Low-Side MOSFET




High Current Handling: 50 A

Fairchild PowerTrench MOSFETs for Clean
Voltage Waveforms and Reduced Ringing

Fairchild SyncFET™ Technology (Integrated
Schottky Diode) in Low-Side MOSFET





Integrated Bootstrap Schottky Diode

Fairchild Green Packaging and RoHS Compliance
3-State 5V PWM Input Gate Driver
Low Shutdown Current IVCC < 6 µA
Diode Emulation for Enhanced Light Load
Efficiency
®
Description
The SPS family is Fairchild’s next-generation, fully
optimized, ultra-compact, integrated MOSFET plus
driver power stage solution for high-current, highfrequency, synchronous buck, DC-DC applications. The
FDMF301155 integrates a driver IC with a bootstrap
Schottky diode and two power MOSFETs into a
thermally enhanced, ultra-compact 5 mm x 5 mm
package.
With an integrated approach, the SPS switching power
stage is optimized for driver and MOSFET dynamic
performance, minimized system inductance, and power
MOSFET RDS(ON). The SPS family uses Fairchild's high®
performance PowerTrench
MOSFET technology,
which reduces switch ringing, eliminating the need for a
snubber circuit in most buck converter applications.
Optimized for Switching Frequencies up to 1.5 MHz
A driver IC with reduced dead times and propagation
delays further enhances the performance. The
FDMF301155 supports diode emulation (using FCCM
pin) for improved light-load efficiency. The FDMF301155
also provides a 3-state 5 V PWM input for compatibility
with a wide range of PWM controllers.
Operating Junction Temperature Range:
-40°C to +125°C
Applications
Optimized / Extremely Short Dead-Times
Under-Voltage Lockout (UVLO) on VCC

Notebook, Tablet PC and Ultrabook

Servers and Workstations, V-Core and Non-V-Core
DC-DC Converters

Desktop and All-in-One Computers, V-Core and
Non-V-Core DC-DC Converters

High-Current DC-DC Point-of-Load Converters

Small Form-Factor Voltage Regulator Modules
Ordering Information
Part Number
Current Rating
Package
Top Mark
FDMF301155
50 A
31-Lead, Clip Bond PQFN SPS, 5.0 mm x 5.0 mm Package
FDMF301155
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
www.onsemi.com
FDMF301155 — Smart Power Stage (SPS) Module
November 2016
FDMF301155 — Smart Power Stage (SPS) Module
Application Diagram
V5V
VIN
CPVCC
PVCC
PWM Input
CVCC
RVCC
VCC
CVIN
VIN
GL
PWM
RBOOT
BOOT
FDMF301155
CBOOT
PHASE
LOUT
FCCM
FCCM Input
SW
VOUT
VSW
AGND
Figure 1.
PGND
COUT
Typical Application Diagram
Functional Block Diagram
VCC
PVCC
BOOT
VCC
VIN
PHASE
DBoot
↓
10uA
↓
10uA
(Q1)
High Side
MOSFET
FCCM
LEVEL
SHIFT
SW
SHOOT- THROUGH
PROTECTION
10k
PWM
HDRV
(Q2)
Low Side
MOSFET
PVCC
CONTROL
LOGIC
LDRV
GL
PGND
AGND
Figure 2.
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
Functional Block Diagram
www.onsemi.com
2
31
N/C
30
N/C
29
1
PVCC
28
2
PGND
PGND
27
3
GL
PGND
26
4
SW
PGND
14
25
5
SW
PGND
15
24
6
13
VIN
7
SW
32
AGND
29
VIN
11
11
30
8
12
FDMF301155
VIN
10
10
31
9
9
PWM
1
FCCM
2
VCC
3
AGND
4
BOOT
5
N/C
6
PHASE
7
VIN
8
28
16
17
18
19
20
21
Figure 3.
22
23
16
17
18
19
20
21
22
23
SW
24
SW
15
SW
25
SW
14
SW
26
SW
13
33
GL
SW
27
SW
12
Pin Configuration - Top View and Transparent View
Pin Definitions
Pin #
Name
Description
1
PWM
PWM input to the gate driver IC
2
FCCM
The FCCM pin enables or disables Diode Emulation. When FCCM is LOW, diode
emulation is allowed. When FCCM is HIGH, continuous conduction mode is forced. High
impedance on the input of FCCM will shut down the driver IC (and module).
3
VCC
4, 32
AGND
Analog ground for analog portions of the IC and for substrate, pin 4 and pin 32 are
internally fused (shorted)
5
BOOT
Supply for high-side MOSFET gate driver. A capacitor from BOOT to PHASE supplies the
charge to turn on the N-channel high-side MOSFET. During the freewheeling interval (LS
MOSFET on), the high side capacitor is recharged by an internal diode connected to
PVCC.
6, 30, 31
N/C
Power supply input for all analog control functions; this is the “quiet” VCC
No connect
7
PHASE
8~11
VIN
Return connection for the boot capacitor
Power input for the power stage
12~15, 28
PGND
Power return for the power stage
16~26
SW
Switching node junction between high and low side MOSFETs; also the input into both the
gate driver SW node comparator and the ZCD comparator
27, 33
GL
Low-side MOSFET gate monitor
29
PVCC
(1)
Power supply input for LS
gate driver and boot diode
Note:
1. LS = Low Side.
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
www.onsemi.com
3
FDMF301155 — Smart Power Stage (SPS) Module
Pin Configuration
Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. TA = TJ = 25°C
Symbol
VCC
Parameter
Min.
Max.
Unit
Supply Voltage
Referenced to AGND
-0.3
7.0
V
PVCC
Drive Voltage
Referenced to AGND
-0.3
7.0
V
VPWM
PWM Signal Input
Referenced to AGND
-0.3
VCC+0.3
V
VFCCM
Skip Mode Input
Referenced to AGND
-0.3
VCC+0.3
V
VGL
Low Gate Manufacturing Test
Pin
Referenced to PGND (DC)
GND-0.3
VCC+0.3
V
Referenced to PGND (AC < 20 ns, 10 µJ)
GND-0.3
VCC+0.3
V
VIN
Power Input
Referenced to PGND
-0.3
30.0
V
Referenced to PGND (DC)
-0.3
30.0
Referenced to PGND (AC < 20 ns, 10 µJ)
-8.0
30.0
Referenced to AGND (DC)
-0.3
33.0
V
DC
-0.3
7.0
V
AC < 20 ns, 10 µJ
-0.3
9.0
V
VPHASE
VSW
PHASE and SW
VBOOT
Bootstrap Supply
VBOOT-PHASE Boot to PHASE Voltage
IO(AV)
(2)
θJ-A
θJ-PCB
Output Current
fSW=300 kHz, VIN=12 V, VOUT=1 V
50
fSW=1000 kHz, VIN=12 V, VOUT=1 V
45
V
A
Junction-to-Ambient Thermal Resistance
12.4
°C/W
Junction-to-PCB Thermal Resistance (under Fairchild SPS Thermal Board)
1.8
°C/W
+125
°C
+150
°C
+150
°C
TA
Ambient Temperature Range
TJ
Maximum Junction Temperature
TSTG
Storage Temperature Range
ESD
Electrostatic Discharge
Protection
-40
-55
Human Body Model, JESD22-A114
1.5
Charged Device Model, JESD22-C101
2.5
kV
Note:
2. IO(AV) is rated with testing Fairchild’s SPS evaluation board at TA = 25°C with natural convection cooling. This
rating is limited by the peak SPS temperature, TJ = 150°C, and varies depending on operating conditions and
PCB layout. This rating may be changed with different application settings.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
Operating Conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC
PVCC
Parameter
Min.
Typ.
Max.
Unit
Control Circuit Supply Voltage
4.5
5.0
5.5
V
Gate Drive Circuit Supply Voltage
4.5
5.0
5.5
V
(3)
(4)
VIN
Output Stage Supply Voltage
4.5
12.0
24.0
V
Notes:
3. 3.0 V VIN is possible according to the application condition.
4. Operating at high VIN can create excessive AC voltage overshoots on the SW-to-GND and BOOT-to-GND nodes
during MOSFET switching transient. For reliable SPS operation, SW to GND and BOOT to GND must remain at
or below the Absolute Maximum Ratings in the table above.
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
www.onsemi.com
4
FDMF301155 — Smart Power Stage (SPS) Module
Absolute Maximum Ratings
Typical value is under VIN=12 V, VCC=PVCC=5 V and TA=TJ=+ 25°C unless otherwise noted. Minimum / Maximum
values are under VIN=12 V, VCC=PVCC=5 V ± 10% and TJ=TA=-40 ~ 125°C unless otherwise noted.
Symbol
Parameter
Condition
Min. Typ.
Max.
Unit
11
µA
Basic Operation
ICC_SD
Quiescent Current with PWM
and FCCM Pin Floating (PS4
Mode)
ICC=IVCC + IPVCC, PWM=Floating,
FCCM=Floating (Non-Switching)
6
ICC_HIGH
Quiescent Current with PWM Pin ICC=IVCC + IPVCC, PWM=Floating,
Floating and VFCCM=5 V
FCCM=5 V
80
µA
ICC_LOW
Quiescent Current with PWM Pin ICC=IVCC + IPVCC, PWM=Floating,
Floating and VFCCM=0 V
FCCM=0V
120
µA
VUVLO_RISE
UVLO Rising Threshold
VCC Rising
3.4
VUVLO_FALL
UVLO Falling Threshold
VCC Falling
POR Delay to Enable IC
VCC UVLO Rising to Internal PWM
Enable
IFCCM_HIGH
Pull-Up Current
VFCCM=5 V
IFCCM_LOW
Pull-Down Current
VFCCM=0 V
VIH_FCCM
FCCM High Level Input Voltage
VCC=PVCC=5 V
3.8
VTRI_FCCM
FCCM 3-State Window
VCC=PVCC=5 V
2.2
2.8
V
VIL_FCCM
FCCM Low Level Input Voltage
VCC=PVCC=5 V
1.0
V
tPS_EXIT
PS4 Exit Latency
VCC=PVCC=5 V
15
µs
IPWM_HIGH
Pull-Up Current
VFCCM=5 V
250
µA
IPWM_LOW
Pull-Down Current
VFCCM=0 V
-250
µA
tD_POR
2.5
3.9
V
3.0
V
15
µs
FCCM Input
50
µA
-50
µA
V
PWM Input
VIH_PWM
PWM High Level Input Voltage
VCC=PVCC=5 V
4.1
VTRI_PWM
PWM 3-State Window
VCC=PVCC=5 V
1.6
VIL_PWM
PWM Low Level Input Voltage
VCC=PVCC=5 V
3-State Shut-off Time
VCC=PVCC=5 V, TJ=25°C
tD_HOLD-OFF
100
V
3.4
175
V
0.7
V
250
ns
PWM Propagation Delays & Dead Times (VIN=12 V, VCC=PVCC=5 V, fSW=1 MHz, IOUT=20 A, TA=25°C)
tPD_PHGLL
PWM HIGH Propagation Delay
PWM Going HIGH to GL Going
LOW, VIH_PWM to 90% GL
25
ns
(5)
tPD_PLGHL
PWM LOW Propagation Delay
PWM Going LOW to GH Going
LOW, VIL_PWM to 90% GH
15
ns
tPD_PHGHH
PWM HIGH Propagation Delay
(FCCM Held LOW)
PWM Going HIGH to GH Going
HIGH, VIH_PWM to 10% GH
(FCCM=LOW, IL=0, Assumes DCM)
15
ns
tPD_TSGHH
Exiting 3-State Propagation
Delay
PWM (from 3-State) Going HIGH to
GH Going HIGH, VIH_PWM to 10% GH
35
ns
tPD_TSGLH
Exiting 3-State Propagation
Delay
PWM (from 3-State) Going LOW to
GL Going HIGH, VIL_PWM to 10% GL
35
ns
tD_DEADON
LS Off to HS On Adaptive Dead
Time
SW <= -0.2 V with GH <= 10%, PWM
Transition LOW to HIGH
25
ns
tD_DEADOFF
HS Off to LS On Adaptive Dead
Time
SW <= -0.2 V with GL <= 10%, PWM
Transition HIGH to LOW
20
ns
Note:
5. GH = Gate High, internal gate pin of the high-side MOSFET.
Continued on the following page…
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
www.onsemi.com
5
FDMF301155 — Smart Power Stage (SPS) Module
Electrical Characteristics
Typical value is under VIN=12 V, VCC=PVCC=5 V and TA=TJ=+ 25°C unless otherwise noted. Minimum / Maximum
values are under VIN=12 V, VCC=PVCC=5 V ± 10% and TJ=TA=-40 ~ 125°C unless otherwise noted.
Symbol
Parameter
Condition
Min. Typ.
Max.
Unit
2.5
Ω
2.5
Ω
High-Side Driver (HDRV, VCC = PVCC = 5 V)
RSOURCE_GH
Output Impedance, Sourcing
Source Current=100 mA
ISOURCE_GH
Output Sourcing Peak Current
GH=2.5 V
RSINK_GH
Output Impedance, Sinking
Sink Current=100 mA
ISINK_GH
1.0
2
1.0
A
Output Sinking Peak Current
GH=2.5 V
4
A
tR_GH
GH Rise Time
GH=10% to 90%, CLOAD=3.0 nF
8
ns
tF_GH
GH Fall Time
GH=90% to 10%, CLOAD=3.0 nF
8
ns
Low-Side Driver (LDRV, VCC=PVCC = 5 V)
RSOURCE_GL
Output Impedance, Sourcing
Source Current=100 mA
ISOURCE_GL
Output Sourcing Peak Current
GL=2.5 V
RSINK_GL
Output Impedance, Sinking
Sink Current=100 mA
ISINK_GL
1.0
2.5
Ω
2
A
0.5
Ω
Output Sinking Peak Current
GL=2.5 V
4
A
tR_GL
GL Rise Time
GL=10% to 90%, CLOAD=3.0 nF
8
ns
tF_GL
GL Fall Time
GL=90% to 10%, CLOAD=3.0 nF
4
ns
VF
Forward-Voltage Drop
IF=10 mA
0.6
V
VR
Breakdown Voltage
IR=1 mA
Boot Diode
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
30
V
www.onsemi.com
6
FDMF301155 — Smart Power Stage (SPS) Module
Electrical Characteristics
50
55
45
50
Module Output Current, Iout (A)
Module Output Current, Iout (A)
Test Conditions: VIN=12 V, VCC=PVCC=5 V, VOUT=1 V, LOUT=250 nH, TA=25°C and natural convection cooling, unless
otherwise noted.
40
35
PCB Temp 300kHz [C]
30
PCB Temp 1000kHz [C]
25
20
15
10
5
45
40
35
PCB Temp 1000kHz [C]
25
20
15
10
5
0
0
25
50
75
100
125
0
150
0
PCB Temp, TPCB (C)
Figure 4.
Safe Operating Area with 12 VIN
Figure 5.
11.0
8.0
12Vi_1Vo_300kHz PVCC & VCC =5V, VOUT = 1V
12Vi_1Vo_500kHz
7.0
12Vi_1Vo_800kHz
12Vi_1Vo_1MHz
Module Power Loss (W)
6.0
50
75
100
125
150
5.0
4.0
3.0
2.0
Safe Operating Area with 19 VIN
19Vi_1Vo_300kHz PVCC & VCC =5V, VOUT = 1V
19Vi_1Vo_500kHz
10.0
1.0
9.0
19Vi_1Vo_800kHz
8.0
19Vi_1Vo_1MHz
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
0.0
0
5
Figure 6.
10
15
20
25
30
Load Current (A)
35
40
45
0
50
Power Loss vs. Output Current
with 12 VIN
5
10
Figure 7.
15
20
25
30
35
Load Current (A)
40
45
50
55
Power Loss vs. Output Current
with 19 VIN
1.4
1.4
PVCC & VCC =5V, VOUT = 1V. FSW = 500kHz, Iout = 30A
Vin = 12V, PVCC & VCC =5V, VOUT = 1V, Iout = 30A
1.3
1.3
1.2
Normalized Module Power Loss (W)
Normalized Module Power Loss (W)
25
PCB Temp, TPCB (C)
9.0
Module Power Loss (W)
PCB Temp 300kHz [C]
30
1.2
1.1
1.1
1.0
1.0
0.9
0.8
0.9
200
300
400
500
600
700
800
900
1000
1100
4
6
Frequency (kHZ)
Figure 8.
10
12
14
16
18
20
VIN (V)
Power Loss vs. Switching Frequency
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
8
Figure 9.
Power Loss vs. Input Voltage
www.onsemi.com
7
FDMF301155 — Smart Power Stage (SPS) Module
Typical Performance Characteristics
Test Conditions: VIN=12 V, VCC=PVCC=5 V, VOUT=1 V, LOUT=250 nH, TA=25°C and natural convection cooling, unless
otherwise noted.
1.4
1.15
Vin = 12V, PVCC & VCC =5V, FSW = 500kHz, Iout = 30A
1.3
1.10
Normalized Power Loss (W)
Normalized Module Power Loss (W)
Vin =12V, VOUT = 1V. FSW = 500kHz, Iout = 30A
1.05
1.00
0.95
1.2
1.1
1.0
0.9
0.8
0.90
4.0
4.5
5.0
5.5
0.5
6.0
1
Figure 10.
Power Loss vs. Driver Supply Voltage
Figure 11.
2
2.5
3
3.5
Power Loss vs. Output Voltage
0.022
0.035
Vin = 12V, PVCC & VCC =5V, VOUT = 1V, Iout = 30A
Vin =12V, VOUT = 1V. FSW = 500kHz, Iout = 30A
Driver Supply Current, I PVCC +I VCC (A)
Driver Supply Current, I PVCC +I VCC (A)
1.5
Module Output Voltage, Vout (V)
Driver Supply Voltage, PVcc & Vcc (V)
0.030
0.025
0.020
0.015
0.020
0.018
0.016
0.014
0.012
0.010
200
300
400
500
600
700
800
900
4.0
1000 1100
Figure 12.
4.5
5.0
5.5
6.0
Driver Supply Voltage, PV cc & Vcc (V)
Frequency (kHZ)
Driver Supply Current vs. Switching
Frequency
Figure 13.
Driver Supply Current vs. Driver
Supply Voltage
1.06
12Vi_1Vo_300kHz
Driver Supply Current, I PVCC +I VCC (A)
1.04
Vin = 12V, PVCC & VCC =5V,
12Vi_1Vo_1MHz
1.02
1.00
0.98
0.96
0.94
0.92
0.90
0
Figure 14.
5
10
15
20
25
30
Load Current (A)
35
40
45
50
Driver Supply Current vs. Output Current
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
www.onsemi.com
8
FDMF301155 — Smart Power Stage (SPS) Module
Typical Performance Characteristics
Test Conditions: VIN=12 V, VCC=PVCC=5 V, VOUT=1 V, LOUT=250 nH, TA=25°C and natural convection cooling, unless
otherwise noted.
3.7
5.0
UVLOUP
PWM Threshold Voltage, VPWM [V]
Driver Supply Voltage, V CC [V]
3.5
3.4
3.3
3.2
3.1
3.0
UVLODN
2.9
-50
-25
Figure 15.
0
25
50
75
100
125
Driver IC Junction Temperature, T J [oC]
150
4.0
VTRI_HI
3.5
3.0
2.5
2.0
VTRI_LO
1.5
1.0
VIL_PWM
0.5
4.50
175
UVLO Threshold vs. Temperature
4.75
5.00
5.25
Driver Supply Voltage, VCC [V]
Figure 16.
5.0
5.50
PWM Threshold vs. Driver Supply Voltage
4.0
VCC = 5V
4.5
TA = 25°C
VIH_PWM
FCCM Threshold Voltage, VFCCM [V]
PWM Threshold Voltage, VPWM [V]
VIH_PWM
0.0
2.8
4.0
VTRI_HI
3.5
3.0
2.5
2.0
VTRI_LO
1.5
1.0
VIL_PWM
0.5
0.0
VIH_FCCM
3.5
VTRI_HI_FCCM
3.0
2.5
VHIZ_FCCM
2.0
VTRI_LO_FCCM
1.5
VIL_FCCM
1.0
-50
-25
Figure 17.
0
25
50
75
100
125
Driver IC Junction Temperature, T J [oC]
150
175
4.50
PWM Threshold vs. Temperature
4.75
5.00
5.25
Driver Supply Voltage, VCC [V]
Figure 18.
4
5.50
FCCM Threshold vs. Driver
Supply Voltage
54
VCC = 5V
VCC = 5V
VIH_FCCM
FCCM Pull-Up Current, IFCCM_HIGH [uA]
FCCM Threshold Voltage, V FCCM [V]
TA = 25°C
4.5
3.6
3.5
VTRI_HI_FCCM
3
2.5
VHIZ_FCCM
2
VTRI_LO_FCCM
1.5
VIL_FCCM
-25
0
25
50
75
100
125
150
50
48
46
44
42
1
-50
52
-50
175
Driver IC Junction Temperature, T J [oC]
Figure 19.
0
25
50
75
100
125
150
175
Driver IC Junction Temperature, T J [oC]
FCCM Threshold vs. Temperature
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
-25
Figure 20.
FCCM Pull-Up Current vs. Temperature
www.onsemi.com
9
FDMF301155 — Smart Power Stage (SPS) Module
Typical Performance Characteristics
Test Conditions: VIN=12 V, VCC=PVCC=5 V, VOUT=1 V, LOUT=250 nH, TA=25°C and natural convection cooling, unless
otherwise noted.
800
10
VCC = 5V, PWM = floating, FCCM = floating
Driver Shut-Down Current, ISHDN [uA]
Boot Diode Forward Voltage, VF [mV]
IF = 10mA
750
700
650
600
550
500
9
8
7
6
5
4
3
-50
-25
0
25
50
75
100
125
Driver IC Junction Temperature, T J [oC]
Figure 21.
150
175
Boot Diode Forward Voltage
vs. Temperature
-50
-25
0
25
50
75
100
125
Driver IC Junction Temperature, T J [oC]
Figure 22.
150
175
Driver Shutdown Current
vs. Temperature
150
Driver Quiescent Current, ICC [uA]
VCC = 5V, PWM = floating
140
FCCM = 0V
130
120
110
100
90
FCCM = 5V
80
70
60
-50
Figure 23.
-25
0
25
50
75
100
125
Driver IC Junction Temperature, T J [oC]
150
175
Driver Quiescent Current vs. Temperature
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
www.onsemi.com
10
FDMF301155 — Smart Power Stage (SPS) Module
Typical Performance Characteristics
VIL_PWM
PWM
tPD_PHGLL = PWM HI to GL LOW, VIH_PWM to 90% GL
GL
90%
90%
10%
10%
GH-PHASE
(internal)
90%
90%
10%
10%
tFALL_GL = 90% GL to 10% GL
tD_DEADON = LS Off to HS On Dead Time, 10% GL to
VBOOT-GND <= PVCC - VF_DBOOT - 1V
tRISE_GH = 10% GH to 90% GH, VBOOT-GND <= PVCC VF_DBOOT - 1V to VSW_PEAK
tPD_PLGHL = PWM LOW to GH LOW, VIL_PWM to 90%
GH, tPD_PLGLH - tD_DEADOFF - tFALL_GH
BOOT-GND
tFALL_GH = 90% GH to 10% GH
PVCC - VF_DBOOT - 1V
tD_DEADOFF = HS Off to LS On Dead Time, VSW <= 0V
to 10% GL
tPD_PLGLH = PWM LOW to GL HI, VIL_PWM to 10% GL
SW
tRISE_GL = 10% GL to 90% GL
tPD_PHGLL
tD_DEADON tRISE_GH
tFALL_GL
tPD_PLGHL
tD_DEADOFF
tFALL_GH
tRISE_GL
tPD_PLGLH
Figure 24.
PWM Timing Diagram
(7)
(7)
VIH_PWM(11)
VIH_PWM
VTRI_HI
VTRI_HI(9)
VTRI_LO(10)
VTRI_LO
VIL_PWM(12)
VIL_PWM
PWM
3-State
Window
3-State
Window
(8)
(8)
GH-PHASE
GL
Figure 25.
PWM Threshold Definition
Notes:
6. The timing diagram in Figure 25 assumes very slow ramp on PWM.
7. Slow ramp of PWM implies the PWM signal remains within the 3-state window for a time >>> tD_HOLD-OFF.
8. VTRI_HI = PWM trip level to enter 3-state on PWM falling edge.
9. VTRI_LO = PWM trip level to enter 3-state on PWM rising edge.
10. VIH_PWM = PWM trip level to exit 3-state on PWM rising edge and enter the PWM HIGH logic state.
11. VIL_PWM = PWM trip level to exit 3-state on PWM falling edge and enter the PWM LOW logic state.
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
www.onsemi.com
11
FDMF301155 — Smart Power Stage (SPS) Module
VIH_PWM
The SPS FDMF301155 is a driver-plus-MOSFET
module optimized for the synchronous buck converter
topology. A PWM input signal is required to properly
drive the high-side and the low-side MOSFETs. The
part is capable of driving speed up to 1.5 MHz.
HIGH, continuous conduction mode is forced. High
impedance on the input of FCCM shuts down the driver
IC (and module).
Table 2.
Power-On Reset (POR & UVLO)
The FDMF301155 incorporates a POR feature that
ensures both LDRV and HDRV are forced inactive
(LDRV = HDRV = 0) until UVLO > 3.4 V (typical rising
threshold). UVLO is performed on VCC (not on PVCC
or VIN).
After all gate drive blocks are fully powered on and
have finished the startup sequence, the internal driver
IC EN_PWM signal is released HIGH, enabling the
driver outputs. Once the driver POR has finished, the
driver follows the state of the PWM signal (it is assumed
that at startup the controller is either in a highimpedance state or forcing the PWM signal to be within
the driver 3-state window).
Disable
Figure 26.
VCC [V]
UVLO
3-State PWM Input
FCCM
GH
GL
3-state
1
0
0
0
1
0
1
1
1
1
0
Driver
Enable State
x
3-State
0
0
0 (ICC < 6 µA)
3-State
0
0
0
1
3-State
1
0
0
1
1
0
0
0
1 when IL > 0
0 when IL < 0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
The FDMF301155 requires four (4) input signals to
perform normal switching operation: VIN, VCC / PVCC,
PWM, and FCCM.
The VIN pins are tied to the system main DC power rail.
The PVCC and VCC pins are typically powered from
the same 5 V source. These pins can be either tied
directly together or tied together through an external RC
filter. The filter resistor / capacitor is used to de-couple
the switching noise from PVCC to VCC. Refer to Figure
1 for RC filter schematic.
FCCM
The FCCM pin can be used to control Diode Emulation
or used to shutdown the driver IC (with ICC < 6 µA, ICC =
current consumed by VCC and PVCC). When FCCM is
LOW, diode emulation is allowed. When FCCM is
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
GL
Power Sequence
PWM Logic Table
PWM
GH
(FCCM = HiZ  Shutdown)
Setting the FCCM pin to a HIGH impedance state (HiZ)
will shutdown the driver IC with ICC < 6 µA. The
FDMF301155 requires a startup latency time of
(<15 µsec) when exiting a HiZ FCCM state. Low ICC
driver shutdown is often needed to support power
saving modes in multi-phase voltage regulator designs.
The FDMF301155 incorporates a 3-state 5 V PWM
input gate drive design. The 3-state gate drive has both
logic HIGH and LOW levels, along with a 3-state
shutdown window. When the PWM input signal enters
and remains within the 3-state window for a defined
hold-off time (tD_HOLD-OFF), both GL and GH are pulled
LOW. This feature enables the gate drive to shutdown
both the high-side and the low-side MOSFETs to
support features such as phase shedding, a common
feature on multi-phase voltage regulators.
Table 1.
FCCM
(FCCM = 0  Diode Emulation / DCM)
Setting the FCCM pin to a LOW state will enable diode
emulation. Diode emulation allows for higher converter
efficiency under light load situations. With diode
emulation is activated, the FDMF301155 will detect the
zero current crossing of the output inductor (at light
loads) and will turn off low side MOSFET gate GL to
prevent negative inductor current from flowing. Diode
emulation ensures discontinuous conduction mode
(DCM) operation. Diode emulation is asynchronous to
the PWM signal. Therefore, the FDMF301155 will
respond to the FCCM input immediately after it changes
state.
Enable
3.4
PWM
(FCCM = 1  Forced CCM)
Setting the FCCM pin to a HIGH state will allow for
forced CCM operation. During forced CCM, the
FDMF301155 will always follow the PWM signal and
allow for negative inductor current.
Driver
State
3.0
FCCM Logic Table
The FCCM pin can be tied to the VCC rail with an
external pull-up resistor and it will maintain HIGH once
the VCC rail turns on. Or the FCCM pin can be directly
tied to the PWM controller for other purposes.
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12
FDMF301155 — Smart Power Stage (SPS) Module
Functional Description
the high-side driver is developed by a bootstrap supply
circuit, consisting of the internal Schottky diode and
external bootstrap capacitor (CBOOT). During startup, the
SW node should be held at PGND, allowing CBOOT to
charge to PVCC through the internal bootstrap diode.
When the PWM input goes HIGH, HDRV begins to
charge the gate of the high-side MOSFET (internal GH
pin). During this transition, the charge is removed from
the CBOOT and delivered to the gate of Q1. As Q1 turns
on, SW rises to VIN, forcing the BOOT pin to VIN +
VBOOT, which provides sufficient VGS enhancement for
Q1. To complete the switching cycle, Q1 is turned off by
pulling HDRV to SW. CBOOT is then recharged to PVCC
when the SW falls to PGND. HDRV output is in phase
with the PWM input. The high-side gate is held LOW
when the driver is disabled or the PWM signal is held
within the 3-state window for longer than the 3-state
hold-off time, tD_HOLD-OFF.
Continuous Current Mode with Positive
Inductor Current (CCM1)
This condition is typical of a moderate-to-heavily loaded
power stage. During this mode, the inductor current is
always flowing towards the output capacitor. The highside MOSFET is hard-switching during the turn-on and
turn-off events. The low-side MOSFET acts a
synchronous rectifier.
Continuous Current Mode with Negative
Inductor Current (CCM2)
This operating mode can occur during two situations:
1.) A converter load transient may force the power
stage to pull energy from the output capacitors and
deliver the energy back to the input capacitors (Boost
Mode). This situation is common in synchronous buck
applications that require output voltage load-line
positioning.
Low-Side Driver
The low-side driver (LDRV) is designed to drive the
gate-source of a ground-referenced, low-RDS(ON),
N-channel MOSFET (Q2). The bias for LDRV is
internally connected between the PVCC and AGND.
When the driver is enabled, the driver output is 180° out
of phase with the PWM input. When the driver is
disabled (FCCM = 0 V), LDRV is held LOW.
During this mode, the negative inductor current (current
flowing into FDMF301155 SW node) may become large
and persist for many cycles. This situation causes the
low-side MOSFET to hard switch and the high-side
MOSFET acts as a synchronous rectifier. It is highly
recommended to check peak SW node voltage stress
during any situation that can generate large negative
inductor currents.
2.) A power stage that is operating in forced CCM
mode with lighter converter loads. Here, the inductor
peak-to-peak ripple current is greater than two times the
load current and the inductor current is flowing both
positive and negative in a switching cycle.
Discontinuous Current Mode (DCM)
This condition is typical of a lightly loaded power stage.
During DCM, the high-side MOSFET turns on into an
un-energized out filter inductor (i.e. zero inductor
current). The inductor current ramps up during the highside MOSFET on-time and is then allowed to ramp back
down to aero amps during the low-side on-time (i.e
inductor current returns to zero every switching cycle.
High-Side Driver
The high-side driver (HDRV) is designed to drive a
floating N-channel MOSFET (Q1). The bias voltage for
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
www.onsemi.com
13
FDMF301155 — Smart Power Stage (SPS) Module
Synchronous Buck Operating Modes
PWM
VIL_PWM
90%
GH to SW
10%
GL
10%
90%
tPD_PHGLL
tPD_PLGHL
tD_DEADON
tPD_THGHH
tPD_PHGLL
tD_DEADON
tD_DEADOFF
tPD_TLGLH
tD_HOLD-OFF
tD_HOLD-OFF
SW
Less than
tD_HOLD-OFF
Inductor
Current
Less than
tD_HOLD-OFF
3-State
GL / GH
tHOLD_OFF
off
Window
Figure 27.
PWM 3-State Timing Diagram (FCCM held HIGH)
VIH_FCCM
FCCM
VIL_FCCM
VIH_PWM
PWM
VIL_PWM
GH to SW
10%
GL
90%
10%
tPD_ZCD
tPD_PHGHH
Delay from PWM going HIGH
to HS VGS HIGH
[ HS turn-on in DCM ]
SW
3-State
GL / GH
tHOLD_OFF
off
Window
CCM
(Pos. Inductor
Current)
Delay from FCCM going
HIGH to LS VGS HIGH
tPD_ZCD
Delay from FCCM going
HIGH to LS VGS HIGH
tPS_EXIT
VIN
CCM
(Neg. Inductor
Current)
DCM
DCM
VOUT
Inductor
Current
SW
(zoom)
-0.5mV
CCM operation with
positive inductor current
CCM operation with
negative inductor current
Figure 28.
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
DCM operation allowed:
Diode Emulation using the GL
(LS MOSFET VGS) to eliminate
negative inductor current
FCCM used
to control
negative
inductor
current
DCM
FCCM used to
place driver IC
is low power
shutdown
mode
CCM
FCCM 3-State Timing Diagram
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14
FDMF301155 — Smart Power Stage (SPS) Module
VIH_PWM
3-State
Window
higher RBOOT value can cause lower efficiency due to
high switching loss of high-side MOSFET.
Decoupling Capacitor for PVCC & VCC
For the supply inputs (PVCC and VCC pins), local
decoupling capacitors are required to supply the peak
driving current and to reduce noise during switching
operation. Use at least 0.68 ~ 1 µF / 0402 ~ 0603 / X5R
~ X7R multi-layer ceramic capacitors for both power
rails. Keep these capacitors close to the PVCC and
VCC pins and PGND and AGND copper planes. If the
de-coupling capacitors need to be located on the bottom
side of board, place through-hole vias on each pad
connecting top side and bottom side PVCC and VCC
nodes with low impedance current paths, see Figure 30
and Figure 31.
Do not add a capacitor or resistor between the BOOT
pin and GND.
PWM (Input)
The PWM pin recognizes three different logic levels
from PWM controller: HIGH, LOW, and 3-state. When
the PWM pin receives a HIGH command, the gate
driver turns on the high-side MOSFET. When the PWM
pin receives a LOW command, the gate driver turns on
the low-side MOSFET. When the PWM pin receives a
voltage signal inside of the 3-state window (VTRI_Window)
and exceeds the 3-state hold-off time, the gate driver
turns off both high-side and low-side MOSFETs. To
recognize the high-impedance 3-state signal from the
controller, the PWM pin has an internal resistor divider
from VCC to PWM to AGND. The resistor divider sets
a voltage level on the PWM pin inside the 3-state
window when the PWM signal from the controller is
high-impedance.
The supply voltage range on PVCC and VCC is 4.5 V ~
5.5 V, and typically 5 V for normal applications.
R-C Filter on VCC
The PVCC pin provides power to the gate drive of the
high-side and low-side power MOSFETs. In most cases,
PVCC can be connected directly to VCC, which is the
pin that provides power to the analog and logic blocks of
the driver. To avoid switching noise injection from PVCC
into VCC, a filter resistor can be inserted between
PVCC and VCC decoupling capacitors.
FCCM (Input)
When the FCCM pin is set HIGH, the driver IC Zero
Cross Detect (ZCD) comparator is disabled and the
high-side and low-side MOSFETs switch in FCCM
(Forced CCM) and follows the PWM signal. When the
FCCM pin is set LOW, the low-side MOSFET turns off
when the SPS driver detects negative inductor current
during the low-side MOSFET turn-on period. This
operating mode is commonly referred to as diode
emulation. The diode emulation feature allows for higher
converter efficiency during light-load condition and PFM
/ DCM operation.
Recommended filter resistor value range is 0 ~ 4.7 Ω,
typically 0 Ω for most applications.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBOOT). A bootstrap capacitor of 0.1 ~ 0.22 µF / 0402 ~
0603 / X5R ~ X7R is usually appropriate for most
switching applications. A series bootstrap resistor may
be needed for specific applications to lower high-side
MOSFET switching speed. The boot resistor is required
when the SPS is switching above 15 V VIN; when it is
effective at controlling VSW overshoot. RBOOT value from
zero to 4.7 Ω is typically recommended to reduce
excessive voltage spike and ringing on the SW node. A
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
Applications that require diode emulation and/or low
shutdown current should actively drive the FCCM pin
from a PWM controller. Do not add any noise filter
capacitor on the FCCM pin.
www.onsemi.com
15
FDMF301155 — Smart Power Stage (SPS) Module
Application Information
Figure 29 shows an example diagram for power loss
and efficiency measurement.
Power loss calculation and equation examples:
PIN = (VIN  IIN) + (VCC  ICC)
PSW = VSW  IOUT
POUT = VOUT  IOUT
PLOSS_MODULE = PIN – PSW
PLOSS_TOTAL = PIN – POUT
EFFIMODULE = (PSW / PIN)  100
EFFITOTAL = (POUT / PIN)  100
[W]
[W]
[W]
[W]
[W]
[%]
[%]
Pulse
Generator
PWM
Power
Supply 1
Power
Supply 2
VIN / IIN
VIN
HS
VCC / ICC
GD
PVCC
LS
VCC
Figure 29.
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
Electronic
Load
VOUT
VSW / IOUT
VOUT / IOUT
Fairchild SPS
Evaluation Board
Power Loss and Efficiency Measurement Diagram
www.onsemi.com
16
FDMF301155 — Smart Power Stage (SPS) Module
Power Loss and Efficiency
Figure 30 and Figure 31 provide an example of singlephase layout for the FDMF301155 and critical
components. All of the high-current paths; such as VIN,
SW, VOUT, and GND coppers; should be short and
wide for low parasitic inductance and resistance. This
helps achieve a more stable and evenly distributed
current flow, along with enhanced heat radiation and
system performance.
ringing. Inserting a boot resistance lowers the SPS
module efficiency. Efficiency versus switching noise
must be considered. RBOOT values from 0.5  to 4.7 
are typically effective in reducing VSW overshoot.
The VIN and PGND pins handle large current transients
with frequency components greater than 100 MHz. If
possible, these pins should be connected directly to the
VIN and board GND planes. The use of thermal relief
traces in series with these pins is not recommended
since this adds extra parasitic inductance to the power
path. This added inductance in series with either the
VIN or PGND pin degrades system noise immunity by
increasing positive and negative VSW ringing.
Input ceramic bypass capacitors must be close to the
VIN and PGND pins. This reduces the high-current
power loop inductance and the input current ripple
induced by the power MOSFET switching operation.
The SW copper trace serves two purposes. In addition
to being the high-frequency current path from the SPS
package to the output inductor, it serves as a heat sink
for the low-side MOSFET. The trace should be short
and wide enough to present a low-impedance path for
the high-frequency, high-current flow between the SPS
and the inductor. The short and wide trace minimizes
electrical losses and SPS temperature rise. The SW
node is a high-voltage and high-frequency switching
node with high noise potential. Care should be taken to
minimize coupling to adjacent traces. Since this copper
trace acts as a heat sink for the low-side MOSFET,
balance using the largest area possible to improve SPS
cooling while maintaining acceptable noise emission.
PGND pad and pins should be connected to the GND
copper plane with multiple vias for stable grounding.
Poor grounding can create a noisy and transient offset
voltage level between PGND and AGND. This could
lead to faulty operation of gate driver and MOSFETs.
Ringing at the BOOT pin is most effectively controlled
by close placement of the boot capacitor. Do not add
any additional capacitors between BOOT to PGND. This
may lead to excess current flow through the BOOT
diode, causing high power dissipation.
The FCCM pin integrates weak internal pull-up and pulldown current sources. The current sources are used to
help hold the FCCM in the 3-state window. This pin
should not have any noise filter capacitors if actively
driven by a PWM controller. Do not float this pin.
An output inductor should be located close to the
FDMF301155 to minimize the power loss due to the SW
copper trace. Care should also be taken so the inductor
dissipation does not heat the SPS.
Multiple vias should be placed on the VIN and VOUT
copper areas to interconnect nodes that are located on
multiple layers (top, inner, and bottom layers). The vias
help to evenly distribute current flow and heat
conduction.
®
PowerTrench MOSFETs are used in the output stage
and are effective at minimizing ringing due to fast
switching. In most cases, no RC snubber on SW node is
required. If a snubber is used, it should be placed close
to the SW and PGND pins. The resistor and capacitor of
the snubber must be sized properly to not generate
excessive heating due to high power dissipation.
Care should be taken when routing the copper pour area
and via placement on the SW copper. A large SW node
copper pour can result in excessive parasitic inductance
and capacitance, which can increase switching noise.
However, the copper pour area and via placement can
affect the efficiency and thermal performance, where a
large copper pour can help decrease thermal resistance
and parasitic resistance. If possible, place the SW node
copper on the top layer with no vias on the SW copper to
minimize switch node parasitic noise. If multiple SW node
layers are needed, vias should be relatively large and of
reasonably low inductance.
Decoupling capacitors on PVCC, VCC, and BOOT
capacitors should be placed as close as possible to the
PVCC ~ PGND, VCC ~ AGND, and BOOT ~ PHASE pin
pairs to ensure clean and stable power supply. Their
routing traces should be wide and short to minimize
parasitic PCB resistance and inductance.
The board layout should include a placeholder for smallvalue series boot resistor on BOOT ~ PHASE. The bootloop size, including series RBOOT and CBOOT, should be
as small as possible.
Critical high-frequency components; such as RBOOT,
CBOOT, RC snubber, and bypass capacitors; should be
located as close to the respective SPS module pins as
possible on the top layer of the PCB. If this is not
feasible, they can be placed on the board bottom side
and their pins connected from bottom to top through a
network of low-inductance vias.
A boot resistor may be required when the SPS is
operating above 15 V VIN and it is effective to control the
high-side MOSFET turn-on slew rate and SW voltage
overshoot. RBOOT can improve noise operating margin in
synchronous buck designs that may have noise issues
due to ground bounce or high positive and negative VSW
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
www.onsemi.com
17
FDMF301155 — Smart Power Stage (SPS) Module
PCB Layout Guideline
FDMF301155 — Smart Power Stage (SPS) Module
PCB Layout Guideline (Continued)
Figure 30.
Figure 31.
Single-Phase Board Layout Example – Top View
Single-Phase Board Layout Example – Bottom View (Mirrored)
© 2015 Semiconductor Components Industries, LLC
FDMF301155 • Rev. 1.0
www.onsemi.com
18
0.10
0.05
3.80±0.10
(0.85)
C.L.
0.50 (2X)
0.30
16
0.40
1.03
1.92±0.10
17 18 19
20
0.40
15
24
14
25
13
26
12
33
0.45
11
1.03±0.10
0.35
0.15
0.85
21 22 23
C.L.
0.55
0.30
27
0.30
28
0.55 (0.22)
29
32
10
30 1.03±0.10
31
9
0.40
C A B
C
7
8
5
6
4
3
2
1
0.50
0.30
PIN #1 INDICATOR
0.30
0.20 (31X)
0.50
(0.38)
1.98±0.10
1.32±0.10
0.50
B
0.10 C
5.00±0.10
2X
PIN#1
INDICATOR
SEE
DETAIL 'A'
A
C.L.
8
9
31
NOTES: UNLESS OTHERWISE SPECIFIED
C.L.
5.00±0.10
15
24
16
0.10 C
23
2X
0.10 C
0.80
0.70
0.08 C
0.30
0.20
SCALE: 2:1
0.05
0.00
C
SEATING
PLANE
A) DOES NOT FULLY CONFORM TO JEDEC
REGISTRATION MO-220, DATED
MAY/2005.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) DRAWING FILE NAME: MKT-PQFN31BREV3
1.90
2.10
2.15
2.70
0.00
0.90
1.37
2.70
2.10
1.95
1.90
1.75
C.L.
23
16
2.70
0.60
0.40
0.05
0.00
2.10
1.90
1.75
26
27
C.L.
28
29
0.50 TYP
30
1.90
12
33
11
0.10
0.27
0.62
32
31
9
0.60(13X)
1
2
3
4
5
6
7
8
0.20
LAND PATTERN
RECOMMENDATION
2.10
0.34
0.07
0.30 (13X)
0.50 TYP
1.76
5.40
15
24
1.90
1.75
1.90
2.10
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