1. Features • Medium-voltage and Standard-voltage Operation – 2.7 (VCC = 2.7V to 5.5V) • Automotive Temperature Range –40°C to +125°C • User Selectable Internal Organization • • • • • • • • – 16K: 2048 x 8 or 1024 x 16 3-wire Serial Interface Sequential Read Operation Schmitt Trigger, Filtered Inputs for Noise Suppression 2 MHz Clock Rate (5V) Compatibility Self-timed Write Cycle (10 ms max) High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years Lead-Free/Halogen-Free Devices Available 8-lead JEDEC SOIC and 8-lead TSSOP Packages Three-wire Automotive Temperature Serial EEPROM 2. Description The AT93C86A provides 16384 bits of serial electrically erasable programmable read only memory (EEPROM), organized as 1024 words of 16 bits each when the ORG pin is connected to VCC and 2048 words of 8 bits each when it is tied to ground. The device is optimized for use in many automotive applications where low-power and low-voltage operations are essential. The AT93C86A is available in space saving 8lead JEDEC SOIC and 8-lead TSSOP packages. Table 2-1. Pin Configuration Pin Name Function CS Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output GND Ground VCC Power Supply ORG Internal Organization DC Don’t Connect 16K (2048 x 8 or 1024 x 16) AT93C86A 8-lead SOIC CS SK DI DO 1 2 3 4 8 7 6 5 VCC DC ORG GND 8-lead TSSOP CS SK DI DO 1 2 3 4 8 7 6 5 VCC DC ORG GND The AT93C86A is enabled through the Chip Select pin (CS), and accessed via a three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO. The write cycle is completely self-timed and no separate erase cycle is required before Write. The write cycle is only enabled when the part is in the Erase/Write Enable state. When CS is brought “high” following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of the part. The AT93C86A is available in a 2.7V to 5.5V version. Rev. 5096E–SEEPR–1/08 Absolute Maximum Ratings* *NOTICE: Operating Temperature..................................–55°C to +125°C Storage Temperature .....................................–65°C to +150°C Voltage on any Pin with Respect to Ground .................................... –1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA Figure 2-1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Block Diagram Vcc GND MEMORY ARRAY ORG 2048 x 8 OR 1024 x 16 ADDRESS DECODER DATA REGISTER OUTPUT BUFFER DI Note: CS MODE DECODE LOGIC SK CLOCK GENERATOR DO When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1 Meg ohm pullup, then the x 16 organization is selected. Table 2-2. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted) Symbol Test Conditions COUT CIN Note: 2 Max Units Conditions Output Capacitance (DO) 5 pF VOUT = 0V Input Capacitance (CS, SK, DI) 5 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. AT93C86A 5096E–SEEPR–1/08 AT93C86A Table 2-3. DC Characteristics Applicable over recommended operating range from: TA = –40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise noted) Symbol Parameter Test Condition VCC1 Supply Voltage VCC2 Supply Voltage ICC Supply Current VCC = 5.0V ISB1 Standby Current ISB2 IIL Min Typ Max Unit 2.7 5.5 V 4.5 5.5 V READ at 1.0 MHz 0.5 2.0 mA WRITE at 1.0 MHz 0.5 2.0 mA VCC = 2.7V CS = 0V 6.0 10.0 µA Standby Current VCC = 5.0V CS = 0V 10.0 15.0 µA Input Leakage VIN = 0V to VCC 0.1 3.0 µA Output Leakage VIN = 0V to VCC 0.1 3.0 µA VIL1 VIH1(1) Input Low Voltage Input High Voltage 2.7V ≤ VCC ≤ 5.5V −−−−0.6 0.8 V 2.0 VCC + 1 V VOL1 VOH1 Output Low Voltage Output High Voltage 2.7V ≤ VCC ≤ 5.5V 0.4 V IOL (1) Note: IOL = 2.1 mA IOH = –0.4 mA 2.4 V 1. VIL min and VIH max are reference only and are not tested. Table 2-4. AC Characteristics Applicable over recommended operating range from TA = –40°C to +125°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Symbol Parameter Test Condition Min Typ Max Units fSK SK Clock Frequency 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 0 0 2 1 MHz tSKH SK High Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 250 ns tSKL SK Low Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 250 ns tCS Minimum CS Low Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 250 ns tCSS CS Setup Time Relative to SK 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 50 50 ns tDIS DI Setup Time Relative to SK 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 100 100 ns tCSH CS Hold Time Relative to SK 0 ns tDIH DI Hold Time Relative to SK 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 100 100 ns tPD1 Output Delay to ‘1’ AC Test 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 500 ns tPD0 Output Delay to ‘0’ AC Test 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 500 ns 3 5096E–SEEPR–1/08 Table 2-4. AC Characteristics (Continued) Applicable over recommended operating range from TA = –40°C to +125°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Symbol Parameter Test Condition tSV CS to Status Valid AC Test tDF CS to DO in High Impedance AC Test CS = VIL tWP (1) Max Units 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 250 ns 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 100 150 ns 10 ms 2.7V ≤ VCC ≤ 5.5V Write Cycle Time Endurance Note: Min 0.1 5.0V, 25°C Typ 4 1M Write Cycles 1. This parameter is characterized and is not 100% tested. Table 2-5. Instruction Set for the AT93C86A Address Instruction Data SB Op Code x8 x 16 READ 1 10 A10 – A0 A9 – A0 Reads data stored in memory, at specified address. EWEN 1 00 11XXXXXXXXX 11XXXXXXXX Write enable must precede all programming modes. ERASE 1 11 A10 – A0 A9 – A0 WRITE 1 01 A10 – A0 A9 – A0 ERAL 1 00 10XXXXXXXXX 10XXXXXXXX WRAL 1 00 01XXXXXXXXX 01XXXXXXXX EWDS 1 00 00XXXXXXXXX 00XXXXXXXX 4 x8 x 16 Comments Erases memory location An – A0. D7 – D0 D15 – D0 Writes memory location An – A0. Erases all memory locations. Valid only at VCC = 4.5V to 5.5V. D7 – D0 D15 – D0 Writes all memory locations. Valid when VCC = 4.5V to 5.5V and Disable Register cleared. Disables all programming instructions. AT93C86A 5096E–SEEPR–1/08 AT93C86A 3. Functional Description The AT93C86A is accessed via a simple and versatile 3-wire serial communication interface. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic “1”) followed by the appropriate Op Code and the desired memory address location. READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C86A supports sequential read operations. The device will automatically increment the internal address pointer and clock out the next memory location as long as CS is held high. In this case, the dummy bit (logic “0”) will not be clocked out between memory locations, thus allowing for a continuous stream of data to be read. ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or VCC power is removed from the part. ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory location to the logical “1” state. The self-timed erase cycle starts once the Erase instruction and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “1” at pin DO indicates that the selected memory location has been erased, and the part is ready for another instruction. WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The self-timed programming cycle tWP starts after the last bit of data is received at serial data input pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is brought high after the end of the self-timed programming cycle tWP. ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The Eral instruction is valid only at VCC = 5.0V ± 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The Wral instruction is valid only at VCC = 5.0V ± 10%. ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturbance, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the Read instruction is independent of both the Ewen and Ewds instructions and can be executed at any time. 5 5096E–SEEPR–1/08 4. Timing Diagrams Figure 4-1. Note: Synchronous Data Timing 1. This is the minimum SK period. Table 4-1. Organization Key for Timing Diagrams AT93C86A (16K) Figure 4-2. 6 I/O x8 x 16 AN A10 A9 DN D7 D15 READ Timing AT93C86A 5096E–SEEPR–1/08 AT93C86A Figure 4-3. EWEN Timing tCS CS SK DI Figure 4-4. 1 0 0 1 ... 1 EWDS Timing tCS CS SK DI Figure 4-5. 1 0 0 0 ... 0 WRITE Timing tCS CS SK DI DO 1 0 1 AN ... A0 DN ... D0 HIGH IMPEDANCE BUSY READY tWP 7 5096E–SEEPR–1/08 Figure 4-6. WRAL Timing(1) tCS CS SK DI DO 1 0 0 0 1 ... DN ... D0 BUSY HIGH IMPEDANCE READY tWP Note: 1. Valid only at VCC = 4.5V to 5.5V. Figure 4-7. ERASE Timing tCS CS STANDBY CHECK STATUS SK DI 1 1 1 AN AN-1 AN-2 ... A0 tDF tSV DO HIGH IMPEDANCE HIGH IMPEDANCE BUSY READY tWP 8 AT93C86A 5096E–SEEPR–1/08 AT93C86A Figure 4-8. ERAL Timing(1) D Note: 1. Valid only at VCC = 4.5V to 5.5V. 9 5096E–SEEPR–1/08 5. AT93C86A Ordering Information Ordering Code Package Operation Range 8S1 8A2 Lead-free/Halogen-free Automotive Temperature (−40°C to 125°C) AT93C86A-10SQ-2.7 AT93C86A-10TQ-2.7 Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options −2.7 10 Low Voltage (2.7V to 5.5V) AT93C86A 5096E–SEEPR–1/08 AT93C86A 6. Packaging Information 6.1 8S1 – JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Note: SYMBOL MIN NOM MAX A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.27 θ 0° – 8° These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 3/17/05 R 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. REV. 8S1 C 11 5096E–SEEPR–1/08 6.2 8A2 – TSSOP 3 2 1 Pin 1 indicator this corner E1 E L1 N L Top View End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A b D MIN NOM MAX NOTE 2.90 3.00 3.10 2, 5 3, 5 E e D A2 6.40 BSC E1 4.30 4.40 4.50 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 e Side View L 0.65 BSC 0.45 L1 Notes: 0.60 0.75 1.00 REF 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02 R 12 4 2325 Orchard Parkway San Jose, CA 95131 TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 8A2 REV. B AT93C86A 5096E–SEEPR–1/08 AT93C86A 7. Revision History Doc. Rev. Date Comments 5096E 1/2008 Moved to new template Replaced Table 5 with correct version 5096D 2/2007 Removed PDIP package offering Removed Pb’d part numbers 5096C 9/2006 Revision history implemented; Removed ‘Preliminary’ status from datasheet. 13 5096E–SEEPR–1/08 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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