1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM Features DDR2 VLP Registered DIMM (RDIMM) MT18HVF12872(P) – 1GB For the latest data sheet and for component data sheets, refer to Micron's Web site: www.micron.com/products/ddr2 Features • • • • • • • • • • • • • • • • • • • • • • Figure 1: Table 1: 240-Pin VLP DIMM (MO-237) Functionally equivelent to R/C “U” and “V” Supports 95°C with double refresh Fits with the ATCA form factor 240-pin, registered dual in-line memory module Fast data transfer rates: PC2-3200, PC2-4200, or PC2-5300 Supports ECC error detection and correction VDD = VDDQ = +1.8V VDDSPD = +1.7V to +3.6V JEDEC-standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option 4-bit prefetch architecture DLL to align DQ and DQS transitions with CK Single rank Multiple internal device banks for concurrent operation Programmable CAS# latency (CL) Posted CAS# additive latency (AL) WRITE latency = READ latency - 1 tCK Programmable burst lengths: 4 or 8 Adjustable data-output drive strength 64ms, 8,192-cycle refresh On-die termination (ODT) Serial presence-detect (SPD) with EEPROM Gold edge contacts Height: 17.9mm (0.705in) Options Marking • Parity • Package 240-pin DIMM (lead-free) • Frequency/CAS latency1 3.0ns @ CL = 5 (DDR2-667)2 3.75ns @ CL = 4 (DDR2-533) 5.0ns @ CL = 3 (DDR2-400) • PCB height 17.9mm (1.18in) P Y -667 -53E -40E Notes: 1. CL = CAS (READ) latency; registered mode will add one clock cycle to CL. 2. Contact Micron for product availability. Addressing 1GB 8K Refresh count Row address 16K (A0–A13) 4 (BA0, BA1) 1KB Device bank address Device page size per bank Device configuration 512Mb (128 Meg x 4) 2K (A0–A9, A11) 1 (S0#) Column address Module rank address Table 2: Key Timing Parameters Data Rate (MT/s) Speed Grade Industry Nomenclature CL = 5 CL = 4 CL = 3 RCD (ns) t RP (ns) t RC (ns) -667 -53E -40E PC2-5300 PC2-4200 PC2-3200 667 – – 533 533 400 – 400 400 15 15 15 15 15 15 55 55 55 PDF: 09005aef82255aba/Source: 09005aef82255a83 HVF18C64_128_256x72G.fm - Rev. B 5/06 EN 1 t Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM Features Figure 2: Module Part Numbers Example Part Number: MT 1 8 HVF1 2 8 7 2 P Y-6 6 7 __ MT 18 H VF 128 72 P Y : 667 Micron Technology PCB Die Revision Number of DRAM DRAM Die Revision Process Technology H Module Speed 1.8V (DDR2 SDRAM) Package Code (lead-free) Y Product Family DDR2 FBGA TS DDR2 DDP (Dual die in package) TD DDR2 flip chip TJ Module Version DDR2 CSP stack Width Depth Blank 184-pin/240-pin registered DIMM VF DDR2 VLP Table 3: Single- or dual-rank DIMM DY Select dual-rank DIMM TF P 184-pin/240-pin registered DIMM w/Parity Part Numbers and Timing (1GB – 128 Meg x 72) Uses 512Mb (128 Meg x 4) – MT47H128M4 DDR2 SDRAM – www.micron.com/products/ddr2 Part Number MT18HVF12872(P)Y-667__ MT18HVF12872(P)Y-53E__ MT18HVF12872(P)Y-40E__ Notes: PDF: 09005aef82255aba/Source: 09005aef82255a83 HVF18C64_128_256x72G.fm - Rev. B 5/06 EN Industry Module Nomenclature Bandwidth PC2-5300 PC2-4200 PC2-3200 Clock Cycle Time (ns) Data Rate (MT/s) 3.0 3.75 5.0 667 533 400 5.3 GB/s 4.2 GB/s 3.2 GB/s Latency DRAM (CL - tRCD - tRP) Speed Grade 5-5-5 4-4-4 3-3-3 -3 -37E -5E 1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18HVF12872PY-667C2. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 4: Pin Assignment 240-Pin RDIMM Front 240-Pin RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CB2 CB3 VSS VDDQ CKE0 VDD NC/BA2 ERR_OUT VDDQ A11 A7 VDD A5 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 A4 VDDQ A2 VDD VSS VSS VDD PAR_IN VDD A10/AP BA0 VDDQ WE# CAS# VDDQ S1# ODT1 VDDQ VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SDA SCL 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 VSS DQ4 DQ5 VSS DQS9 DQS9# VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DQS10 DQS10# VSS RFU RFU VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DQS11 DQS11# VSS DQ22 DQ23 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 VSS DQ28 DQ29 VSS DQS12 DQS12# VSS DQ30 DQ31 VSS CB4 CB5 VSS DQS17 DQS17# VSS CB6 CB7 VSS VDDQ CKE1 VDD NC NC VDDQ A12 A9 VDD A8 A6 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 VDDQ A3 A1 VDD CK0 CK0# VDD A0 VDD BA1 VDDQ RAS# S0# VDDQ ODT0 NC/A13 VDD VSS DQ36 DQ37 VSS DQS13 DQS13# VSS DQ38 DQ39 VSS DQ44 DQ45 VSS 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 DQS14 DQS14# VSS DQ46 DQ47 VSS DQ52 DQ53 VSS RFU RFU VSS DQS15 DQS15# VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS16 DQS16# VSS DQ62 DQ63 VSS VDDSPD SA0 SA1 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS RESET# NC Vss DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PDF: 09005aef82255aba/Source: 09005aef82255a83 HVF18C64_128_256x72G.fm - Rev. B 5/06 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM Pin Assignments and Descriptions Table 5: Pin Descriptions Refer to Table 4 on page 3 for more information Symbol Type Source Description ODT0 Input (SSTL18) Register CK0, CK0# Input (SSTL18) PLL CKE0 Input (SSTL18) Input (SSTL18) Input (SSTL18) Input (SSTL18) Register A0–A13 Input (SSTL18) Register PAR_IN Register SCL Input (SSTL18) Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS#, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM.. Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Bank address inputs: BA0–BA1/BA2 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0–BA1/BA2 define which mode register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command. Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0–BA1/BA2) or all device banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Parity bit for the address and control bus. SA0–SA2 Input SPD RESET# Input (LVCMOS) Register DQS0–DQS17, DQS0#–DQS17# I/O (SSTL18) DRAM DQ0–DQ63 I/O (SSTL18) I/O (SSTL18) I/O DRAM Serial clock for presence-detect: SCL is used to synchronize the presencedetect data transfer to and from the module. Presence-detect address inputs: These pins are used to configure the presence-detect device. Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used during power up to ensure that CKE is LOW and DQs are High-Z. Data strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. Data input/output: Bidirectional data bus. DRAM Check bits. Register VDD Output (open drain) Supply VDDQ Supply S0# RAS#, CAS#, WE# BA0, BA1 CB0–CB7 SDA ERR_OUT PDF: 09005aef82255aba/Source: 09005aef82255a83 HVF18C64_128_256x72G.fm - Rev. B 5/06 EN Register Register Register SPD SPD DRAM, PLL, Register DRAM Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. Parity error found on the address and control bus. Power supply: 1.8V ±0.1V. DQ power supply: 1.8V ±0.1V. 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM Pin Assignments and Descriptions Table 5: Pin Descriptions (continued) Refer to Table 4 on page 3 for more information Symbol Type Source VREF Supply VSS VDDSPD NC RFU Supply Supply – – DRAM, PLL, Register ALL SPD PDF: 09005aef82255aba/Source: 09005aef82255a83 HVF18C64_128_256x72G.fm - Rev. B 5/06 EN Description SSTL_18 reference voltage. Ground. Serial EEPROM positive power supply: +1.7V to +3.6V. No connect: These pins should be left unconnected. Reserved for future use. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM Functional Block Diagram Functional Block Diagram Figure 3: Functional Block Diagram VSS RS0# DQS9 DQS9# DQS0 DQS0# DM CS# DQS DQS# DM CS# DQS DQS# DQ0 DQ1 DQ2 DQ3 DQ DQ DQ DQ DQ4 DQ5 DQ6 DQ7 U1 DQS1 DQS1# DQ DQ DQ DQ DM CS# DQS DQS# DQ12 DQ13 DQ14 DQ15 U2 DQ DQ DQ DQ DQ20 DQ21 DQ22 DQ23 U3 DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ U15 DQS14 DQS14# DM CS# DQS DQS# DM CS# DQS DQS# DQ DQ DQ DQ DQ44 DQ45 DQ46 DQ47 U9 DQS6 DQS6# DQ DQ DQ DQ U14 DQS15 DQS15# DM CS# DQS DQS# DM CS# DQS DQS# DQ DQ DQ DQ DQ52 DQ53 DQ54 DQ55 U10 DQ DQ DQ DQ U13 DQS16 DQS16# DQS7 DQS7# DM CS# DQS DQS# DQ DQ DQ DQ DM CS# DQS DQS# DQ60 DQ61 DQ62 DQ63 U11 DQ DQ DQ DQ U12 DQS17 DQS17# DQS8 DQS8# DM CS# DQS DQS# CB0 CB1 CB2 CB3 U18 DM CS# DQS DQS# DQ36 DQ37 DQ38 DQ39 U8 DQS5 DQS5# DQ56 DQ57 DQ58 DQ59 DQ DQ DQ DQ DQS13 DQS13# DM CS# DQS DQS# DQ48 DQ49 DQ50 DQ51 U19 DM CS# DQS DQS# DQ28 DQ29 DQ30 DQ31 U4 DQS4 DQS4# DQ40 DQ41 DQ42 DQ43 DQ DQ DQ DQ DQS12 DQS12# DQS3 DQS3# DQ32 DQ33 DQ34 DQ35 U20 DM CS# DQS DQS# DM CS# DQS DQS# DQ24 DQ25 DQ26 DQ27 DQ DQ DQ DQ DQS11 DQS11# DQS2 DQS2# DQ16 DQ17 DQ18 DQ19 U21 DQS10 DQS10# DM CS# DQS DQS# DQ8 DQ9 DQ10 DQ11 DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQS# CB4 CB5 CB6 CB7 U5 DQ DQ DQ DQ U17 U16 S0# BA0–BA1 A0–A12 RAS# CAS# WE# CKE0 ODT0 PAR_IN R E G I S T E R U6 RS0#: DDR2 SDRAMs RBA0–RBA1: DDR2 SDRAMs RA0-RA12: DDR2 SDRAMs RRAS#: DDR2 SDRAMs RCAS#: DDR2 SDRAMs RWE#: DDR2 SDRAMs RCKE0: DDR2 SDRAMs RODT0: DDR2 SDRAMs ERR_OUT 120 VDDSPD Serial PD VDD DDR2 SDRAMS VDDQ DDR2 SDRAMS VREF DDR2 SDRAMS VSS DDR2 SDRAMS RESET# CK# DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 REGISTER x 2 CK0 CK0# PLL RESET# U7 SCL Serial PD WP A0 A1 SDA A2 SA0 SA1 SA2 CK Unless otherwise noted, resister values a 22Ω per industry standard PDF: 09005aef82255aba/Source: 09005aef82255a83 HVF18C64_128_256x72G.fm - Rev. B 5/06 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM General Description General Description Refer to the DDR2 component data sheets for complete functionality. For the 1GB RDIMM device, refer to the 512Mb (128 Meg x 4) component data sheet. DDR2 SDRAM modules are high-speed, CMOS, dynamic random-access 1GB memory modules organized in x72 configuration. DRAM specifications require the refresh rate to double when TCASE exceeds 85°C. This also includes the use of the high-temperature refresh option. DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bitwide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. PLL and Register Operation DDR2 SDRAM modules operate in registered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM devices on the following rising clock edge (data access is delayed by one clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differential clock signals (CK, CK#) to the DDR2 SDRAM devices. The registers and PLL minimize system and clock loading. PLL clock timing is defined by JEDEC specifications and ensured by use of the JEDEC clock reference board. Registered mode will add one clock cycle to CL. Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. PDF: 09005aef82255aba/Source: 09005aef82255a83 HVF18C64_128_256x72G.fm - Rev. B 5/06 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 6 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 6: Absolute Maximum DC Ratings Parameter Symbol Min Max Units VDD supply voltage relative to VSS VDDQ supply voltage relative to VSS VDDL supply voltage relative to Vss Voltage on any pin relative to VSS Storage temperature (2X refresh at 95°C) DDR2 SDRAM device operating temperature Input leakage current; Any input 0V ≤ VIN ≤ VDD; VREF input 0V ≤ VIN ≤ 0.95V; all other pins not under test = 0V Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQs and ODT are disabled VREF leakage current; VREF = valid VREF level VDD VDDQ VDDL VIN, VOUT TSTG TCASE II –1.0 –0.5 –0.5 –0.5 –55 0 –10 2.3 2.3 2.3 2.3 100 95 10 V V V V °C °C µA Ioz –10 10 µA IVREF –46 46 µA Command/address, RAS#, CAS#, WE# S#, CKE, CK, CK#, DM DQ, DQS, DQS# Capacitance At DDR2 data rates, Micron encourages designers to simulate the performance of the module to achieve optimum values. When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simulations to close timing budgets. Table 7: DRAM Interface for DRAM I/O DRAM (at each individual device pin) Parameter Input high (logic 1) voltage Input low (logic 0) voltage Input high (logic 1) voltage (-667 speed grade) Input low(logic 0) voltage (-667 speed grade) Input leakage current; any input 0V ≤ VIN ≤ VDD; all other pins not under test = 0V Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ and ODT disabled Input/output capacitance PDF: 09005aef82255aba/Source: 09005aef82255a83 HVF18C64_128_256x72G.fm - Rev. B 5/06 EN 8 Symbol Min Max Units VIH(DC) VIL(DC) VIH(AC) VIL(AC) Ii VREF(DC) + 125 –300 VREF(DC) + 200 – –10 VDDQ + 300 VREF(DC) - 125 – VREF(DC) - 200 10 mV mV mV mV uA Ioz –10 10 uA CIO 5.5 10.5 pF Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM IDD Specifications IDD Specifications Table 8: DDR2 IDD Specifications and Conditions – 1GB Values shown for MT47H128M4 DDR2 SDRAM only and are computed from values specified in the 512Mb (128 Meg x 4) component data sheet Parameter/Condition Symbol t t t t Operating one bank active-precharge current; CK = CK (IDD), RC = RC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), t RCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current; All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0 inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current; All device banks open, Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current; All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current; All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) -1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching -667 -53E -40E Units a 1,620 1,440 1,440 mA IDD1a 1,890 1,710 1,620 mA IDD2Pb 126 126 126 mA IDD2Qb 810 720 630 mA IDD2Nb 900 810 720 mA IDD3Pb 630 540 450 mA 216 216 216 mA IDD3Nb 1,170 990 810 mA IDD4Wa 3,060 2,520 2,070 mA IDD4Ra 3,240 2,610 2,070 mA IDD5b 3,240 3,060 2,970 mA IDD6b 126 126 126 mA IDD7a 4,320 4,050 3,960 mA IDD0 Notes: 1. a = Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. 2. b = Value calculated reflects all module ranks in this operating condition. PDF: 09005aef82255aba/Source: 09005aef82255a83 HVF18C64_128_256x72G.fm - Rev. B 5/06 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM Registers Registers Table 9: Register ( uses SSTU32865 devices) Parameter Symbol Pins Condition Min Max Units DC high-level input voltage VIH(DC) SSTL_18 VREF(DC) +125 VDDQ + 250 mV DC low-level input voltage VIL(DC) SSTL_18 0 VREF(DC) - 125 mV AC high-level input voltage VIH(AC) SSTL_18 VREF(DC) + 250 VDD mV AC low-level input voltage VIL(AC) Address, Control, Command Address, Control, Command Address, Control, Command Address, Control, Command Parity output Parity output All pins All pins All pins SSTL_18 0 VREF(DC) - 250 mV 1.2 – –5 – – – 0.5 5 100 40mA mV mV µA µA µA – Varies by mfr µA – Varies by mfr µA 2.5 3.5 pF – Varies by mfr pF Output high voltage Output low voltage Input current Static standby Static operating VOH VOL II IDD IDD Dynamic operating – clock tree IDDD Dynamic operating (per each input) IDDD Input capacitance (per device, per pin) Input capacitance (per device, per pin) CI PDF: 09005aef82255aba/Source: 09005aef82255a83 HVF18C64_128_256x72G.fm - Rev. B 5/06 EN LVCMOS LVCMOS VI = VDDQ or VSSQ RESET# = VSSQ (I/O = 0) RESET# = VSSQ; VI = VIH(AC) or VIL(DC) I/O = 0 N/A RESET# = VDD, VI = VIH(AC) or VIL(AC), I0 = 0; CK and CK# switching 50% duty cycle N/A RESET# = VDD, VI = VIH(AC) or VIL(AC), I0 = 0; CK and CK# switching 50% duty cycle; One data input switching at tCK/2, 50% duty cycle All inputs VI = VREF ±250mV; except RESET# VDDQ = 1.8V RESET# VI = VDDQ or VSSQ 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM PLL PLL Table 10: PLL (uses a 97U877B device) Parameter Symbol Pins Condition DC high-level input voltage DC low-level input voltage Input voltage (limits) DC high-level input voltage DC low-level input voltage Input differential-pair cross voltage Input differential voltage Input differential voltage Input current VIH VIL VIN VIH VIL VIX RESET# RESET# RESET#, CK, CK# CK, CK# CK, CK# CK, CK# LVCMOS LVCMOS VID(DC) VID(AC) II CK, CK# CK, CK# RESET# CK, CK# Output disabled current IODL Static supply current Dynamic supply IDDLD IDD N/A CIN Each input Input capacitance Table 11: Min Differential Input Differential Input Differential Input Differential Input Differential Input VI = VDDQ or VSSQ VI = VDDQ or VSSQ RESET# = VSSQ; VI = VIH(AC) or VIL(DC) CK = CK# = LOW CK, CK# = 270 MHz, all outputs open (not connected to PCB) VI = VDDQ or VSSQ Max 0.65 × VDD – – 0.35 × VDD –0.3 VDDQ + 0.3 0.65 × VDD – – 0.35 × VDD (VDDQ/2) - (VDDQ/2) + 0.15 0.15 0.3 VDDQ + 0.4 0.6 VDDQ + 0.4 –10 10 –250 250 100 – Units mV mV mV mV mV V V V µA µA µA – – 500 300 uA mA 2 3 pF PLL Clock Driver Timing Requirements and Switching Characteristics Note: 1 0°C ≤ TOPR ≤ +55°C VDD = +1.8V ±0.1V Parameter Stabilization time Input clock slew rate SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth (-3dB from unity gain) Notes: PDF: 09005aef82255aba/Source: 09005aef82255a83 HVF18C64_128_256x72G.fm - Rev. B 5/06 EN Symbol Min Max Units tL – 1.0 30 0.0 2.0 15 4 33 –0.50 – µs V/ns kHZ % MHz tLS I 1. Timing and switching specifications for the PLL listed above are critical for proper operation of the DDR2 SDRAM Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this PLL is available in JEDEC Standard JESD82. 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM Serial Presence-Detect Serial Presence-Detect Table 12: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA Input leakage current: VIN = GND to VDD Output leakage current: VOUT = GND to VDD Standby current Power supply current, READ: SCL clock frequency = 100 KHz Power supply current, WRITE: SCL clock frequency = 100 KHz Table 13: Symbol Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICCR ICCW 1.7 VDDSPD × 0.7 –0.6 – 0.10 0.05 1.6 0.4 2 3.6 VDDSPD + 0.5 VDDSPD × 0.3 0.4 3 3 4 1 3 V V V V µA µA µA mA mA Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Notes: PDF: 09005aef82255aba/Source: 09005aef82255a83 HVF18C64_128_256x72G.fm - Rev. B 5/06 EN Symbol Min Max Units Notes tAA 0.2 1.3 200 – 0 0.6 0.6 – 1.3 – – 100 0.6 0.6 – 0.9 – – 300 – – – 50 – 0.3 400 – – – 10 µs µs ns ns µs µs µs ns µs µs KHz ns µs µs ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR fSCL tSU:DAT tSU:STA t SU:STO tWRC 2 2 3 4 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM Serial Presence-Detect Table 14: Serial Presence-Detect Matrix “1”/“0”: serial data, “driven to HIGH”/“driven to LOW” Byte Description 0 1 2 3 4 5 6 7 8 9 Number of SPD bytes used by Micron Total number of bytes in SPD device Fundamental memory type Number of row addresses on assembly Number of column addresses on assembly DIMM height and module ranks Module data width Module data width (continued) Module voltage interface levels SDRAM cycle time, tCK (CL = MAX value, see byte 18) 10 SDRAM access from clock,tAC (CL = MAX value, see byte 18) 11 12 13 14 15 16 17 18 Module configuration type Refresh rate/type SDRAM device width (primary SDRAM) Error-checking SDRAM data width Reserved Burst lengths supported Number of banks on SDRAM device CAS latencies supported 19 20 21 22 Module thickness DDR2 DIMM type SDRAM module attributes SDRAM device attributes: weak driver (01) or 50Ω ODT (03) 23 SDRAM cycle time, tCK, MAX CL - 1 24 SDRAM access from CK, tAC, MAX CL - 1 25 SDRAM cycle time, tCK, MAX CL - 2 26 SDRAM access from CK, tAC, MAX CL - 2 27 28 29 30 MIN row precharge time, tRP MIN row active to row active, tRRD MIN RAS# to CAS# delay, tRCD MIN RAS# pulse width, tRAS (see note 1) 31 Module rank density PDF: 09005aef82255aba/Source: 09005aef82255a83 HVF18C64_128_256x72G.fm - Rev. B 5/06 EN Entry (Version) MT18HVF12872/ MT18HVF12872P 128 256 DDR2 SDRAM 13, 14 10 17.9mm, single rank 72 0 SSTL 1.8V -667 -53E -40E -667 -53E -40E ECC/ECC and parity 7.81µs/SELF 4 4 80 08 08 0E 0B 00 48 00 05 30 3D 50 45 50 60 02/06 82 04 04 00 0C 08 38 18 01 01 04 03 01 3D 50 45 50 60 50 00 45 00 3C 1E 3C 2D 28 01 4, 8 4 or 8 -667 (5, 4, 3) -53E/-40E (4, 3) Registered DIMM -667 -53E/-40E -667 -53E/-40E -667 -53E -40E -667 -53E/-40E(N/S) -667 -53E/-40E(N/S) -667/-53E -40E 1GB 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM Serial Presence-Detect Table 14: Serial Presence-Detect Matrix (continued) “1”/“0”: serial data, “driven to HIGH”/“driven to LOW” Byte Description 32 Address and command setup time, tISb 33 Address and command hold time, tIHb 34 Data/data mask input setup time, tDSb 35 Data/data mask input hold time, tDHb 36 37 Write recovery time, tWR Write to read CMD delay, tWTR 38 39 40 41 Read to precharge CMD delay, tRTP Memory analysis probe Extension for bytes 41 and 42 MIN active auto refresh time, tRC 42 43 44 MIN auto refresh to active/ auto refresh command period, tRFC SDRAM device MAX cycle time, tCKMAX SDRAM device MAX DQS–DQ skew time, tDQSQ 45 SDRAM device MAX read data hold skew factor, tQHS 46 47–61 62 63 PLL relock time Optional features, not supported SPD revision Checksum for bytes 0–62 64 65-71 72 73-90 91 92 93 94 95-98 99-127 Manufacturer’s JEDEC ID code Manufacturer’s JEDEC ID code Manufacturing location Module part number (ASCII) PCB identification code Identification code (continued) Year of manufacture in BCD Week of manufacture in BCD Module serial number Manufacturer-specific data (RSVD) Notes: PDF: 09005aef82255aba/Source: 09005aef82255a83 HVF18C64_128_256x72G.fm - Rev. B 5/06 EN Entry (Version) MT18HVF12872/ MT18HVF12872P -667 -53E -40E -667 -53E -40E -667/-53E -40E -667 -53E -40E 20 25 35 27 37 47 10 15 17 22 27 3C 1E 28 1E 00 00 3C 37 69 -667/-53E -40E -667/-53E -40E -667 -53E -40E -667 -53E -40E Release 1.2 -667 -53E -40E MICRON (continued) 01–12 1–9 0 80 18 1E 23 22 28 2D 0F 00 12 8D/91 38/3C 9F/A3 2C FF 01–0C Variable data 01–09 00 Variable data Variable data Variable data – 1. The tRAS SPD value shown is based on the JEDEC standard value of 45ns; the actual device specification is tRAS = 40ns. 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM Module Dimensions Module Dimensions Figure 4: 240-Pin DDR2 DIMM 3.99 (0.157) MAX FRONT VIEW 133.50 (5.256) 133.20 (5.244) 2.00 (0.079) R (4X) U1 U2 U3 U4 U5 U6 2.50 (0.098) D (2X) 2.30 (0.091) TYP U9 U8 U10 U11 U7 10.00 (0.394) TYP 0.75 (0.029) R PIN 1 1.0 (0.039) TYP 1.0 (0.039) TYP 0.80 (0.040) TYP PIN 120 18.05 (0.711) 17.75 (0.699) 1.37 (0.054) 1.17 (0.046) 5.0 (0.250) TYP 63.0 (2.48) TYP 55.0 (2.16) TYP 123.0 (4.84) TYP BACK VIEW U12 U13 U14 U15 U16 U17 U19 U18 U20 U21 3.05 (0.012) TYP PIN 240 PIN 121 2.20 (0.087) TYP 70.68 (2.78) TYP Notes: 1. All dimensions are in millimeters (inches). 2. The dimensional diagram is for reference only. Refer to the MO document for complete design dimensions. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 [email protected] www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef82255aba/Source: 09005aef82255a83 HVF18C64_128_256x72G.fm - Rev. B 5/06 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved.