FUJITSU SEMICONDUCTOR DATA SHEET DS07-12525-2E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89680 Series MB89689/P689/W689/PV680 ■ OUTLINE The MB89680 series is a line of single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as dual-clock control system, four operating speed control stages, timers, PWM timer, a serial interface, a UART, an A/D converter, and an external interrupt. ■ FEATURES • • • • • • • • • • • • • • • • • • F2MC-8L family CPU core Dual-clock control system Maximum memory space: 64 Kbytes Minimum execution time: 0.5 µs/8 MHz Interrupt processing time: 4.5 µs/8 MHz I/O ports: max. 85 channels 21-bit timebase counter 8-bit PWM timer 8/16-bit timer UART Serial I/O with 1-byte buffer 8-bit A/D converter Pulse width counter Modem signal output External interrupts: 16 channels Power-on reset function Low-power consumption modes (subclock mode, watch mode, sleep mode, and stop mode) CMOS technology ■ PACKAGE 100-pin Plastic QFP 100-pin Ceramic QFP 100-pin Ceramic MQFP (FPT-100P-M06) (FPT-100C-A02) (MQP-100C-P01) MB89680 Series ■ PRODUCT LINEUP Part number Item Classification ROM size MB89689 MB89P689 MB89W689 Mass-produced One-time PROM product product (mask ROM product) 60 K × 8 bits (internal mask ROM) EPROM product 60 K × 8 bits (internal PROM) MB89PV680 Piggyback/ evaluation product (for development) 60 K × 8 bits (internal EPROM) 60 K × 8 bits (external ROM) 2.0 K × 8 bits RAM size Instruction bit length 8 bits Instruction length 1 byte to 3 bytes Data bit length 1, 8, 16 bits Number of instructions 136 Clock generator Built-in Minimum execution time 0.5 µs/8 MHz to 8 µs/8 MHz, 61 µs/32.768 kHz Interrupt processing time 4.5 µs/8 MHz to 72 µs/8 MHz, 562.5 µs/32.768 kHz Ports ( ) indicate dual function ports Output ports (N-ch open-drain): Output ports (CMOS): I/O ports (N-ch open-drain): I/O ports (CMOS): Total: 8 bits × 1 channel 8-bit PWM timer 8 bits × 2 channels, or 16 bits × 1 channel 8/16-bit timer/counter With 1-byte buffer × 1 channel 8-bit serial I/O 8 bits × 8 channels 8-bit A/D converter UART Pulse width counter Full-duplex double buffer Transfer data length: 6 bits to 8 bits 8 baud rates selectability, external clock available 5-bit noise reduction circuit Pulse edge detectable and selectable (rising, falling, and both edges) Software modem transmission circuit 1200-bps/2400-bps modem output External interrupt 16 channels Timebase timer 21 bits Watch prescaler 15 bits Standby mode Watch mode, subclock mode, sleep mode, and stop mode Process Power supply voltage* EPROM for use 21 (8) 8 (0) 8 (6) 48 (29) 85 (43) CMOS 2.2 V to 6.0 V 2.7 V to 6.0 V MBM27C512-20TV * : Varies with conditions such as the operating frequency. (See section “■ ELECTRICAL CHARACTERISTICS.”) 2 MB89680 Series ■ PACKAGE AND CORRESPONDING PRODUCTS MB89689 MB89P689 Package MB89W689 MB89PV680 × × FPT-100P-M06 FPT-100C-A02 × MQP-100C-P01 × : Available × × × : Not available Note: For more information about each package, see section “■ Package Dimensions.” ■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. 2. Current Consumption In the case of the MB89PV680, add the current consumed by the EPROM which is connected to the top socket. When operated at low speed, the product with an OTPROM or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “■ Mask Options.” Take particular care on the following points: • Options are fixed on the MB89PV680. 3 MB89680 Series ■ PIN ASSIGNMENT 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PA7/INT3 PA6/INT2 PA5/INT1 PA4/INT0 PA3/INLB N.C. AVR (AVCC) VCC P57/AN07 P56/AN06 P55/AN05 P54/AN04 P53/AN03 P52/AN02 P51/AN01 P50/AN00 (AVSS) VSS PA2/INLA PA1/INL9 PA0/INL8 (Top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P25 P26 P27 P40 P41 P42 P43 P44 P30/PWM P31/BUZR P32/MSKI P33 P34 P35/UCK1 P36/UI1 P37/UO1 P60/TMO1 P61/TMO2 P62/TCLK VCC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCC X1A X0A MOD0 MOD1 X0 X1 VSS RST P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 (FPT-100P-M06) (FPT-100C-A02) 4 P97/INL7 P96/INL6 P95/INL5 P94/INL4 P93/INL3 P92/INL2 P91/INL1 P90/INL0 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75/BSO2 P74/BSI2 P73/BSK2 VSS P72/UO2 P71/UI2 P70/UCK2 P67/BSO1 P66/BSI1 P65/BSK1 P64 P63/MSKO MB89680 Series O2 O3 VSS N.C. O4 O5 OE A2 N.C. A3 A11 A4 A9 A5 A8 A6 A7 A1 A12 A10 A15 A0 N.C. CE 101 N.C. V CC O8 132 01 A14 O7 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P97/INL7 P96/INL6 P95/INL5 P94/INL4 P93/INL3 P92/INL2 P91/INL1 P90/INL0 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75/BSO2 P74/BSI2 P73/BSK2 VSS P72/UO2 P71/UI2 P70/UCK2 P67/BSO1 P66/BSI1 P65/BSK1 P64 P63/MSKO P25 P26 P27 P40 P41 P42 P43 P44 P30/PWM P31/BUZR P32/MSKI P33 P34 P35/UCK1 P36/UI1 P37/UO1 P60/TMO1 P61/TMO2 P62/TCLK VCC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCC X1A X0A MOD0 MOD1 X0 X1 VSS RST P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 O6 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PA7/INT3 PA6/INT2 PA5/INT1 PA4/INT0 PA3/INLB N.C. AVR (AVCC) VCC P57/AN07 P56/AN06 P55/AN05 P54/AN04 P53/AN03 P52/AN02 P51/AN01 P50/AN00 (AVSS) VSS PA2/INLA PA1/INL9 PA0/INL8 (Top view) (MQP-100C-P01) • Pin assignment on package top (MB89PV680 only) Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 101 N.C. 109 A2 117 N.C. 125 OE 102 A15 110 A1 118 O4 126 N.C. 103 A12 111 A0 119 O5 127 A11 104 A7 112 N.C. 120 O6 128 A9 105 A6 113 O1 121 O7 129 A8 106 A5 114 O2 122 O8 130 A13 107 A4 115 O3 123 CE 131 A14 108 A3 116 VSS 124 A10 132 VCC N.C.: Internally connected. Do not use. 5 MB89680 Series ■ PIN DESCRIPTION Pin no. Pin name QFP*1, MQFP*2 Function 1 VCC — Power supply pin 2 X1A A Subclock crystal oscillator pins (32.768 kHz) 3 X0A 4 MOD0 B 5 MOD1 Operating mode selection pins Connect to VSS (GND) when using. 6 X0 A Main clock crystal oscillator pins (8 MHz) 7 X1 8 VSS — Power supply (GND) pin 9 RST C Reset input pin 10 to 17 P00 to P07 D General-purpose I/O ports 18 to 25 P10 to P17 D General-purpose I/O ports 26 to 33 P20 to P27 F General-purpose output ports 34 to 38 P40 to P44 I General-purpose output ports 39 P30/PWM E General-purpose I/O port Also serve as an 8-bit PWM. 40 P31/BUZR E General-purpose I/O port Also serve as a buzzer output. 41 P32/MSKI E General-purpose I/O port Also serve as a pulse width counter. 42, 43 P33, P34 E General-purpose I/O ports 44, 45, 46 P35/UCK1, P36/UI1, P37/UO1 E General-purpose I/O ports Also serve as a UART I/O 1. 47, 48, 49 P60/TMO1, P61/TMO2, P62/TCLK E General-purpose I/O ports Also serve as an 8/16-bit timer. 50 VCC — Power supply pin 51 P63/MSKO E General-purpose I/O port Also serve as a modem output. 52 P64 E General-purpose I/O port 53, 54, 55 P65/BSK1, P66/BSI1, P67/BSO1 E General-purpose I/O ports Also serve as a serial I/O 1 with 1-byte buffer. *1: FPT-100P-M06, FPT-100C-A02 *2: MQP-100C-P01 6 Circuit type (Continued) MB89680 Series (Continued) Pin no. QFP*1, MQFP*2 Pin name Circuit type Function 56, 57, 58 P70/UCK2, P71/UI2, P72/UO2 H General-purpose I/O ports Also serve as a UART I/O 2. 59 VSS — Power supply (GND) pin 60, 61, 62 P73/BSK2, P74/BSI2, P75/BSO2 H General-purpose I/O ports Also serve as a serial I/O 2 with 1-byte buffer. 63, 64 P76, P77 H General-purpose I/O ports 65 to 72 P80 to P87 I General-purpose output ports 73 to 80 P90/INL0 to P97/INL7 E General-purpose I/O ports External interrupt input is hysteresis input. 81 to 83 PA0/INL8 to PA2/INLA E General-purpose I/O ports External interrupt input is hysteresis input. VSS (AVSS) — (A/D converter) power supply (GND) pin P50/AN00 to P57/AN07 G General-purpose I/O ports Also serve as an analog input. 93 VCC (AVCC) — (A/D converter) power supply pin 94 AVR — A/D converter reference voltage input pin 95 N.C. — Internally connected pins Be sure to leave them open. PA3/INLB, PA4/INT0 to PA7/INT3 E General-purpose I/O ports External interrupt input is hysteresis input. 84 85 to 92 96 to 100 *1: FPT-100P-M06, FPT-100C-A02 *2: MQP-100C-P01 7 MB89680 Series ■ I/O CIRCUIT TYPE Type Circuit Remarks A X1, X1A • Main clock (A2) (At an oscillation feedback resistor of approximately 1 MΩ/5.0 V) • Subclock (A1) (At an oscillation feedback resistor of approximately 4.5 MΩ/5.0 V * X0, X0A * The subclock circuit in the MB89PV680 contains no oscillation feedback resistor. Standby control signal B C • At an output pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V • Hysteresis input R P-ch N-ch D • CMOS output • CMOS input • Pull-up resistor optional R P-ch P-ch N-ch E • CMOS output • Hysteresis input • Pull-up resistor optional R P-ch P-ch N-ch (Continued) 8 MB89680 Series (Continued) Type Circuit Remarks F • CMOS output P-ch N-ch G • N-ch open-drain output • Analog input P-ch N-ch Analog input H • N-ch open-drain output • Hysteresis input • Pull-up resistor optional R P-ch N-ch I • N-ch open-drain output • Pull-up resistor optional R P-ch N-ch 9 MB89680 Series ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AV CC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode. 10 MB89680 Series ■ PROGRAMMING TO THE EPROM ON THE MB89P689/W689 The MB89P689/W689 is an OTPROM version of the MP89680 series. 1. Features • 60-Kbyte PROM on chip • Options can be set using the EPROM programmer. • Equivalent to the MBM27C1001 in EPROM mode (when programmed with the EPROM programmer) and supporting the 4-byte programming mode 2. Memory Space Memory space in each mode such as 60-Kbyte PROM, option area is diagrammed below. Address Single chip 00000H EPROM mode (Corresponding addresses on the EPROM programmer) 00000H I/O 00080H RAM 2 KB Not available 00880H Not available 00FE4H 00FE4H Option area Option area 00FFCH 01000H 00FFCH 01000H PROM 60 KB PROM 60 KB 0FFFFH 0FFFFH Not available 1FFFFH 3. Programming to the EPROM In EPROM mode, the MB89P689 functions equivalent to the MBM27C1001. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. When the operating ROM area for a single chip is 60 Kbytes (1000H to FFFFH) the PROM can be programmed as follows: • Programming procedure (1) Set the EPROM programmer to MBM27C1001. (2) Load program data into the EPROM programmer at 1000H to FFFFH. Load option data into addresses 0FE4H to 0FFCH of the EPROM programmer. (For information about each corresponding option, see “8. Setting PROM Options.”) (3) Program to 0FE4H to 0FFCH and 1000H to FFFFH with the EPROM programmer. 11 MB89680 Series 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. Program, verify Aging +150°C, 48 Hrs. Data verification Assembly 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 6. MB89W689 Erasure In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an ultraviolet light source. A dosage of 10 W-seconds/cm2 is required to completely erase an internal EPROM. This dosage can be obtained by exposure to an ultraviolent lamp (wavelength of 2537 Angstroms (Å)) with intensity of 12000µW/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the internal EPROM and similar devices, will erase with light sources having wavelengths shorter than 4000 Å. Although erasure time will be much longer than with UV source at 2537 Å, nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package windows should be covered by an opaque label or substance. 12 MB89680 Series 7. EPROM Programmer Socket Adapter Part no. MB89P689PF Package QFP-100 Compatible socket adapter Sun Hayato Co., Ltd. ROM-100QF-32DP-8LA Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106 8. Setting PROM Options The programming procedure is the same as that for the program data. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: • PROM option bit map Address 00FE4H Bit 7 Bit 6 Bit 5 Vacancy Vacancy Vacancy Bit 4 Single/dualclock system Readable Readable Readable 1: Dual clock and writable and writable and writable 2: Single clock Bit 3 Bit 2 Bit 1 Bit 0 Reset output 1: Yes 0: No Power-on reset 1: Yes 0: No Oscillation stabilization time 11 218/FCH 01 212/FCH 10 216/FCH 00 2 3/FCH P07 Pull-up 00FE8H 1: No 0: Yes P06 Pull-up 1: No 0: Yes P05 Pull-up 1: No 0: Yes P04 Pull-up 1: No 0: Yes P03 Pull-up 1: No 0: Yes P02 Pull-up 1: No 0: Yes P01 Pull-up 1: No 0: Yes P00 Pull-up 1: No 0: Yes P17 Pull-up 00FECH 1: No 0: Yes P16 Pull-up 1: No 0: Yes P15 Pull-up 1: No 0: Yes P14 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes P37 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes P67 Pull-up P66 Pull-up P65 Pull-up P64 Pull-up Readable Readable Readable 1: No and writable and writable and writable 0: Yes P63 Pull-up 1: No 0: Yes P62 Pull-up 1: No 0: Yes P61 Pull-up 1: No 0: Yes P60 Pull-up 1: No 0: Yes P97 Pull-up 1: No 0: Yes P96 Pull-up 1: No 0: Yes P95 Pull-up 1: No 0: Yes P94 Pull-up 1: No 0: Yes P93 Pull-up 1: No 0: Yes P92 Pull-up 1: No 0: Yes P91 Pull-up 1: No 0: Yes P90 Pull-up 1: No 0: Yes PA7 Pull-up 00FFCH 1: No 0: Yes PA6 Pull-up 1: No 0: Yes PA5 Pull-up 1: No 0: Yes PA4 Pull-up 1: No 0: Yes PA3 Pull-up 1: No 0: Yes PA2 Pull-up 1: No 0: Yes PA1 Pull-up 1: No 0: Yes PA0 Pull-up 1: No 0: Yes 00FF0H 00FF4H 00FF8H Notes: • Note that the option setting area addresses are at intervals of four addresses to support the 4-byte programming mode. • In three bytes between adjacent setup addresses, the value written to the preceding setup address is mirrored. Be sure to set the same data in the programmer. • Each bit is set to ‘1’ as the initialized value. 13 MB89680 Series ■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C512-20TV 2. Programming Socket Adapter Package LCC-32 (Rectangle) Adapter socket part number ROM-32LC-28DP-YG Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106 3. Memory Space Address MB89PV680 MBM27C512 0000H I/O 0080H 0100H Register 0200H RAM 2 KB 0880H 1000H 1000H External ROM 60 KB FFFFH EPROM 60 KB FFFFH 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C512. (2) Load program data into the EPROM programmer at 1000H to FFFFH. (3) Program to 1000H to FFFFH with the EPROM programmer. 14 MB89680 Series ■ BLOCK DIAGRAM CMOS I/O Timebase timer P30/PWM Reset circuit (Watchdog) RST X0 X1 Port 3 8-bit PWM timer Buzzer output P31/BUZR P32/MSKI P33 P34 P35/UCK1 P36/UI1 P37/UO1 Modem timer Main clock oscillator (max 8 MHz) UART Clock controller Port 5 8 8-bit A/D converter 8 P50/AN00 t o P57/AN07 CMOS I/O 8/16-bit timer P60/TMO1 P61/TMO2 P62/TCLK Port 6 8 CMOS I/O port 1 P40 t o P44 CMOS I/O port 2 Modem output 8-bit serial I/O with 1-byte buffer P63/MSKO P64 P65/BSK1 P66/BSI1 P67/BSO1 N-ch open-drain I/O P70/UCK2 P71/UI2 P72/UO2 P73/BSK2 P74/BSI2 P75/BSO2 P76 P77 RAM Port 7 P20 to P27 8 5 N-ch open-drain output CMOS I/O port 0 Internal data bus P10 to P17 8 N-ch open-drain output port 4 Internal data bus P00 to P07 Subclock oscillator (32.768 kHz) F2MC-8L CPU ROM N-ch open-drain output port 8 CMOS I/O Other pins VCC × 2, VSS × 2 MOD0, MOD1, N.C. AVCC, AVR, AVSS External interrupt 2 External interrupt 1 12 4 Port 9 and port A X0A X1A 8 8 4 4 P80 t o P87 P90/INL0 t o P97/INL7 PA0/INL8 t o PA3/INLB PA4/INT0 t o PA7/INT3 15 MB89680 Series ■ CPU CORE 1. Memory Space The microcontrollers of the MB89680 series offer 64 Kbytes of memory for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end of I/O area, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89680 series is structured as illustrated below. • Memory space MB89689 0000H 0000H I/O MB89PV680 0000H I/O I/O 007FH 0080H 007FH 0080H 007FH 0080H 00FFH 0100H 00FFH 0100H 00FFH 0100H Register 01FFH 0200H RAM 2.0 KB 087FH 0880H Register 01FFH 0200H 0FFFH 1000H Register 01FFH 0200H 0FFFH 1000H Vacancy 0FFFH 1000H ROM 60 KB FFFFH RAM 2.0 KB 087FH 0880H Vacancy ROM 60 KB FFFFH RAM 2.0 KB 087FH 0880H Vacancy 16 MB89P689 MB89W689 External ROM 60 KB FFFFH MB89680 Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): A 16-bit register for indicating the instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code 16 bits Initial value : Program counter PC FFFDH A : Accumulator T : Temporary accumulator Indeterminate IX : Index register Indeterminate EP : Extra pointer Indeterminate SP : Stack pointer Indeterminate PS : Program status Indeterminate I-flag = 0, IL1, 0 = 11 The other bit values are indeterminate. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) • Structure of the program status register 15 PS 14 13 12 RP 11 10 9 8 Vacancy Vacancy Vacancy RP 7 6 H I 5 4 IL1, 0 3 2 1 0 N Z V C CCR 17 MB89680 Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. • Rule for conversion of actual addresses of the general-purpose register area Lower OP codes RP “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ b1 b0 ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared to ‘0’ at the reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level High-low 0 0 0 High 0 1 1 1 0 2 1 1 3 Low N-flag: Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit is cleared to ‘0’. Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise. V-flag: Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the overflow does not occur. C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. Set to the shift-out value in the case of a shift instruction. 18 MB89680 Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used. The bank currently in use is indicated by the register bank pointer (RP). • Register bank configuration This address = 0100H + 2 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 19 MB89680 Series ■ I/O MAP Address Read/write Register name 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H Register description (Vacancy) 06H 07H (R/W) SYCC System clock control register 08H (R/W) SMC Standby control register 09H (R/W) WDTC Watchdog timer control register 0AH (R/W) TBTC Timebase timer control register 0BH (R/W) WPCR Watch prescaler control register 0CH (R/W) PDR3 Port 3 data register 0DH (R/W) DDR3 Port 3 data direction register 0EH (R/W) PDR4 Port 4 data register 0FH (R/W) BZCR Buzzer register 10H (R/W) PDR5 Port 5 data register 11H (Vacancy) 12H (R/W) PDR6 Port 6 data register 13H (R/W) DDR6 Port 6 data direction register 14H (R/W) PDR7 Port 7 data register 15H 16H (Vacancy) (R/W) PDR8 17H Port 8 data register (Vacancy) 18H (R/W) PDR9 Port 9 data register 19H (R/W) DDR9 Port 9 data direction register 1AH (R/W) PDRA Port A data register 1BH (R/W) DDRA Port A data direction register 1CH (Vacancy) 1DH 1EH (R/W) CNTR PWM control register 1FH (W) COMR PWM compare register 20H (Vacancy) 21H 22H (R/W) SBMR Serial mode register with 1 byte buffer (Continued) 20 MB89680 Series (Continued) Address Read/write Register name 23H (R/W) SBFR (W) SBUFW Serial buffer write register (R) SBUFR Serial buffer read register 25H (R) SBDR Serial data register with 1 byte buffer 26H (R/W) T2CR Timer 2 control register 27H (R/W) T1CR Timer 1 control register 28H (R/W) T2DR Timer 2 data register 29H (R/W) T1DR Timer 1 data register 2AH (R/W) MODC Modem output control register 2BH (R/W) MODA Modem output data register 24H 2CH Register description Serial flag register with 1 byte buffer (Vacancy) 2DH (R/W) ADC1 A/D converter control 1 register 2EH (R/W) ADC2 A/D converter control 2 register 2FH (R/W) ADCD A/D converter data register 30H (R/W) EIE1 External interrupt 1 enable register 31H (R/W) EIF1 External interrupt 1 flag register 32H (R/W) EIE2 External interrupt 2 enable register 33H (R/W) EIF2 External interrupt 2 flag register 34H (R/W) MDC1 Modem timer control 1 register 35H (R/W) MDC2 Modem timer control 2 register 36H (R) MLDH Modem timer “H” level data register 37H (R) MLDL Modem timer “L” level data register 38H (R/W) SMC UART serial mode control register 39H (R/W) SRC UART serial rate control register 3AH (R/W) SSD UART serial status and data register 3BH (R) SIDR UART serial input data register 3CH (W) SODR UART serial output data register 3DH (R/W) SSEL Serial I/O port switching register 3EH to 7BH (Vacancy) 7CH (W) ILR1 Interrupt level 1 setting register 7DH (W) ILR2 Interrupt level 2 setting register 7EH (W) ILR3 Interrupt level 3 setting register 7FH (Vacancy) Note: Do not use (vacancies). 21 MB89680 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol Value Unit Remarks Min. Max. VCC VSS – 0.3 VSS + 7.0 V AVCC VSS – 0.3 VSS + 7.0 V Set VCC = AVCC* AVR VSS – 0.3 VSS + 7.0 V AVR must not exceed “AVCC + 0.3 V”. VI VSS – 0.3 VCC + 0.3 V Except P4, P7, P8 VI VSS – 0.3 VSS + 7.0 V P4, P7, P8 Output voltage VO VSS – 0.3 VCC + 0.3 V “L” level maximum output current IOL 20 mA Peak value “L” level average output current I OLAV 10 mA Average value (operating current × operating rate) “L” level total maximum output current ∑IOL 120 mA Peak value “L” level total average output current ∑IOLAV 40 mA Average value (operating current × operating rate) “H” level maximum output current IOH –20 mA Peak value “H” level average output current I OHAV –10 mA Average value (operating current × operating rate) “H” level total maximum output current ∑IOH –60 mA Peak value “H” level total average output current ∑IOHAV –20 mA Average value (operating current × operating rate) Power consumption PD 200 mW Operating temperature TA –40 +85 °C Storage temperature Tstg –55 +150 °C Power supply voltage Input voltage * : Use AVCC and VCC set to the same voltage. Take care so that AVCC does not exceed VCC, such as when power is turned on. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 22 MB89680 Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Symbol Parameter Value Unit Remarks Min. Max. VCC, AVCC 2.2* 6.0* V Normal operation assurance range* (MB89689) VCC, AVCC 2.7* 6.0* V Normal operation assurance range* (MB89P689/W689/PV680) VCC, AVCC 1.5 6.0 V Retains the RAM state in stop mode A/D converter reference input voltage AVR 0.0 AVCC V Operating temperature TA –40 +85 °C Power supply voltage * : This values vary with the operating frequency. See Figure 1. Figure 1 Operating Voltage vs. Main Clock Operating Frequency 6 Operating voltage (V) 5 Analog accuracy assured in the AVCC = 3.5 V to 6.0 V range Operation assurance range 4 3 2 1 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 Main clock operating frequency (MHz) (at an instruction cycle of 4/F CH) Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent of the instruction cycle, see minimum execution time if the operating speed is switched using a gear. 23 MB89680 Series WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 24 MB89680 Series 3. DC Characteristics (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter “H” level input voltage “L” level input voltage Pin name Symbol Condition Value Min. Typ. Max. Unit VIH P0, P1 0.7 VCC — VCC + 0.3 V VIHS P3, P6, P9, PA, RST, MOD0, MOD1, X0, X0A 0.8 VCC — VCC + 0.3 V VIHS2 P7 0.8 VCC VSS + 7.0 V VIL P0, P1 VILS VSS − 0.3 — 0.3 VCC V P3, P6, P7, P9, PA, RST, MOD0, MOD1, X0, X0A VSS − 0.3 — 0.2 VCC V — Open-drain output pin applied VD voltage P4, P7, P8 VSS − 0.3 — VSS + 7.0 V P5 VSS − 0.3 — VCC + 0.3 V “H” level output voltage VOH P0 to P3, P6, P9, PA 2.4 — — V VOL1 P0 to P4, P6 to P9, IOL = 4.0 mA PA — — 0.4 V VOL2 RST IOL = 4.0 mA — — 0.4 V ILI P0 to P9, PA, MOD0, MOD1 0.45 V < VI < VCC — — ±5 µA VCC FCH = 8 MHz VCC = 5.0 V Main clock opration Highest gear speed — 13 26 mA VCC FCH = 8 MHz VCC = 5.0 V Main sleep mode Highest gear speed — 4 8 mA “L” level output voltage Input leakage current (Hi-z output leakage current) ICC Power supply current ICCS1 IOH = –2.0 mA Remarks FCH = 32.768 kHz ICCS2 VCC VCC = 3.0 V Subclock sleep mode — 25 50 µA ICCH1 VCC TA = +25°C Subclock stop mode — — 1 µA (Continued) 25 MB89680 Series (Continued) (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Pin name Symbol ICCH2 VCC Condition TA = +85°C Subclock stop mode Value Unit Min. Typ. Max. — 1 10 µA Remarks FCL = 32.768 kHz Power supply current ICSB VCC VCC = 3.0 V Subclock operation — 50 100 µA ICCT VCC VCC = 3.0 V Watch mode — — 15 µA IA AVCC — 1.5 3.5 When A/D mA conversion is activated — 1 5 µA — 10 — pF FCH = 8 MHz IAH Input capacitance CIN 26 AVCC Other than AVCC, AVSS, VCC, and VSS f = 1 MHz When A/D conversion is stopped MB89680 Series 4. AC Characteristics (1) Reset Timing (VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter RST “L” pulse width tZLZH RST “H” pulse width tZHZL Value Condition — Unit Min. Max. 48 tXCYL* — ns 24 tXCYL* — ns Remarks * : tXCYL is the oscillation cycle input to the X0. tZHZL tZLZH RST 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC (2) Specifications for Power-on Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Power supply rising time tR Power supply cut-off time tOFF Condition — Value Unit Remarks Min. Max. — 50 ms Power-on reset function only 1 — ms Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time selected. For example, when the main clock is operating at F CH = 8 MHz and the oscillation stabilization time is 212/FCH, the oscillation stabilization time is 0.5 ms. Therefore, the maximum value of power supply rising time is about 0.5 ms. When increasing the supply voltage during operation, voltage variation should be within twice the intended increment so that the voltage rises as smoothly as possible. tR tOFF 4.5 V VCC 0.2 V 0.2 V 0.2 V 27 MB89680 Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Input clock frequency Clock cycle time Input clock duty rate Input clock rising/falling time Symbol Pin name Condition Value Min. Typ. Max. Unit Remarks FCH X0, X1 1 — 8 MHz Main clock FCL X0A, X1A — 32.768 — kHz Subclock tHCYL X0, X1 125 — 1000 ns Main clock tLCYL X0A, X1A — 30.5 — µs Subclock duty*1 X0 30 — 70 % 2 — duty1* X1 30 — 70 % tCR1 X0 — — 24 ns tCF1 X0 — — 24 ns tCR2 X0A — — 200 ns tCF2 X0A — — 200 ns External clock *1: duty = PWH/tHCYL *2: duty1= PWHL/tHCYL • Main clock timing conditions tHCYL 0.8 VCC 0.8 VCC 0.8 VCC X0 0.2 VCC PWH 0.2 VCC PWL tCR tCF • Main clock configurations When a crystal or ceramic resonator is used X0 When an external clock is used X0 X1 X1 Open FCH C0 28 C1 FCH MB89680 Series • Subclock timing conditions tLCYL 0.8 VCC 0.8 VCC 0.8 VCC X0A 0.2 VCC PWHL 0.2 VCC PWLL tCR tCF • Subclock configurations When a crystal or ceramic resonator is used X0A When an external clock is used X0A X1A X1A Open FCL C0 C1 FCL (4) Instruction Cycle (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Minimum execution time (instruction cycle) Symbol Value (typical) Unit Remarks tinst 4/FCH, 8/FCH, 16/FCH, 64/FCH µs (4/FCH) tinst = 0.5 µs when operating at FCH = 8 MHz tinst 2/FCL µs tinst = 61.036 µs when operating at FCL = 32.768 kHz 29 MB89680 Series (5) Serial I/O Timing (AVCC = VCC = 5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter Pin name Condition Value Max. 2 tinst* — µs –200 200 ns 1/2 tinst* — µs Serial clock cycle time tSCYC BSK/UCK BSK/UCK ↓ → BSO/UO time tSLOV BSK/UCK, BSO/UO Valid BSI/UI → BSK/UCK ↑ tIVSH BSI/UI, BSK/UCK BSK/UCK ↑ → valid BSI/UI hold time tSHIX BSK/UCK, BSI/UI 1/2 tinst* — µs Serial clock “H” pulse width tSHSL BSK/UCK 1 tinst* — µs Serial clock “L” pulse width tSLSH BSK/UCK 1 tinst* — µs BSK/UCK ↓ → BSO/UO time tSLOV BSK/UCK, BSO/UO 0 200 ns Valid BSI/UI → BSK/UCK ↑ tIVSH BSI/UI, BSK/UCK 1/2 tinst* — µs BSK/UCK ↑ → valid BSI/UI hold time tSHIX BSK/UCK, BSI/UI 1/2 tinst* — µs Internal shift clock mode External shift clock mode * : For information on tinst, see “(4) Instruction Cycle.” • Internal shift clock mode tSCYC BSK/UCK 2.4 V 0.8 V 0.8 V t SLOV 2.4 V BSO/UO 0.8 V tIVSH BSI/UI tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH BSK/UCK tSHSL 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV BSO/UO 2.4 V 0.8 V tIVSH BSI/UI 30 Unit Min. tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC Remarks MB89680 Series (6) Peripheral Input Timing (AVCC = VCC = 5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Value Pin Min. Max. Unit Peripheral input “H” level pulse width tILIH INL0 to INLB, INT0 to INT3 2 tinst* — µs Peripheral input “L” level pulse width tIHIL INL20 to INLB, INT0 to INT3 2 tinst* — µs Remarks * : For information on tinst, see “(4) Instruction Cycle.” tILIH tIHIL INL0 to INLB INT0 to INT3 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC 31 MB89680 Series 5. A/D Converter Electrical Characteristics (AVCC = VCC = 3.5 V to 6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Pin name Condition Resolution — — AVR = AVCC = 5.0 V Total error — Linearity error Differential linearity error Parameter Value Unit Remarks Min. Typ. Max. — — 8 bit — — — ±1.5 LSB — — — — ±1.0 LSB — — — — ±0.9 LSB AVss –1.0 LSB AVss +0.5 LSB AVss +2.0 LSB mV AVR AVR = AVCC Zero transition voltage V0T — Full-scale transition voltage VFST — –3.0 LSB AVR –1.5 LSB AVR mV Interchannel disparity — — — — 0.5 LSB A/D mode conversion time — — — 44 — tinst* Sense mode conversion time — — — 12 — tinst* — — 10 µA Analog port input current IAIN AN00 to AN07 — Analog input voltage — AN00 to AN07 0.0 — AVR V Reference voltage — AVR 0.0 — AVCC V — 100 300 µA — — 1 µA Reference voltage supply current IR AVR IRH AVR AVR = AVCC = 5.0 V 1 LSB = AVR/256 * : For information on tinst, see “(4) Instruction Cycle.” 6. A/D Converter Glossary • Resolution Analog changes that are identifiable by the A/D converter When the number of bits is 8, analog voltage can be divided into 28 = 256. • Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics • Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error (unit: LSB) The difference between theoretical and actual conversion values 32 MB89680 Series Digital output 1111 1111 1111 • 1110 0000 0000 0000 • • • • • • • • • • • • • • • • • • • Theoretical conversion value Actual conversion value (1 LSB × N + VOT) 1 LSB = AVR 256 Linearity error = Linearity error Differential linearity error = Total error = VNT – (1 LSB × N + VOT) 1 LSB V( N + 1 ) T – VNT – 1 1 LSB VNT – (1 LSB × N + 1 LSB) 1 LSB 0010 0001 0000 VOT VNT V(N + 1)T VFST Analog input 7. Notes on Using A/D Converter • Input impedance of the analog input pins The A/D converter used for the MB89890 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after starting A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 10 kΩ). Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of approx. 0.1 µF for the analog input pin. • Analog Input Equivalent Circuit Sample hold circuit C ≅ 33 pF Analog input pin Comparator If the analog input impedance is higher than 10 kΩ, it is recommended to connect an external capacitor of approx. 0.1 µF. R ≅ 6 kΩ Close for 8 instruction cycles after starting A/D conversion. Analog channel selector • Error The smaller the | AVR – AVSS |, the greater the error would become relatively. 33 MB89680 Series ■ INSTRUCTIONS (136 INSTRUCTIONS) Execution instructions can be divided into the following four groups: • • • • Transfer Arithmetic operation Branch Others Table 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols Symbol Meaning dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir: b Bit direct address (8:3 bits) rel Branch relative address (8 bits) @ Register indirect (Example: @A, @IX, @EP) A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) AH Upper 8 bits of accumulator A (8 bits) AL Lower 8 bits of accumulator A (8 bits) T Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) TH Upper 8 bits of temporary accumulator T (8 bits) TL Lower 8 bits of temporary accumulator T (8 bits) IX Index register IX (16 bits) (Continued) 34 MB89680 Series (Continued) Symbol Meaning EP Extra pointer EP (16 bits) PC Program counter PC (16 bits) SP Stack pointer SP (16 bits) PS Program status PS (16 bits) dr Accumulator A or index register IX (16 bits) CCR Condition code register CCR (8 bits) RP Register bank pointer RP (5 bits) Ri General-purpose register Ri (8 bits, i = 0 to 7) × Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (×) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (( × )) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • • • • “–” indicates no change. dH is the 8 upper bits of operation description data. AL and AH must become the contents of AL and AH prior to the instruction executed. 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 35 MB89680 Series Table 2 Transfer Instructions (48 instructions) Mnemonic ~ # Operation TL TH AH NZVC MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 – – – – – AL AL AL AL AL AL AL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off 5 4 2 3 4 5 3 1 1 3 2 2 – – – AL AL AL – – – AH AH AH – – – dH dH dH –––– –––– –––– ++–– ++–– ++–– MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) AL AL AL – – – – – – – – – – – – – – – AL AL – – – – AH AH AH – – – – – – – – – – – – – – – – AH – – – – dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– Notes: • During byte transfer to A, T ← A is restricted to low bytes. • Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 36 MB89680 Series Table 3 Mnemonic ~ # ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROLC A 2 1 CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation TL TH AH NZVC OP code (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) → C→A – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 C ← A← – – – ++–+ 02 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) (Continued) 37 MB89680 Series (Continued) Mnemonic ~ # AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ # 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI 38 ~ # 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Branch Instructions (17 instructions) Operation If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt Table 5 TL TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – dH – – –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 Other Instructions (9 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – dH – – – – – – – –––– –––– –––– –––– –––– –––R –––S –––– –––– 40 50 41 51 00 81 91 80 90 L F CMP ADDC ADDC A SUBC SUBC A MOV A XOR AND OR CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP MOV CMP DAS MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel R0 R0 #0 rel rel rel rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel R1 R1 #1 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BP A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel R2 R2 #2 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BN A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel R3 R3 #3 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNZ A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel R4 R4 #4 rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BZ A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel R5 R5 #5 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BGE A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel R6 R6 #6 rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BLT A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel R7 R7 #7 rel 8 9 A B C D E F rel CMP CLRB BBC MOVW MOVW MOVW XCHW MOV CMP ADDC SUBC MOV XOR AND OR MOV dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8 CLRB BBC MOVW MOVW MOVW XCHW dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX XOR AND OR DAA A,#d8 A,#d8 A,#d8 XCH XOR AND OR A, T A A A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 MOV A SETC 7 6 CMP JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP E 5 D MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 C 4 B CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC A RORC CMPW ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP A A SETI 9 3 8 ROLC 7 2 6 DIVU A 5 PUSHW POPW MOV MOVW CLRI A A A,ext A,PS 4 MULU RETI 3 1 RET 2 SWAP 1 NOP 0 0 H MB89680 Series ■ INSTRUCTION MAP 39 MB89680 Series ■ MASK OPTIONS Part number MB89689 MB89P689 MB89W689 MB89PV680 Specifying procedure Spcify when ordering masking Set with EPROM programmer Setting not possible Selectable by pin Selectable by pin Fixed to without a pull-up resistor Selectable Selectable Fixed to with power-on reset No. 1 Pull-up resistors P00 to P07, P10 to P17, P30 to P37, P60 to P67, P90 to P97, PA0 to PA7 2 Power-on reset (POR) With power-on reset Without power-on reset 3 Oscillation stabilization time selection (OSC) The initial value of the main clock oscillation stabilization time can be set with WTM1 and WTM0 bit. 4 Reset pin output (RST) With reset output Without reset output Selectable Selectable 5 Clock mode selection (CLK) Dual-clock mode Single-clock mode Selectable Selectable Selectable WTM1 WTM0 0 0: 23/FCH 0 1: 212/FCH 1 0: 216/FCH 1 1: 218/FCH Selectable WTM1 WTM0 0 0: 23/FCH 0 1: 212/FCH 1 0: 216/FCH 1 1: 218/FCH Fixed to oscillation stabilization time of 218/FCH Fixed to with reset output Fixed to dual clock ■ ORDERING INFORMATION Part number 40 Package MB89689PF MB89P689PF 100-pin Plastic QFP (FPT-100P-M06) MB89W689CF 100-pin Ceramic QFP (FPT-100C-A02) MB89PV680CF 100-pin Ceramic MQFP (MQP-100C-P01) Remarks MB89680 Series ■ PACKAGE DIMENSIONS 100-pin Plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) 3.35(.132)MAX (Mounting height) 80 20.00±0.20(.787±.008) 0.05(.002)MIN (STAND OFF) 51 81 50 14.00±0.20 (.551±.008) 12.35(.486) REF 17.90±0.40 (.705±.016) 16.30±0.40 (.642±.016) INDEX 31 100 "A" LEAD No. 1 30 0.65(.0256)TYP 0.30±0.10 (.012±.004) 0.13(.005) 0.15±0.05(.006±.002) M Details of "A" part Details of "B" part 0.25(.010) "B" 0.10(.004) 0.30(.012) 0.18(.007)MAX 18.85(.742)REF 0.53(.021)MAX 22.30±0.40(.878±.016) C 0 10° 0.80±0.20 (.031±.008) 1994 FUJITSU LIMITED F100008-3C-2 Dimensions in mm (inches) 100-pin Ceramic QFP (FPT-100C-A02) 0.51(.020) TYP 8.89(.350)DIA TYP 17.91(.705) TYP 16.00(.630) 14.00±0.25 TYP (.551±.010) 12.34(.486) REF 16.31(.642) TYP INDEX AREA 0.30±0.05 0.65±0.15 (.0256±.0060) (.012±.002) 18.85(.742)REF 0.15±0.05 (.006±.002) 1.60(.063) TYP 0.65±0.15 (.0256±.0060) 4.45(.175)MAX 20.00±0.25 (.787±.010) 23.90(.941) TYP 22.00(.866) TYP 22.30(.878) TYP C 1994 FUJITSU LIMITED F100013SC-1-2 0.80(.0315) TYP Dimensions in mm (inches) 41 MB89680 Series 100-pin Ceramic MQFP (MQP-100C-P01) 18.70(.736)TYP INDEX AREA 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 12.35(.486)TYP +0.40 1.20 –0.20 +.016 .047 –.008 0.65±0.15 (.0256±.0060) 0.65±0.15 (.0256±.0060) 1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 1.27±0.13 (.050±.005) 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP 0.30(.012)TYP 7.62(.300)TYP 0.30±0.08 (.012±.003) 18.85(.742) TYP 0.30±0.08 (.012±.003) +0.40 1.20 –0.20 +.016 .047 –.008 9.48(.373)TYP 11.68(.460)TYP 10.82(.426) 0.15±0.05 MAX (.006±.002) C 42 1994 FUJITSU LIMITED M100001SC-1-2 Dimensions in mm (inches) MB89680 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9802 FUJITSU LIMITED Printed in Japan 44 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. 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