APW7303 3A 24V 340kHz synchronous Buck Converter Features General Description • Wide Input Voltage from 4.5V to 24V • 3A Continuous Output Current APW7303 is a 3A synchronous buck converter with integrated power MOSFETs. The APW7303 design with a • Adjustable Output Voltage from 0.92V to 20V • Intergrated N-MOSFET • Fixed 340kHz Switching Frequency • Stable with Low ESR Ceramic Output Capacitors • Power-On-Reset Detection • Programmable Soft-Start • Over-Temperature Protection rent-limit) into a single package. This device, available SOP-8P, provides a very compact • Current-Limit Protection with Frequency Foldback system solution external components and PCB area. • Enable/Shutdown Function • Small SOP-8P Packages • Lead Free and Green Devices Available current-mode control scheme, can convert wide input voltage of 4.5V to 24V to the output voltage adjustable from 0.92V to 20V to provide excellent output voltage regulation. The APW7303 is also equipped with Power-on-reset, softstart, and whole protections (over-temperature, and cur- Pin Configuration (RoHS Compliant) APW7303 BS VIN LX GND Applications • LCD Monitor/TV • Set-Top Box • DSL, Switch HUB • Notebook Computer 1 2 3 4 9 GND 8 7 6 5 SS EN COMP FB SOP-8P (Top View) 9 Exposed Pad The pin 4 must be connected to the pin 9 (Exposed Pad) Simplified Application Circuit VIN APW7303 VOUT ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 1 www.anpec.com.tw APW7303 Ordering and Marking Information Package Code KA : SOP-8P Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7303 Assembly Material Handling Code Temperature Range Package Code APW7303 KA : APW7303 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol Parameter VIN VIN Supply Voltage (VIN to GND) VLX LX to GND Voltage EN, FB, COMP, SS to GND Voltage Rating Unit -0.3 ~ 30 V -1 ~VIN+0.3 V -0.3 ~ 6 V VBS BS to GND Voltage VLX-0.3 ~ VLX+6 V PD Power Dissipation Internally Limited W TJ Junction Temperature 150 o TSTG Storage Temperature -65 ~ 150 o 260 o TSDR Maximum Lead Soldering Temperature, 10 Seconds C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Thermal Characteristics Symbol θJA θJC Parameter Junction-to-Ambient Resistance in Free Air Typical Value (Note 2) SOP-8P Junction-to-Case Resistance in Free Air (Note 3) SOP-8P Unit 75 o 15 o C/W C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P package. Recommended Operating Conditions (Note 4) Symbol Range Unit VIN Supply Voltage 4.5 ~ 24 V VOUT Converter Output Voltage 0.92~20 V IOUT Converter Output Current 0~3 A VIN Parameter Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 2 www.anpec.com.tw APW7303 Recommended Operating Conditions (Cont.) (Note 4) Symbol TA TJ Parameter Range Ambient Temperature Junction Temperature Unit -40 ~ 85 o -40 ~ 125 o C C Note 4 : Refer to the typical application circuit. Electrical Characteristics Refer to the typical application circuits. These specifications apply over VIN=12V, and TA=25°C, unless otherwise specified. Symbol Parameter APW7303 Test Conditions Unit Min. Typ. Max. SUPPLY CURRENT IVIN IVIN_SD VIN Supply Current VFB=1V, VEN=3V, LX=NC - 1.9 - mA VIN Shutdown Supply Current VEN=0V - 20 40 µA 3.9 4.1 4.3 V - 0.5 - V 0.9 0.92 0.94 V 300 340 380 kHz 110 - kHz POWER-ON-RESET (POR) VIN POR Voltage Threshold VIN Rising VIN POR Hysteresis REFERENCE VOLTAGE VREF Reference Voltage Regulated on FB pin OSCILLATOR AND DUTY CYCLE FOSC Oscillator Frequency Foldback Frequency VFB=0V - Maximum Converter’s Duty VFB=0.92V - 90 - % Minimum On Time (Note 5) - 220 - ns High/low Side MOSFET On Resistance IOUT=3A - 85 - mΩ High/Low Side MOSFET Leakage Current VEN=0V, VLX=0V - - 10 µA POWER MOSFET CURRENT-MODE PWM CONVERTER GEA Error Amplifier Transconductance AVEA Error Amplifier Voltage Gain GCS Switch Current to COMP Voltage Transresistance - 820 - µA/V COMP=NC (Note 5) - 400 - V/V (Note 5) - 5.2 - A/V PROTECTIONS ILIM TOTP High Side MOSFET Current-Limit Peak Current - 5.3 6.5 A Low Side MOSFET Current-Limit From Drain to Source - 1 - A Over-Temperature Trip Point (Note 5) - 160 - °C Over-Temperature Hysteresis (Note 5) - 50 - °C Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 3 www.anpec.com.tw APW7303 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VIN=12V, and TA=25 °C, unless otherwise specified. Symbol Parameter APW7303 Test Conditions Unit Min. Typ. Max. - 6 - µA SOFT-START, ENABLE AND INPUT CURRENTS ISS Soft-Start Current EN Enable Threshold Voltage VIN=4.5~24V 0.4 - 2 V EN Under-Voltage Lockout (UVLO) Threshold VEN rising 2.3 2.5 2.7 V - 200 - mV EN UVLO Hysteresis Note 5: Gurantee by design. Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 4 www.anpec.com.tw APW7303 Typical Operating Characteristics Refer to the “Typical Application Circuit” The test conditions are VIN=12V, VOUT=3.3V, L1=10µH, C2=22µF, TA= 25oC unless otherwise specified. Reference Voltage vs. Junction Temperature 360 0.935 Oscillation Frequency, FOSC (kHz) Reference Voltage, VREF (V) 0.94 0.93 0.925 0.92 0.915 0.91 0.905 0.9 -50 -25 0 25 50 75 100 125 Oscillator Frequency vs. Junction Temperature 350 340 330 320 310 300 -50 150 Junction Temperature, TJ (° C) -25 0 25 50 75 100 VIN Input Current vs. Supply Voltage 150 Output Current vs. Efficiency 2 100 VIN=12V 95 1.8 90 Efficiency (%) VIN Input Current , IVIN(mA) 125 Junction Temperature, TJ (° C) 1.6 1.4 1.2 85 80 VOUT=5V 75 VOUT=3.3V 70 65 VOUT=2.5V 60 55 1.0 0 4 8 12 16 20 50 24 VIN Supply Voltage , VIN(V) Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 0 0.5 1 1.5 2 2.5 3 Output Current, IOUT(A) 5 www.anpec.com.tw APW7303 Operating Waveforms Refer to the “Typical Application Circuit” The test conditions are VIN=12V, VOUT=3.3V, L1=10µH, C2=22µF, TA= 25oC unless otherwise specified. Power Off Power On R OUT =3.3Ω R OUT =3.3Ω VIN VIN 1 1 V OUT VOUT 2 2 I L1 IL 1 3 3 CH1: VIN, 5V/Div, DC CH2: VOUT , 2V/Div, DC CH3: IL1, 2A/Div, DC CH1: VIN, 5V/Div, DC CH2: VOUT , 2V/Div, DC CH3: IL1, 2A/Div, DC TIME: 5ms/Div Load Transient Response Load Transient Response IOUT =0.5A-3A -0.5 A, rise/fall time=10 µs I OUT =0A-3A- 0A, rise/fall time=10 µs VOUT V OUT 1 1 IOUT I OUT 2 2 CH1: VOUT , 200mV/Div, offset=3.3V CH2: IL1, 1A/Div, DC TIME: 50µs/Div CH1: VOUT , 200mV/Div, offset=3.3V CH2: IL1, 1A/Div, DC TIME: 50µs/Div Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 6 www.anpec.com.tw APW7303 Operating Waveforms Refer to the “Typical Application Circuit” The test conditions are VIN=12V, VOUT=3.3V, L1=10µH, C2=22µF, TA= 25oC unless otherwise specified. Short Circuit Over Current VOUT is shorted to GND by a short wire IOUT =0~7A VOUT VOUT 1 1 I L1 I L1 2 2 CH1: VOUT , 1V/Div, DC CH2: IL1, 2A/Div, DC TIME: 0.5s/Div CH1: VOUT , 1V/Div, DC CH2: IL1, 2A/Div, DC TIME: 50µs/Div Switching Waveform Switching Waveform IOUT =3A IOUT =0A VOUT VOUT 1 1 IL 1 IL 1 2 2 CH1: VOUT, 5V/Div, DC CH2: IL1, 2A/Div, DC TIME: 2µs/Div CH1: VOUT, 5V/Div, DC CH2: IL1, 0.5A/Div, DC TIME: 2µs/Div Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 7 www.anpec.com.tw APW7303 Operating Waveforms Refer to the “Typical Application Circuit” The test conditions are VIN=12V, VOUT=3.3V, L1=10µH, C2=22µF, TA= 25oC unless otherwise specified. Line Transient Response VIN =12 to 20 V, rise/fall time=10 µs, Line Transient Response VIN =12 to 20 V, rise/fall time=10 µs, IOUT =0 A V IN ROUT =8Ω V IN 1 1 VOUT VOUT 2 2 CH1: VIN, 5V/Div, DC CH2: VOUT , 100mV/Div, DC CH1: VIN, 5V/Div, DC CH2: VOUT , 100mV/Div, DC TIME: 50µs/Div TIME: 50µs/Div Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 8 www.anpec.com.tw APW7303 Pin Description PIN FUNCTION NO. NAME 1 BS High-Side Gate Drive Boost Input. BS supplies the voltage to drive the high-side N-channel MOSFET. At least 10nF capacitor should be connected from LX to BS to supply the high side switch. 2 VIN Power Input. VIN supplies the power (4.5V to 24V) to the control circuitry, gate drivers and step-down converter switches. Connecting a ceramic bypass capacitor and a suitably large capacitor between VIN and GND eliminates switching noise and voltage ripple on the input to the IC. 3 LX Power Switching Output. LX is the Drain of the N-Channel power MOSFET to supply power to the output LC filter. 4 GND 5 FB Output feedback Input. The APW7303 senses the feedback voltage via FB and regulates the voltage at 0.92V. Connecting FB with a resistor-divider from the converter’s output sets the output voltage from 0.92V to 20V. 6 COMP Output of the error amplifier. Connect a series RC network from COMP to GND to compensate the regulation control loop. In some cases, an additional capacitor from COMP to GND is required. 7 EN Enable Input. EN is a digital input that turns the regulator on or off. Pull up with 100kΩ resistor for automatic startup. 8 SS Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND to set the soft-start period. A 0.1µF capacitor sets the soft-start period to 15ms. To disable the soft-start feature, leave SS unconnected. 9 Ground. Connect the exposed pad on backside to Pin 4. Exposed Connect the exposed pad to the system ground plan with large copper area for dissipating heat into the Pad ambient air. Block Diagram VIN 2 Current Sense Amplifier LOC Over Temperature Protection Power-OnReset Current Limit 5V 1 BS POR 5V OTP 6µA Gate Driver Fault Logics SS 8 Inhibit Gate Control 3 LX 5V FB 5 Gm VREF Current Compartor Error Amplifier Gate Driver COMP 6 2.5V EN 7 UVLO Enable 1.5V Slope Compensation Internal Regulator Oscillator 340kHz/ 110kHz 5V VIN Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 9 4 GND LOC FB 0.6V Current Sense Amplifier www.anpec.com.tw APW7303 Typical Application Circuit VIN 4.5V~24V C1 10µF 2 1 VIN C3 10nF BS R4 100K 7 LX EN VOUT 3.3V/2A 3 L1 10µF C2 22µF APW7303 8 SS 6 C4 0.1µF 5 COMP FB R1 24K GND R3 6.8K 4 R2 9.1K C5 3.9nF Recommended Feedback Compensation Value Vin(V) VOUT(V) L1(µH) C2(µF) R1(KΩ) R2(KΩ) R3(KΩ) C5(nF) 24 5 10 22(Ceremic) 39 9.1 6.8 3.9 12 5 10 44 (Ceremic) 39 9.1 5 1.5 24 9.1 6.8 3.9 15 9.1 6.8 3.9 12 3.3 10 22 (Ceremic) 12 2.5 10 22 (Ceremic) Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 10 www.anpec.com.tw APW7303 Function Description Main Control Loop Enable / Shutdown The APW7303 is a constant frequency current mode switching regulator. During normal operation, the inter- Driving EN to ground places the APW7303 in shutdown. When in shutdown, the internal power MOSFET turns off, nal N-channel power MOSFET is turned on each cycle when the oscillator sets an internal RS latch and would all internal circuitry shuts down. Current-Limit Protection be turned off when an internal current comparator (ICMP) resets the latch. The peak inductor current at which ICMP The APW7303 monitors the output current, flowing through the N-Channel power MOSFET, and limits the resets the RS latch is controlled by the voltage on the COMP pin, which is the output of the error amplifier IC from damages during overload, short-circuit and overvoltage conditions. (EAMP). An external resistive divider connected between VOUT and ground allows the EAMP to receive an output Frequency Foldback feedback voltage VFB at FB pin. When the load current increases, it causes a slight decrease in VFB relative to The foldback frequency is controlled by the FB voltage. When the FB pin voltage is under 0.6V, the frequency of the 0.92V reference, which in turn causes the COMP voltage to increase until the average inductor current matches the oscillator will be reduced to 110kHz. This lower frequency allows the inductor current to safely discharge, the new load current. thereby preventing current runaway. The oscillator’s frequency will switch to its designed rate when the feedback VIN Power-On-Reset (POR) and EN Under-voltage Lockout voltage on FB rises above the rising frequency foldback threshold (0.6V, typical) again. The APW7303 keep monitoring the voltage on VIN pin to prevent wrong logic operations which may occur when Soft-Start VIN voltage is not high enough for the internal control The APW7303 provides the programmed soft-start func- circuitry to operate. The VIN POR has a rising threshold of 4.1V (typical) with 0.5V of hysteresis. tion to limit the inrush current. The soft-start time can be programmed by the external capacitor between SS and An external under-voltage lockout (UVLO) is sensed at the EN pin. The EN UVLO has a rising threshold of 2.5V GND. Typical charge current is 6µA, and the soft-start time is 15ms with 0.1µF capacitor. with 0.2V of hysteresis. The EN pin should be connected a resistor divider from VIN to EN. Boostrap Capacitor After the VIN and EN voltages exceed their respective voltage thresholds, the IC starts a start-up process and The APW7303 is a N-channel MOSFET step down then ramps up the output voltage to the setting of output voltage. converter. The MOSFET requires a gate voltage that is higher than input voltage, thus a boost capacitor should Over-Temperature Protection (OTP) be connected between LX and BS pins to drive the gate of the N-channel MOSFET. Typical boostrap capacitor value The over-temperature circuit limits the junction tempera- is from 10nF to 100nF. ture of the APW7303. When the junction temperature exceeds TJ = +160oC, a thermal sensor turns off the power MOSFET, allowing the devices to cool. The thermal sensor allows the converter to start a start-up process and regulate the output voltage again after the junction temperature cools by 50oC. The OTP is designed with a 50oC hysteresis to lower the average TJ during continuous thermal overload conditions, increasing lifetime of the lC. Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 11 www.anpec.com.tw APW7303 Application Information T=1/FOSC Setting Output Voltage The regulated output voltage is determined by: VOUT = 0.92 × (1 + R1 VLX DT I IOUT ) ⋅ ( V) R2 IL To prevent stray pickup, please locate resistors R1 and R2 close to APW7303. IOUT IQ1 I ICOUT Inductor Capacitor Selection Use small ceramic capacitors for high frequency VOUT decoupling and bulk capacitors to supply the surge current needed each time the N-channel power MOSFET VOUT (Q1) turns on. Place the small ceramic capacitors physically close to the VIN and between the VIN and GND. Figure 1. Converter Waveforms Output Capacitor Selection The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable An output capacitor is required to filter the output and supply the load transient current. The filtering requirements operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and are the function of the switching frequency and the ripple current (DI). The output ripple is the sum of the voltages, largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than having phase shift, across the ESR and the ideal output capacitor. The peak-to-peak voltage of the ESR is calcu- the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current (IRMS) ated as the following equations: of the bulk input capacitor is calculated as the following equation: D = V OUT V IN ........... (1) IRMS = IOUT D × (1 − D) ⋅ ( A ) ∆I = V OUT × (1 − D ) F OSC × L ........... (2) where D is the duty cycle of the power MOSFET. V ESR = ∆ I × ESR ........... (3) The peak- to-peak voltage of the ideal output capacitor is For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tanta- calculated as the following equations: lum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. ∆VCOUT = much smaller than the VESR and can be ignored. Therefore, the AC peak-to-peak output voltage(∆VOUT) is shown below: CIN Q1 IL LX Q2 IOUT ∆VOUT = ∆I × ESR ⋅ ( V ) VOUT L ICOUT ........... (4) For the applications using bulk capacitors, the ∆VCOUT is VIN VIN IQ1 ∆I 8 × FOSC × COUT ESR ........... (5) For the applications using bulk capacitors, the VESR is much smaller than the ∆V COUT and can be ignored. Therefore, the AC peak-to-peak output voltage(∆VOUT) is to COUT ∆VCOUT. Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 12 www.anpec.com.tw APW7303 Application Information(Cont.) Output Capacitor Selection (Cont.) VOUT ·(VIN - VOUT) ≤ 1.2 340000 ·L ·VIN The load transient requirements are the function of the slew rate (di/dt) and the magnitude of the transient load L≥ urrent. These requirements are generally met with a mix of capacitors and careful layout. High frequency ca- VOUT ·(VIN - VOUT) 408000 ·VIN (H) ........... (6) where VIN = VIN(MAX) pacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter ca- Table2 Inductor Selection Guide Vender pacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit Model Inductance DCR Current (µH) (mΩ) Rating(A) CYNTEC PCMB063T-100MS 10 62 4 Gausstek PL94P051M-15U 15 50 3 Gausstek PL94P051M-10U 10 38 3.8 board wiring that could cancel the usefulness of these low inductance components. An aluminum electrolytic capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Table1 Capacitor Selection Guide Capacitance Voltage Model TC Si2e Vender Rating(V) (µF) muRata GRM31CR61E106K 10 X5R 25 1206 muRata GRM31CR61C226K 22 X5R 16 1206 Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies permit the use of a smaller inductor for the same amount of inductor ripple current. However, this is at the expense of efficiency due to an increase in MOSFET gate charge losses. The equation (2) shows that the inductance value has a direct effect on ripple current. Accepting larger values of ripple current allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ∆I< 0.4 x IOUT(max). Please be noticed that the maximum ripple current occurs at the maximum input voltage. The minimum inductance of the inuctor is calculated by using the following equation: Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 13 www.anpec.com.tw APW7303 Package Information SOP-8P D SEE VIEW A h X 45o E THERMAL PAD E1 E2 D1 c A1 0.25 A2 A b e GAUGE PLANE SEATING PLANE θ L VIEW A S Y M B O L SOP-8P MILLIMETERS MIN. INCHES MAX. A MIN. MAX. 1.60 A1 0.00 0.063 0.15 0.000 0.006 0.049 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 0.138 D1 2.50 3.50 0.098 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 3.00 0.079 0.118 E2 2.00 e 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0o C 8oC 0 0oC 8o C Note : 1. Followed from JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 14 www.anpec.com.tw APW7303 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.40±0.20 5.20±0.20 2.10±0.20 SOP-8P 4.0±0.10 8.0±0.10 (mm) Devices Per Unit Package Type Unit Quantity SOP-8P Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 15 www.anpec.com.tw APW7303 Taping Direction Information SOP-8P USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 16 www.anpec.com.tw APW7303 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 17 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7303 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Nov., 2012 18 www.anpec.com.tw