Renesas M38505MAH-XXXSS 8-bit cisc single-chip microcomputer 740 family / 38000 sery Datasheet

REJ09B0080-0103Z
8
3850 Group (Spec. H)
User's Manual
RENESAS 8-BIT CISC SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
Before using this material, please visit our website to confirm that this is the most
current document available.
Rev. 1.03
Revision date: Sep. 18, 2003
www.renesas.com
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•
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programs, algorithms, or circuit application examples contained in these materials.
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3850 Group (Spec. H) User’s Manual
REVISION HISTORY
Rev.
Date
Description
Page
1.0 Aug. 30, 2001
–
Summary
First edition issued
1.1 Sep. 10, 2001 3-5
Limits and test conditions into Table 3.1.5 are partly added.
1.02 Aug. 29, 2003 1-6
1-7
1-7
1-37
1-38
2-103
2-104
2-105
2-106
Fig. 4 is partly revised.
Table 2 is partly added.
Note of Table 3 is added.
Fig. 42 is partly revised.
Fig. 43 is partly revised.
Clause name of “2.11 Flash memory mode” is revised.
Notes of Fig. 2.11.3 are partly revised.
Table 2.11.2 is partly revised.
Explanations of “[Beginning procedure]” of “2.11.6 CPU rewrite mode” are partly
added.
Explanations of this page are added.
Parameter of Table 3.1.4 is partly revised.
Fig. 3.2.16 is partly revised.
Fig. 3.2.20 is partly revised.
Fig. 3.2.24 is partly revised.
2-107
3-4
3-20
3-22
3-24
1.03 Sep. 18, 2003 1-51
Fig. 52 is partly revised.
(1/1)
Preface
This user’s manual describes Renesas’s CMOS 8-bit
microcomputers 3850 Group (Spec. H).
After reading this manual, the user should have a
through knowledge of the functions and features of
the 3850 Group (Spec. H), and should be able to
fully utilize the product. The manual starts with
specifications and ends with application examples.
For details of software, refer to the “740 Family
Software Manual”.
The user who is using the 3850 Group (standard)
needs to refer to not this manual but “3850/3851 Group
User’s Manual”.
BEFORE USING THIS MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development. Chapter 3 also includes necessary information for
systems development. You must refer to that chapter.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
● CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, such
as the electrical characteristics, the notes, and the list of registers.
✽For the mask ROM confirmation form, the ROM programming confirmation form, and the mark
specifications, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/en/
rom).
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bit attributes
Bits
(Note 1)
Contents immediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (CPUM) [Address : 3B16]
B
Name
0
Processor mode bits
1
Function
b1 b0
0 0 : Single-chip mode
01:
1 0 : Not available
11:
0 : 0 page
1 : 1 page
At reset
R W
0
0
0
2
Stack page selection bit
3
0
✕
4
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
0
✕
5
Fix this bit to “0.”
1
6
Main clock (XIN-XOUT) stop bit
7
Internal system clock selection bit
: Bit in which nothing is arranged
0 : Operating
1 : Stopped
0 : XIN-XOUT selected
1 : XCIN-XCOUT selected
✽
✽
: Bit that is not used for control of the corresponding function
Note 1:. Contents immediately after reset release
0....... “0” at reset release
1....... “1” at reset release
?....... Undefined at reset release
✽.......Contents determined by option at reset release
Note 2: Bit attributes......... The attributes of control register bits are classified into 3 bytes : read-only, writeonly and read and write. In the figure, these attributes are represented as follows :
R....... Read
...... Read enabled
✕.......Read disabled
W......Write
..... Write enabled
✕...... Write disabled
Table of contents
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES .................................................................................................................................... 1-2
APPLICATION ................................................................................................................................ 1-2
PIN CONFIGURATION .................................................................................................................. 1-2
FUNCTIONAL BLOCK .................................................................................................................. 1-3
PIN DESCRIPTION ........................................................................................................................ 1-4
PART NUMBERING ....................................................................................................................... 1-5
GROUP EXPANSION .................................................................................................................... 1-6
Memory Type ............................................................................................................................ 1-6
Memory Size ............................................................................................................................. 1-6
Packages ................................................................................................................................... 1-6
Notes on differences between 3850 group (standard) and 3850 group (spec. H) ......... 1-7
FUNCTIONAL DESCRIPTION ...................................................................................................... 1-8
Central Processing Unit (CPU) .............................................................................................. 1-8
Memory .................................................................................................................................... 1-12
I/O Ports .................................................................................................................................. 1-14
Interrupts ................................................................................................................................. 1-18
Timers ...................................................................................................................................... 1-21
Serial I/O ................................................................................................................................. 1-23
Pulse Width Modulation (PWM) ........................................................................................... 1-30
A-D Converter ......................................................................................................................... 1-32
Watchdog Timer ..................................................................................................................... 1-33
Reset Circuit ........................................................................................................................... 1-34
Clock Generating Circuit ....................................................................................................... 1-36
Flash Memory Version ........................................................................................................... 1-39
NOTES ON PROGRAMMING ..................................................................................................... 1-73
NOTES ON USAGE ..................................................................................................................... 1-73
DATA REQUIRED FOR MASK ORDERS ................................................................................ 1-74
DATA REQUIRED FOR ONE TIME PROM PROGRAMMING ORDERS ............................. 1-74
ROM PROGRAMMING METHOD .............................................................................................. 1-74
FUNCTIONAL DESCRIPTION SUPPLEMENT ......................................................................... 1-75
CHAPTER 2 APPLICATION
2.1 I/O port ..................................................................................................................................... 2-2
2.1.1 Memory map ................................................................................................................... 2-2
2.1.2 Relevant registers .......................................................................................................... 2-2
2.1.3 Terminate unused pins .................................................................................................. 2-3
2.1.4 Notes on I/O port ........................................................................................................... 2-4
2.1.5 Termination of unused pins .......................................................................................... 2-5
2.2 Interrupt ................................................................................................................................... 2-6
2.2.1 Memory map ................................................................................................................... 2-6
2.2.2 Relevant registers .......................................................................................................... 2-7
2.2.3 Interrupt source ............................................................................................................ 2-10
2.2.4 Interrupt operation ........................................................................................................ 2-11
2.2.5 Interrupt control ............................................................................................................ 2-14
2.2.6 INT interrupt .................................................................................................................. 2-17
2.2.7 Notes on interrupts ...................................................................................................... 2-18
3850 Group (Spec. H) User’s Manual
i
Table of contents
2.3 Timer ....................................................................................................................................... 2-20
2.3.1 Memory map ................................................................................................................. 2-20
2.3.2 Relevant registers ........................................................................................................ 2-20
2.3.3 Timer application examples ........................................................................................ 2-27
2.3.4 Notes on timer .............................................................................................................. 2-39
2.4 Serial I/O ................................................................................................................................ 2-40
2.4.1 Memory map ................................................................................................................. 2-40
2.4.2 Relevant registers ........................................................................................................ 2-41
2.4.3 Serial I/O connection examples ................................................................................. 2-48
2.4.4 Setting of serial I/O transfer data format ................................................................. 2-50
2.4.5 Serial I/O application examples ................................................................................. 2-51
2.4.6 Notes on serial I/O ...................................................................................................... 2-71
2.5 PWM ........................................................................................................................................ 2-74
2.5.1 Memory map ................................................................................................................. 2-74
2.5.2 Relevant registers ........................................................................................................ 2-74
2.5.3 PWM output circuit application example ................................................................... 2-76
2.5.4 Notes on PWM ............................................................................................................. 2-78
2.6 A-D converter ....................................................................................................................... 2-79
2.6.1 Memory map ................................................................................................................. 2-79
2.6.2 Relevant registers ........................................................................................................ 2-79
2.6.3 A-D converter application examples .......................................................................... 2-82
2.6.4 Notes on A-D converter .............................................................................................. 2-84
2.7 Watchdog timer .................................................................................................................... 2-85
2.7.1 Memory map ................................................................................................................. 2-85
2.7.2 Relevant registers ........................................................................................................ 2-85
2.7.3 Watchdog timer application examples ....................................................................... 2-87
2.7.4 Notes on watchdog timer ............................................................................................ 2-88
2.8 Reset ....................................................................................................................................... 2-89
2.8.1 Connection example of reset IC ................................................................................ 2-89
2.8.2 Notes on RESET pin ................................................................................................... 2-90
2.9 Clock generating circuit .................................................................................................... 2-91
2.9.1 Relevant registers ........................................................................................................ 2-91
2.9.2 Clock generating circuit application example ........................................................... 2-92
2.10 Standby function ............................................................................................................... 2-95
2.10.1 Relevant registers ...................................................................................................... 2-95
2.10.2 Stop mode ................................................................................................................... 2-96
2.10.3 Wait mode ................................................................................................................. 2-100
2.11 Flash memory mode ....................................................................................................... 2-103
2.11.1 Overview .................................................................................................................... 2-103
2.11.2 Memory map ............................................................................................................. 2-103
2.11.3 Relevant registers .................................................................................................... 2-104
2.11.4 Parallel I/O mode ..................................................................................................... 2-105
2.11.5 Standard serial I/O mode ........................................................................................ 2-105
2.11.6 CPU rewrite mode ................................................................................................... 2-106
2.11.7 Flash memory mode application examples .......................................................... 2-108
2.11.8 Notes on CPU rewrite mode .................................................................................. 2-113
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2
3.1.1 Absolute maximum ratings ............................................................................................ 3-2
3.1.2 Recommended operating conditions ............................................................................ 3-3
ii
3850 Group (Spec. H) User’s Manual
Table of contents
3.1.3 Electrical characteristics ................................................................................................ 3-4
3.1.4 A-D converter characteristics ....................................................................................... 3-6
3.1.5 Timing requirements and switching characteristics ................................................... 3-7
3.2 Standard characteristics .................................................................................................... 3-11
3.2.1 Flash memory version power source current standard characteristics ................ 3-11
3.2.2 Mask ROM version power source current standard characteristics ..................... 3-14
3.2.3 PROM version power source current standard characteristics .............................. 3-17
3.2.4 Flash memory version port standard characteristics .............................................. 3-20
3.2.5 Mask ROM version port standard characteristics .................................................... 3-22
3.2.6 PROM version port standard characteristics ............................................................ 3-24
3.2.7 A-D conversion standard characteristics ................................................................... 3-26
3.3 Notes on use ........................................................................................................................ 3-31
3.3.1 Notes on input and output ports ................................................................................ 3-31
3.3.2 Termination of unused pins ........................................................................................ 3-32
3.3.3 Notes on interrupts ...................................................................................................... 3-33
3.3.4 Notes on timer .............................................................................................................. 3-34
3.3.5 Notes on serial I/O ...................................................................................................... 3-34
3.3.6 Notes on PWM ............................................................................................................. 3-37
3.3.7 Notes on A-D converter .............................................................................................. 3-37
3.3.8 Notes on watchdog timer ............................................................................................ 3-37
3.3.9 Notes on RESET pin ................................................................................................... 3-38
3.3.10 Notes on using stop mode ....................................................................................... 3-38
3.3.11 Notes on wait mode .................................................................................................. 3-38
3.3.12 Notes on CPU rewrite mode of flash memory version ......................................... 3-39
3.3.13 Notes on restarting oscillation .................................................................................. 3-39
3.3.14 Notes on programming .............................................................................................. 3-40
3.3.15 EPROM Version/One Time PROM Version/Flash Memory Version .................... 3-42
3.3.16 Handling of Source Pins ........................................................................................... 3-42
3.3.17 Differences between 3850 group (standard) and 3850 group (spec. H) ........... 3-42
3.4 Countermeasures against noise ...................................................................................... 3-43
3.4.1 Shortest wiring length .................................................................................................. 3-43
3.4.2 Connection of bypass capacitor across V SS line and V CC line ............................... 3-45
3.4.3 Wiring to analog input pins ........................................................................................ 3-46
3.4.4 Oscillator concerns ....................................................................................................... 3-47
3.4.5 Setup for I/O ports ....................................................................................................... 3-48
3.4.6 Providing of watchdog timer function by software .................................................. 3-49
3.5 List of registers ................................................................................................................... 3-50
3.6 Package outline ................................................................................................................... 3-66
3.7 Machine instructions .......................................................................................................... 3-68
3.8 List of instruction code ..................................................................................................... 3-79
3.9 SFR memory map ................................................................................................................ 3-80
3.10 Pin configurations ............................................................................................................. 3-81
3850 Group (Spec. H) User’s Manual
iii
List of figures
List of figures
CHAPTER 1 HARDWARE
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1 M38503MXH-XXXFP/SP pin configuration ...................................................................... 1-2
2 Functional block diagram ................................................................................................... 1-3
3 Part numbering .................................................................................................................... 1-5
4 Memory expansion plan ..................................................................................................... 1-6
5 740 Family CPU register structure ................................................................................... 1-8
6 Register push and pop at interrupt generation and subroutine call ........................... 1-9
7 Structure of CPU mode register ..................................................................................... 1-11
8 Memory map diagram ...................................................................................................... 1-12
9 Memory map of special function register (SFR) .......................................................... 1-13
10 Port block diagram (1) ................................................................................................... 1-15
11 Port block diagram (2) ................................................................................................... 1-16
12 Port block diagram (3) ................................................................................................... 1-17
13 Interrupt control ............................................................................................................... 1-20
14 Structure of interrupt-related registers ......................................................................... 1-20
15 Structure of timer XY mode register ............................................................................ 1-21
16 Structure of timer count source selection register ..................................................... 1-21
17 Block diagram of timer X, timer Y, timer 1, and timer 2 ......................................... 1-22
18 Block diagram of clock synchronous serial I/O1 ........................................................ 1-23
19 Operation of clock synchronous serial I/O1 function ................................................ 1-23
20 Block diagram of UART serial I/O1 ............................................................................. 1-24
21 Operation of UART serial I/O1 function ...................................................................... 1-25
22 Structure of serial I/O1 control registers ..................................................................... 1-26
23 Structure of serial I/O2 control registers 1, 2 ............................................................ 1-27
24 Block diagram of serial I/O2 ......................................................................................... 1-28
25 Timing chart of serial I/O2 ............................................................................................ 1-28
26 S CMP2 output operation ................................................................................................... 1-29
27 Timing of PWM period ................................................................................................... 1-30
28 Block diagram of PWM function ................................................................................... 1-30
29 Structure of PWM control register ............................................................................... 1-31
30 PWM output timing when PWM register or PWM prescaler is changed ................ 1-31
31 Structure of AD control register ................................................................................... 1-32
32 Structure of A-D conversion registers ......................................................................... 1-32
33 Block diagram of A-D converter ................................................................................... 1-32
34 Block diagram of Watchdog timer ................................................................................ 1-33
35 Structure of Watchdog timer control register ............................................................. 1-33
36 Reset circuit example .................................................................................................... 1-34
37 Reset sequence .............................................................................................................. 1-34
38 Internal status at reset .................................................................................................. 1-35
39 Ceramic resonator circuit .............................................................................................. 1-36
40 External clock input circuit ............................................................................................ 1-36
41 Structure of MISRG ........................................................................................................ 1-37
42 System clock generating circuit block diagram (Single-chip mode) ........................ 1-37
43 State transitions of system clock ................................................................................. 1-38
44 Block diagram of flash memory version ...................................................................... 1-40
45 Flash memory control registers .................................................................................... 1-42
3850 Group (Spec. H) User’s Manual
List of figures
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62
63
64
65
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67
68
69
70
71
72
73
74
75
76
77
CPU rewrite mode set/reset flowchart ......................................................................... 1-42
Program flowchart ........................................................................................................... 1-44
Erase flowchart ............................................................................................................... 1-44
Full status check flowchart and remedial procedure for errors ............................... 1-46
ROM code protect control address .............................................................................. 1-47
ID code store addresses ............................................................................................... 1-48
Pin connection diagram in parallel I/O mode ............................................................. 1-51
Page program flowchart ................................................................................................. 1-53
Block erase flowchart ..................................................................................................... 1-53
Full status check flowchart and remedial procedure for errors ............................... 1-55
Connection for serial I/O mode .................................................................................... 1-58
Timing for page read ..................................................................................................... 1-60
Timing for reading the status register ......................................................................... 1-60
Timing for clearing the status register ........................................................................ 1-60
Timing for the page program ........................................................................................ 1-61
Timing for erasing all blocks ........................................................................................ 1-61
Timing for download ....................................................................................................... 1-62
Timing for version information output .......................................................................... 1-62
Timing for the ID check ................................................................................................. 1-63
ID code storage addresses ........................................................................................... 1-63
Full status check flowchart and remedial procedure for errors ............................... 1-65
Example circuit application for the standard serial I/O mode .................................. 1-65
Vcc power up/power down timing ................................................................................ 1-69
AC wave for read operation .......................................................................................... 1-70
AC electrical characteristics test condition for read operation ................................ 1-70
AC wave for program operation (WE control) ............................................................ 1-71
AC wave for program operation (CE control) ............................................................. 1-71
AC wave for erase operation (WE control) ................................................................ 1-72
AC wave for erase operation (CE control) ................................................................. 1-72
Programming and testing of One Time PROM version ............................................ 1-74
A-D conversion equivalent circuit ................................................................................. 1-76
A-D conversion timing chart .......................................................................................... 1-76
CHAPTER 2 APPLICATION
Fig. 2.1.1 Memory map of I/O port relevant registers .............................................................. 2-2
Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4) ...................................................................... 2-2
Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4) ....................................... 2-3
Fig. 2.2.1 Memory map of registers relevant to interrupt ........................................................ 2-6
Fig. 2.2.2 Structure of Interrupt edge selection register .......................................................... 2-7
Fig. 2.2.3 Structure of Interrupt request register 1 ................................................................... 2-8
Fig. 2.2.4 Structure of Interrupt request register 2 ................................................................... 2-8
Fig. 2.2.5 Structure of Interrupt control register 1 .................................................................... 2-9
Fig. 2.2.6 Structure of Interrupt control register 2 .................................................................... 2-9
Fig. 2.2.7 Interrupt operation diagram ....................................................................................... 2-11
Fig. 2.2.8 Changes of stack pointer and program counter upon acceptance of interrupt request
........................................................................................................................................................ 2-12
Fig. 2.2.9 Time up to execution of interrupt processing routine ........................................... 2-13
Fig. 2.2.10 Timing chart after acceptance of interrupt request ............................................. 2-13
Fig. 2.2.11 Interrupt control diagram ......................................................................................... 2-14
Fig. 2.2.12 Example of multiple interrupts ................................................................................ 2-16
Fig. 2.2.13 Sequence of changing relevant register ............................................................... 2-18
3850 Group (Spec. H) User’s Manual
v
List of figures
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2.2.14 Sequence of check of interrupt request bit .......................................................... 2-19
2.3.1 Memory map of registers relevant to timers .......................................................... 2-20
2.3.2 Structure of Prescaler 12, Prescaler X, Prescaler Y ............................................ 2-20
2.3.3 Structure of Timer 1 .................................................................................................. 2-21
2.3.4 Structure of Timer 2 .................................................................................................. 2-21
2.3.5 Structure of Timer X, Timer Y ................................................................................. 2-22
2.3.6 Structure of Timer XY mode register ...................................................................... 2-23
2.3.7 Structure of Timer count source selection register ............................................... 2-24
2.3.8 Structure of Interrupt request register 1 ................................................................. 2-25
2.3.9 Structure of Interrupt request register 2 ................................................................. 2-25
2.3.10 Structure of Interrupt control register 1 ................................................................ 2-26
2.3.11 Structure of Interrupt control register 2 ................................................................ 2-26
2.3.12 Timers connection and setting of division ratios ................................................. 2-28
2.3.13 Relevant registers setting ....................................................................................... 2-28
2.3.14 Control procedure ..................................................................................................... 2-29
2.3.15 Peripheral circuit example ....................................................................................... 2-30
2.3.16 Timers connection and setting of division ratios ................................................. 2-30
2.3.17 Relevant registers setting ....................................................................................... 2-31
2.3.18 Control procedure ..................................................................................................... 2-32
2.3.19 Judgment method of valid/invalid of input pulses ............................................... 2-33
2.3.20 Relevant registers setting ....................................................................................... 2-34
2.3.21 Control procedure ..................................................................................................... 2-35
2.3.22 Timers connection and setting of division ratios ................................................. 2-36
2.3.23 Relevant registers setting ....................................................................................... 2-37
2.3.24 Control procedure ..................................................................................................... 2-38
2.4.1 Memory map of registers relevant to Serial I/O .................................................... 2-40
2.4.2 Structure of Serial I/O2 control register 1 .............................................................. 2-41
2.4.3 Structure of Serial I/O2 control register 2 .............................................................. 2-41
2.4.4 Structure of Serial I/O2 register ............................................................................... 2-42
2.4.5 Structure of Transmit/Receive buffer register ........................................................ 2-42
2.4.6 Structure of Serial I/O1 status register ................................................................... 2-43
2.4.7 Structure of Serial I/O1 control register .................................................................. 2-44
2.4.8 Structure of UART control register .......................................................................... 2-44
2.4.9 Structure of Baud rate generator ............................................................................. 2-45
2.4.10 Structure of Interrupt edge selection register ...................................................... 2-45
2.4.11 Structure of Interrupt request register 1 ............................................................... 2-46
2.4.12 Structure of Interrupt request register 2 ............................................................... 2-46
2.4.13 Structure of Interrupt control register 1 ................................................................ 2-47
2.4.14 Structure of Interrupt control register 2 ................................................................ 2-47
2.4.15 Serial I/O connection examples (1) ....................................................................... 2-48
2.4.16 Serial I/O connection examples (2) ....................................................................... 2-49
2.4.17 Serial I/O transfer data format ............................................................................... 2-50
2.4.18 Connection diagram ................................................................................................. 2-51
2.4.19 Timing chart .............................................................................................................. 2-51
2.4.20 Registers setting relevant to transmitting side ..................................................... 2-52
2.4.21 Registers setting relevant to receiving side ......................................................... 2-53
2.4.22 Control procedure of transmitting side .................................................................. 2-54
2.4.23 Control procedure of receiving side ...................................................................... 2-55
2.4.24 Connection diagram ................................................................................................. 2-56
2.4.25 Timing chart (Serial I/O1) ....................................................................................... 2-56
2.4.26 Registers setting relevant to Serial I/O1 .............................................................. 2-57
2.4.27 Setting of serial I/O1 transmission data ............................................................... 2-57
3850 Group (Spec. H) User’s Manual
List of figures
Fig. 2.4.28 Control procedure of Serial I/O1 ............................................................................ 2-58
Fig. 2.4.29 Registers setting relevant to Serial I/O2 .............................................................. 2-59
Fig. 2.4.30 Setting of serial I/O2 transmission data ............................................................... 2-59
Fig. 2.4.31 Control procedure of Serial I/O2 ............................................................................ 2-60
Fig. 2.4.32 Connection diagram ................................................................................................. 2-61
Fig. 2.4.33 Timing chart .............................................................................................................. 2-62
Fig. 2.4.34 Relevant registers setting ....................................................................................... 2-62
Fig. 2.4.35 Control procedure of master unit ........................................................................... 2-63
Fig. 2.4.36 Control procedure of slave unit ............................................................................. 2-64
Fig. 2.4.37 Connection diagram ................................................................................................. 2-65
Fig. 2.4.38 Timing chart (using UART) ..................................................................................... 2-65
Fig. 2.4.39 Registers setting relevant to transmitting side ..................................................... 2-67
Fig. 2.4.40 Registers setting relevant to receiving side ......................................................... 2-68
Fig. 2.4.41 Control procedure of transmitting side .................................................................. 2-69
Fig. 2.4.42 Control procedure of receiving side ...................................................................... 2-70
Fig. 2.4.43 Sequence of setting serial I/O1 control register again ....................................... 2-72
Fig. 2.5.1 Memory map of registers relevant to PWM ........................................................... 2-74
Fig. 2.5.2 Structure of PWM control register ........................................................................... 2-74
Fig. 2.5.3 Structure of PWM prescaler ..................................................................................... 2-75
Fig. 2.5.4 Structure of PWM register ........................................................................................ 2-75
Fig. 2.5.5 Connection diagram ................................................................................................... 2-76
Fig. 2.5.6 PWM output timing ..................................................................................................... 2-76
Fig. 2.5.7 Setting of relevant registers ..................................................................................... 2-77
Fig. 2.5.8 PWM output ................................................................................................................ 2-77
Fig. 2.5.9 Control procedure ....................................................................................................... 2-78
Fig. 2.6.1 Memory map of registers relevant to A-D converter ............................................ 2-79
Fig. 2.6.2 Structure of A-D control register .............................................................................. 2-79
Fig. 2.6.3 Structure of A-D conversion register (high-order) ................................................. 2-80
Fig. 2.6.4 Structure of A-D conversion register (low-order) ................................................... 2-80
Fig. 2.6.5 Structure of Interrupt request register 2 ................................................................. 2-81
Fig. 2.6.6 Structure of Interrupt control register 2 .................................................................. 2-81
Fig. 2.6.7 Connection diagram ................................................................................................... 2-82
Fig. 2.6.8 Relevant registers setting ......................................................................................... 2-82
Fig. 2.6.9 Control procedure for 8-bit read .............................................................................. 2-83
Fig. 2.6.10 Control procedure for 10-bit read .......................................................................... 2-83
Fig. 2.7.1 Memory map of registers relevant to watchdog timer .......................................... 2-85
Fig. 2.7.2 Structure of Watchdog timer control register ......................................................... 2-85
Fig. 2.7.3 Structure of CPU mode register .............................................................................. 2-86
Fig. 2.7.4 Watchdog timer connection and division ratio setting .......................................... 2-87
Fig. 2.7.5 Relevant registers setting ......................................................................................... 2-88
Fig. 2.7.6 Control procedure ....................................................................................................... 2-88
Fig. 2.8.1 Example of poweron reset circuit ............................................................................ 2-89
Fig. 2.8.2 RAM backup system .................................................................................................. 2-89
Fig. 2.9.1 Structure of CPU mode register .............................................................................. 2-91
Fig. 2.9.2 Connection diagram ................................................................................................... 2-92
Fig. 2.9.3 Status transition diagram during power failure ...................................................... 2-92
Fig. 2.9.4 Setting of relevant registers ..................................................................................... 2-93
Fig. 2.9.5 Control procedure ....................................................................................................... 2-94
Fig. 2.10.1 Structure of MISRG ................................................................................................. 2-95
Fig. 2.10.2 Oscillation stabilizing time at restoration by reset input .................................... 2-97
Fig. 2.10.3 Execution sequence example at restoration by occurrence of INT0 interrupt request
........................................................................................................................................................ 2-99
3850 Group (Spec. H) User’s Manual
vii
List of figures
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
2.10.4
2.11.1
2.11.2
2.11.3
2.11.4
2.11.5
2.11.6
2.11.7
2.11.8
2.11.9
Reset input time ..................................................................................................... 2-101
Memory map of flash memory version for 3850 Group ................................... 2-103
Memory map of registers relevant to flash memory ......................................... 2-104
Structure of Flash memory control register ........................................................ 2-104
Rewrite example of built-in flash memory in serial I/O mode ......................... 2-108
Connection example in serial I/O mode (1) ....................................................... 2-109
Connection example in serial I/O mode (2) ....................................................... 2-109
Connection example in serial I/O mode (3) ....................................................... 2-110
Example of rewrite system for built-in flash memory in CPU rewrite mode . 2-111
CPU rewrite mode beginning/release flowchart ................................................. 2-112
CHAPTER 3 APPENDIX
Fig. 3.1.1 Circuit for measuring output switching characteristics ............................................ 3-9
Fig. 3.1.2 Timing diagram ........................................................................................................... 3-10
Fig. 3.2.1 Flash memory version power source current standard characteristics (in high-speed
mode, f(X IN) = 8 MHz) ............................................................................................... 3-11
Fig. 3.2.2 Flash memory version power source current standard characteristics (in high-speed
mode, f(X IN) = 4 MHz) ............................................................................................... 3-11
Fig. 3.2.3 Flash memory version power source current standard characteristics (in middlespeed mode, f(X IN) = 8 MHz) ................................................................................... 3-12
Fig. 3.2.4 Flash memory version power source current standard characteristics (in middlespeed mode, f(X IN) = 4 MHz) ................................................................................... 3-12
Fig. 3.2.5 Flash memory version power source current standard characteristics (in low-speed
mode) ........................................................................................................................... 3-13
Fig. 3.2.6 Mask ROM version power source current standard characteristics (in high-speed
mode, f(X IN) = 8 MHz) ............................................................................................... 3-14
Fig. 3.2.7 Mask ROM version power source current standard characteristics (in high-speed
mode, f(X IN) = 4 MHz) ............................................................................................... 3-14
Fig. 3.2.8 Mask ROM version power source current standard characteristics (in middle-speed
mode, f(X IN) = 8 MHz) ............................................................................................... 3-15
Fig. 3.2.9 Mask ROM version power source current standard characteristics (in middle-speed
mode, f(X IN) = 4 MHz) ............................................................................................... 3-15
Fig. 3.2.10 Mask ROM version power source current standard characteristics (in low-speed
mode) ......................................................................................................................... 3-16
Fig. 3.2.11 PROM version power source current standard characteristics (in high-speed mode,
f(X IN) = 8 MHz) ......................................................................................................... 3-17
Fig. 3.2.12 PROM version power source current standard characteristics (in high-speed mode,
f(X IN) = 4 MHz) ......................................................................................................... 3-17
Fig. 3.2.13 PROM version power source current standard characteristics (in middle-speed
mode, f(X IN) = 8 MHz) ............................................................................................. 3-18
Fig. 3.2.14 PROM version power source current standard characteristics (in middle-speed
mode, f(X IN) = 4 MHz) ............................................................................................. 3-18
Fig. 3.2.15 PROM version power source current standard characteristics (in low-speed mode)
........................................................................................................................................................ 3-19
Fig. 3.2.16 CMOS output port P-channel side characteristics (Ta = 25 °C) ....................... 3-20
Fig. 3.2.17 CMOS output port N-channel side characteristics (Ta = 25 °C) ...................... 3-20
Fig. 3.2.18 N-channel open-drain output port N-channel side characteristics (Ta = 25 °C) .. 3-21
Fig. 3.2.19 CMOS large current output port N-channel side characteristics (Ta = 25 °C) . 3-21
Fig. 3.2.20 CMOS output port P-channel side characteristics (Ta = 25 °C) ....................... 3-22
Fig. 3.2.21 CMOS output port N-channel side characteristics (Ta = 25 °C) ...................... 3-22
Fig. 3.2.22 N-channel open-drain output port N-channel side characteristics (Ta = 25 °C) .. 3-23
viii
3850 Group (Spec. H) User’s Manual
List of figures
Fig. 3.2.23 CMOS large current output port N-channel side characteristics (Ta = 25 °C) . 3-23
Fig. 3.2.24 CMOS output port P-channel side characteristics (Ta = 25 °C) ....................... 3-24
Fig. 3.2.25 CMOS output port N-channel side characteristics (Ta = 25 °C) ...................... 3-24
Fig. 3.2.26 N-channel open-drain output port N-channel side characteristics (Ta = 25 °C) .. 3-25
Fig. 3.2.27 CMOS large current output port N-channel side characteristics (Ta = 25 °C) . 3-25
Fig. 3.2.28 Definition of A-D conversion accuracy .................................................................. 3-26
Fig. 3.2.29 Flash memory version (M38507F8) A-D conversion standard characteristics .. 3-28
Fig. 3.2.30 Mask ROM version (M38503M2H, M38503M4H, M38504M6, M38507M8) A-D conversion
standard characteristics ............................................................................................. 3-29
Fig. 3.2.31 PROM version (M38504E6) A-D conversion standard characteristics ............. 3-30
Fig. 3.3.1 Sequence of changing relevant register ................................................................. 3-33
Fig. 3.3.2 Sequence of check of interrupt request bit ............................................................ 3-34
Fig. 3.3.3 Sequence of setting serial I/O1 control register again ......................................... 3-36
Fig. 3.3.4 Initialization of processor status register ................................................................ 3-40
Fig. 3.3.5 Sequence of PLP instruction execution .................................................................. 3-40
Fig. 3.3.6 Stack memory contents after PHP instruction execution ..................................... 3-40
Fig. 3.3.7 Status flag at decimal calculations .......................................................................... 3-41
Fig. 3.4.1 Selection of packages ............................................................................................... 3-43
Fig. 3.4.2 Wiring for the RESET pin ......................................................................................... 3-43
Fig. 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-44
Fig. 3.4.4 Wiring for CNV SS pin .................................................................................................. 3-44
Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM version, the EPROM version, and the flash
memory version ................................................................................................................... 3-45
Fig. 3.4.6 Bypass capacitor across the V SS line and the V CC line ........................................ 3-45
Fig. 3.4.7 Analog signal line and a resistor and a capacitor ................................................ 3-46
Fig. 3.4.8 Wiring for a large current signal line ...................................................................... 3-47
Fig. 3.4.9 Wiring of RESET pin ................................................................................................. 3-47
Fig. 3.4.10 V SS pattern on the underside of an oscillator ...................................................... 3-48
Fig. 3.4.11 Setup for I/O ports ................................................................................................... 3-48
Fig. 3.4.12 Watchdog timer by software ................................................................................... 3-49
Fig. 3.5.1 Structure of Port Pi .................................................................................................... 3-50
Fig. 3.5.2 Structure of Port Pi direction register ..................................................................... 3-50
Fig. 3.5.3 Structure of Serial I/O2 control register 1 .............................................................. 3-51
Fig. 3.5.4 Structure of Serial I/O2 control register 2 .............................................................. 3-51
Fig. 3.5.5 Structure of Serial I/O2 register ............................................................................... 3-52
Fig. 3.5.6 Structure of Transmit/Receive buffer register ........................................................ 3-52
Fig. 3.5.7 Structure of Seial I/O1 status register .................................................................... 3-53
Fig. 3.5.8 Structure of Seial I/O1 control register ................................................................... 3-54
Fig. 3.5.9 Structure of UART control register .......................................................................... 3-54
Fig. 3.5.10 Structure of Baud rate generator ........................................................................... 3-55
Fig. 3.5.11 Structure of PWM control register ......................................................................... 3-55
Fig. 3.5.12 Structure of PWM prescaler ................................................................................... 3-55
Fig. 3.5.13 Structure of PWM register ...................................................................................... 3-56
Fig. 3.5.14 Structure of Prescaler 12, Prescaler X, Prescaler Y .......................................... 3-56
Fig. 3.5.15 Structure of Timer 1 ................................................................................................ 3-57
Fig. 3.5.16 Structure of Timer 2 ................................................................................................ 3-57
Fig. 3.5.17 Structure of Timer XY mode register .................................................................... 3-58
Fig. 3.5.18 Structure of Timer X, Timer Y ............................................................................... 3-59
Fig. 3.5.19 Structure of Timer count source selection register ............................................. 3-59
Fig. 3.5.20 Structure of A-D control register ............................................................................ 3-60
Fig. 3.5.21 Structure of A-D conversion low-order register ................................................... 3-60
Fig. 3.5.22 Structure of A-D conversion high-order register .................................................. 3-61
3850 Group (Spec. H) User’s Manual
ix
List of figures
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
x
3.5.23
3.5.24
3.5.25
3.5.26
3.5.27
3.5.28
3.5.29
3.5.30
3.5.31
Structure
Structure
Structure
Structure
Structure
Structure
Structure
Structure
Structure
of
of
of
of
of
of
of
of
of
MISRG ................................................................................................. 3-61
Watchdog timer control register ....................................................... 3-62
Interrupt edge selection register ...................................................... 3-62
CPU mode register ............................................................................ 3-63
Interrupt request register 1 ............................................................... 3-63
Interrupt request register 2 ............................................................... 3-64
Interrupt control register 1 ................................................................ 3-64
Interrupt control register 2 ................................................................ 3-65
Flash memory control register .......................................................... 3-65
3850 Group (Spec. H) User’s Manual
List of tables
List of tables
CHAPTER 1 HARDWARE
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
1 Pin description ................................................................................................................. 1-4
2 Support products ............................................................................................................. 1-7
3 3850 group (standard) and 3850 group (spec. H) corresponding products ............ 1-7
4 Differences between 3850 group (standard) and 3850 group (spec. H) ................. 1-7
5 Push and pop instructions of accumulator or processor status register ................. 1-9
6 Set and clear instructions of each bit of processor status register ....................... 1-10
7 I/O port function ............................................................................................................. 1-14
8 Interrupt vector addresses and priority ...................................................................... 1-19
9 Summary of M38507F8 (flash memory version) ....................................................... 1-39
10 List of software commands (CPU rewrite mode) .................................................... 1-43
11 Definition of each bit in status register .................................................................... 1-45
12 Relationship between control signals and bus operation modes ......................... 1-49
13 Description of Pin Function (Flash Memory Parallel I/O Mode) ........................... 1-50
14 Software command list (parallel I/O mode) ............................................................. 1-52
15 Status register .............................................................................................................. 1-54
16 Pin functions (Flash memory standard serial I/O mode) ....................................... 1-57
17 Software commands (Standard serial I/O mode 1) ................................................ 1-59
18 Status register (SRD) .................................................................................................. 1-64
19 Status register 1 (SRD1) ............................................................................................ 1-64
20 Absolute maximum ratings ......................................................................................... 1-66
21 Flash memory mode Electrical characterstics ......................................................... 1-66
22 Read-only mode ........................................................................................................... 1-67
23 Read/Write mode (WE control) .................................................................................. 1-67
24 Read/Write mode (CE control) .................................................................................. 1-68
25 Erase and program operation .................................................................................... 1-68
26 Vcc power up/power down timing ............................................................................. 1-68
27 Programming adapter .................................................................................................. 1-74
28 Relative formula for a reference voltage V REF of A-D converter and V ref ..................... 1-75
29 Change of A-D conversion register during A-D conversion .................................. 1-75
CHAPTER 2 APPLICATION
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
2.1.1 Termination of unused pins ..................................................................................... 2-3
2.2.1 Interrupt sources, vector addresses and priority of 3850 group ...................... 2-10
2.2.2 List of interrupt bits according to interrupt source ............................................. 2-15
2.3.1 CNTR 0/CNTR 1 active edge switch bit function .................................................... 2-23
2.4.1 Setting examples of Baud rate generator values and transfer bit rate values (1) ... 2-66
2.4.2 Setting examples of Baud rate generator values and transfer bit rate values (2) ... 2-66
2.10.1 State in stop mode ............................................................................................... 2-96
2.10.2 State in wait mode .............................................................................................. 2-100
2.11.1 Setting of programmers when parallel programming ..................................... 2-105
2.11.2 Connection example to programmer when serial programming (4 wires) .. 2-105
3850 Group (Spec. H) User’s Manual
xi
List of tables
CHAPTER 3 APPENDIX
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
xii
3.1.1 Absolute maximum ratings ....................................................................................... 3-2
3.1.2 Recommended operating conditions (1) ................................................................ 3-3
3.1.3 Recommended operating conditions (2) ................................................................ 3-4
3.1.4 Electrical characteristics (1) ..................................................................................... 3-4
3.1.5 Electrical characteristics (2) ..................................................................................... 3-5
3.1.6 A-D converter characteristics .................................................................................. 3-6
3.1.7 Timing requirements (1) ........................................................................................... 3-7
3.1.8 Timing requirements (2) ........................................................................................... 3-7
3.1.9 Switching characteristics (1) .................................................................................... 3-8
3.1.10 Switching characteristics (2) .................................................................................. 3-8
3.5.1 CNTR 0/CNTR1 active edge switch bit function .................................................... 3-58
3850 Group (Spec. H) User’s Manual
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATION
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
NOTES ON USAGE
DATA REQUIRED FOR MASK ORDERS
DATA REQUIRED FOR One Time
PROM PROGRAMMING ORDERS
ROM PROGRAMMING METHOD
FUNCTIONAL DESCRIPTION
SUPPLEMENT
HARDWARE
DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION
DESCRIPTION
The 3850 group (spec. H) is the 8-bit microcomputer based on the
740 family core technology.
The 3850 group (spec. H) is designed for the household products
and office automation equipment and includes serial I/O functions,
8-bit timer, and A-D converter.
FEATURES
●Basic machine-language instructions ...................................... 71
●Minimum instruction execution time .................................. 0.5 µs
(at 8 MHz oscillation frequency)
●Memory size
ROM ................................................................... 8K to 32K bytes
RAM ................................................................. 512 to 1024 bytes
●Programmable input/output ports ............................................ 34
●Interrupts ................................................. 15 sources, 14 vectors
●Timers ............................................................................. 8-bit ✕ 4
●Serial I/O1 .................... 8-bit ✕ 1(UART or Clock-synchronized)
●Serial I/O2 ................................... 8-bit ✕ 1(Clock-synchronized)
●PWM ............................................................................... 8-bit ✕ 1
●A-D converter ............................................... 10-bit ✕ 5 channels
●Watchdog timer ............................................................ 16-bit ✕ 1
●Clock generating circuit ..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
In high-speed mode .................................................. 4.0 to 5.5 V
(at 8 MHz oscillation frequency)
In middle-speed mode ............................................... 2.7 to 5.5 V
(at 8 MHz oscillation frequency)
In low-speed mode .................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency)
●Power dissipation
In high-speed mode .......................................................... 34 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode
Except M38507F8FP/SP ................................................... 60 µW
M38507F8FP/SP ............................................................. 450 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
●Operating temperature range .................................... –20 to 85°C
APPLICATION
Office automation equipment, FA equipment, Household products,
Consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
M38503MXH-XXXFP/SP
VCC
VREF
AVSS
P44/INT3/PWM
P43/INT2/SCMP2
P42/INT1
P41/INT0
P40/CNTR1
P27/CNTR0/SRDY1
P26/SCLK1
P25/TxD
P24/RxD
P23
P22
CNVSS
VPP
P21/XCIN
P20/XCOUT
RESET
XIN
XOUT
VSS
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P30/AN0
P31/AN1
P32/AN2
P33/AN3
P34/AN4
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04
P05
P06
P07
P10/(LED0)
P11/(LED1)
P12/(LED2)
P13/(LED3)
P14/(LED4)
P15/(LED5)
P16/(LED6)
P17/(LED7)
: Flash memory version
Package type : FP ........................... 42P2R-A/E (42-pin plastic-molded SSOP)
Package type : SP ........................... 42P4B (42-pin plastic-molded SDIP)
Fig. 1 M38503MXH-XXXFP/SP pin configuration
1-2
3850 Group (Spec. H) User’s Manual
20
3850 Group (Spec. H) User’s Manual
AVSS
VREF
2 3
A-D
converter
(10)
Watchdog
timer
P WM
(8)
Reset
Sub-clock Sub-clock
input
output
XCIN XCOUT
Main-clock
output
XOUT
Clock generating circuit
19
Main-clock
input
XIN
I/O port P4
4 5 6 7 8
P4(5)
RAM
ROM
INT0–
INT3
FUNCTIONAL BLOCK DIAGRAM
I/O port P3
38 39 40 41 42
P3(5)
21
VS S
PC H
SI/O1(8)
C P U
1
VC C
PS
PC L
S
Y
X
A
18
RESET
Reset input
P2(8)
CNTR0
I/O port P2
9 10 11 12 13 1416 17
15
CNVSS
XCIN
XCOUT
P1(8)
I/O port P1
22 23 24 25 26 27 28 29
CNTR1
Prescaler Y(8)
Prescaler X(8)
Prescaler 12(8)
I/O port P0
30 31 32 33 34 35 36 37
P0(8)
Timer Y( 8 )
Timer X( 8 )
Timer 2( 8 )
Timer 1( 8 )
SI/O2(8)
HARDWARE
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK
Fig. 2 Functional block diagram
1-3
HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Table 1 Pin description
Pin
VCC, VSS
Power source
CNVSS
CNVSS input
RESET
Reset input
XIN
Clock input
XOUT
Clock output
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04–P07
I/O port P0
P10–P17
I/O port P1
Function except a port function
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
•Reset input pin for active “L”.
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
•8-bit CMOS I/O port.
• Serial I/O2 function pin
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure.
P20/XCOUT
P21/XCIN
P22
P23
Functions
Name
•P10 to P17 (8 bits) are enabled to output large current for LED drive.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
I/O port P2
•CMOS compatible input level.
•P20, P21, P24 to P27: CMOS3-state output structure.
P24/RxD
P25/TxD
• Sub-clock generating circuit I/O
pins (connect a resonator)
• Serial I/O1 function pin
•P22, P23: N-channel open-drain structure.
P26/SCLK1
• Serial I/O1 function pin/
Timer X function pin
P27/CNTR0/
SRDY1
P30/AN0–
P34/AN4
•8-bit CMOS I/O port with the same function as port P0.
I/O port P3
•CMOS 3-state output structure.
P40/CNTR1
P41/INT0
P42/INT1
•8-bit CMOS I/O port with the same function as port P0.
I/O port P4
•CMOS compatible input level.
• Timer Y function pin
• Interrupt input pins
•CMOS 3-state output structure.
• Interrupt input pin
• SCMP2 output pin
• Interrupt input pin
• PWM output pin
P43/INT2/SCMP2
P44/INT3/PWM
1-4
• A-D converter input pin
•CMOS compatible input level.
3850 Group (Spec. H) User’s Manual
HARDWARE
PART NUMBERING
PART NUMBERING
Product name
M3850 3
M
4
H– XXX
SP
Package type
SP : 42P4B
FP : 42P2R-A/E
SS : 42S1B-A
ROM number
Omitted in One Time PROM version shipped in blank,
EPROM version, and flash memory version.
– : standard
Omitted in One Time PROM version shipped in blank, EPROM
version, and flash memory version.
H–: Partial specification changed version
ROM/PROM/Flash memory size
9 : 36864 bytes
1 : 4096 bytes
A : 40960 bytes
2 : 8192 bytes
3 : 12288 bytes B : 45056 bytes
4 : 16384 bytes C : 49152 bytes
5 : 20480 bytes D : 53248 bytes
6 : 24576 bytes E : 57344 bytes
7 : 28672 bytes F : 61440 bytes
8 : 32768 bytes
The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they
cannot be used as a user’s ROM area.
However, they can be programmed or erased in the flash memory version,
so that the users can use them.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
F : Flash memory version
RAM size
0 : 192 bytes
5 : 768 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
4 : 640 bytes
9 : 2048 bytes
Fig. 3 Part numbering
3850 Group (Spec. H) User’s Manual
1-5
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
RAM size ............................................................... 512 to 1 K bytes
Renesas Technology plans to expand the 3850 group (spec. H) as
follows.
Packages
Memory Type
42P4B ......................................... 42-pin shrink plastic-molded DIP
42P2R-A/E ......................................... 42-pin plastic-molded SSOP
42S1B-A .................. 42-pin shrink ceramic DIP (EPROM version)
Support for mask ROM, One Time PROM, and flash memory versions.
Memory Size
Flash memory size ......................................................... 32 K bytes
One Time PROM size ..................................................... 24 K bytes
Mask ROM size ................................................... 8 K to 32 K bytes
Memory Expansion Plan
ROM size (bytes)
As of Aug. 2003
ROM
exteranal
AAAAAAAA
AAAAAAAA
M38507M8/F8
AAAAAAAA
Mass production
32K
28K
AAAAAAAA
AAAAAAAA
M38504M6/E6
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
M38503M4H
AAAAAAAA
AAAAAAA
AAAAAAAA
AAAAAAAA
M38503M2H
AAAAAAAA
AAAAAAAA
Mass production
24K
20K
Mass production
16K
12K
Mass production
8K
384
512
640
768
1152
896
1024
RAM size (bytes)
Fig. 4 Memory expansion plan
1-6
3850 Group (Spec. H) User’s Manual
1280
1408
1536
2048
HARDWARE
GROUP EXPANSION
Currently support products are listed below.
As of Aug. 2003
Table 2 Support products
Product name
M38503M2H-XXXSP
M38503M2H-XXXFP
M38503M4H-XXXSP
M38503M4H-XXXFP
M38504M6-XXXSP
M38504E6-XXXSP
M38504E6SP
M38504E6SS
M38504M6-XXXFP
M38504E6-XXXFP
M38504E6FP
M38507M8-XXXSP
M38507M8-XXXFP
M38507F8SP
M38507F8FP
ROM size (bytes)
ROM size for User in ( )
RAM size (bytes)
8192
(8062)
512
16384
(16254)
512
Package
42P4B
42P2R-A/E
424P4B
42P2R-A/E
424P4B
24576
(24446)
640
42S1B-A
42P2R-A/E
32768
(32638)
1024
Table 3 3850 group (standard) and 3850 group (spec. H)
corresponding products
3850 group (standard) (Note)
3850 group (spec. H)
M38503M2-XXXFP/SP
M38503M2H-XXXFP/SP
M38503M4-XXXFP/SP
M38503M4H-XXXFP/SP
M38503E4-XXXFP/SP
M38504M6-XXXFP/SP
M38503E4FP/SP
M38504E6-XXXFP/SP
M38503E4SS
M38504E6FP/SP
42P4B
42P2R-A/E
424P4B
42P2R-A/E
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
Mask ROM version
Flash memory version
Note: The user who is using the 3850 Group (standard) needs to
refer to not this manual but “3850/3851 Group User’s
Manual”.
M38504E6SS
M38507M8-XXXFP/SP
M38507F8FP/SP
Table 4 Differences between 3850 group (standard) and 3850 group (spec. H)
3850 group (standard)
Serial I/O
1: Serial I/O (UART or Clock-synchronized)
A-D converter
Large current port
Unserviceable in low-speed mode
5: P13–P17
3850 group (spec. H)
2: Serial I/O1 (UART or Clock-synchronized)
Serial I/O2 (Clock-synchronized)
Serviceable in low-speed mode
8: P10–P17
Notes on differences between 3850 group (standard) and 3850 group (spec. H)
(1) The absolute maximum ratings of 3850 group (spec. H) is smaller than that of 3850 group (standard).
•Power source voltage Vcc = –0.3 to 6.5 V
•CNVss input voltage VI = –0.3 to Vcc +0.3 V
(2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may be some differences between 3850 group (standard) and 3850 group
(spec. H).
(3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after reset.)
(4) Fix bit 3 of the CPU mode register to “1”.
(5) Be sure to perform the termination of unused pins.
3850 Group (Spec. H) User’s Manual
1-7
HARDWARE
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 3850 group (spec. H) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and
machine instructions or the 740 Family Software Manual for details on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine
calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b0
b7
Y
b7
Index register Y
b0
S
b15
b7
PCH
Stack pointer
b0
Program counter
PCL
b7
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
1-8
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt request
(Note)
M (S)
Execute JSR
Push return address
on stack
M (S)
(PCH)
(S)
(S) – 1
M (S)
(PCL)
(S)
(S)– 1
(S)
M (S)
(S)
M (S)
(S)
Subroutine
(S) – 1
(PCL)
Push return address
on stack
(S) – 1
(PS)
Push contents of processor
status register on stack
(S) – 1
Interrupt
Service Routine
Execute RTS
POP return
address from stack
(PCH)
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTI
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
Note: Condition for acceptance of an interrupt
(S)
(S) + 1
(PS)
M (S)
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
POP contents of
processor status
register from stack
POP return
address
from stack
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 5 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PLA
Processor status register
PHP
PLP
3850 Group (Spec. H) User’s Manual
1-9
HARDWARE
FUNCTIONAL DESCRIPTION
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 6 Set and clear instructions of each bit of processor status register
C flag
Set instruction
Clear instruction
1-10
SEC
CLC
Z flag
_
_
I flag
D flag
SEI
CLI
SED
CLD
3850 Group (Spec. H) User’s Manual
B flag
_
_
T flag
V flag
SET
CLT
_
N flag
_
CLV
_
HARDWARE
FUNCTIONAL DESCRIPTION
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.
b7
b0
1
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 : Not available
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Fix this bit to “1”.
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0 0 : φ = f(XIN)/2 (high-speed mode)
0 1 : φ = f(XIN)/8 (middle-speed mode)
1 0 : φ = f(XCIN)/2 (low-speed mode)
1 1 : Not available
Fig. 7 Structure of CPU mode register
3850 Group (Spec. H) User’s Manual
1-11
HARDWARE
FUNCTIONAL DESCRIPTION
MEMORY
Special Function Register (SFR) Area
Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
The Special Function Register area in the zero page contains
control registers such as I/O ports and timers.
Special Page
RAM
Access to this area with only 2 bytes is possible in the special
page addressing mode.
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size
(bytes)
Address
XXXX16
192
256
384
512
640
768
896
1024
1536
2048
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
000016
SFR area
Zero page
004016
RAM
010016
XXXX16
Not used
0FF016
SFR area (Note)
0FFF16
Not used
YYYY16
ROM area
Reserved ROM area
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
(128 bytes)
ZZZZ16
ROM
FF0016
FFDC16
Interrupt vector area
FFFE16
FFFF16
Reserved ROM area
Note: Flash memory version only
Fig. 8 Memory map diagram
1-12
3850 Group (Spec. H) User’s Manual
Special page
HARDWARE
FUNCTIONAL DESCRIPTION
000016
Port P0 (P0)
002016
Prescaler 12 (PRE12)
000116
Port P0 direction register (P0D)
002116
Timer 1 (T1)
000216
Port P1 (P1)
002216
Timer 2 (T2)
000316
Port P1 direction register (P1D)
002316
Timer XY mode register (TM)
000416
Port P2 (P2)
002416
Prescaler X (PREX)
000516
Port P2 direction register (P2D)
002516
Timer X (TX)
000616
Port P3 (P3)
002616
Prescaler Y (PREY)
000716
Port P3 direction register (P3D)
002716
Timer Y (TY)
000816
Port P4 (P4)
002816
Timer count source selection register (TCSS)
000916
Port P4 direction register (P4D)
002916
000A16
002A16
000B16
002B16
Reserved ✽
000C16
002C16
Reserved ✽
000D16
002D16
Reserved ✽
000E16
002E16
Reserved ✽
000F16
002F16
Reserved ✽
001016
003016
Reserved ✽
001116
003116
Reserved ✽
001216
Reserved ✽
003216
001316
Reserved ✽
003316
001416
Reserved ✽
003416
A-D control register (ADCON)
001516
Serial I/O2 control register 1 (SIO2CON1)
003516
A-D conversion low-order register (ADL)
001616
Serial I/O2 control register 2 (SIO2CON2)
003616
A-D conversion high-order register (ADH)
001716
Serial I/O2 register (SIO2)
003716
Reserved ✽
001816
Transmit/Receive buffer register (TB/RB)
003816
MISRG
001916
Serial I/O1 status register (SIOSTS)
003916
Watchdog timer control register (WDTCON)
001A16
Serial I/O1 control register (SIOCON)
003A16
Interrupt edge selection register (INTEDGE)
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1 (IREQ1)
001D16
PWM control register (PWMCON)
003D16
Interrupt request register 2 (IREQ2)
001E16
PWM prescaler (PREPWM)
003E16
Interrupt control register 1 (ICON1)
001F16
PWM register (PWM)
003F16
Interrupt control register 2 (ICON2)
0FFE16
Flash memory control register (FMCR)
✽ Reserved : Do not write any data to this addresses, because these areas are reserved.
Fig. 9 Memory map of special function register (SFR)
3850 Group (Spec. H) User’s Manual
1-13
HARDWARE
FUNCTIONAL DESCRIPTION
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be
input port or output port.
When “0” is written to the bit corresponding to a pin, that pin
becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Table 7 I/O port function
Pin
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04–P07
P10–P17
P20/XCOUT
P21/XCIN
P22
P23
P24/RxD
P25/TxD
P26/SCLK1
P27/CNTR0/SRDY1
P30/AN0–
P34/AN4
P40/CNTR1
P41/INT0
P42/INT1
P43/INT2/SCMP2
Name
I/O Structure
Non-Port Function
Serial I/O2 function I/O
Port P0
Related SFRs
Serial I/O2 control register
CMOS compatible
input level
CMOS 3-state output
Sub-clock generating
circuit
CPU mode register
CMOS compatible
input level
N-channel open-drain
output
Port P2
Input/output,
individual
bits
Port P3
CMOS compatible
input level
CMOS 3-state output
(6)
(7)
(8)
Serial I/O1 function I/O
Serial I/O1 control register
(9)
(10)
(11)
Serial I/O1 function I/O
Serial I/O1 control register
Timer XY mode register
(12)
Timer X function I/O
A-D conversion input
A-D control register
(13)
Timer Y function I/O
Timer XY mode register
(14)
External interrupt input
Interrupt edge selection
register
(15)
External interrupt input
Interrupt edge selection
register
Serial I/O2 control register
(16)
Interrupt edge selection
register
PWM control register
(17)
SCMP2 output
External interrupt input
PWM output
Note: When bits 5 to 7 of Ports P3 and P4 are read out, the contents are undefined.
1-14
Ref.No.
(1)
(2)
(3)
(4)
(5)
Port P1
Port P4
P44/INT3/PWM
Input/Output
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
(2) Port P01
(1) Port P00
P01/SOUT2 P-channel output disable bit
Direction
register
Data bus
Serial I/O2 Transmit completion signal
Serial I/O2 port selection bit
Direction
register
Port latch
Data bus
Port latch
Serial I/O2 input
Serial I/O2 output
(3) Port P02
(4) Port P03
P02/SCLK2 P-channel output disable bit
SRDY2 output enable bit
Serial I/O2 synchronous
clock selection bit
Serial I/O2 port selection bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
Serial I/O2 ready output
Serial I/O2 clock output
Serial I/O2 external clock input
(6) Port P20
(5) Ports P04-P07,P1
Port XC switch bit
Direction
register
Data bus
Direction
register
Data bus
Port latch
Port latch
Oscillator
Port P21
(7) Port P21
Port XC switch bit
Port XC switch bit
(8) Ports P22,P23
Direction
register
Data bus
Direction
register
Port latch
Data bus
Port latch
Sub-clock generating circuit input
Fig. 10 Port block diagram (1)
3850 Group (Spec. H) User’s Manual
1-15
HARDWARE
FUNCTIONAL DESCRIPTION
(10) Port P25
(9) Port P24
Serial I/O1 enable bit
Receive enable bit
P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Direction
register
Direction
register
Port latch
Data bus
Port latch
Data bus
Serial I/O1 input
Serial I/O1 output
(11) Port P26
(12) Port P27
Pulse output mode
Serial I/O1 mode selection bit
Serial I/O1 enable bit
SRDY1 output enable bit
Direction
register
Serial I/O1 synchronous
clock selection bit
Serial I/O1 enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Direction
register
Data bus
Port latch
Port latch
Data bus
Pulse output mode
Serial ready output
Serial I/O1 clock output
Timer output
External clock input
(13) Ports P30-P34
CNTR0 interrupt
input
(14) Port P40
Direction
register
Direction
register
Port latch
Data bus
Port latch
Data bus
Pulse output mode
Timer output
A-D converter input
Analog input pin selection bit
CNTR1 interrupt
input
(16) Port P43
Serial I/O2 I/O
comparison signal control bit
(15) Ports P41,P42
Direction
register
Data bus
Port latch
Interrupt input
Direction
register
Data bus
Port latch
Serial I/O2 I/O
comparison signal output
Interrupt input
Fig. 11 Port block diagram (2)
1-16
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
(17) Port P44
PWM output enable bit
Direction
register
Data bus
Port latch
PWM output
Interrupt input
Fig. 12 Port block diagram (3)
3850 Group (Spec. H) User’s Manual
1-17
HARDWARE
FUNCTIONAL DESCRIPTION
INTERRUPTS
■Notes
Interrupts occur by 15 sources among 15 sources: six external,
eight internal, and one software.
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer XY mode register (address 2316)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt edge selection register (address 3A16)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
➀Set the corresponding interrupt enable bit to “0” (disabled).
➁Set the interrupt edge select bit or the interrupt source select bit
to “1”.
➂Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃Set the corresponding interrupt enable bit to “1” (enabled).
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
1-18
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Table 8 Interrupt vector addresses and priority
Vector Addresses (Note 1)
Priority
Interrupt Source
Low
High
1
FFFC16
FFFD16
Reset (Note 2)
Interrupt Request
Generating Conditions
Remarks
At reset
Non-maskable
External interrupt
(active edge selectable)
INT0
2
FFFB16
FFFA16
At detection of either rising or
falling edge of INT0 input
Reserved
3
FFF916
FFF816
Reserved
INT1
4
FFF716
FFF616
At detection of either rising or
falling edge of INT1 input
External interrupt
(active edge selectable)
INT2
5
FFF516
FFF416
At detection of either rising or
falling edge of INT2 input
External interrupt
(active edge selectable)
INT3/ Serial I/O2
6
FFF316
FFF216
At detection of either rising or
falling edge of INT 3 input/ At
completion of serial I/O2 data
reception/transmission
External interrupt
(active edge selectable)
Switch by Serial I/O2/INT3
interrupt source bit
Reserved
Timer X
Timer Y
Timer 1
Timer 2
7
8
9
FFF116
FFF016
Reserved
FFEF16
FFED16
10
11
FFEB16
FFE916
FFEE16
FFEC16
FFEA16
FFE816
At timer X underflow
At timer Y underflow
At timer 1 underflow
Serial I/O1
reception
12
FFE716
FFE616
At completion of serial I/O1 data
reception
Valid when serial I/O1 is selected
Serial I/O1
transmission
13
FFE516
FFE416
At completion of serial I/O1
transfer shift or when transmission buffer is empty
Valid when serial I/O1 is selected
CNTR0
14
FFE316
FFE216
At detection of either rising or
falling edge of CNTR0 input
External interrupt
(active edge selectable)
CNTR1
15
FFE116
FFE016
At detection of either rising or
falling edge of CNTR1 input
External interrupt
(active edge selectable)
A-D converter
BRK instruction
16
FFDF16
FFDE16
At completion of A-D conversion
17
FFDD16
FFDC16
At BRK instruction execution
STP release timer underflow
At timer 2 underflow
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3850 Group (Spec. H) User’s Manual
1-19
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 13 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 active edge selection bit
INT1 active edge selection bit
0 : Falling edge active
1 : Rising edge active
INT2 active edge selection bit
INT3 active edge selection bit
Serial I/O2 / INT3 interrupt source bit
0 : INT3 interrupt selected
1 : Serial I/O2 interrupt selected
Not used (returns “0” when read)
b7
b0 Interrupt request register 1
(IREQ1 : address 003C16)
b7
b0 Interrupt request register 2
(IREQ2 : address 003D16)
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Serial I/O1 reception interrupt request bit
Serial I/O1 transmit interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
AD converter interrupt request bit
Not used (returns “0” when read)
INT0 interrupt request bit
Reserved
INT1 interrupt request bit
INT2 interrupt request bit
INT3 / Serial I/O2 interrupt request bit
Reserved
Timer X interrupt request bit
Timer Y interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 1
(ICON1 : address 003E16)
INT0 interrupt enable bit
Reserved(Do not write “1” to this bit.)
INT1 interrupt enable bit
INT2 interrupt enable bit
INT3 / Serial I/O2 interrupt enable bit
Reserved(Do not write “1” to this bit.)
Timer X interrupt enable bit
Timer Y interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 14 Structure of interrupt-related registers
1-20
3850 Group (Spec. H) User’s Manual
Interrupt control register 2
(ICON2 : address 003F16)
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Serial I/O1 reception interrupt enable bit
Serial I/O1 transmit interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupts disabled
1 : Interrupts enabled
HARDWARE
FUNCTIONAL DESCRIPTION
TIMERS
Timer 1 and Timer 2
The 3850 group (spec. H) has four timers: timer X, timer Y, timer
1, and timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “0016”, an underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
The count source of prescaler 12 is the oscillation frequency
which is selected by timer 12 count source selection bit. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer
underflow sets the interrupt request bit.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts the count source selected by Timer count source
selection bit.
b0
b7
Timer XY mode register
(TM : address 002316)
Timer X operating mode bit
b1b0
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR0 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer X count stop bit
0: Count start
1: Count stop
Timer Y operating mode bits
b5b4
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR1 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer Y count stop bit
0: Count start
1: Count stop
Fig. 15 Structure of timer XY mode register
b7
b0
Timer count source selection register
(TCSS : address 002816)
Timer X count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Timer Y count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Timer 12 count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XCIN)
Not used (returns “0” when read)
Fig. 16 Structure of timer count source selection register
(2) Pulse Output Mode
The timer counts the count source selected by Timer count source
selection bit. Whenever the contents of the timer reach “0016”, the
signal output from the CNTR0 (or CNTR1) pin is inverted. If the
CNTR0 (or CNTR1) active edge selection bit is “0”, output begins
at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P27 ( or port P40) direction register to output mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 or
CNTR1 pin.
When the CNTR0 (or CNTR1) active edge selection bit is “0”, the
rising edge of the CNTR0 (or CNTR1) pin is counted.
When the CNTR0 (or CNTR1) active edge selection bit is “1”, the
falling edge of the CNTR0 (or CNTR1) pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer
counts the selected signals by the count source selection bit while
the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) active edge selection bit is “1”, the timer counts it while the CNTR0
(or CNTR1) pin is at “L”.
The count can be stopped by setting “1” to the timer X (or timer Y)
count stop bit in any mode. The corresponding interrupt request
bit is set each time a timer underflows.
■Note
When switching the count source by the timer 12, X and Y count
source bit, the value of timer count is altered in unconsiderable
amount owing to generating of a thin pulses in the count input
signals.
Therefore, select the timer count source before set the value to
the prescaler and the timer.
3850 Group (Spec. H) User’s Manual
1-21
HARDWARE
FUNCTIONAL DESCRIPTION
Data bus
f(XIN)/16
(f(XCIN)/16 at low-speed mode)
Prescaler X latch (8)
f(XIN)/2
Pulse width
(f(XCIN)/2 at low-speed mode)
Timer X count source selection bit measurement
mode
Timer mode
Pulse output mode
Prescaler X (8)
CNTR0 active edge
selection bit
“0 ”
P27/CNTR0
Event
counter
mode
“1 ”
Timer X (8)
To timer X interrupt
request bit
Timer X count stop bit
To CNTR0 interrupt
request bit
CNTR0 active
edge selection “1”
bit
“0”
Q
Toggle flip-flop T
Q
R
Timer X latch write pulse
Pulse output mode
Port P27
latch
Port P27
direction register
Timer X latch (8)
Pulse output mode
Data bus
f(XIN)/16
(f(XCIN)/16 at low-speed mode)
Prescaler Y latch (8)
f(XIN)/2
(f(XCIN)/2 at low-speed mode)
Timer Y count source selection bit
Pulse width
measurement mode
Timer mode
Pulse output mode
Prescaler Y (8)
CNTR1 active edge
selection bit
“0”
P40/CNTR1
Event
counter
mode
“1”
Port P40
direction register
Timer Y (8)
To timer Y interrupt
request bit
Timer Y count stop bit
To CNTR1 interrupt
request bit
CNTR1 active
edge selection “1”
bit
Q
Toggle flip-flop T
Q
Port
P40latch
Timer Y latch (8)
“0 ”
R
Timer Y latch write pulse
Pulse output mode
Pulse output mode
Data bus
Prescaler 12 latch (8)
f(XIN)/16
(f(XCIN)/16 at low-speed mode)
f(XCIN)
Prescaler 12 (8)
Timer 1 latch (8)
Timer 2 latch (8)
Timer 1 (8)
Timer 2 (8)
To timer 2 interrupt
request bit
Timer 12 count source selection bit
To timer 1 interrupt
request bit
Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2
1-22
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
SERIAL I/O
●SERIAL I/O1
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O1 mode selection bit of the serial I/O1 control register (bit
6 of address 001A16) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
Data bus
Serial I/O1 control register
Address 001816
Receive buffer register
Receive buffer full flag (RBF)
Receive shift register
P24/RXD
Address 001A16
Receive interrupt request (RI)
Shift clock
Clock control circuit
P26/SCLK1
XIN
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
1/4
Address 001C16
BRG count source selection bit
1/4
P27/SRDY1
F/F
Clock control circuit
Falling-edge detector
Shift clock
P25/TXD
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
Transmit buffer register
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Address 001816
Data bus
Fig. 18 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY1
Write pulse to receive/transmit
buffer register (address 001816)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has
ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 19 Operation of clock synchronous serial I/O1 function
3850 Group (Spec. H) User’s Manual
1-23
HARDWARE
FUNCTIONAL DESCRIPTION
(2) Asynchronous Serial I/O (UART) Mode
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit (b6) of the serial I/O1
control register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
Data bus
Address 001816
P24/RXD
Serial I/O1 control register Address 001A16
Receive buffer register
OE
Character length selection bit
ST detector
7 bits
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
1/16
8 bits
PE FE
SP detector
Clock control circuit
UART control register
Address 001B16
Serial I/O1 synchronous clock selection bit
P26/SCLK1
XIN
BRG count source selection bit Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16
1/4
ST/SP/PA generator
Transmit shift completion flag (TSC)
1/16
P25/TXD
Transmit shift register
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer register
Address 001816
Transmit buffer empty flag (TBE)
Serial I/O1 status register Address 001916
Data bus
Fig. 20 Block diagram of UART serial I/O1
1-24
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
Serial output TXD
TBE=0
TBE=1
ST
D0
D1
SP
TSC=1
ST
D0
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read
signal
SP
D1
Generated at 2nd bit in 2-stop-bit mode
RBF=0
RBF=1
Serial input RXD
ST
D0
D1
SP
RBF=1
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 21 Operation of UART serial I/O1 function
[Transmit Buffer Register/Receive Buffer
Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Serial I/O1 Status Register (SIOSTS)] 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O1 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O1 Control Register (SIOCON)] 001A16
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P25/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
3850 Group (Spec. H) User’s Manual
1-25
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
b7
Serial I/O1 status register
(SIOSTS : address 001916)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
BRG count source selection bit (CSS)
0: f(XIN)
1: f(XIN)/4
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O1 is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O1 is selected, external clock input divided by 16
when UART is selected.
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
b0
Serial I/O1 control register
(SIOCON : address 001A16)
SRDY1 output enable bit (SRDY)
0: P27 pin operates as ordinary I/O pin
1: P27 pin operates as SRDY1 output pin
Overrun error flag (OE)
0: No error
1: Overrun error
b7
b0
UART control register
(UARTCON : address 001B16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P24 to P27 operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P24 to P27 operate as serial I/O1 pins)
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P25/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 22 Structure of serial I/O1 control registers
■Notes on serial I/O
When setting the transmit enable bit of serial I/O1 to “1”, the serial
I/O1 transmit interrupt request bit is automatically set to “1”. When
not requiring the interrupt occurrence synchronized with the transmission enalbed, take the following sequence.
➀Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
➁Set the transmit enable bit to “1”.
➂Set the serial I/O1 transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➃Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).
1-26
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
●SERIAL I/O2
The serial I/O2 can be operated only as the clock synchronous type.
As a synchronous clock for serial transfer, either internal clock or
external clock can be selected by the serial I/O2 synchronous clock
selection bit (b6) of serial I/O2 control register 1.
The internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selection
bits (b2, b1, b0) of serial I/O2 control register 1.
Regarding SOUT2 and SCLK2 being output pins, either CMOS output
format or N-channel open-drain output format can be selected by the
P0 1 /S OUT2 , P0 2 /S CLK2 P-channel output disable bit (b7) of
serial I/O2 control register 1.
When the internal clock has been selected, a transfer starts by a
write signal to the serial I/O2 register (address 001716). After completion of data transfer, the level of the SOUT2 pin goes to high impedance automatically but bit 7 of the serial I/O2 control register 2 is not
set to “1” automatically.
When the external clock has been selected, the contents of the serial
I/O2 register is continuously sifted while transfer clocks are input.
Accordingly, control the clock externally. Note that the SOUT2 pin does
not go to high impedance after completion of data transfer.
To cause the SOUT2 pin to go to high impedance in the case where
the external clock is selected, set bit 7 of the serial I/O2 control register 2 to “1” when SCLK2 is “H” after completion of data transfer. After
the next data transfer is started (the transfer clock falls), bit 7 of the
serial I/O2 control register 2 is set to “0” and the SOUT2 pin is put into
the active state.
Regardless of the internal clock to external clock, the interrupt request bit is set after the number of bits (1 to 8 bits) selected by the
optional transfer bit is transferred. In case of a fractional number of
bits less than 8 bits as the last data, the received data to be stored in
the serial I/O2 register becomes a fractional number of bits close to
MSB if the transfer direction selection bit of serial I/O2 control register 1 is LSB first, or a fractional number of bits close to LSB if the said
bit is MSB first. For the remaining bits, the previously received data
is shifted.
At transmit operation using the clock synchronous serial I/O, the SCMP2
signal can be output by comparing the state of the transmit pin SOUT2
with the state of the receive pin SIN2 in synchronization with a rise of
the transfer clock. If the output level of the SOUT2 pin is equal to the
input level to the SIN2 pin, “L” is output from the SCMP2 pin. If not, “H”
is output. At this time, an INT2 interrupt request can also be generated. Select a valid edge by bit 2 of the interrupt edge selection register (address 003A16).
b7
b0
Serial I/O2 control register 1
(SIO2CON1 : address 001516)
Internal synchronous clock selection bits
b2 b1 b0
0
0
0
0
1
1
0
0
1
1
1
1
0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
0: f(XIN)/128 f(XCIN)/128 in low-speed mode)
1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK2 output pin
SRDY2 output enable bit
0: P03 pin is normal I/O pin
1: P03 pin is SRDY2 output pin
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
P01/SOUT2 ,P02/SCLK2 P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode )
b7
b0
Serial I/O2 control register 2
(SIO2CON2 : address 001616)
Optional transfer bits
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0: 1 bit
1: 2 bit
0: 3 bit
1: 4 bit
0: 5 bit
1: 6 bit
0: 7 bit
1: 8 bit
Not used ( returns "0" when read)
Serial I/O2 I/O comparison signal control bit
0: P43 I/O
1: SCMP2 output
SOUT2 pin control bit (P01)
0: Output active
1: Output high-impedance
Fig. 23 Structure of Serial I/O2 control registers 1, 2
[Serial I/O2 Control Registers 1, 2 (SIO2CON1 /
SIO2CON2)] 001516, 001616
The serial I/O2 control registers 1 and 2 are containing various selection bits for serial I/O2 control as shown in Figure 23.
3850 Group (Spec. H) User’s Manual
1-27
HARDWARE
FUNCTIONAL DESCRIPTION
Internal synchronous
clock selection bits
1/8
XCIN
“10”
“00”
“01”
XIN
1/16
1/32
Divider
Main clock division ratio
selection bits (Note)
Data bus
1/64
1/128
1/256
P03 latch
Serial I/O2 synchronous
clock selection bit
“0”
P03/SRDY2
SCLK2
SRDY2
Synchronous circuit
“1”
SRDY2 output enable bit
“1”
“0”
External clock
P02 latch
Optional transfer bits (3)
“0”
P02/SCLK2
Serial I/O2
interrupt request
Serial I/O counter 2 (3)
“1”
Serial I/O2 port selection bit
P01 latch
“0”
P01/SOUT2
“1”
Serial I/O2 port selection bit
Serial I/O2 register (8)
P00/SIN2
P43 latch
“0”
D
P43/SCMP2/INT2
Q
“1”
Serial I/O2 I/O comparison
signal control bit
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.
Fig. 24 Block diagram of Serial I/O2
Transfer clock (Note 1)
Write-in signal to
serial I/O2 register
(Note 2)
Serial I/O2 output SOUT2
D0
D1
.
D2
D3
D4
D5
D6
D7
Serial I/O2 input SIN2
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected
by setting bits 0 to 2 of serial I/O2 control register 1.
2: When the internal clock is selected as a transfer clock, the SOUT2 pin has high impedance after transfer completion.
Fig. 25 Timing chart of Serial I/O2
1-28
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
SCMP2
SCLK2
SOUT2
SIN2
Judgement of I/O data comparison
Fig. 26 SCMP2 output operation
3850 Group (Spec. H) User’s Manual
1-29
HARDWARE
FUNCTIONAL DESCRIPTION
PULSE WIDTH MODULATION (PWM)
PWM Operation
The 3850 group (spec. H) has a PWM function with an 8-bit
resolution, based on a signal that is the clock input X IN or that
clock input divided by 2.
When bit 0 (PWM enable bit) of the PWM control register is set to
“1”, operation starts by initializing the PWM output circuit, and
pulses are output starting at an “H”.
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.
Data Setting
The PWM output pin also functions as port P4 4. Set the PWM
period by the PWM prescaler, and set the “H” term of output pulse
by the PWM register.
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255) :
PWM period = 255 ✕ (n+1) / f(XIN)
= 31.875 ✕ (n+1) µs
(when f(XIN) = 8 MHz,count source selection bit = “0”)
Output pulse “H” term = PWM period ✕ m / 255
= 0.125 ✕ (n+1) ✕ m µs
(when f(XIN) = 8 MHz,count source selection bit = “0”)
31.875 ✕ m ✕ (n+1)
µs
255
PWM output
T = [31.875 ✕ (n+1)] µs
m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM period (when f(XIN) = 8 MHz,count source
selection bit = “0”)
Fig. 27 Timing of PWM period
Data bus
PWM
prescaler pre-latch
PWM
register pre-latch
Transfer control circuit
PWM
prescaler latch
PWM
register latch
PWM prescaler
PWM register
Count source
selection bit
(XCIN
“0”
XIN
at low-speed mode)
1/2
Port P44
“1”
Port P44 latch
PWM enable bit
Fig. 28 Block diagram of PWM function
1-30
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
PWM control register
(PWMCON : address 001D16)
PWM function enable bit
0: PWM disabled
1: PWM enabled
Count source selection bit
0: f(XIN) (f(XCIN) at low-speed mode)
1: f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Not used (return “0” when read)
Fig. 29 Structure of PWM control register
A
B
B = C
T
T2
C
PWM output
T
PWM register
write signal
PWM prescaler
write signal
T
T2
(Changes “H” term from “A” to “B”.)
(Changes PWM period from “T” to “T2”.)
When the contents of the PWM register or PWM prescaler have changed, the PWM
output will change from the next period after the change.
Fig. 30 PWM output timing when PWM register or PWM prescaler is changed
■Note
The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin.
The length of this “L” level output is as follows:
n+1
2 • f(XIN)
sec
(Count source selection bit = 0, where n is the value set in the prescaler)
n+1
f(XIN)
sec
(Count source selection bit = 1, where n is the value set in the prescaler)
3850 Group (Spec. H) User’s Manual
1-31
HARDWARE
FUNCTIONAL DESCRIPTION
A-D CONVERTER
[A-D Conversion Registers (ADL, ADH)]
003516, 003616
b7
b0
AD control register
(ADCON : address 003416)
The A-D conversion registers are read-only registers that store the
result of an A-D conversion. Do not read these registers during an
A-D conversion.
Analog input pin selection bits
b2 b1 b0
0
0
0
0
1
[AD Control Register (ADCON)] 003416
The AD control register controls the A-D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 4 indicates the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
0
0
1
1
0
0: P30/AN0
1: P31/AN1
0: P32/AN2
1: P33/AN3
0: P34/AN4
Not used (returns “0” when read)
A-D conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
Comparison Voltage Generator
Fig. 31 Structure of AD control register
The comparison voltage generator divides the voltage between
AVSS and VREF into 1024 and outputs the divided voltages.
Channel Selector
10-bit reading
(Read address 003616 before 003516)
The channel selector selects one of ports P30/AN0 to P34/AN4 and
inputs the voltage to the comparator.
b7
b0
b9 b8
b7
b0
(Address 003616)
Comparator and Control Circuit
The comparator and control circuit compare an analog input voltage with the comparison voltage, and the result is stored in the
A-D conversion registers. When an A-D conversion is completed,
the control circuit sets the A-D conversion completion bit and the
A-D interrupt request bit to “1”.
Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A-D conversion.
When the A-D converter is operated at low-speed mode, f(X IN )
and f(XCIN) do not have the lower limit of frequency, because of
the A-D converter has a built-in self-oscillation circuit.
(Address 003516) b7 b6 b5 b4 b3 b2 b1 b0
Note : The high-order 6 bits of address 003616 become “0”
at reading.
8-bit reading (Read only address 003516)
b7
Fig. 32 Structure of A-D conversion registers
Data bus
AD control register
(Address 003416)
b7
b0
3
A-D control circuit
Channel selector
P30/AN0
P31/AN1
P32/AN2
P33/AN3
P34/AN4
Comparator
A-D interrupt request
A-D conversion high-order register (Address 003616)
A-D conversion low-order register (Address 003516)
10
Resistor ladder
VREF AVSS
Fig. 33 Block diagram of A-D converter
1-32
b0
(Address 003516) b9 b8 b7 b6 b5 b4 b3 b2
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
WATCHDOG TIMER
●Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 003916) permits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to 131.072 ms at f(XIN)
= 8 MHz frequency and 32.768 s at f(XCIN) = 32 kHz frequency.
When this bit is set to “1”, the count source becomes the signal
divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case
is set to 512 µs at f(XIN) = 8 MHz frequency and 128 ms at f(XCIN)
= 32 kHz frequency. This bit is cleared to “0” after reset.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control register (address 0039 16) after reset, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
003916) and an internal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 0039 16 ) may be
started before an underflow. When the watchdog timer control register (address 003916) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read.
●Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 003916) permits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, once the STP
instruction is executed, an internal reset occurs. When this bit is
set to “1”, it cannot be rewritten to “0” by program. This bit is
cleared to “0” after reset.
●Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
003916), each watchdog timer H and L is set to “FF16”.
“FF16” is set when
watchdog timer
control register is
written to.
XCIN
Data bus
“0 ”
“10”
Main clock division
ratio selection bits
(Note)
XIN
“FF16” is set when
watchdog timer
control register is
written to.
Watchdog timer L (8)
1/16
“1”
“00”
“01”
Watchdog timer H (8)
Watchdog timer H count
source selection bit
STP instruction disable bit
STP instruction
Reset
circuit
RESET
Internal reset
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 34 Block diagram of Watchdog timer
b7
b0
Watchdog timer control register
(WDTCON : address 003916)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 35 Structure of Watchdog timer control register
3850 Group (Spec. H) User’s Manual
1-33
HARDWARE
FUNCTIONAL DESCRIPTION
RESET CIRCUIT
To reset the microcomputer, RESET pin must be held at an “L”
level for 20 cycles or more of XIN. Then the RESET pin is returned
to an “H” level (the power source voltage must be between 2.7 V
and 5.5 V, and the oscillation must be stable), reset is released.
After the reset is completed, the program starts from the address
contained in address FFFD 16 (high-order byte) and address
FFFC16 (low-order byte). Make sure that the reset input voltage is
less than 0.54 V for VCC of 2.7 V.
Poweron
RESET
VCC
Power source
voltage
0V
Reset input
voltage
0V
(Note)
0.2VCC
Note : Reset release voltage; Vcc = 2.7 V
RESET
VCC
Power source
voltage detection
circuit
Fig. 36 Reset circuit example
XIN
φ
RESET
RESETOUT
Address
?
?
?
?
FFFC
FFFD
ADH,L
Reset address from the vector table.
Data
?
?
?
?
ADL
ADH
SYNC
XIN: 8 to 13 clock cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 2 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
3: All signals except XIN and RESET are internals.
Fig. 37 Reset sequence
1-34
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Address Register contents
Address Register contents
(1)
Port P0 (P0)
000016
0016
(34) MISRG
003816
(2)
Port P0 direction register (P0D)
000116
0016
(35) Watchdog timer control register (WDTCON)
003916 0 0 1 1 1 1 1 1
(3)
Port P1 (P1)
000216
0016
(36) Interrupt edge selection register (INTEDGE)
003A16
(4)
Port P1 direction register (P1D)
000316
0016
(37) CPU mode register (CPUM)
003B16 0 1 0 0 1 0 0 0
(5)
Port P2 (P2)
000416
0016
(38) Interrupt request register 1 (IREQ1)
003C16
0016
(6)
Port P2 direction register (P2D)
000516
0016
(39) Interrupt request register 2 (IREQ2)
003D16
0016
(7)
Port P3 (P3)
000616
0016
(40) Interrupt control register 1 (ICON1)
003E16
0016
(8)
Port P3 direction register (P3D)
000716
0016
(41) Interrupt control register 2 (ICON2)
003F16
0016
(9)
Port P4 (P4)
0016
0016
000816
0016
(42) Processor status register
(PS)
(10) Port P4 direction register (P4D)
000916
0016
(43) Program counter
(PCH)
FFFD16 contents
(11) Serial I/O2 control register 1 (SIO2CON1)
001516
0016
(PCL)
FFFC16 contents
(12) Serial I/O2 control register 2 (SIO2CON2)
001616 0 0 0 0 0 1 1 1
(13) Serial I/O2 register (SIO2)
001716 X X X X X X X X
(14) Transmit/Receive buffer register (TB/RB)
001816 X X X X X X X X
(15) Serial I/O1 status register (SIOSTS)
001916 1 0 0 0 0 0 0 0
(16) Serial I/O1 control register (SIOCON)
001A16
(17) UART control register (UARTCON)
001B16 1 1 1 0 0 0 0 0
(18) Baud rate generator (BRG)
001C16 X X X X X X X X
(19) PWM control register (PWMCON)
001D16
(20) PWM prescaler (PREPWM)
001E16 X X X X X X X X
(21) PWM register (PWM)
001F16 X X X X X X X X
(22) Prescaler 12 (PRE12)
002016
FF16
(23) Timer 1 (T1)
002116
0116
(24) Timer 2 (T2)
002216
0016
(25) Timer XY mode register (TM)
002316
0016
(26) Prescaler X (PREX)
002416
FF16
(27) Timer X (TX)
002516
FF16
(28) Prescaler Y (PREY)
002616
FF16
(29) Timer Y (TY)
002716
FF16
(30) Timer count source selection register (TCSS)
002816
0016
(31) A-D control register (ADCON)
003416 0 0 0 1 0 0 0 0
(32) A-D conversion low-order register (ADL)
003516 X X X X X X X X
(33) A-D conversion high-order register (ADH)
003616 0 0 0 0 0 0 X X
X X X X X 1X X
0016
0016
Note : X : Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
Fig. 38 Internal status at reset
3850 Group (Spec. H) User’s Manual
1-35
HARDWARE
FUNCTIONAL DESCRIPTION
CLOCK GENERATING CIRCUIT
(2) Wait mode
The 3850 group (spec. H) has two built-in oscillation circuits. An
oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants
in accordance with the resonator manufacturer’s recommended
values. No external resistor is needed between X IN and X OUT
since a feed-back resistor exists on-chip. However, an external
feed-back resistor is needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After reset is released, this mode is selected.
To ensure that the interrupts will be received to release the STP or
WIT state, their interrupt enable bits must be set to “1” before executing of the STP or WIT instruction.
When releasing the STP state, the prescaler 12 and timer 1 will
start counting the clock XIN divided by 16. Accordingly, set the
timer 1 interrupt enable bit to “0” before executing the STP instruction.
■Note
When using the oscillation stabilizing time set after STP instruction
released bit set to “1”, evaluate time to stabilize oscillation of the
used oscillator and set the value to the timer 1 and prescaler 12.
(2) High-speed mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
■Note
If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time
is required for the sub-clock to stabilize, especially immediately after power on and at returning from the stop mode. When switching
the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3•f(XCIN).
XCIN
XCOUT
Rf
CCIN
XIN
XOUT
Rd
CCOUT
CI N
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1”. When the main clock XIN is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
The sub-clock XCIN-XCOUT oscillating circuit can not directly input
clocks that are generated externally. Accordingly, make sure to
cause an external resonator to oscillate.
Fig. 39 Ceramic resonator circuit
XCIN
Oscillation Control
(1) Stop mode
Rf
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillation stops. When the oscillation
stabilizing time set after STP instruction released bit is “0”, the
prescaler 12 is set to “FF16” and timer 1 is set to “0116”. When the
oscillation stabilizing time set after STP instruction released bit is
“1”, set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1.
Either X IN or X CIN divided by 16 is input to the prescaler 12 as
count source. Oscillator restarts when an external interrupt is received, but the internal clock φ is not supplied to the CPU (remains
at “H”) until timer 1 underflows. The internal clock φ is supplied for
the first time, when timer 1 underflows. This ensures time for the
clock oscillation using the ceramic resonators to be stabilized.
When the oscillator is restarted by reset, apply “L” level to the
RESET pin until the oscillation is stable since a wait time will not
be generated.
1-36
XCOUT
XIN
XOUT
Open
Rd
External oscillation
circuit
CCIN
CCOUT
Vcc
Vss
Fig. 40 External clock input circuit
3850 Group (Spec. H) User’s Manual
COUT
HARDWARE
FUNCTIONAL DESCRIPTION
[MISRG (MISRG)] 003816
b0
b7
MISRG
(MISRG : address 003816)
MISRG consists of three control bits (bits 1 to 3) for middle-speed
mode automatic switch and one control bit (bit 0) for oscillation
stabilizing time set after STP instruction released.
By setting the middle-speed mode automatic switch start bit to “1”
while operating in the low-speed mode and setting the middlespeed mode automatic switch set bit to “1”, X IN oscillation
automatically starts and the mode is automatically switched to the
middle-speed mode.
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
1: Automatically set nothing
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enable
Middle-speed mode automatic switch wait time set bit
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start
Not used (return “0” when read)
Note: When the mode is automatically switched from the low-speed mode to
the middle-speed mode, the value of CPU mode register (address 003B16)
changes.
Fig. 41 Structure of MISRG
XCOUT
XCIN
“0”
“1”
Port XC
switch bit
XOUT
XIN
Main clock division ratio
selection bits (Note 1)
Low-speed mode
1/2
1/4
Prescaler 12
1/2
High-speed or
middle-speed
mode
FF16
(Note 3)
Timer 1
0116
Reset or
STP instruction
(Note 2)
Main clock division ratio
selection bits (Note 1)
Middle-speed mode
Timing φ (internal clock)
High-speed or
low-speed mode
Main clock stop bit
Q
S
R
S Q
STP instruction
WIT instruction
R
Reset
Q S
R
STP instruction
Reset
Interrupt disable flag l
Interrupt request
Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b4) to “1”.
2: At reset, f(XIN)/16 is supplied to the prescaler 12 as the count source. When executing the STP instruction, the count
source supplied before the STP instruction execution is supplied.
3: When bit 0 of MISRG is “0”, “FF16” is set to the prescaler 12 and “0116” is set to Timer 1. When bit 0 of MISRG is “1”,
set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and Timer 1.
Fig. 42 System clock generating circuit block diagram (Single-chip mode)
3850 Group (Spec. H) User’s Manual
1-37
HARDWARE
FUNCTIONAL DESCRIPTION
Reset
C
“0 M4
CM ” ←
“1 6 →
”←
“1
”
→
“0
”
”
“0
→
M
”
←
C ”
“0
“1 M6 →
←
C ”
“1
4
Middle-speed mode
(f(φ) = 1 MHz)
CM7 = 0
CM6 = 1
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
CM7 = 0
CM6 = 0
CM5 = 0 (8 MHz oscillating)
CM4 = 0 (32 kHz stopped)
CM6
“1” ←→ “0”
C
“0 M7
CM ” ←
“1 6 →
“1
”←
”
→
“0
”
Middle-speed mode
automatic switch set bit = “1”
High-speed mode
(f(φ) = 4 MHz)
CM7 = 0
CM6 = 0
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
CM7
“1” ←→ “0”
CM7 = 0
CM6 = 1
CM5 = 0 (8 MHz oscillating)
CM4 = 0 (32 kHz stopped)
CM4
“1” ←→ “0”
High-speed mode
(f(φ) = 4 MHz)
CM6
“1” ←→ “0”
CM4
“1” ←→ “0”
Middle-speed mode
(f(φ) = 1 MHz)
Low-speed mode
(f(φ)=16 kHz)
CM7 = 1
CM6 = 0
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16)
CM5
“1” ←→ “0”
Middle-speed mode automatic
switch start bit = “1”
Low-speed mode
(f(φ)=16 kHz)
CM7 = 1
CM6 = 0
CM5 = 1 (8 MHz stopped)
CM4 = 1 (32 kHz oscillating)
CM4 : Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
CM5 : Main clock (XIN- XOUT) stop bit
0 : Operating
1 : Stopped
CM7, CM6: Main clock division ratio selection bit
b7 b6
0 0 : φ = f(XIN)/2 ( High-speed mode)
0 1 : φ = f(XIN)/8 (Middle-speed mode)
1 0 : φ = f(XCIN)/2 (Low-speed mode)
1 1 : Not available
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 : Timer operates in the wait mode.
4 : When bit 0 of MISRG is “0” and the stop mode is ended, a delay of approximately 1 ms occurs by connecting timer 1 in middle/high-speed
mode.
5 : When bit 0 of MISRG is “0” and the stop mode is ended, the following is performed.
(1) After the clock is restarted, a delay of approximately 256 ms occurs in low-speed mode if Timer 12 count source selection bit is “0”.
(2) After the clock is restarted, a delay of approximately 16 ms occurs in low-speed mode if Timer 12 count source selection bit is “1”.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed
mode.
7: When switching to the middle-speed mode by the middle-speed mode automatic switch bit of MISRG, the waiting time set by the middlespeed mode automatic switch wait time set bit is generated automatically, and switch to the middle-speed mode.
8 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 43 State transitions of system clock
1-38
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
FLASH MEMORY VERSION
Summary
Table 9 shows the summary of the M38507F8 (flash memory version).
Table 9 Summary of M38507F8 (flash memory version)
Item
Specification
Power source voltage
Vcc = 2.7–5.5 V (Note 1)
Vcc = 2.7–3.6 V (Note 2)
Program/Erase VPP voltage
4.5–5.5 V, f(XIN) = 8 MHz
Flash memory mode
3 modes (Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode)
User ROM area
1 block (32 Kbytes)
Boot ROM area
1 block (4 Kbytes) (Note 3)
Erase block division
Program method
Byte program
Erase method
Batch erasing
Program/Erase control method
Program/Erase control by software command
Number of commands
6 commands
Number of program/Erase times
100 times
ROM code protection
Available in parallel I/O mode, and standard serial I/O mode
Notes 1: The power source voltage must be Vcc = 4.5–5.5 V at program and erase operation.
2: The power source voltage can be Vcc = 3.0–3.6 V also at program and erase operation.
3: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory.
This Boot ROM area can be rewritten in only parallel I/O mode.
3850 Group (Spec. H) User’s Manual
1-39
HARDWARE
FUNCTIONAL DESCRIPTION
Flash Memory Mode
The M38507F8 (flash memory version) has an internal new DINOR
(DIvided bit line NOR) flash memory that can be rewritten with a
single power source when VCC is 5 V, and 2 power sources when
VCC is 3.3-5.0 V.
For this flash memory , three flash memory modes are available in
which to read, program, and erase: parallel I/O and standard serial I/
O modes in which the flash memory can be manipulated using a
programmer and a CPU rewrite mode in which the flash memory can
be manipulated by the Central Processing Unit (CPU). Each mode is
detailed in the pages to follow.
The flash memory of the M38507F8 is divided into User ROM area
and Boot ROM area as shown in Figure 44.
In addition to the ordinary user ROM area to store a microcomputer
operation control program, the flash memory has a Boot ROM area
that is used to store a program to control rewriting in CPU rewrite
and standard serial I/O modes. This Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from
the factory. However, the user can write a rewrite control program in
this area that suits the user’s application system. This Boot ROM
area can be rewritten in only parallel I/O mode.
Parallel I/O mode
800016
Block 1 : 32 kbyte
FFFF16
F00016
4 kbyte
FFFF16
User ROM area
Boot ROM area
BSEL = 0
BSEL = 1
CPU rewrite mode, standard serial I/O mode
800016
Block 1 : 32 kbyte
Product name
Flash memory
start address
FFFF16
F00016
4 kbyte
FFFF16
User ROM area
M38507F8
800016
User area / Boot area selection bit = 0
Boot ROM area
User area / Boot area selection bit = 1
Notes 1: The Boot ROM area can be rewritten in only parallel
input/output mode. (Access to any other areas is inhibited.)
2: To specify a block, use the maximum address in the block.
Fig. 44 Block diagram of flash memory version
1-40
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
CPU Rewrite Mode
In CPU rewrite mode, the on-chip flash memory can be operated on
(read, program, or erase) under control of the Central Processing
Unit (CPU).
In CPU rewrite mode, only the user ROM area shown in Figure 44
can be rewritten; the Boot ROM area cannot be rewritten. Make sure
the program and block erase commands are issued for only the user
ROM area and each block area.
The control program for CPU rewrite mode can be stored in either
user ROM or Boot ROM area. In the CPU rewrite mode, because the
flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM area before it can be executed.
Bit 2 is the CPU rewrite mode entry flag. This bit can be read to
check whether the CPU rewrite mode has been entered or not.
Bit 3 is the flash memory reset bit used to reset the control circuit of
the internal flash memory. This bit is used when exiting CPU rewrite
mode and when flash memory access has failed. When the CPU
rewrite mode select bit is “1”, writing “1” for this bit resets the control
circuit. To release the reset, it is necessary to set this bit to “0”.
Bit 4 is the User area/Boot area selection bit. When this bit is set to
“1”, Boot ROM area is accessed, and CPU rewrite mode in Boot
ROM area is available. In boot mode, this bit is set “1” automatically.
Operation of this bit must be in RAM area.
Figure 46 shows a flowchart for setting/releasing the CPU rewrite
mode.
Microcomputer Mode and Boot Mode
Precautions on CPU Rewrite Mode
The control program for CPU rewrite mode must be written into the
user ROM or Boot ROM area in parallel I/O mode beforehand. (If the
control program is written into the Boot ROM area, the standard serial I/O mode becomes unusable.)
See Figure 44 for details about the Boot ROM area.
Normal microcomputer mode is entered when the microcomputer is
reset with pulling CNVSS pin low. In this case, the CPU starts operating using the control program in the user ROM area.
When the microcomputer is reset by pulling the P41/INT0 pin high,
the CNVSS pin high, the CPU starts operating using the control program in the Boot ROM area (program start address is FFFC 16,
FFFD16 fixation). This mode is called the “boot” mode.
Described below are the precautions to be observed when rewriting
the flash memory in CPU rewrite mode.
(1) Operation speed
During CPU rewrite mode, set the internal clock frequency 4MHz
or less using the main clock division ratio selection bits (bit 6, 7 at
003B16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode .
(3) Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory.
(4) Watchdog timer
Block Address
Block addresses refer to the maximum address of each block. These
addresses are used in the block erase command. In case of the
M38507F8, it has only one block.
In case of the watchdog timer has been running already, the internal reset generated by watchdog timer underflow does not
happen, because of watchdog timer is always clearing during
program or erase operation.
(5) Reset
Outline Performance (CPU Rewrite Mode)
In the CPU rewrite mode, the CPU erases, programs and reads the
internal flash memory as instructed by software commands. This rewrite control program must be transferred to internal RAM before it
can be executed.
The CPU rewrite mode is accessed by applying 5V ± 10% to the
CNVSS pin and writing “1” for the CPU rewrite mode select bit (bit 1
in address 0FFE16). Software commands are accepted once the
mode is accessed.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or in
error can be verified by reading the status register.
Figure 45 shows the flash memory control register.
_____
Bit 0 is the RY/BY status flag used exclusively to read the operating
status of the flash memory. During programming and erase operations, it is “0”. Otherwise, it is “1”.
Bit 1 is the CPU rewrite mode select bit. When this bit is set to “1” and
5V ± 10% are applied to the CNVSS pin, the M38507F8 accesses the
CPU rewrite mode. Software commands are accepted once the
mode is accessed. In CPU rewrite mode, the CPU becomes unable
to access the internal flash memory directly. Therefore, use the control program in RAM for write to bit 1. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. The bit can be set
to “0” by only writing a “0”.
Reset is always valid. In case of CNVSS = H when reset is released, boot mode is active. So the program starts from the address contained in address FFFC16 and FFFD16 in boot ROM
area.
3850 Group (Spec. H) User’s Manual
1-41
HARDWARE
FUNCTIONAL DESCRIPTION
Flash memory control register
b7 b6
b5
b4 b3
b2
b1
b0
Symbol
Address
When reset
FM CR
0FFE16
XXX00001
Bit name
Bit symbol
Function
FMCR0
RY/BY status flag
0: Busy (being written or erased)
1: Ready
FMCR1
CPU rewrite mode
select bit (Note 2)
FMCR2
CPU rewrite mode
entry flag
0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)
0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)
FMCR3
Flash memory reset bit
(Note 3)
0: Normal operation
1: Reset
FMCR4
User area / Boot area
selection bit
0: User ROM area
1: Boot ROM area
R WW
R
Nothing is assigned.
When write, set “0”. When read, values are indeterminate.
Notes 1: The contents of the flash memory control register after reset is released become
“XXX00001”.
2: For this bit to be set to “1”, write “0” and then “1” to bit 1 in succession.
3: In order to perform flash memory reset by this bit setup, while the CPU rewriting
mode selection bit is set to “1”, write “1” to bit 3. In order to reset release, write “0”
to bit 3 in the next.
Fig. 45 Flash memory control registers
Program in ROM
Program in RAM
Start
*1
Single-chip mode, or boot mode
Set CPU mode register (Note 1)
Transfer CPU rewrite mode control
program to internal RAM
Jump to transferred control program in RAM
(Subsequent operations are executed by control
program in this RAM)
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)
Check the CPU rewrite mode entry flag
Using software command execute erase,
program, or other operation
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 2)
*1
Write “0” to CPU rewrite mode select bit
End
Notes 1: Set bit 6, 7 (Main clock division ratio selection bits ) at CPU mode register (003B16).
2: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to
execute a read array command or reset the flash memory.
Fig. 46 CPU rewrite mode set/reset flowchart
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3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Software Commands
Read Status Register Command (7016)
Table 10 lists the software commands.
After setting the CPU rewrite mode select bit to “1”, write a software
command to specify an erase or program operation.
The content of each software command is explained below.
When the command code “7016” is written in the first bus cycle, the
content of the status register is read out at the data bus (D0–D7) by a
read in the second bus cycle.
The status register is explained in the next section.
Read Array Command (FF16)
Clear Status Register Command (5016)
The read array mode is entered by writing the command code “FF16”
in the first bus cycle. When an address to be read is input in one of
the bus cycles that follow, the content of the specified address is
read out at the data bus (D0–D7).
The read array mode is retained intact until another command is written. And after power on and after recover from deep power down
mode, this mode is selected also.
This command is used to clear the bits SR1,SR4 and SR5 of the
status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “5016” in the first bus cycle.
Table 10 List of software commands (CPU rewrite mode)
First bus cycle
Command
Cycle number
Mode
Address
Second bus cycle
Data
(D0 to D7)
Mode
Address
Data
(D0 to D7)
Read
X
SRD (Note 1)
Read array
1
Write
Read status register
2
Write
X
7016
Clear status register
1
Write
X
5016
Program
2
Write
X
4016
Write
Erase all block
2
Write
X
2016
Write
Block erase
2
Write
X
2016
Write
X
(Note 4)
FF16
WA (Note 2)
BA
WD (Note 2)
X
2016
(Note 3)
D016
Notes 1: SRD = Status Register Data
2: WA = Write Address, WD = Write Data
3: BA = Block Address (Enter the maximum address of each block.)
4: X denotes a given address in the user ROM area .
3850 Group (Spec. H) User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
Program Command (4016)
Block Erase Command (2016/D016)
Program operation starts when the command code “4016” is written
in the first bus cycle. Then, if the address and data to program are
written in the 2nd bus cycle, program operation (data programming
and verification) will start.
Whether the write operation is completed can be confirmed by read_____
ing the status register or the RY/BY status flag. When the program
starts, the read status register mode is accessed automatically and
the content of the status register is read into the data bus (D0–D7).
The status register bit 7 (SR7) is set to “0” at the same time the write
operation starts and is returned to “1” upon completion of the write
operation. In this case, the read status register mode remains active
until the read array command (FF16) is written.
____
The RY/BY status flag is “0” during write operation and “1” when the
write operation is completed as is the status register bit 7.
At program end, program results can be checked by reading the status register.
By writing the command code “2016” in the first bus cycle and the
confirmation command code “D016” in the second bus cycle that
follows to the block address of a flash memory block, the system
initiates a block erase (erase and erase verify) operation.
Whether the block erase operation is completed can be confirmed
____
by reading the status register or the RY/BY status flag. At the same
time the block erase operation starts, the read status register mode
is automatically entered, so the content of the status register can be
read out. The status register bit 7 (SR7) is set to “0” at the same time
the block erase operation starts and is returned to “1” upon completion of the block erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written.
____
The RY/BY status flag is “0” during block erase operation and “1”
when the block erase operation is completed as is the status register
bit 7.
After the block erase operation is completed, the status register can
be read out to know the result of the block erase operation. For de-
Erase All Blocks Command (2016/2016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “2016” in the second bus cycle that follows, the system starts erase all blocks( erase and erase verify).
Whether the erase all blocks command is terminated can be con____
firmed by reading the status register or the RY/BY status flag. When
the erase all blocks operation starts, the read status register mode is
accessed automatically and the content of the status register can be
read out. The status register bit 7 (SR7) is set to “0” at the same time
the erase operation starts and is returned to “1” upon completion of
the erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written.
____
The RY/BY status flag is “0” during erase operation and “1” when the
erase operation is completed as is the status register bit 7.
At erase all blocks end, erase results can be checked by reading the
status register. For details, refer to the section where the status register is detailed.
Start
Write 2016
Write
Status register
read
SR7=1?
or
RY/BY=1?
Start
YES
Erase completed
Write 4016
Fig. 48 Erase flowchart
Status register
read
SR7=1?
or
RY/BY=1?
NO
YES
NO
SR4=0?
Program
error
YES
Program
completed
Fig. 47 Program flowchart
1-44
NO
YES
SR5=0?
Write Write address
Write data
2016:Erase all blocks
D016:Block erase
2016/D016
Block address
3850 Group (Spec. H) User’s Manual
NO
Erase error
HARDWARE
FUNCTIONAL DESCRIPTION
Status Register
Sequencer status (SR7)
The status register shows the operating state of the flash memory
and whether erase operations and programs ended successfully or
in error. It can be read in the following ways.
(1) By reading an arbitrary address from the user ROM area after
writing the read status register command (7016)
(2) By reading an arbitrary address from the user ROM area in the
period from when the program starts or erase operation starts to
when the read array command (FF16) is input
After power-on, and after recover from deep power down mode, the
sequencer status is set to “1”(ready).
The sequencer status indicates the operating status of the device.
This status bit is set to “0” (busy) during write or erase operation and
is set to “1” upon completion of these operations.
Table 11 shows the status register.
Also, the status register can be cleared in the following way.
(1) By writing the clear status register command (5016)
(2) In the deep power down mode
(3) In the power supply off state
After a reset, the status register is set to “8016”.
Each bit in this register is explained below.
Erase status (SR5)
The erase status informs the operating status of erase operation to
the CPU. When an erase error occurs, it is set to “1”.
The erase status is reset to “0” when cleared.
Program status (SR4)
The program status informs the operating status of write operation to
the CPU. When a write error occurs, it is set to “1”.
The program status is reset to “0” when cleared.
If “1” is written for any of the SR5 or SR4 bits, the program, erase all
blocks, and block erase commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register.
Also, any commands are not correct, both SR5 and SR4 are set to
“1”.
Table 11 Definition of each bit in status register
Each bit of
SRD0 bits
Status name
SR7 (bit7)
SR6 (bit6)
Sequencer status
Reserved
SR5 (bit5)
SR4 (bit4)
Erase status
Program status
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Definition
“1”
“0”
Ready
-
Busy
-
Terminated in error
Terminated in error
Terminated normally
Terminated normally
Reserved
Reserved
-
-
Reserved
Reserved
-
-
3850 Group (Spec. H) User’s Manual
1-45
HARDWARE
FUNCTIONAL DESCRIPTION
Full Status Check
By performing full status check, it is possible to know the execution
results of erase and program operations. Figure 49 shows a full sta-
tus check flowchart and the action to be taken when each error occurs.
Read status register
SR4=1 and SR5
=1 ?
YES
Command
sequence error
NO
SR5=0?
NO
Block erase error
Execute the clear status register command (5016)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Should a block erase error occur, the block in error
cannot be used.
YES
SR4=0?
NO
Program error
Should a program error occur, the block in error
cannot be used.
YES
End (block erase, program)
Note: When one of SR5 to SR4 is set to “1” , none of the program, erase all blocks,
and block erase commands is accepted. Execute the clear status register
command (5016) before executing these commands.
Fig. 49 Full status check flowchart and remedial procedure for errors
1-46
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Functions To Inhibit Rewriting Flash Memory
Version
To prevent the contents of the flash memory version from being read
out or rewritten easily, the device incorporates a ROM code protect
function for use in parallel I/O mode and an ID code check function
for use in standard serial I/O mode.
ROM code protect function
The ROM code protect function is the function inhibit reading out or
modifying the contents of the flash memory version by using the
ROM code protect control address (FFDB 16) during parallel I/O
mode. Figure 50 shows the ROM code protect control address
(FFDB16). (This address exists in the user ROM area.)
If one of the pair of ROM code protect bits is set to “0”, ROM code
protect is turned on, so that the contents of the flash memory version are protected against readout and modification. ROM code
protect is implemented in two levels. If level 2 is selected, the flash
memory is protected even against readout by a shipment inspection
LSI tester, etc. When an attempt is made to select both level 1 and
level 2, level 2 is selected by default.
If both of the two ROM code protect reset bits are set to “00”, ROM
code protect is turned off, so that the contents of the flash memory
version can be read out or modified. Once ROM code protect is
turned on, the contents of the ROM code protect reset bits cannot
be modified in parallel I/O mode. Use the serial I/O or some other
mode to rewrite the contents of the ROM code protect reset bits.
ROM code protect control address
b7
b6
b5
b4
b3
b2
b1
b0
1 1
Symbol
ROMCP
Address
FFDB16
When reset
FF1 6
Function
Bit name
Bit symbol
Reserved bit
Always set this bit to “1”
ROM code protect level
2 set bit (Note 1, 2)
b3 b2
ROMCP2
ROM code protect reset
bit (Note 3)
b5 b4
ROMCR
ROMCP1
ROM code protect level
1 set bit (Note 1)
b7 b6
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
00: Protect removed
01: Protect set bit effective
10: Protect set bit effective
11: Protect set bit effective
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
Notes 1: When ROM code protect is turned on, the on-chip flash memory is protected against
readout or modification in parallel input/output mode.
2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and
ROM code protect level 2. However, since these bits cannot be changed in parallel
input/output mode, they need to be rewritten in serial input/output mode or some other
mode.
Fig. 50 ROM code protect control address
3850 Group (Spec. H) User’s Manual
1-47
HARDWARE
FUNCTIONAL DESCRIPTION
ID Code Check Function
Use this function in standard serial I/O mode. When the contents of
the flash memory are not blank, the ID code sent from the peripheral
unit is compared with the ID code written in the flash memory to see
if they match. If the ID codes do not match, the commands sent from
the peripheral unit are not accepted. The ID code consists of 8-bit
data, the areas of which are FFD416 to FFDA16. Write a program
which has had the ID code preset at these addresses to the flash
memory.
Address
FFD416
ID1
FFD516
ID2
FFD616
ID3
FFD716
ID4
FFD816
ID5
FFD916
ID6
FFDA16
ID7
FFDB16
ROM cord Protect control
Interrupt vector area
Fig. 51 ID code store addresses
1-48
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Parallel I/O Mode
Bus Operation Modes
The parallel I/O mode is entered by making connections shown in
Figure 52 and then turning the Vcc power supply on.
Read
Address
The user ROM is only one block as shown in Figure 44. The block
address referred to in this data sheet is the maximum address value
of each block.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in
Figure 44 can be rewritten. The BSEL pin is used to choose between
these two areas. The user ROM area is selected by pulling the BSEL
input low; the boot ROM area is selected by driving the BSEL input high.
Both areas of flash memory can be operated on in the same way.
Program and block erase operations can be performed in the user
ROM area. The user ROM area and its block is shown in Figure 44.
The user ROM area is 32 Kbytes in size. In parallel I/O mode, it is
located at addresses 800016 through FFFF16. The boot ROM area is
4 Kbytes in size. In parallel I/O mode, it is located at addresses
F00016 through FFFF16. Make sure program and block erase operations are always performed within this address range. (Access to
any location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block. The boot ROM area has had a standard serial
I/O mode control program stored in it when shipped from the
Renesas factory. Therefore, using the device in standard serial input/output mode, you do not need to write to the boot ROM area.
Functional Outline (Parallel I/O Mode)
In parallel I/O mode, bus operation modes—Read, Output Disable,
Standby, Write, and Deep Power Down—are selected by the status
_____ _____ _____
_____
of the CE, OE, WE, and RP input pins.
The contents of erase, program, and other operations are selected
by writing a software command. The data, status register, etc. in
memory can only be read out by a read after software command
input.
Program and erase operations are controlled using software commands.
The following explains about bus operation modes, software commands, and status register.
_____
_____
The Read mode is entered by pulling the OE pin low when the CE
_____
_____
pin is low and the WE and RP pins are high. There are two read
modes: array, and status register, which are selected by software
command input. In read mode, the data corresponding to each software command entered is output from the data I/O pins D0–D7. The
read array mode is automatically selected when the device is powered on or after it exits deep power down mode.
Output Disable
_____
The output disable mode is entered by pulling the CE pin low and the
_____ _____
_____
WE, OE, and RP pins high. Also, the data I/O pins are placed in the
high-impedance state.
Standby
_____
_____
The standby mode is entered by driving the CE pin high when the RP
pin is high. Also, the data I/O pins are placed in the high-impedance
_____
state. However, if the CE pin is set high during erase or program
operation, the internal control circuit does not halt immediately and
normal power consumption is required until the operation under way
is completed.
Write
_____
_____
The write mode is entered by pulling the WE pin low when the CE pin
_____
_____
is low and the OE and RP pins are high. In this mode, the device
accepts the software commands or write data entered from the data
I/O pins. A program, erase, or some other operation is initiated depending on the content of the software command entered here. The
input data such as address and software command is latched at the
_____
_____
rising edge of WE or CE whichever occurs earlier.
Deep Power Down
_____
The deep power down is entered by pulling the RP pin low. Also, the
data I/O pins are placed in the high-impedance state. When the device is freed from deep power down mode, the read array mode is
selected and the content of the status register is set to “8016”. If the
_____
RP pin is pulled low during erase or program operation, the operation under way is canceled and the data in the relevant block becomes invalid.
Table 12 Relationship between control signals and bus operation modes
Pin name
_____
_____
______
_____
CE
OE
WE
RP
Array
VIL
VIL
VIH
VIH
Data output
Status register
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIH
Status register data output
High impedance
Program
VIH
VIL
X
VIH
X
VIL
VIH
VIH
High impedance
Command/data input
Erase all blocks
Block erase
VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIH
Command input
Command input
X
X
X
VIL
High impedance
Mode
Read
Output disabled
Stand by
Write
Deep power down
D0 to D7
Note : X can be VIL or VIH.
3850 Group (Spec. H) User’s Manual
1-49
HARDWARE
FUNCTIONAL DESCRIPTION
Table 13 Description of Pin Function (Flash Memory Parallel I/O Mode)
Pin name
Signal name
I/O
Function
Apply 5.0 ± 0.5 V to the Vcc pin and 0 V to the Vss pin.
VCC,VSS
Power supply input
CNVSS
CNVSS
I
Connect this pin to Vcc.
RESET
Reset input
I
Reset input pin. When reset is held low, more than 20 cycles of clock are
required at the XIN pin.
X IN
Clock input
I
XOUT
Clock output
O
Connect a ceramic or crystal resonator between the XIN and XOUT pins.
When entering an externally drived clock, enter it from XIN and leave XOUT
open.
AVSS
Analog power supply input
VREF
Reference voltage input
P00 to P07
Data I/O D0 to D7
P10 to P17
Address input A8 to A15
I
These are address A8–A15 input pins.
P20 to P27
Address input A0 to A7
I
These are address A0–A7 input pins.
P30
BSEL input
I
This is a BSEL input pin.
P31
RP input
I
This is a RP input pin.
P32
WE input
I
This is a WE input pin.
P33
CE input
I
This is a CE input pin.
P34
OE input
I
This is a OE input pin.
P40
RY/BY output
O
This is a RY/BY output pin.
P41
Input P41
I
Enter low signals to this pin.
P42 to P44
Input P4
I
Input “H” or “L” or keep open.
1-50
Connect AVss to Vss.
I
Input AD reference voltage or keep open.
I/O
These are data D0–D7 input/output pins.
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
VCC
VSS
RY/BY
A7
A6
A5
A4
A3
A2
A1
A0
✽
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
M38507F8SP/FP
VCC
VREF
AVSS
P44/INT3/PWM
P43/INT2/SCMP2
P42/INT1
P41/INT0
P40/CNTR1
P27/CNTR0/SRDY1
P26/SCLK1
P25/SCL2/TxD
P24/SDA2/RxD
P23
P22
CNVSS
P21/XCIN
P20/XCOUT
RESET
XIN
XOUT
VSS
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Mode setup method
Signal
P30/AN0
P31/AN1
P32/AN2
P33/AN3
P34/AN4
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04
P05
P06
P07
P10/(LED0)
P11/(LED1)
P12/(LED2)
P13/(LED3)
P14/(LED4)
P15/(LED5)
P16/(LED6)
P17/(LED7)
BSEL
RP
WE
CE
OE
D0
D1
D2
D3
D4
D5
D6
D7
A8
A9
A10
A11
A12
A13
A14
A15
✽ Connect oscillator circuit
Value
CNVSS
VCC
P41/INT0
VSS
RESET
VSS
Fig. 52 Pin connection diagram in parallel I/O mode
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HARDWARE
FUNCTIONAL DESCRIPTION
Software Commands
Read Status Register Command (7016)
Table 14 lists the software commands. By entering a software command from the data I/O pins (D0–D7) in Write mode, specify the content of the operation, such as erase or program operation, to be performed.
The following explains the content of each software command.
When the command code “7016” is written in the first bus cycle, the
content of the status register is output from the data I/O pins (D0–D7)
by a read in the second bus cycle. Since the content of the status
_____
_____
_____
_____
register is updated at the falling edge of OE or CE, the OE or CE
signal must be asserted each time the status is read. The status
register is explained in the next section.
Read Array Command (FF16)
The read array mode is entered by writing the command code “FF16”
in the first bus cycle. When an address to be read is input in one of
the bus cycles that follow, the content of the specified address is
output from the data I/O pins (D0–D7).
The read array mode is retained intact until another command is written.
The read array mode is also selected automatically when the device
is powered on and after it exits deep power down mode.
Clear Status Register Command (5016)
This command is used to clear the bits SR4,SR5 of the status register after they have been set. These bits indicate that operation has
ended in an error. To use this command, write the command code
“5016” in the first bus cycle.
Table 14 Software command list (parallel I/O mode)
Second bus cycle
First bus cycle
Command
Cycle number
Mode
Data
Address
(D0 to D7)
Mode
Data
Address
(D0 to D7)
X
SRD(Note 1)
Read array
1
Write
X(Note 4)
FF16
Read status register
Clear status register
2
1
Write
Write
X
X
7016
5016
Read
Program
All block erase
2
2
Write
Write
X
X
4016
2016
Write
Write
WA(Note 2) WD(Note 2)
X
2016
Block erase
2
Write
X
2016
Write
BA(Note 3)
Notes 1: SRD = Status Register Data
2: WA = Write Address, WD = Write Data
3: BA = Block Address (Enter the maximum address of each block)
4: X denotes a given address in the user ROM area or boot ROM area.
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3850 Group (Spec. H) User’s Manual
D016
HARDWARE
FUNCTIONAL DESCRIPTION
____
Program Command (4016)
The program operation starts when the command code “4016” is written in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, program operation (data programming and verification) will start.
Whether the write operation is completed can be confirmed by read_____
ing the status register or the RY/BY signal status. When the program
starts, the read status register mode is accessed automatically and
the content of the status register can be read out from the data bus
(D0–D7). The status register bit 7 (SR7) is set to “0” at the same time
the write operation starts and is returned to “1” upon completion of
the write operation. In this case, the read status register mode remains active until the read array command (FF16) is written.
____
The RY/BY pin is “L” during write operation and “H” when the write
operation is completed as is the status register bit 7.
At program end, program results can be checked by reading the status register.
Erase All Blocks Command (2016/2016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “2016” in the second bus cycle that follows, the system starts erase all blocks( erase and erase verify).
Whether the erase all blocks command is terminated can be con____
firmed by reading the status register or the RY/BY signal status .
When the erase all blocks operation starts, the read status register
mode is accessed automatically and the content of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the
same time the erase operation starts and is returned to “1” upon
completion of the erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written.
The RY/BY pin is “L” during erase operation and “H” when the erase
operation is completed as is the status register bit 7.
At erase all blocks end, erase results can be checked by reading the
status register. For details, refer to the section where the status register is detailed.
Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “D016” in the second bus cycle that
follows to the block address of a flash memory block, the system
initiates a block erase (erase and erase verify) operation.
Whether the block erase operation is completed can be confirmed
____
by reading the status register or the RY/BY signal. At the same time
the block erase operation starts, the read status register mode is
automatically entered, so the content of the status register can be
read out. The status register bit 7 (SR7) is set to “0” at the same time
the block erase operation starts and is returned to “1” upon completion of the block erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written.
____
The RY/BY pin is “L” during block erase operation and “H” when the
block erase operation is completed as is the status register bit 7.
After the block erase operation is completed, the status register can
be read out to know the result of the block erase operation. For details, refer to the section where the status register is detailed.
Start
Start
Write 4016
Write
Write 2016
Write address
Write data
Write
Status register
read
SR7=1?
or
RY/BY=1?
NO
SR7=1?
or
RY/BY=1?
NO
YES
NO
Program
error
SR5=0?
YES
NO
Erase error
YES
Program completed
(Read command
FF16 write)
Fig. 53 Page program flowchart
2016:Erase all blocks
D016:Block erase
Status register
read
YES
SR4=0?
2016/D016
Block address
Erase completed
(Read command
FF16 write)
Fig. 54 Block erase flowchart
3850 Group (Spec. H) User’s Manual
1-53
HARDWARE
FUNCTIONAL DESCRIPTION
Status Register
Program Status (SR4)
The status register indicates status such as whether an erase operation or a program ended successfully or in error. It can be read under
the following conditions.
(1) In the read array mode when the read status register command
(7016) is written and the block address is subsequently read.
(2) In the period from when the program write or auto erase starts to
when the read array command (FF16)
The program status reports the operating status of the write operation. If a write error occurs, it is set to “1”. When the program status is
cleared, it is set to “0”.
If “1” is written for any of the SR5, SR4 bits, the program erase all
blocks, block erase, commands are not accepted. Before executing
these commands, execute the clear status register command (5016)
and clear the status register.
Also, any commands are not correct, both SR5 and SR4 are set to
“1”.
The status register is cleared in the following situations.
(1) By writing the clear status register command (5016)
(2) In the deep power down mode
(3) In the power supply off state
Table 15 gives the definition of each status register bit. When power
is turned on or returning from the deep power down mode, the status
register outputs “8016”.
Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. When power is turned on or returning from the deep power
down mode, “1” is set for it. This bit is “0” (busy) during the write or
erase operations and becomes “1” when these operations ends.
Full Status Check
Results from executed erase and program operations can be known
by running a full status check. Figure 55 shows a flowchart of the full
status check and explains how to remedy errors which occur.
____
Ready/Busy (RY/BY) pin
____
The RY/BY pin is an output pin (N-chanel open drain output) which,
like the sequencer status (SR7), indicates the operating status of the
flash memory. It is “L” level during auto program or auto erase operations and becomes to the high impedance state (ready state) when
____
these operations end. The RY/BY pin requires an external pull-up.
Erase Status (SR5)
The erase status reports the operating status of the erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
Table 15 Status register
Each bit of
SRD0 bits
SR7 (D7)
Sequencer status
SR6 (D6)
SR5 (D5)
Reserved
Erase status
SR4 (D4)
SR3 (D3)
Program status
Reserved
SR2 (D2)
SR1 (D1)
Reserved
Reserved
SR0 (D0)
Reserved
1-54
Status name
Definition
“1”
“0”
Ready
-
Busy
-
Ended in error
Ended in error
Ended successfully
Ended successfully
-
-
-
-
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Read status register
SR4=1 and SR5
=1 ?
YES
Command
sequence error
NO
SR5=0?
NO
Block erase error
Execute the clear status register command (5016)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Should a block erase error occur, the block in error
cannot be used.
YES
SR4=0?
NO
Program error
Should a program error occur, the block in error
cannot be used.
YES
End (block erase, program)
Note: When one of SR5 to SR4 is set to “1” , none of the program, all blocks erase, or block erase
is accepted. Execute the clear status register command (5016) before executing these commands.
Fig. 55 Full status check flowchart and remedial procedure for errors
3850 Group (Spec. H) User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
Standard serial I/O mode
The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program,
erase, etc.) the internal flash memory. This I/O is clock synchronized
serial. This modes require a purpose-specific peripheral unit.
The standard serial I/O mode is different from the parallel I/O mode
in that the CPU controls flash memory rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. The standard serial I/O
mode is started by connecting “H” to the P26 (SCLK1) pin and the
P41(INT0) pin and “H” to the CNVSS pin (when VCC = 4.5 V to 5.5 V,
connect to VCC; when VCC = 2.7 V to 4.5 V, supply 4.5 V to 5.5 V to
Vpp from an external source), and releasing the reset operation. (In
the ordinary command mode, set CNVss pin to “L” level.)
This control program is written in the boot ROM area when the product is shipped from Renesas Technology Corp. Accordingly, make
note of the fact that the standard serial I/O mode cannot be used if
the boot ROM area is rewritten in the parallel I/O mode. Figure 56
shows the pin connections for the standard serial I/O mode. Serial
data I/O uses SI/O1 data serially in 8-bit units.
To use standard serial I/O mode. The operation uses the four SI/O1
pins SCLK1, RxD, TxD and SRDY1 (BUSY). The SCLK1 pin is the
transfer clock input pin through which an external transfer clock is
input. The TxD pin is for CMOS output. The SRDY1 (BUSY) pin outputs an “L” level when ready for reception and an “H” level when
reception starts.
In the standard serial I/O mode, only the user ROM area indicated in
Figure 44 can be rewritten. The boot ROM cannot.
In the standard serial I/O mode, a 7-byte ID code is used. When
there is data in the flash memory, commands sent from the peripheral unit (programmer) are not accepted unless the ID code
matches.
Overview of standard serial I/O mode
In standard serial I/O mode, software commands, addresses and
data are input and output between the MCU and peripheral units
(serial programer, etc.) using 4-wire clock-synchronized serial I/O
(SI/O1).
In reception, software commands, addresses and program data are
synchronized with the rise of the transfer clock that is input to the
SCLK1 pin, and are then input to the MCU via the RxD pin. In transmission, the read data and status are synchronized with the fall of
the transfer clock, and output from the TxD pin.
The TxD pin is for CMOS output. Transfer is in 8-bit units with LSB
first.
When busy, such as during transmission, reception, erasing or program execution, the SRDY1 (BUSY) pin is “H” level. Accordingly, always start the next transfer after the SRDY1 (BUSY) pin is “L” level.
Also, data and status registers in memory can be read after inputting
software commands. Status, such as the operating state of the flash
memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained software commands, status registers, etc.
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3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Table 16 Pin functions (Flash memory standard serial I/O mode)
Pin
Name
Description
I/O
VCC,VSS
Power input
CNVSS
CNVSS
I
Connect to VCC when VCC = 4.5 V to 5.5 V.
Connect to Vpp (=4.5 V to 5.5 V) when VCC = 2.7 V to 4.5 V.
RESET
Reset input
I
Reset input pin. While reset is “L” level, a 20 cycle or longer clock
must be input to XIN pin.
XIN
Clock input
I
XOUT
Clock output
O
Connect a ceramic resonator or crystal oscillator between XIN and
XOUT pins. To input an externally generated clock, input it to XIN pin
and open XOUT pin.
AVSS
Analog power supply input
VREF
Reference voltage input
I
Enter the reference voltage for AD from this pin.
P00 to P07
Input port P0
I
Input “H” or “L” level signal or open.
P10 to P17
Input port P1
I
Input “H” or “L” level signal or open.
P20 to P23
Input port P2
I
Input “H” or “L” level signal or open.
P24
RxD input
I
Serial data input pin
P25
TxD output
O
Serial data output pin
P26
SCLK1 input
I
Serial clock input pin
P27
BUSY output
O
BUSY signal output pin
P30 to P34
Input port P3
I
Input “H” or “L” level signal or open.
P40, P42 to P44
Input port P4
I
Input “H” or “L” level signal or open.
P41
Input P41
I
Input “H” level signal, when reset is released.
Apply program/erase protection voltage to Vcc pin and 0 V to Vss pin.
Connect AVSS to VSS .
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HARDWARE
FUNCTIONAL DESCRIPTION
VCC
VSS
P41
BUSY
SCLK1
TxD
RXD
RxD
✽ 2 VPP
RESET
✽1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
M38507F8SP/FP
VCC
VREF
AVSS
P44/INT3/PWM
P43/INT2/SCMP2
P42/INT1
P41/INT0
P40/CNTR1
P27/CNTR0/SRDY1
P26/SCLK1
P25/TxD
P24/RxD
P23
P22
CNVSS
P21/XCIN
P20/XCOUT
RESET
XIN
XOUT
VSS
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P30/AN0
P31/AN1
P32/AN2
P33/AN3
P34/AN4
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04
P05
P06
P07
P10/(LED0)
P11/(LED1)
P12/(LED2)
P13/(LED3)
P14/(LED4)
P15/(LED5)
P16/(LED6)
P17/(LED7)
Mode setup method
Signal
Value
CNVSS
4.5 to 5.5 V
P26/SCLK1
VCC ✽ 3
P41/INT0
VCC ✽ 3
RESET
VSS → VCC
Notes 1: Connect oscillator circuit
2: Connect to Vcc when Vcc = 4.5 V to 5.5 V.
Connect to VPP (=4.5 V to 5.5 V) when Vcc = 2.7 V to 4.5 V.
3: It is necessary to apply Vcc only when reset is released.
Fig. 56 Connection for serial I/O mode
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3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Software Commands
Table 17 lists software commands. In the standard serial I/O mode,
erase operations, programs and reading are controlled by transferring software commands via the RxD pin. Software commands are
Table 17 Software commands (Standard serial I/O mode 1)
1st byte
Control command
transfer 2nd byte 3rd byte
explained here below. Basically, the software commands of the
standard serial I/O mode is as same as that of the parallel I/O mode,
but it is excluded 1 command of block erase, and it is added 3 command of ID check, download function, version data output function.
4th byte 5th byte 6th byte
1
Page read
FF16
Address
(middle)
Address
(high)
Data
output
Data
output
Data
output
Data
output to
259th byte
2
Page program
4116
Address
(middle)
Address
(high)
Data
input
Data
input
Data
input
Data input
to 259th
byte
3
Erase all blocks
A716
D016
4
Read status register
7016
SRD
output
5
Clear status register
5016
6
ID check
7
Download function
8
Version data output function
When ID is
not verified
Not
acceptable
Not
acceptable
Not
acceptable
Acceptable
SRD1
output
Not
acceptable
F516
Address
(low)
FB16
Version
data
output
Address
(middle)
Size
(high)
FA16 Size (low)
Version
data
output
Address
(high)
Checksum
Version
data
output
ID size
ID1
To
Data required
input number
of times
Version Version
data
data
output output
To ID7
Version
data
output to
9th byte
Acceptable
Not
acceptable
Acceptable
Notes 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral
unit to the flash memory microcomputer.
2: SRD refers to status register data. SRD1 refers to status register 1 data.
3: All commands can be accepted when the flash memory is totally blank.
4: Address high (A16 to A23) must be “0016”.
3850 Group (Spec. H) User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
Page Read Command
This command reads the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page read
command as explained here following.
(1) Transfer the “FF16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 (“0016”) with the 2nd
and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes)
specified with addresses A8 to A23 will be output sequentially
from the smallest address first in sync with the fall of the clock.
SCLK1
FF16
RxD
A8 to
A15
A16 to
A23
data255
data0
TxD
SRDY1(BUSY)
Fig. 57 Timing for page read
Read Status Register Command
Clear Status Register Command
This command reads status information. When the “7016” command
code is sent with the 1st byte, the contents of the status register
(SRD) specified with the 2nd byte and the contents of status register
1 (SRD1) specified with the 3rd byte are read.
This command clears the bits (SR4–SR5) which are set when the
status register operation ends in error. When the “5016” command
code is sent with the 1st byte, the aforementioned bits are cleared.
When the clear status register operation ends, the SRDY1 (BUSY)
signal changes from the “H” to the “L” level.
SCLK1
SCLK1
RxD
RxD
TxD
SRD
output
SRDY1(BUSY)
Fig. 58 Timing for reading the status register
1-60
5016
7016
TxD
SRD1
output
SRDY1(BUSY)
Fig. 59 Timing for clearing the status register
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Page Program Command
This command writes the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page program
command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 (“0016”) with the 2nd
and 3rd bytes respectively.
(3) From the 4th byte onward, as write data (D0–D7) for the page (256
bytes) specified with addresses A8 to A23 is input sequentially from
the smallest address first, that page is automatically written.
When reception setup for the next 256 bytes ends, the SRDY1
(BUSY) signal changes from the “H” to the “L” level. The result of the
page program can be known by reading the status register. For
more information, see the section on the status register.
SCLK1
RxD
A8 to
A15
4116
A16 to
A23
data0
data255
TxD
SRDY1(BUSY)
Fig. 60 Timing for the page program
Erase All Blocks Command
This command erases the content of all blocks. Execute the erase all
blocks command as explained here following.
(1) Transfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D016” with the 2nd byte. With
the verify command code, the erase operation will start and continue for all blocks in the flash memory.
When block erasing ends, the SRDY1 (BUSY) signal changes from
the “H” to the “L” level . The result of the erase operation can be
known by reading the status register.
SCLK1
RxD
A716
D016
TxD
SRDY1(BUSY)
Fig. 61 Timing for erasing all blocks
3850 Group (Spec. H) User’s Manual
1-61
HARDWARE
FUNCTIONAL DESCRIPTION
Download Command
(4) The program to execute is sent with the 5th byte onward.
This command downloads a program to the RAM for execution. Execute the download command as explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is
added to all data sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches, the
downloaded program is executed. The size of the program will vary
according to the internal RAM.
SCLK1
RxD
FA16
Data size Data size
(low)
(high)
Check
sum
Program
data
Program
data
TxD
SRDY1(BUSY)
Fig. 62 Timing for download
(1) Transfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte onward.
This data is composed of 8 ASCII code characters.
Version Information Output Command
This command outputs the version information of the control program stored in the boot area. Execute the version information output
command as explained here following.
SCLK1
RxD
FB16
TxD
‘V’
‘E’
‘R’
SRDY1(BUSY)
Fig. 63 Timing for version information output
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3850 Group (Spec. H) User’s Manual
‘X’
HARDWARE
FUNCTIONAL DESCRIPTION
ID Check
the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively.
(3) Transfer the number of data sets of the ID code with the 5th byte.
(4) The ID code is sent with the 6th byte onward, starting with the 1st
byte of the code.
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 (“0016”) of
SCLK1
RxD
F516
D416
FF16
0016
ID size
ID1
ID7
TxD
SRDY1(BUSY)
Fig. 64 Timing for the ID check
ID Code
sent from the peripheral units is not accepted. An ID code contains 8
bits of data. Area is, from the 1st byte, addresses FFD4 16 to
FFDA16. Write a program into the flash memory, which already has
the ID code set for these addresses.
When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command
Address
FFD416
ID1
FFD516
ID2
FFD616
ID3
FFD716
ID4
FFD816
ID5
FFD916
ID6
FFDA16
ID7
FFDB16
ROM cord Protect control
Interrupt vector area
Fig. 65 ID code storage addresses
3850 Group (Spec. H) User’s Manual
1-63
HARDWARE
FUNCTIONAL DESCRIPTION
Status Register (SRD)
The sequencer status indicates the operating status of the device.
This status bit is set to “0” (busy) during write or erase operation and
is set to “1” upon completion of these operations.
The status register indicates operating status of the flash memory
and status such as whether an erase operation or a program ended
successfully or in error. It can be read by writing the read status
register command (7016). Also, the status register is cleared by writing the clear status register command (5016).
Table 18 gives the definition of each status register bit. After clearing
the reset, the status register outputs “8016”.
The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”.
Sequencer status (SR7)
Program Status (SR4)
After power-on and recover from deep power down mode, the sequencer status is set to “1”(ready).
The program status reports the operating status of the auto write
operation. If a write error occurs, it is set to “1”. When the program
status is cleared, it is set to “0”.
Erase Status (SR5)
Table 18 Status register (SRD)
Definition
SRD0 bits
Status name
“1”
SR7 (bit7)
Sequencer status
Ready
Busy
SR6 (bit6)
SR5 (bit5)
Reserved
Erase status
Terminated in error
Terminated normally
SR4 (bit4)
SR3 (bit3)
Program status
Reserved
Terminated in error
-
Terminated normally
-
SR2 (bit2)
SR1 (bit1)
Reserved
Reserved
-
-
SR0 (bit0)
Reserved
-
-
“0”
Status Register 1 (SRD1)
Check Sum Consistency Bit (SR12)
Status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can
be read after the SRD by writing the read status register command
(7016). Also, status register 1 is cleared by writing the clear status
register command (5016).
Table 19 gives the definition of each status register bit. “0016” is output when power is turned on and the flag status is maintained even
after the reset.
This flag indicates whether the check sum matches or not when a
program is downloaded for execution using the download function.
Boot Update Completed Bit (SR15)
This flag indicates whether the control program was downloaded to
the RAM or not, using the download function.
ID Check Completed Bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check.
Data Reception Time Out (SR9)
This flag indicates when a time out error is generated during data
reception. If this flag is attached during data reception, the received
data is discarded and the microcomputer returns to the command
wait state.
Table 19 Status register 1 (SRD1)
SRD1 bits
SR15 (bit7)
SR14 (bit6)
Boot update completed bit
Reserved
SR13 (bit5)
SR12 (bit4)
Reserved
Checksum match bit
SR11 (bit3)
SR10 (bit2)
ID check completed bits
SR9 (bit1)
SR8 (bit0)
1-64
Definition
Status name
Data reception time out
Reserved
“1”
“0”
Update completed
-
Not Update
-
Match
00
01
Not verified
Verification mismatch
10
11
Reserved
Verified
Time out
-
3850 Group (Spec. H) User’s Manual
Mismatch
Normal operation
-
HARDWARE
FUNCTIONAL DESCRIPTION
Full Status Check
Results from executed erase and program operations can be known
by running a full status check. Figure 66 shows a flowchart of the full
status check and explains how to remedy errors which occur.
Read status register
SR4=1 and SR5
=1 ?
YES
Execute the clear status register command (5016)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Command
sequence error
NO
SR5=0?
NO
Should a block erase error occur, the block in error
cannot be used.
Erase error
YES
SR4=0?
NO
Should a program error occur, the block in error
cannot be used.
Program error
YES
End (block erase, program)
Note: When one of SR5 to SR4 is set to “1”, none of the program, erase all blocks
commands is accepted. Execute the clear status register command (5016) before
executing these commands.
Fig. 66 Full status check flowchart and remedial procedure for errors
Example Circuit Application for The Standard
Serial I/O Mode
Figure 67 shows a circuit application for the standard serial I/O
mode. Control pins will vary according to programmer, therefore
see the peripheral unit manual for more information.
P41
Clock input
SCLK1
BUSY output
SRDY1 (BUSY)
Data input
RXD
Data output
TXD
VPP power
source input
CNVss
M38507F8
Notes 1: Control pins and external circuitry will vary according to peripheral unit. For more
information, see the peripheral unit manual.
2: In this example, the Vpp power supply is supplied from an external source (writer). To use
the user’s power source, connect to 4.5 V to 5.5 V.
3: It is necessary to apply Vcc to SCLK pin only when reset is released.
Fig. 67 Example circuit application for the standard serial I/O mode
3850 Group (Spec. H) User’s Manual
1-65
HARDWARE
FUNCTIONAL DESCRIPTION
Flash memory Electrical characteristics
Table 20 Absolute maximum ratings
Symbol
VCC
VI
VI
VI
VI
VO
VO
Pd
Topr
Tstg
Parameter
Power source voltage
Input voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
VREF
Input voltage P22, P23
Input voltage RESET, XIN
Input voltage CNVSS
Output voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
XOUT
Output voltage P22, P23
Power dissipation
Operating temperature
Storage temperature
Conditions
All voltages are based on VSS.
Output transistors are cut off.
Ta = 25 °C
Ratings
–0.3 to 6.5
Unit
V
–0.3 to VCC +0.3
V
–0.3 to 5.8
–0.3 to VCC +0.3
–0.3 to VCC +0.3
V
V
V
–0.3 to VCC +0.3
V
–0.3 to 5.8
1000 (Note)
25±5
–40 to 125
V
mW
°C
°C
Note: The rating becomes 300 mW at the 42P2R-A/E package.
Table 21 Flash memory mode Electrical characteristics
(Ta = 25oC, VCC = 4.5 to 5.5V unless otherwise noted)
Limits
Symbol
IPP1
IPP2
IPP3
VIL
VIH
VPP
VCC
Parameter
Conditions
VPP power source current (read)
VPP power source current (program)
VPP power source current (erase)
“L” input voltage (Note)
“H” input voltage (Note)
VPP power source voltage
VCC power source voltage
Microcomputer mode operation at
VCC = 2.7 to 5.5V
Microcomputer mode operation at
VCC = 2.7 to 3.6V
3850 Group (Spec. H) User’s Manual
Typ.
Max.
Unit
0
2.0
4.5
100
60
30
0.8
VCC
5.5
µA
mA
mA
V
V
V
4.5
5.5
V
3.0
3.6
V
VPP = VCC
VPP = VCC
VPP = VCC
Note: Input pins for parallel I/O mode.
1-66
Min.
HARDWARE
FUNCTIONAL DESCRIPTION
AC Electrical characteristics
(Ta = 25oC, VCC = 4.5 to 5.5V unless otherwise noted)
Table 22 Read-only mode
Symbol
tRC
ta (AD)
ta (CE)
ta (OE)
tCLZ
tDF(CE)
tOLZ
tDF(OE)
tPHZ
tOH
tOEH
tPS
Parameter
Read cycle time
Address access time
_____
CE access time
_____
OE access time
_____
Output enable time (after CE)
_____
Output floating time (after CE)
_____
Output enable time (after OE)
_____
Output floating time (after OE)
_____
Output floating time (after PR)
_____ _____
Output valid time (after CE, OE, address)
Write recovery time (before read)
_____
RP recovery time
Limits
Min.
200
Typ.
Max.
100
100
80
0
25
0
25
300
0
200
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Note : Timing measurement condition is showed in Figure 68.
_____
Table 23 Read / Write mode (WE control)
Symbol
tWC
tAS
tAH
tDS
tDH
tCS
tCH
tWP
tWPH
tDAP
tDAE
tWHRL
tPS
Parameter
Write cycle time
Address set up time
Address hold time
Data set up time
Data hold time
_____
CE set up time
_____
CE hold time
_____
WE pulse width
“H” write pulse width
Program time
Erase all blocks time
_____
RY/BY delay time
_____
RP recovery time
Limits
Min.
200
100
25
100
25
0
0
100
50
Typ.
Max.
25
1.5
200
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
ns
µs
Note : The read timing parameter in the command write operation mode is same as that of the read-only mode.
Typical value is at VCC = 5.0 V, Ta = 25 °C condition.
3850 Group (Spec. H) User’s Manual
1-67
HARDWARE
FUNCTIONAL DESCRIPTION
Flash memory mode Electrical characteristics
(Ta = 25oC, VCC = 4.5 to 5.5V unless otherwise noted)
_____
Table 24 Read / Write mode (CE control)
tWC
tAS
tAH
tDS
tDH
tWS
tWH
tCEP
tCEPH
tDAP
tDAE
tEHRL
tPS
Limits
Parameter
Symbol
Min.
200
100
25
100
25
0
0
100
50
Write cycle time
Address set up time
Address hold time
Data set up time
Data hold time
______
WE set up time
WE hold time
_____
CE pulse width
_____
“H” CE pulse width
Program time
Erase all blocks time
______
Typ.
Unit
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
ns
µs
25
1.5
_____
200
RY/BY delay time
_____
RP recovery time
10
Note : The read timing parameter in the command write operation mode is same as that of the read-only mode.
Typical value is at VCC = 5.0 V, Ta = 25 °C condition.
Table 25 Erase and program operation
Parameter
Erase all blocks time
Block erase time
Program time (1byte)
Min.
Typ.
1.5
1.0
25
Max.
Unit
s
s
µs
Table 26 VCC power up / power down timing
Symbol
Parameter
RP = VIH set up time
(after rised VCC = VCC min.)
_____
tVCS
Min.
10
Typ.
Max.
Unit
µs
Note : Miserase or miswrite may happen, in case of noise pulse due to the power supply on or off is input to the control pins. Therefore disableing the
write mode is need for prevent from memory data break at the power supply on or off. 10µs (min.) waiting_____
time is need to initiate read or write operation after VCC rises to VCC min. at power supply on. The memory data is protected owing to keep the
RP pin VIL level at power supply off. The
_____
_____
RP pin must be kept VIL level for 10µs (min.)
after V CC rises to VCC min. at the _____
power supply on. The RP pin must be kept VIL level until the VCC
_____
falls to the GND level at power supply off. RP pin doesn't have latch mode, so RP pin must be kept VIH level during read, erase and program operation.
1-68
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Inhibit read / write
Inhibit read / write
VCC
Inhibit read / write
5.0V
GND
tVCS
RP
VIH
VIL
CE
VIH
VIL
WE
tPS
tPS
VIH
VIL
Fig. 68 VCC power up / power down timing
3850 Group (Spec. H) User’s Manual
1-69
HARDWARE
FUNCTIONAL DESCRIPTION
VIH
Address
CE
Valid address
VIL
tRC
VIH
ta (AD)
VIL
OE
VIH
VIL
WE
tDF(CE)
ta (CE)
tOEH
tDF(OE)
VIH
ta (OE)
VIL
tOH
tOLZ
DATA
VOH
HIGH-Z
VOL
RP
tCLZ
HIGH-Z
Valid output
tPS
tPHZ
VIH
VIL
Fig. 69 AC wave for read operation
1.3V
AC electrical characteristics test condition
1N914
Input voltage : VIL = 0V, VIH = 5.0V
Input signal rising time, falling time : 10ns
3.3kΩ
Timing measurement
Reference voltage : 1.5V
measurement pin
CL =100pF
Load circuit : 1TTL gate+
CL(100pF )
Fig. 70 AC electrical characteristics test condition for read operation
1-70
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Program
VIH
Valid Address
Address
VIL
tWC
Read status
register
Write read array
command
Valid Address
tAS
ta(CE)
tAH
VIH
CE
VIL
OE
tCS
tCH
tWP
VIH
VIL
WE
ta(OE)
tOEH
tWPH
VIH
VIL
DATA
tDS
VIH
40H
VIL
DIN
SRD
tDH
VoH
RY/BY
tWHRL
VoL
tPS
VIH
RP
FFH
tDAP
VIL
_____
Fig. 71 AC wave for program operation (WE control)
Program
VIH
Address
tWC
tAS
Write read array
command
Valid Address
Valid Address
VIL
Read status
register
tAH
ta(CE)
VIH
CE
VIL
OE
ta(OE)
VIH
VIL
tCEP
tWH
tWS
tOEH
VIH
WE
VIL
tDS
VIH
DATA
40H
DIN
SRD
FFH
VIL
tDH
VoH
RY/BY
tEHRL
VoL
VIH
RP
tPS
tDAP
VIL
_____
Fig. 72 AC wave for program operation (CE control)
3850 Group (Spec. H) User’s Manual
1-71
HARDWARE
FUNCTIONAL DESCRIPTION
Read status
register
Erase
VIH
Address
Valid Address
Valid Address
VIL
tAS
tWC
tAH
ta(CE)
VIH
CE
VIL
tCS
tCH
ta(OE)
VIH
OE
VIL
tOEH
tDAE
tWPH
VIH
WE
VIL
tWP
20H
VIL
tDH
tDS
VIH
DATA
Write read array
command
SRD
D0H
FFH
tWHRL
VOH
RY/BY
VOL
tPS
RP
VIH
VIL
_____
Fig. 73 AC wave for erase operation (WE control)
Read status
register
Erase
VIH
Address
Valid Address
Valid Address
VIL
tWC
CE
Write read array
command
tAH
tAS
ta(CE)
VIH
VIL
OE
tCEPH
tCEP
VIH
ta(OE)
tOEH
VIL
tWS
WE
tDAE
tWH
VIH
VIL
DATA
20H
VIL
RY/BY
tDH
tDS
VIH
SRD
D0H
tEHRL
VOH
VOL
tPS
RP
VIH
VIL
_____
Fig. 74 AC wave for erase operation (CE control)
1-72
3850 Group (Spec. H) User’s Manual
FFH
HARDWARE
NOTES ON PROGRAMMING/NOTES ON USAGE
NOTES ON PROGRAMMING
Processor Status Register
A-D Converter
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) in the middle/high-speed mode is
at least on 500 kHz during an A-D conversion.
Do not execute the STP instruction during an A-D conversion.
Instruction Execution Time
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt
request register, execute at least one instruction before performing a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direction registers.
The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency in
high-speed mode.
NOTES ON USAGE
Differences between 3850 group (standard)
and 3850 group (spec. H)
(1) The absolute maximum ratings of 3850 group (spec. H) is
smaller than that of 3850 group (standard).
•Power source voltage Vcc = –0.3 to 6.5 V
•CNVss input voltage VI = –0.3 to Vcc +0.3 V
(2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may
be some differences between 3850 group (standard) and 3850
group (spec. H).
(3) Do not write any data to the reserved area and the reserved
bit. (Do not change the contents after rest.)
(4) Fix bit 3 of the CPU mode register to “1”.
(5) Be sure to perform the termination of unused pins.
Handling of Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (V SS pin) and between power
source pin (VCC pin) and analog power source input pin (AVSS
pin). Besides, connect the capacitor to as close as possible. For
bypass capacitor which should not be located too far from the pins
to be connected, a ceramic capacitor of 0.01 µF–0.1µF is recommended.
EPROM Version/One Time PROM Version/
Flash Memory Version
Serial I/O
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY1 signal, set the transmit
enable bit, the receive enable bit, and the SRDY1 output enable bit
to “1”.
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed.
SOUT2 pin for serial I/O2 goes to high impedance after transmission is completed.
When an external clock is used as synchronous clock in serial I/
O1 or serial I/O2, write transmission data to the transmit buffer
register or serial I/O2 register while the transfer clock is “H”.
The CNVss pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss
pin and Vss pin or Vcc pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational interference even if it is connected to Vss pin or Vcc pin via a
resistor.
3850 Group (Spec. H) User’s Manual
1-73
HARDWARE
DATA REQUIRED FOR MASK ORDERS/DATA REQUIRED FOR One Time PROM PROGRAMMING ORDERS/ROM PROGRAMMING METHOD
DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
The following are necessary when ordering a mask ROM production:
1. Mask ROM Order Confirmation Form✽
2. Mark Specification Form✽
3. Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk.
The built-in PROM of the blank One Time PROM version and buitin EPROM version can be read or programmed with a
general-purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
DATA REQUIRED FOR One Time PROM
PROGRAMMING ORDERS
The following are necessary when ordering a PROM programming
service:
1. ROM Programming Confirmation Form✽
2. Mark Specification Form✽ (only special mark with customer’s
trade mark logo)
3. Data to be programmed to PROM, in EPROM form (three identical copies) or one floppy disk.
Table 27 Programming adapter
Name of Programming Adapter
Package
PCA4738S-42A
42P4B, 42S1B
PCA4738F-42A
42P2R-A/E
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in
Figure 75 is recommended to verify programming.
✽For the mask ROM confirmation, the ROM programming confirmation form, and the mark specifications, refer to the “Renesas
Technology Corp.” Homepage (http://www.renesas.com/en/rom).
Programming with PROM
programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
Caution : The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 75 Programming and testing of One Time PROM version
1-74
3850 Group (Spec. H) User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT
A-D Converter
By repeating the above operations up to the lowest-order bit of the
A-D conversion register, an analog value converts into a digital
value.
A-D conversion completes at 61 clock cycles (15.25 µs at f(XIN) = 8
MHz) after it is started, and the result of the conversion is stored
into the A-D conversion register.
Concurrently with the completion of A-D conversion, A-D conversion
interrupt request occurs, so that the AD conversion interrupt request
bit is set to “1”.
A-D conversion is started by setting AD conversion completion bit to
“0”. During A-D conversion, internal operations are performed as
follows.
1. After the start of A-D conversion, A-D conversion register goes to
“0016”.
2. The highest-order bit of A-D conversion register is set to “1”, and
the comparison voltage Vref is input to the comparator. Then, Vref
is compared with analog input voltage VIN.
3. As a result of comparison, when Vref < VIN, the highest-order bit
of A-D conversion register becomes “1”. When V ref > V IN, the
highest-order bit becomes “0”.
Table 28 Relative formula for a reference voltage VREF of A-D
converter and Vref
When n = 0
Vref = 0
VREF
✕n
1024
n: Value of A-D converter (decimal numeral)
When n = 1 to 1023
Vref =
Table 29 Change of A-D conversion register during A-D conversion
Change of A-D conversion register
Value of comparison voltage (Vref)
At start of conversion
0
0
0
0
0
0
0
0
0
0
First comparison
1
0
0
0
0
0
0
0
0
0
Second comparison
✽1
1
0
0
0
0
0
0
0
0
Third comparison
✽1 ✽ 2
1
0
0
0
0
0
0
0
After completion of tenth
comparison
A result of A-D conversion
✽1 ✽2
✽3 ✽ 4 ✽5 ✽ 6
✽7 ✽8 ✽9 ✽10
0
VREF
2
VREF
±
2
VREF
4
VREF
±
2
VREF
4
±
VREF
8
VREF
±
2
VREF
4
±
••••
±
VREF
1024
✽1–✽10: A result of the first comparison to the tenth comparison
3850 Group (Spec. H) User’s Manual
1-75
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 76 shows the A-D conversion equivalent circuit, and Figure
77 shows the A-D conversion timing chart.
VCC
VSS
VCC AVSS
About 2 kΩ
VIN
AN0
Sampling
clock
AN1
C
AN2
Chopper
amplifier
AN3
AN4
A-D conversion register (high-order)
b4
b2 b1 b0
A-D control register
A-D conversion register
(low-order)
Vref
VREF
Built-in
D-A converter
Reference
clock
AD conversion interrupt request
AV SS
Fig. 76 A-D conversion equivalent circuit
φ
Write signal for A-D
control register
61 cycles
AD conversion
completion bit
Sampling clock
Fig. 77 A-D conversion timing chart
1-76
3850 Group (Spec. H) User’s Manual
CHAPTER 2
APPLICATION
2.1 I/O port
2.2 Interrupt
2.3 Timer
2.4 Serial I/O
2.5 PWM
2.6 A-D converter
2.7 Watchdog timer
2.8 Reset
2.9 Clock generating circuit
2.10 Standby function
2.11 Flash memory mode
APPLICATION
2.1 I/O port
2.1 I/O port
This paragraph describes the setting method of I/O port relevant registers, notes etc.
2.1.1 Memory map
Address
000016
Port P0 (P0)
000116
Port P0 direction register (P0D)
000216
Port P1 (P1)
000316
Port P1 direction register (P1D)
000416
Port P2 (P2)
000516
Port P2 direction register (P2D)
000616
Port P3 (P3)
000716
Port P3 direction register (P3D)
000816
Port P4 (P4)
000916
Port P4 direction register (P4D)
Fig. 2.1.1 Memory map of I/O port relevant registers
2.1.2 Relevant registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (i = 0, 1, 2, 3, 4)
(Pi: addresses 0016, 0216, 0416, 0616, 0816)
b
Name
Functions
At reset R W
0 Port Pi0
0
●In output mode
Write •••••••• Port latch
1 Port Pi1
0
Read •••••••• Port latch
2 Port Pi2
0
●In input mode
3 Port Pi3
0
Write •••••••• Port latch
4 Port Pi4
0
Read •••••••• Value of pin
5 Port Pi5
0
6 Port Pi6
0
7 Port Pi7
0
Note: When reading bit 5, 6 or 7 of ports 3 and 4, the contents are undefined.
Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4)
2-2
3850 Group (Spec. H) User’s Manual
APPLICATION
2.1 I/O port
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (i = 0, 1, 2, 3, 4)
(PiD: addresses 0116, 0316, 0516, 0716, 0916)
b
Name
0 Port Pi direction
register
1
2
3
4
5
6
7
Functions
0 : Port Pi0 input mode
1 : Port Pi0 output mode
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4)
2.1.3 Terminate unused pins
Table 2.1.1 Termination of unused pins
Termination
Pins/Ports name
P0, P1, P2, P3, P4
• Set to the input mode and connect each to VCC or VSS through a resistor of 1 kΩ
to 10 kΩ.
• Set to the output mode and open at “L” or “H” output state.
VREF
AVSS
XOUT
Connect to Vss (GND).
Connect to Vss (GND).
Open (only when using external clock)
3850 Group (Spec. H) User’s Manual
2-3
APPLICATION
2.1 I/O port
2.1.4 Notes on I/O port
(1) Notes in standby state
In standby state✽1, do not make input levels of an I/O port “undefined”, especially for I/O ports of the
N-channel open-drain. When setting the N-channel open-drain port as an output, do not make input
levels of an I/O port “undefined”, too.
Pull-up (connect the port to V CC ) or pull-down (connect the port to V SS ) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
● Reason
When setting as an input port with its direction register, the transistor becomes the OFF state,
which causes the ports to be the high-impedance state.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the
state that input levels of an I/O port are “undefined”. This may cause power source current.
In I/O ports of N-channel open-drain, when the contents of the port latch are “1”, even if it is set
as an output port with its direction register, it becomes the same phenomenon as the case of an
input port.
✽1 standby state: stop mode by executing STP instruction
wait mode by executing WIT instruction
(2) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction ✽2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
•As for bit which is set for input port:
The pin state is read in the CPU, and is written to this bit after bit managing.
•As for bit which is set for output port:
The bit value is read in the CPU, and is written to this bit after bit managing.
Note the following:
•Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
•As for a bit of which is set for an input port, its value may be changed even when not specified
with a bit managing instruction in case where the pin state differs from its port latch contents.
✽2 Bit managing instructions: SEB and CLB instructions
2-4
3850 Group (Spec. H) User’s Manual
APPLICATION
2.1 I/O port
2.1.5 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to V CC or VSS through each resistor of 1 kΩ to 10 kΩ.
A for pins whose potential affects to operation modes such as pins CNVSS, INT or others, select
the VCC pin or the VSS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to V CC or VSS through each resistor of
1 kΩ to 10 kΩ.
Set the I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
➃ The AVss pin when not using the A-D converter :
• When not using the A-D converter, handle a power source pin for the A-D converter, AVss pin
as follows:
AVss: Connect to the Vss pin.
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to V CC or V SS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or V SS ).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to V CC or V SS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
3850 Group (Spec. H) User’s Manual
2-5
APPLICATION
2.2 Interrupt
2.2 Interrupt
This paragraph explains the registers setting method and the notes relevant to the interrupt.
2.2.1 Memory map
003A16
Interrupt edge selection register (INTEDGE)
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.2.1 Memory map of registers relevant to interrupt
2-6
3850 Group (Spec. H) User’s Manual
APPLICATION
2.2 Interrupt
2.2.2 Relevant registers
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register
(INTEDGE: address 3A16)
b
Name
0 INT0 active edge
selection bit
1 INT1 active edge
selection bit
2 INT2 active edge
selection bit
3 INT3 active edge
selection bit
4 SeriaI/O2/INT3
interrupt source bit
Functions
0: Falling edge active
1: Rising edge active
0: Falling edge active
1: Rising edge active
0: Falling edge active
1: Rising edge active
0: Falling edge active
1: Rising edge active
0: INT3 interrupt selected
1: Serial I/O2 interrupt
selected
5 Nothing is arranged for this bit. This is a write
6 disabled bit. When this bit is read out, the
7 contents are “0”.
At reset R W
0
0
0
0
0
0
0
0
0
Fig. 2.2.2 Structure of Interrupt edge selection register
3850 Group (Spec. H) User’s Manual
2-7
APPLICATION
2.2 Interrupt
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
Name
Functions
At reset R W
0
✽
1 When writing to this bit, set “0” to this bit.
0
✽
2 INT1 interrupt
request bit
3 INT2 interrupt
request bit
4 INT3/Serial I/O2
interrupt request bit
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0 INT0 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
5 When writing to this bit, set “0” to this bit.
0 : No interrupt request issued
6 Timer X interrupt
1 : Interrupt request issued
request bit
0 : No interrupt request issued
7 Timer Y interrupt
request bit
1 : Interrupt request issued
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.2.3 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
Name
0 Timer 1 interrupt
request bit
1 Timer 2 interrupt
request bit
2 Serial I/O1 receive
interrupt request bit
3 Serial I/O1 transmit
interrupt request bit
4 CNTR0 interrupt
request bit
5 CNTR1 interrupt
request bit
6 A-D converter
interrupt request bit
Functions
At reset R W
0 : No interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.2.4 Structure of Interrupt request register 2
2-8
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
1 : Interrupt request issued
3850 Group (Spec. H) User’s Manual
0
APPLICATION
2.2 Interrupt
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Interrupt control register 1
(ICON1 : address 3E16)
b
Name
Functions
0 INT0 interrupt
enable bit
1 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
2 INT1 interrupt
enable bit
3 INT2 interrupt
enable bit
4 INT3/Serial I/O2
interrupt enable bit
5 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
6 Timer X interrupt
enable bit
7 Timer Y interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.2.5 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
0 Timer 1 interrupt
enable bit
1 Timer 2 interrupt
enable bit
2 Serial I/O1 receive
interrupt enable bit
3 Serial I/O1 transmit
interrupt enable bit
4 CNTR0 interrupt
enable bit
CNTR
1 interrupt
5
enable bit
6 A-D converter
interrupt enable bit
7 Fix this bit to “0”.
Functions
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.2.6 Structure of Interrupt control register 2
3850 Group (Spec. H) User’s Manual
2-9
APPLICATION
2.2 Interrupt
2.2.3 Interrupt source
The 3850 group permits interrupts of 15 sources. These are vector interrupts with a fixed priority system.
Accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority
interrupt is accepted first. This priority is determined by hardware, but a variety of priority processing can
be performed by software, using an interrupt enable bit and an interrupt disable flag.
For interrupt sources, vector addresses and interrupt priority, refer to Table 2.2.1.
Table 2.2.1 Interrupt sources, vector addresses and priority of 3850 group
Interrupt Source
Priority
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
FFFB16
FFFA16
Reset (Note 2)
INT0
1
2
Reserved
INT1
3
4
FFF916
FFF716
FFF816
FFF616
INT2
5
FFF516
FFF416
INT3
6
FFF316
FFF216
Reserved
Timer X
Timer Y
Timer 1
Timer 2
Serial I/O1
received
Serial I/O1
transmit
7
8
9
10
11
12
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
13
FFE516
FFE416
CNTR0
14
FFE316
FFE216
CNTR1
15
FFE116
FFE016
A-D converter
BRK instruction
16
17
FFDF16
FFDD16
FFDE16
FFDC16
Serial I/O2
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
Reserved
At detection of either rising or
falling edge of INT1 input
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At completion of serial I/O2 data
transfer
Reserved
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At completion of serial I/O1 data
reception
At completion of serial I/O1
transfer shift or when transmission buffer is empty
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At completion of A-D conversion
At BRK instruction execution
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
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3850 Group (Spec. H) User’s Manual
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Switch by Serial I/O2/INT3 interrupt
source bit
STP release timer underflow
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Non-maskable software interrupt
APPLICATION
2.2 Interrupt
2.2.4 Interrupt operation
When an interrupt request is accepted, the contents of the following registers just before acceptance of the
interrupt requests are automatically pushed onto the stack area in the order of ➀, ➁ and ➂.
➀High-order contents of program counter (PC H)
➁Low-order contents of program counter (PC L)
➂Contents of processor status register (PS)
After the contents of the above registers are pushed onto the stack area, the accepted interrupt vector
address enters the program counter and consequently the interrupt processing routine is executed.
When the RTI instruction is executed at the end of the interrupt processing routine, the contents of the
above registers pushed onto the stack area are restored to the respective registers in the order of ➂, ➁
and ➀; and the microcomputer resumes the processing executed just before acceptance of the interrupts.
Figure 2.2.7 shows an interrupt operation diagram.
Executing routine
·······
Interrupt occurs
(Accepting interrupt request)
Suspended
operation
Resume processing
Contents of program counter (high-order) are pushed onto stack
Contents of program counter (low-order) are pushed onto stack
Contents of processor status register are pushed onto stack
·······
Interrupt
processing
routine
RTI instruction
Contents of processor status register are popped from stack
Contents of program counter (low-order) are popped from stack
Contents of program counter (high-order) are popped from stack
: Operation commanded by software
: Internal operation performed automatically
Fig. 2.2.7 Interrupt operation diagram
3850 Group (Spec. H) User’s Manual
2-11
APPLICATION
2.2 Interrupt
(1) Processing upon acceptance of interrupt request
Upon acceptance of an interrupt request, the following operations are automatically performed.
➀The processing being executed is stopped.
➁The contents of the program counter and the processor status register are pushed onto the stack
area. Figure 2.2.8 shows the changes of the stack pointer and the program counter upon acceptance
of an interrupt request.
➂Concurrently with the push operation, the jump destination address (the beginning address of the
interrupt processing routine) of the occurring interrupt stored in the vector address is set in the
program counter, then the interrupt processing routine is executed.
➃After the interrupt processing routine is started, the corresponding interrupt request bit is automatically
cleared to “0”. The interrupt disable flag is set to “1” so that multiple interrupts are disabled.
Accordingly, for executing the interrupt processing routine, it is necessary to set the jump destination
address in the vector area corresponding to each interrupt.
Stack area
Program counter
PCL Program counter (low-order)
PCH Program counter (high-order)
Interrupt disable flag = “0”
Stack pointer
S
(S)
(S)
Interrupt
request is
accepted
Program counter
PCL
Vector address
PCH
(from Interrupt vector area)
Stack area
Interrupt disable flag = “1”
(s) – 3
Processor status register
Stack pointer
S
Program counter (low-order)
(S) – 3
(S) Program counter (high-order)
Fig. 2.2.8 Changes of stack pointer and program counter upon acceptance of interrupt request
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3850 Group (Spec. H) User’s Manual
APPLICATION
2.2 Interrupt
(2) Timing after acceptance of interrupt request
The interrupt processing routine begins with the machine cycle following the completion of the
instruction that is currently being executed.
Figure 2.2.9 shows the time up to execution of interrupt processing routine and Figure 2.2.10 shows
the timing chart after acceptance of interrupt request.
Interrupt request generated
Start of interrupt processing
Waiting time for Stack push and
post-processing Vector fetch
of pipeline
Main routine
Interrupt processing routine
✽
0 to 16 cycles
2 cycles
5 cycles
7 to 23 cycles
(When f(XIN) = 8 MHz, 1.75 µs to 5.75 µs)
✽ When executing DIV instruction
Fig. 2.2.9 Time up to execution of interrupt processing routine
Waiting time for pipeline
post-processing
Push onto stack
Vector fetch
Interrupt operation starts
φ
SYNC
RD
WR
Address bus
Data bus
PC
S, SPS
Not used
S-1, SPS S-2, SPS
PCH
PCL
PS
BL
BH
AL
AL, AH
AH
SYNC : CPU operation code fetch cycle
(This is an internal signal that cannot be observed from the external unit.)
BL, BH : Vector address of each interrupt
AL, AH : Jump destination address of each interrupt
SPS : “0016” or “0116”
Fig. 2.2.10 Timing chart after acceptance of interrupt request
3850 Group (Spec. H) User’s Manual
2-13
APPLICATION
2.2 Interrupt
2.2.5 Interrupt control
The acceptance of all interrupts, excluding the BRK instruction interrupt, can be controlled by the interrupt
request bit, interrupt enable bit, and an interrupt disable flag, as described in detail below. Figure 2.2.11
shows an interrupt control diagram.
Interrupt request bit
Interrupt enable bit
Interrupt request
Interrupt disable flag
BRK instruction
Reset
Fig. 2.2.11 Interrupt control diagram
The interrupt request bit, interrupt enable bit and interrupt disable flag function independently and do not
affect each other. An interrupt is accepted when all the following conditions are satisfied.
●Interrupt request bit .......... “1”
●Interrupt enable bit ........... “1”
●Interrupt disable flag ........ “0”
Though the interrupt priority is determined by hardware, a variety of priority processing can be performed
by software using the above bits and flag. Table 2.2.2 shows a list of interrupt control bits according to the
interrupt source.
(1) Interrupt request bits
The interrupt request bits are allocated to the interrupt request register 1 (address 3C16) and interrupt
request register 2 (address 3D 16).
The occurrence of an interrupt request causes the corresponding interrupt request bit to be set to
“1”. The interrupt request bit is held in the “1” state until the interrupt is accepted. When the interrupt
is accepted, this bit is automatically cleared to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to “1”, by software.
(2) Interrupt enable bits
The interrupt enable bits are allocated to the interrupt control register 1 (address 003E 16) and the
interrupt control register 2 (address 3F 16).
The interrupt enable bits control the acceptance of the corresponding interrupt request.
When an interrupt enable bit is “0”, the corresponding interrupt request is disabled. If an interrupt
request occurs when this bit is “0”, the corresponding interrupt request bit is set to “1” but the
interrupt is not accepted. In this case, unless the interrupt request bit is set to “0” by software, the
interrupt request bit remains in the “1” state.
When an interrupt enable bit is “1”, the corresponding interrupt is enabled. If an interrupt request
occurs when this bit is “1”, the interrupt is accepted (when interrupt disable flag = “0”).
Each interrupt enable bit can be set to “0” or “1” by software.
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3850 Group (Spec. H) User’s Manual
APPLICATION
2.2 Interrupt
(3) Interrupt disable flag
The interrupt disable flag is allocated to bit 2 of the processor status register. The interrupt disable
flag controls the acceptance of interrupt request except BRK instruction.
When this flag is “1”, the acceptance of interrupt requests is disabled. When the flag is “0”, the
acceptance of interrupt requests is enabled. This flag is set to “1” with the SEI instruction and is set
to “0” with the CLI instruction.
When a main routine branches to an interrupt processing routine, this flag is automatically set to “1”,
so that multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI
instruction within the interrupt processing routine. Figure 2.2.12 shows an example of multiple interrupts.
Table 2.2.2 List of interrupt bits according to interrupt source
Interrupt source
INT0
INT1
INT2
INT 3/Serial I/O2
Timer X
Timer Y
Timer 1
Timer 2
Serial I/O1 reception
Serial I/O1 transmission
CNTR0
CNTR1
A-D converter
Interrupt enable bit
Address
003E16
003E16
003E16
003E16
003E16
003E16
003F 16
003F 16
003F 16
003F 16
003F 16
003F 16
003F 16
3850 Group (Spec. H) User’s Manual
Bit
b0
b2
b3
b4
b6
b7
b0
b1
b2
b3
b4
b5
b6
Interrupt request bit
Address
003C 16
003C 16
003C 16
003C 16
003C 16
003C 16
003D 16
003D 16
003D 16
003D 16
003D 16
003D 16
003D 16
Bit
b0
b2
b3
b4
b6
b7
b0
b1
b2
b3
b4
b5
b6
2-15
APPLICATION
2.2 Interrupt
Interrupt request
Nesting
Reset
Time
Main routine
I=1
C1 = 0, C2 = 0
Interrupt
request 1
C1 = 1
I=0
Interrupt 1
I=1
Interrupt
request 2
Multiple interrupt
C2 = 1
I=0
Interrupt 2
I=1
RTI
I=0
RTI
I=0
I : Interrupt disable flag
C1 : Interrupt enable bit of interrupt 1
C2 : Interrupt enable bit of interrupt 2
: Set automatically.
: Set by software.
Fig. 2.2.12 Example of multiple interrupts
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3850 Group (Spec. H) User’s Manual
APPLICATION
2.2 Interrupt
2.2.6 INT interrupt
The INT interrupt requests is generated when the microcomputer detects a level change of each INT pin
(INT 0–INT 3).
(1) Active edge selection
INT 0–INT3 can be selected from either a falling edge or rising edge detection as an active edge by
the interrupt edge selection register. In the “0” state, the falling edge of the corresponding pin is
detected. In the “1” state, the rising edge of the corresponding pin is detected.
(2) INT 3 interrupt source selection
Which of interrupt source of the serial I/O2/INT 3 interrupt source can be selected by the serial I/O2/
INT 3 interrupt source bit (bit 4 of address 3A 16 ). (Set this bit to “0” when using INT 3.)
3850 Group (Spec. H) User’s Manual
2-17
APPLICATION
2.2 Interrupt
2.2.7 Notes on interrupts
(1) Change of relevant register settings
When the setting of the following registers or bits is changed, the interrupt request bit may be set
to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following
sequence.
•Interrupt edge selection register (address 3A 16)
•Timer XY mode register (address 2316)
Set the above listed registers or bits as the following sequence.
Set the corresponding interrupt enable bit to “0”
(disabled) .
↓
Set the interrupt edge select bit (active edge switch
bit) or the interrupt (source) select bit to “1”.
↓
NOP (One or more instructions)
↓
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
↓
Set the corresponding interrupt enable bit to “1”
(enabled).
Fig. 2.2.13 Sequence of changing relevant register
■ Reason
When setting the followings, the interrupt request bit may be set to “1”.
•When setting external interrupt active edge
Concerned register: Interrupt edge selection register (address 3A 16)
Timer XY mode register (address 23 16)
•When switching interrupt sources of an interrupt vector address where two or more interrupt
sources are allocated.
Concerned register: Interrupt edge selection register (address 3A 16)
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3850 Group (Spec. H) User’s Manual
APPLICATION
2.2 Interrupt
(2) Check of interrupt request bit
● When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request
register immediately after this bit is set to “0” by using a data transfer instruction, execute one
or more instructions before executing the BBC or BBS instruction.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 2.2.14 Sequence of check of interrupt request bit
■ Reason
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt
request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
3850 Group (Spec. H) User’s Manual
2-19
APPLICATION
2.3 Timer
2.3 Timer
This paragraph explains the registers setting method and the notes relevant to the timers.
2.3.1 Memory map
Address
002016
Prescaler 12 (PRE12)
002116
Timer 1 (T1)
002216
Timer 2 (T2)
002316
Timer XY mode register (TM)
002416
Prescaler X (PREX)
002516
Timer X (TX)
002616
Prescaler Y (PREY)
002716
Timer Y (TY)
002816
Timer count source selection register (TCSS)
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
003F16
Fig. 2.3.1 Memory map of registers relevant to timers
2.3.2 Relevant registers
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY)
(addresses 2016, 2416, 2616)
b
Functions
0 • Set a count value of each prescaler.
1 • The value set in this register is written to both
2 each prescaler and the corresponding
3 prescaler latch at the same time.
• When this register is read out, the count value
4
of the corresponding prescaler is read out.
5
6
7
Fig. 2.3.2 Structure of Prescaler 12, Prescaler X, Prescaler Y
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3850 Group (Spec. H) User’s Manual
At reset R W
1
1
1
1
1
1
1
1
APPLICATION
2.3 Timer
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1
(T1: address 2116)
b
Functions
0 • Set timer 1 count value.
1 • The value set in this register is written to both
2 the timer 1 and the timer 1 latch at the same
3 time.
• When the timer 1 is read out, the count value
4
of the timer 1 is read out.
5
6
7
At reset R W
1
0
0
0
0
0
0
0
Fig. 2.3.3 Structure of Timer 1
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2
(T2: address 2216)
b
Functions
0 • Set timer 2 count value.
1 • The value set in this register is written to both
2 timer 2 and the timer 2 latch at the same time.
3 • When timer 2 is read out, the count value of
the timer 2 is read out.
4
5
6
7
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.3.4 Structure of Timer 2
3850 Group (Spec. H) User’s Manual
2-21
APPLICATION
2.3 Timer
Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0
Timer X, Timer Y
(TX, TY: addresses 2516, 2716)
b
Functions
0 • Set each timer count value.
1 • The value set in this register is written to both
2 each timer and the corresponding timer latch
3 at the same time.
• When each timer is read out, the count value
4
of the corresponding timer is read out.
5
6
7
Fig. 2.3.5 Structure of Timer X, Timer Y
2-22
3850 Group (Spec. H) User’s Manual
At reset R W
1
1
1
1
1
1
1
1
APPLICATION
2.3 Timer
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY mode register
(TM: address 2316)
b
Name
0 Timer X operating
mode bits
1
2
3
4
5
6
7
Functions
b1 b0
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width
measurement mode
CNTR0 active edge Refer to Table 2.3.1
switch bit
Timer X count stop 0: Count start
1: Count stop
bit
Timer Y operating b5 b4
0 0: Timer mode
mode bits
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width
measurement mode
CNTR1 active edge Refer to Table 2.3.1
switch bit
Timer Y count stop 0: Count start
1: Count stop
bit
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.3.6 Structure of Timer XY mode register
Table 2.3.1 CNTR0/CNTR 1 active edge switch bit function
Timer X /Timer Y Set
Timer function
operation modes value
“0”
Timer mode
No influence to timer count
“1”
No influence to timer count
“0”
Pulse output
Pulse output start: Beginning
mode
at “H” level
“1”
Pulse output start: Beginning
CNTR0 / CNTR 1 interrupt request
occurrence source
CNTR 0/CNTR 1 input signal falling edge
CNTR 0/CNTR 1 input signal rising edge
Output signal falling edge count
Output signal rising edge count
at “L” level
Event counter
mode
Pulse width
measurement mode
“0”
“1”
“0”
“1”
Rising edge count
Falling edge count
“H” level width measurement
“L” level width measurement
Input signal falling edge count
Input signal rising edge count
Input signal falling edge count
Input signal rising edge count
3850 Group (Spec. H) User’s Manual
2-23
APPLICATION
2.3 Timer
Timer count source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Timer count source selection register
(TCSS: address 2816)
b
Name
Functions
0
0: f(XIN)/16 (f(XCIN)/16 at
Timer Y count
low-speed mode)
source selection bit
1: f(XIN)/2 (f(XCIN)/2 at lowspeed mode)
0
1
2 Timer 12 count
0: f(XIN)/16 (f(XCIN)/16 at
low-speed mode)
source selection bit
1: f(XCIN)
0
3 Nothing is arranged for this bit. This is a write
4 disabled bit. When this bit is read out, the
5 contents are “0”.
6
7
0
0
0
0
0
Fig. 2.3.7 Structure of Timer count source selection register
2-24
At reset R W
0: f(XIN)/16 (f(XCIN)/16 at
0 Timer X count
low-speed mode)
source selection bit
1: f(XIN)/2 (f(XCIN)/2 at lowspeed mode)
3850 Group (Spec. H) User’s Manual
APPLICATION
2.3 Timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
Name
Functions
At reset R W
0
✽
1 When writing to this bit, set “0” to this bit.
0
✽
2 INT1 interrupt
request bit
3 INT2 interrupt
request bit
4 INT3/Serial I/O2
interrupt request bit
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0 INT0 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
5 When writing to this bit, set “0” to this bit.
0 : No interrupt request issued
6 Timer X interrupt
1 : Interrupt request issued
request bit
0 : No interrupt request issued
7 Timer Y interrupt
request bit
1 : Interrupt request issued
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.3.8 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
Name
0 Timer 1 interrupt
request bit
1 Timer 2 interrupt
request bit
2 Serial I/O1 receive
interrupt request bit
3 Serial I/O1 transmit
interrupt request bit
4 CNTR0 interrupt
request bit
5 CNTR1 interrupt
request bit
6 A-D converter
interrupt request bit
Functions
At reset R W
0 : No interrupt request issued
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
✽: “0” can be set by software, but “1” cannot be set.
0
Fig. 2.3.9 Structure of Interrupt request register 2
3850 Group (Spec. H) User’s Manual
2-25
APPLICATION
2.3 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Interrupt control register 1
(ICON1 : address 3E16)
b
Name
Functions
0 INT0 interrupt
enable bit
1 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
2 INT1 interrupt
enable bit
3 INT2 nterrupt
enable bit
4 INT3/Serial I/O2
interrupt enable bit
5 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
6 Timer X interrupt
enable bit
7 Timer Y interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.3.10 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
0 Timer 1 interrupt
enable bit
1 Timer 2 interrupt
enable bit
2 Serial I/O1 receive
interrupt enable bit
3 Serial I/O1 transmit
interrupt enable bit
4 CNTR0 interrupt
enable bit
5 CNTR1 interrupt
enable bit
6 A-D converter
interrupt enable bit
7 Fix this bit to “0”.
Functions
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 2.3.11 Structure of Interrupt control register 2
2-26
3850 Group (Spec. H) User’s Manual
At reset R W
0
0
0
0
0
0
0
0
APPLICATION
2.3 Timer
2.3.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of Event interval (Timer X, Timer Y, Timer 1, Timer 2)
When a certain time, by setting a count value to each timer, has passed, the timer interrupt request
occurs.
<Use>
•Generation of an output signal timing
•Generation of a wait time
[Function 2] Control of Cyclic operation (Timer X, Timer Y, Timer 1, Timer 2)
The value of the timer latch is automatically written to the corresponding timer each time the timer
underflows, and each timer interrupt request occurs in cycles.
<Use>
•Generation of cyclic interrupts
•Clock function (measurement of 250 ms); see Application example 1
•Control of a main routine cycle
[Function 3] Output of Rectangular waveform (Timer X, Timer Y)
The output level of the CNTR pin is inverted each time the timer underflows (in the pulse output
mode).
<Use>
•Piezoelectric buzzer output; see Application example 2
•Generation of the remote control carrier waveforms
[Function 4] Count of External pulses (Timer X, Timer Y)
External pulses input to the CNTR pin are counted as the timer count source (in the event counter
mode).
<Use>
•Frequency measurement; see Application example 3
•Division of external pulses
•Generation of interrupts due to a cycle using external pulses as the count source; count of a
reel pulse
[Function 5] Measurement of External pulse width (Timer X, Timer Y)
The “H” or “L” level width of external pulses input to CNTR pin is measured (in the pulse width
measurement mode).
<Use>
•Measurement of external pulse frequency (measurement of pulse width of FG pulse ✽ for a
motor); see Application example 4
•Measurement of external pulse duty (when the frequency is fixed)
FG pulse ✽: Pulse used for detecting the motor speed to control the motor speed.
3850 Group (Spec. H) User’s Manual
2-27
APPLICATION
2.3 Timer
(2) Timer application example 1: Clock function (measurement of 250 ms)
Outline: The input clock is divided by the timer so that the clock can count up at 250 ms intervals.
Specifications: •The clock f(X IN) = 4.19 MHz (222 Hz) is divided by the timer X.
•The clock is counted up in the process routine of the timer X interrupt which occurs
at 250 ms intervals.
Figure 2.3.12 shows the timers connection and setting of division ratios; Figure 2.3.13 shows the
relevant registers setting; Figure 2.3.14 shows the control procedure.
f(XIN) = 4.19 MHz
Timer X count source
selection bit
Prescaler X
Timer X
Timer X interrupt
request bit
1/16
1/256
1/256
0 or 1
Dividing by 4 with software
1/4
250 m s
0 : No interrupt request issued
1 : Interrupt request issued
Fig. 2.3.12 Timers connection and setting of division ratios
Timer count source selection register (address 2816)
b7
b0
TCSS
0
Timer X count source : f(XIN)/16
Timer XY mode register (address 2316)
b7
b0
1
TM
0 0
Timer X operating mode: Timer mode
Timer X count: Stop
Clear to “0” when starting count.
Prescaler X (address 2416)
b7
b0
PREX
255
Timer X (address 2516)
b7
Set “division ratio – 1”
b0
TX
255
Interrupt request register 1 (address 3C16)
b7
IREQ1
b0
0
Timer X interrupt request
(becomes “1” at 250 ms intervals)
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
1
Timer X interrupt: Enabled
Fig. 2.3.13 Relevant registers setting
2-28
3850 Group (Spec. H) User’s Manual
1 second
APPLICATION
2.3 Timer
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
•All interrupts disabled
.....
TM
IREQ1
ICON1
XXXX1X002
(address 2316)
0
(address 3C16), bit6
1
(address 3E16), bit6
•Timer X : Timer mode
•Clear Timer X interrupt request bit
•Timer X interrupt enabled
.....
TCSS
PREX
TX
0
256 – 1
256 – 1
•Timer X count source : f(XIN)/16
•Set “division ratio – 1” to Prescaler X and Timer X
(address 2316), bit3
0
•Timer X count start
.....
(address 2816), bit0
(address 2416)
(address 2516)
TM
.....
•Interrupts enabled
CLI
Main processing
.....
<Procedure for completion of clock set>
(Note 1)
TM
PREX
TX
IREQ1
TM
(address 2316), bit3
(address 2416)
(address 2516)
(address 3C16), bit6
(address 2316), bit3
•Reset Timer to restart count from 0 second after completion of
clock set
1
256 – 1
256 – 1
0
0
Note 1: Perform procedure for completion of clock set only
when completing clock set.
Timer X interrupt process routine
CLT (Note 2)
CLD (Note 3)
Push registers to stack
Note 2: When using Index X mode flag (T)
Note 3: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
Y
Clock stop ?
•Judge whether clock stops
N
Clock count up (1/4 second to year)
Pop registers
•Clock count up
•Pop registers pushed to stack
RTI
Fig. 2.3.14 Control procedure
3850 Group (Spec. H) User’s Manual
2-29
APPLICATION
2.3 Timer
(3) Timer application example 2: Piezoelectric buzzer output
Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer
output.
Specifications: •The rectangular waveform, dividing the clock f(X IN) = 4.19 MHz (2 22 Hz) into about
2 kHz (2048 Hz), is output from the P27/CNTR 0 pin.
•The level of the P2 7/CNTR 0 pin is fixed to “H” while a piezoelectric buzzer output
stops.
Figure 2.3.15 shows a peripheral circuit example, and Figure 2.3.16 shows the timers connection and
setting of division ratios. Figure 2.3.17 shows the relevant registers setting, and Figure 2.3.18 shows
the control procedure.
The “H” level is output while a piezoelectric buzzer output stops.
CNTR0 output
P27/CNTR0
PiPiPi.....
244 µs 244 µs
Set a division ratio so that the
underflow output period of the timer X
can be 244 µs.
3850 Group
Fig. 2.3.15 Peripheral circuit example
Timer X count
source selection Prescaler X
bit
f(XIN) = 4.19
MHz
1/16
1
Timer X
Fixed
1/64
1/2
Fig. 2.3.16 Timers connection and setting of division ratios
2-30
3850 Group (Spec. H) User’s Manual
CNTR0
APPLICATION
2.3 Timer
Timer count source selection register (address 2816)
b7
b0
0
TCSS
Timer X count source: f(XIN)/16
Timer XY mode register (address 2316)
b7
b0
1 0 0 1
TM
Timer X operating mode : Pulse output mode
CNTR0 active edge switch : Output starting at “H” level
Timer X count : Stop
Clear to “0” when starting count
Timer X (address 2516)
b7
b0
TX
63
Set “division ratio – 1”
Prescaler X (address 2416)
b7
b0
PREX
0
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
0
Timer X interrupt disabled
Fig. 2.3.17 Relevant registers setting
3850 Group (Spec. H) User’s Manual
2-31
APPLICATION
2.3 Timer
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
P2 (address 0416), bit7
P2D (address 0516)
1
1XXXXXXX2
.....
TCSS
ICON1
TM
TX
PREX
•Timer X count source: f(XIN)/16
•Timer X interrupt disabled
•CNTR0 output stopped at this point (buzzer output stopped)
•Set (division ratio – 1) to timer X, prescaler X
(address 2816), bit0
0
(address 3E16), bit6
0
XXXX10012
(address 2316)
64–1
(address 2516)
1-1
(address 2416)
.....
Main processing
.....
•Processing buzzer request, generated during main
processing, in output unit
Output unit
Yes
Buzzer request ?
No
TM
TX
(address 2316), bit3
(address 2516)
1
64-1
TM
(address 2316), bit3
Start of piezoelectric buzzer output
Stop of piezoelectric buzzer
output
Fig. 2.3.18 Control procedure
2-32
0
3850 Group (Spec. H) User’s Manual
APPLICATION
2.3 Timer
(4) Timer application example 3: Frequency measurement
Outline: The following two values are compared to judge whether the frequency is within a valid
range.
•A value by counting pulses input to P4 0/CNTR 1 pin with the timer.
•A reference value
Specifications: •Clock f(X IN) = 4.19 MHz (2 22 Hz)
•The pulse is input to the P4 0/CNTR 1 pin and counted by the timer Y.
•A count value is read out at about 2 ms intervals, the timer 1 interrupt interval.
When the count value is 28 to 40, it is judged that the input pulse is valid.
•Because the timer is a down-counter, the count value is compared with 227 to 215
(Note).
Note: 227 to 215 = {255 (initial value of counter) – 28} to {255 – 40}; 28 to 40 means the number
of valid value.
Figure 2.3.19 shows the judgment method of valid/invalid of input pulses; Figure 2.3.20 shows the
relevant registers setting; Figure 2.3.21 shows the control procedure.
Input pulse
71.4 µs or more
(less than 14 kHz)
71.4 µs
(14 kHz)
50 µs
(20 kHz)
Valid
Invalid
2 ms = 28 counts
71.4 µs
50 µs or less
(20 kHz or more)
Invalid
2 ms
50 µs
= 40 counts
Fig. 2.3.19 Judgment method of valid/invalid of input pulses
3850 Group (Spec. H) User’s Manual
2-33
APPLICATION
2.3 Timer
Timer XY mode register (address 2316)
b7
TM
1
b0
1 1 0
Timer Y operating mode: Event counter mode
CNTR1 active edge switch: Falling edge count
Timer Y count: Stop
Clear to “0” when starting count
Timer count source selection register (address 2816)
b7
b0
TCSS
0
Timer 1 count source: f(XIN)/16
Prescaler 12 (address 2016)
b7
PRE12
b0
63
Timer 1 (address 2116)
b7
b0
7
T1
Set “division ratio – 1”
Prescaler Y (address 2616)
b7
b0
0
PREY
Timer Y (address 2716)
b7
TY
b0
Set 255 just before counting pulses
(After a certain time has passed, the number of input
pulses is decreased from this value.)
255
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
0
Timer Y interrupt: Disabled
Interrupt control register 2 (address 3F16)
b7
ICON2
b0
1
Timer 1 interrupt: Enabled
Interrupt request register 1 (address 3C16)
b7
IREQ1
b0
0
Judgment of Timer Y interrupt request bit
( “1” of this bit when reading the count value indicates the 256 or more
pulses input in the condition of Timer Y = 255)
Fig. 2.3.20 Relevant registers setting
2-34
3850 Group (Spec. H) User’s Manual
APPLICATION
2.3 Timer
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
SEI
•All interrupts disabled
.....
TM
TCSS
PRE12
T1
PREY
TY
ICON1
ICON2
(address 2316)
(address 2816)
(address 2016)
(address 2116)
(address 2616)
(address 2716)
(address 3E16), bit7
(address 3F16), bit0
1110XXXX2
XXXXX0XX2
64 – 1
8–1
1–1
256 – 1
0
1
•Timer Y operating mode : Event counter mode
(Count a falling edge of pulses input from CNTR1 pin.)
•Set division ratio so that Timer 1 interrupt will occur at
2 ms intervals.
•Timer Y initial value set
•Timer Y interrupt: Disabled
•Timer 1 interrupt: Enabled
.....
(address 2316), bit7
TM
0
•Timer Y count start
.....
•Interrupts enabled
CLI
Timer 1 interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
1
IREQ1(address 3C16), bit7 ?
•Process as out of range when the count value is 256 or more
0
(A)
TY (address 2716)
•Read the count value
•Store the count value into Accumulator (A)
In range
•Compare the read value with
reference value
•Store the comparison result to
flag Fpulse
214 < (A) < 228
Out of range
Fpulse
TY
IREQ1
0
Fpulse
(address 2716)
(address 3C16), bit7
256 – 1
0
1
•Initialize the counter value
•Clear Timer Y interrupt request bit
Process judgment result
Pop registers
•Pop registers pushed to stack
RTI
Fig. 2.3.21 Control procedure
3850 Group (Spec. H) User’s Manual
2-35
APPLICATION
2.3 Timer
(5) Timer application example 4: Measurement of FG pulse width for motor
Outline: The timer X counts the “H” level width of the pulses input to the CNTR 0 pin. An underflow
is detected by the timer X interrupt and an end of the input pulse “H” level is detected by
the CNTR0 interrupt.
Specifications: •The timer X counts the “H” level width of the FG pulse input to the CNTR 0 pin.
<Example>
When the clock frequency is 4.19 MHz, the count source is 3.8 µs, which is obtained by dividing
the clock frequency by 16. Measurement can be made up to 250 ms in the range of FFFF 16 to
0000 16.
Figure 2.3.22 shows the timers connection and setting of division ratio; Figure 2.3.23 shows the
relevant registers setting; Figure 2.3.24 shows the control procedure.
Timer X count source
selection bit
Prescaler X
f(XIN) = 4.19 MHz
1/16
1/256
Timer X
1/256
Timer X interrupt
request bit
0 or 1
250 ms
0 : No interrupt request issued
1 : Interrupt request issued
Fig. 2.3.22 Timers connection and setting of division ratios
2-36
3850 Group (Spec. H) User’s Manual
APPLICATION
2.3 Timer
Timer XY mode register (address 2316)
b7
b0
TM
1 0 1 1
Timer X operating mode: Pulse width measurement mode
CNTR0 active edge switch: “H” level width measurement
Timer X count: Stop
Clear to “0” when starting count
Prescaler X (address 2416)
b7
b0
PREX
255
Timer X (address 2516)
b7
Set “division ratio – 1”
b0
TX
255
Interrupt request register 1 (address 3C16)
b7
IREQ1
b0
0
Timer X interrupt request
(Set to “1” automatically when Timer X underflows)
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
1
Timer X interrupt: Enabled
Interrupt request register 2 (address 3D16)
b7
IREQ2
b0
0
CNTR0 interrupt request
(Set to “1” automatically when “H” level input came to the end)
Interrupt control register 2 (address 3F16)
b7
ICON2
b0
1
CNTR0 interrupt: Enabled
Fig. 2.3.23 Relevant registers setting
3850 Group (Spec. H) User’s Manual
2-37
APPLICATION
2.3 Timer
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
•All interrupts disabled
.....
TM
PREX
TX
IREQ1
ICON1
IREQ2
ICON2
....
TM
(address 2316)
XXXX10112
(address 2416)
256–1
(address 2516)
256–1
(address 3C16), bit6
0
(address 3E16), bit6
1
(address 3D16), bit4
0
(address 3F16), bit4
1
•Timer X: Pulse width measurement mode
(Measure “H” level of pulses input from CNTR0 pin.)
•Set division ratio so that Timer X interrupt will occur at
250 ms intervals.
•Clear Timer X interrupt request bit
•Timer X interrupt enabled
•Clear CNTR0 interrupt request bit
•CNTR0 interrupt enabled
(address 2316), bit3
•Timer X count start
0
....
CLI
•Interrupts enabled
Timer X interrupt process routine
•Error occured
Error processing
RTI
CNTR0 interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
(A)
Low-order 8-bit result of
pulse width measurement
(A)
High-order 8-bit result of
pulse width measurement
(address 2416)
PREX
(address 2516)
TX
Pop registers
PREX
Inverted (A)
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
•Read the count value and store it to RAM
TX
Inverted (A)
256–1
256–1
•Division ratio set so that Timer X interrupt will
occur at 250 ms intervals.
•Pop registers pushed to stack
RTI
Fig. 2.3.24 Control procedure
2-38
3850 Group (Spec. H) User’s Manual
APPLICATION
2.3 Timer
2.3.4 Notes on timer
● If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
● When switching the count source by the timer 12, X and Y count source selection bits, the value
of timer count is altered in unconsiderable amount owing to generating of thin pulses in the count
input signals.
Therefore, select the timer count source before set the value to the prescaler and the timer.
3850 Group (Spec. H) User’s Manual
2-39
APPLICATION
2.4 Serial I/O
2.4 Serial I/O
This paragraph explains the registers setting method and the notes relevant to the Serial I/O.
2.4.1 Memory map
Address
001516
Serial I/O2 control register 1 (SIO2CON1)
001616
Serial I/O2 control register 2 (SIO2CON2)
001716
Serial I/O2 register (SIO2)
001816
Transmit/Receive buffer register (TB/RB)
001916
Serial I/O1 status register (SIOSTS)
001A16
Serial I/O1 control register (SIOCON)
001B16
UART control register (UARTCON)
001C16
Baud rate generator (BRG)
003A16
Interrupt edge selection register (INTEDGE)
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
003F16
Fig. 2.4.1 Memory map of registers relevant to Serial I/O
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3850 Group (Spec. H) User’s Manual
APPLICATION
2.4 Serial I/O
2.4.2 Relevant registers
Serial I/O2 control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register 1 (SIO2CON1: address 1516)
b
Name
0 Internal
synchronous clock
1 selection bits
2
3 Serial I/O2 port
selection bit
4 SRDY2 output
enable bit
5 Transfer direction
selection bit
6 Serial I/O2
synchronous
clock selection bit
7 P01/SOUT2,
P02/SCLK2
P-channel output
disable bit
Functions
b2b1b0
0 0 0: f(XIN)/8
0 0 1: f(XIN)/16
0 1 0: f(XIN)/32
0 1 1: f(XIN)/64
1 1 0: f(XIN)/128
1 1 1: f(XIN)/256
0: I/O port (P01, P02)
1: SOUT2, SCLK2 signal output
0: I/O port (P03)
1: SRDY2 signal output
0: LSB first
1: MSB first
0: External clock
1: Internal clock
0: CMOS output
1: N-channel open-drain
output
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.4.2 Structure of Serial I/O2 control register 1
Serial I/O2 control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register 2
(SIO2CON2: address 1616)
b
Name
0 Optional transfer
bits
1
2
Functions
b2b1b0
0 0 0: 1 bit
0 0 1: 2 bit
0 1 0: 3 bit
0 1 1: 4 bit
1 0 0: 5 bit
1 0 1: 6 bit
1 1 0: 7 bit
1 1 1: 8 bit
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
3
4
5
6 Serial I/O2
I/O comparison
signal control bit
7 SOUT2 pin control
bit (P01)
0: P43 I/O
1: SCMP2 output
0: Output active
1: Output high-impedance
At reset R W
1
1
1
0
0
0
0
✕
✕
✕
0
Fig. 2.4.3 Structure of Serial I/O2 control register 2
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.4 Serial I/O
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register
(SIO2: address 1716)
b
0
1
2
3
4
5
6
7
Name
Functions
This register becomes shift register.
At transmit: Set transmit data to this register.
At receive: Received data is stored to this
register.
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Fig. 2.4.4 Structure of Serial I/O2 register
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB: address 1816)
b
Functions
0
1
2
3
4
5
6
7
The transmission data is written to or the
receive data is read out from this buffer register.
• At write: A data is written to the transmit buffer
register.
• At read: The contents of the receive buffer
register are read out.
Fig. 2.4.5 Structure of Transmit/Receive buffer register
2-42
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
3850 Group (Spec. H) User’s Manual
APPLICATION
2.4 Serial I/O
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 status register (SIOSTS: address 1916)
b
Name
0 Transmit buffer
empty flag (TBE)
1 Receive buffer full
flag (RBF)
2 Transmit shift
register shift
completion flag
(TSC)
Functions
0: Buffer full
1: Buffer empty
0: Buffer empty
1: Buffer full
0: Transmit shift in progress
1: Transmit shift completed
3 Overrun error flag 0: No error
(OE)
1: Overrun error
4 Parity error flag
0: No error
(PE)
1: Parity error
5 Framing error flag 0: No error
(FE)
1: Framing error
6 Summing error flag 0: (OE) U (PE) U (FE) = 0
(SE)
1: (OE) U (PE) U (FE) = 1
7 Nothing is arranged for this bit. This bit is a
write disabled bit. When this bit is read out, the
contents are “1”.
At reset R W
✕
0
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
1
✕
Fig. 2.4.6 Structure of Serial I/O1 status register
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.4 Serial I/O
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register
(SIOCON: address 1A16)
b
Name
Functions
0 BRG count source 0: f(XIN)
selection bit (CSS) 1: f(XIN)/4
Serial
I/O1
When clock synchronous
1
synchronous clock serial I/O is selected,
selection bit (SCS) 0: BRG output divided by 4
1: External clock input
When UART is selected,
0: BRG output divided by 16
1: External clock input
divided by16
At reset R W
0
0
2 SRDY1 output
enable bit (SRDY)
0: I/O port (P27)
1: SRDY1 output pin
0
3 Transmit interrupt
source selection
bit (TIC)
0: Transmit buffer empty
1: Transmit shift operation
completion
0
4 Transmit enable bit
(TE)
5 Receive enable bit
(RE)
6 Serial I/O1 mode
selection bit (SIOM)
0: Transmit disabled
1: Transmit enabled
0: Receive disabled
1: Receive enabled
0: UART
1: Clock synchronous
serial I/O
0: Serial I/O1 disabled
(P24 to P27: normal I/O pins)
1: Serial I/O1 enabled
(P24 to P27: Serial I/O pins)
0
7 Serial I/O1 enable
bit (SIOE)
0
0
0
Fig. 2.4.7 Structure of Serial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register
(UARTCON: address 1B16)
b
Name
Functions
0 Character length
selection bit (CHAS)
1 Parity enable bit
(PARE)
2 Parity selection bit
(PARS)
3 Stop bit length
selection bit (STPS)
4 P25/TxD P-channel
output disable bit
(POFF)
0: 8 bits
1: 7 bits
0: Parity checking disabled
1: Parity checking enabled
0: Even parity
1: Odd parity
0: 1 stop bit
1: 2 stop bits
In output mode
0: CMOS output
1: N-channel open-drain
output
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read
7 out, the contents are “1”.
Fig. 2.4.8 Structure of UART control register
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3850 Group (Spec. H) User’s Manual
At reset R W
0
0
0
0
0
1
1
1
✕
✕
✕
APPLICATION
2.4 Serial I/O
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator(BRG : address 1C16)
b
Functions
0 Set a count value of baud rate generator.
1
2
3
4
5
6
7
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Fig. 2.4.9 Structure of Baud rate generator
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register
(INTEDGE: address 3A16)
b
Name
0 INT0 active edge
selection bit
1 INT1 active edge
selection bit
2 INT2 active edge
selection bit
3 INT3 active edge
selection bit
4 SeriaI/O2/INT3
interrupt source bit
Functions
0: Falling edge active
1: Rising edge active
0: Falling edge active
1: Rising edge active
0: Falling edge active
1: Rising edge active
0: Falling edge active
1: Rising edge active
0: INT3 interrupt selected
1: Serial I/O2 interrupt
selected
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read out,
7 the contents are “0”.
At reset R W
0
0
0
0
0
0
0
0
0
Fig. 2.4.10 Structure of Interrupt edge selection register
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.4 Serial I/O
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
Name
Functions
At reset R W
0
✽
1 When writing to this bit, set “0” to this bit.
0
✽
2 INT1 interrupt
request bit
3 INT2 interrupt
request bit
4 INT3/Serial I/O2
interrupt request bit
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0 INT0 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
5 When writing to this bit, set “0” to this bit.
0 : No interrupt request issued
6 Timer X interrupt
1 : Interrupt request issued
request bit
0 : No interrupt request issued
7 Timer Y interrupt
request bit
1 : Interrupt request issued
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.4.11 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
Name
0 Timer 1 interrupt
request bit
1 Timer 2 interrupt
request bit
2 Serial I/O1 receive
interrupt request bit
3 Serial I/O1 transmit
interrupt request bit
4 CNTR0 interrupt
request bit
5 CNTR1 interrupt
request bit
6 A-D converter
interrupt request bit
Functions
At reset R W
0 : No interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.4.12 Structure of Interrupt request register 2
2-46
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
1 : Interrupt request issued
3850 Group (Spec. H) User’s Manual
0
APPLICATION
2.4 Serial I/O
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Interrupt control register 1
(ICON1 : address 3E16)
b
Name
Functions
0 INT0 interrupt
enable bit
1 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
2 INT1 interrupt
enable bit
3 INT2 nterrupt
enable bit
4 INT3/Serial I/O2
interrupt enable bit
5 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
6 Timer X interrupt
enable bit
7 Timer Y interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.4.13 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
0
Timer 1 interrupt
enable bit
Timer 2 interrupt
enable bit
Serial I/O1 receive
interrupt enable bit
Serial I/O1 transmit
interrupt enable bit
CNTR0 interrupt
enable bit
CNTR1 interrupt
enable bit
A-D converter
interrupt enable bit
Fix this bit to “0”.
1
2
3
4
5
6
7
Functions
At reset R W
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
0
0
Fig. 2.4.14 Structure of Interrupt control register 2
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.4 Serial I/O
2.4.3 Serial I/O connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.4.15 shows connection examples of a peripheral IC equipped with the CS pin.
There are connection examples using a clock synchronous serial I/O mode.
(1) Only transmission
(Using the RXD pin as an I/O port)
Port
CS
SCLK1
CLK
TX D
3850 group
Port
CS
SCLK1
CLK
TX D
RX D
DATA
Peripheral IC
(OSD controller etc.)
(3) Transmission and reception
(When connecting RXD with TXD)
(When connecting IN with OUT in
peripheral IC)
3850 group
OUT
Peripheral IC
(E 2 PROM etc.)
(4) Connection of plural IC
CS
Port
CS
SCLK1
CLK
SCLK1
CLK
3850
group ✽1
IN
OUT
IC✽2
Peripheral
(E2 PROM etc.)
TX D
IN
RX D
OUT
Port
Peripheral IC 1
3850 group
Select an N-channel open-drain output for TXD pin output control.
Use the OUT pin of peripheral IC which is an N-channel opendrain output and becomes high impedance during receiving data.
Notes 1: “Port” means an output port controlled by software.
2: When serial I/O2 is used, SOUT2 and SIN2 are used,
not TxD and RxD.
Fig. 2.4.15 Serial I/O connection examples (1)
2-48
IN
Port
TX D
RX D
✽1:
✽2:
(2) Transmission and reception
3850 Group (Spec. H) User’s Manual
CS
CLK
IN
OUT
Peripheral IC 2
APPLICATION
2.4 Serial I/O
(2) Connection with microcomputer
Figure 2.4.16 shows connection examples with another microcomputer.
(1) Selecting internal clock
(2) Selecting external clock
SCLK1
CLK
TXD
IN
TXD
IN
OUT
R XD
OUT
RXD
3850 group
SCLK1
Microcomputer
(3) Using SRDY1 signal output function
(Selecting an external clock)
SRDY1
RDY
SCLK1
CLK
TXD
R XD
3850 group
IN
OUT
Microcomputer
3850 group
CLK
Microcomputer
(4) In UART ✽
TXD
R XD
R XD
TXD
3850 group
Microcomputer
✽ When serial I/O2 is used, UART cannot be used.
Note: When serial I/O2 is used, SOUT2 and SIN2 are used, not TxD and RxD.
Fig. 2.4.16 Serial I/O connection examples (2)
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APPLICATION
2.4 Serial I/O
2.4.4 Setting of serial I/O transfer data format
A clock synchronous or clock asynchronous (UART) can be selected as a data format of Serial I/O1.
A clock synchronous is used as a data format of Serial I/O2.
Figure 2.4.17 shows the serial I/O transfer data format.
1ST-8DATA-1SP
ST
LSB
MSB
SP
1ST-7DATA-1SP
ST
LSB
MSB
SP
1ST-8DATA-1PAR-1SP
ST
LSB
MSB
PAR
PAR
SP
MSB
2SP
SP
1ST-7DATA-1PAR-1SP
ST
UART
LSB
MSB
1ST-8DATA-2SP
ST
LSB
1ST-7DATA-2SP
ST
Serial I/O1
LSB
MSB
2SP
1ST-8DATA-1PAR-2SP
ST
LSB
MSB
PAR
PAR
2SP
1ST-7DATA-1PAR-2SP
ST
Clock synchronous
Serial I/O
LSB
LSB first
LSB first (1 to 8 bits optional transfer)
Serial I/O2
Clock synchronous
Serial I/O
MSB first (1 to 8 bits optional transfer)
Fig. 2.4.17 Serial I/O transfer data format
2-50
MSB
3850 Group (Spec. H) User’s Manual
ST : Start bit
SP : Stop bit
PAR : Parity bit
2SP
APPLICATION
2.4 Serial I/O
2.4.5 Serial I/O application examples
(1) Communication using clock synchronous serial I/O (transmit/receive)
Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O.
The SRDY1 signal is used for communication control.
Figure 2.4.18 shows a connection diagram, and Figure 2.4.19 shows a timing chart.
Figure 2.4.20 shows a registers setting relevant to the transmitting side, and Figure 2.4.21 shows
registers setting relevant to the receiving side.
Transmitting side
Receiving side
P41/INT0
SRDY1
SCLK1
SCLK1
TXD
R XD
3850 group
3850 group
Fig. 2.4.18 Connection diagram
Specifications : •
•
•
•
The Serial I/O is used (clock synchronous serial I/O is selected.)
Synchronous clock frequency : 125 kHz (f(X IN) = 4 MHz is divided by 32)
The SRDY1 (receivable signal) is used.
The receiving side outputs the SRDY1 signal at intervals of 2 ms (generated by timer),
and 2-byte data is transferred from the transmitting side to the receiving side.
SRDY1
••••
SCLK1
••••
TX D
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1
••••
2 ms
Fig. 2.4.19 Timing chart
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.4 Serial I/O
Transmitting side
Serial I/O1 status register (Address : 1916)
b7
b0
SIOSTS
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O1 control register (Address : 1A16)
b7
SIOCON
b0
1 1 0 1
0 0
BRG count source : f(XIN)
Serial I/O1 synchronous clock : BRG/4
Transmit enabled
Receive disabled
Clock synchronous serial I/O
Serial I/O1 enabled
Baud rate generator (Address : 1C16)
b7
BRG
b0
Set “division ratio – 1”.
7
Interrupt edge selection register (Address : 3A16)
b7
INTEDGE
b0
0
INT0 interrupt edge selection bit : Falling edge active
Fig. 2.4.20 Registers setting relevant to transmitting side
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APPLICATION
2.4 Serial I/O
Receiving side
Serial I/O1 status register (Address : 1916)
b7
b0
SIOSTS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : At completing reception
“0” : At reading out contents of Receive buffer register
Serial I/O1 control register (Address : 1A16)
b7
SIOCON 1 1 1 1
b0
1 1
Serial I/O1 synchronous clock : External clock
SRDY1 output enabled
Transmit enabled
Set this bit to “1”, using SRDY1 output.
Receive enabled
Clock synchronous serial I/O
Serial I/O1 enabled
Fig. 2.4.21 Registers setting relevant to receiving side
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.4 Serial I/O
Figure 2.4.22 shows a control procedure of the transmitting side, and Figure 2.4.23 shows a control
procedure of the receiving side.
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
.....
1101xx002
SIOCON (Address : 1A16)
8–1
(Address : 1C16)
BRG
0
INTEDGE (Address : 3A16), bit0
0
IREQ1 (Address:3C16), bit0?
• Detection of INT0 falling edge
1
IREQ1 (Address : 3C16), bit0
TB/RB (Address : 1816)
0
The first byte of a
transmission data
SIOSTS (Address : 1916), bit0?
0
1
TB/RB (Address : 1816)
The second byte of a
transmission data
SIOSTS (Address : 1916), bit0?
0
1
SIOSTS (Address : 1916), bit2?
0
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
• Judgment of transferring from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
• Judgment of transferring from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
1
Fig. 2.4.22 Control procedure of transmitting side
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3850 Group (Spec. H) User’s Manual
APPLICATION
2.4 Serial I/O
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
.....
SIOCON (Address : 1A16)
1111x11x2
N
Pass 2 ms?
• An interval of 2 ms generated by Timer
Y
TB/RB (Address : 1816)
Dummy data
• SRDY1 output
SRDY1 signal is output by writing data to the TB.
Using the SRDY1, set Transmit enable bit
(bit4) of the SIOCON to “1”.
0
SIOSTS (Address : 1916), bit1?
• Judgment of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data
Receive buffer full flag is set to “0” by reading data.
Read out reception data from
TB/RB (Address : 1816)
0
SIOSTS (Address : 1916), bit1?
• Judgment of completion of receiving
(Receive buffer full flag)
1
Read out reception data from
TB/RB (Address : 1816)
• Reception of the second byte data.
Receive buffer full flag is set to “0” by reading data.
Fig. 2.4.23 Control procedure of receiving side
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.4 Serial I/O
(2) Output of serial data (control of peripheral IC)
Outline : 4-byte data is transmitted and received, using the clock synchronous serial I/O.
The CS signal is output to a peripheral IC through port P43.
Figure 2.4.24 shows a connection diagram, and Figure 2.4.25 shows a timing chart.
P43
SCLK1
CS
CLK
DATA
TXD
3850 group
P43
CS
SCLK2
CLK
CS
CS
CLK
CL
K
DATA
DATA
DATA
SOUT2
3850 group
Peripheral IC
(1) Example for using Serial I/O1
Peripheral IC
(2) Example for using Serial I/O2
Fig. 2.4.24 Connection diagram
Specifications : • The Serial I/O is used (clock synchronous serial I/O is selected.)
• Synchronous clock frequency : 125 kHz (f(X IN) = 4 MHz is divided by 32)
• Transfer direction : LSB first
• The Serial I/O interrupt is not used.
• Port P43 is connected to the CS pin (“L” active) of the peripheral IC for transmission
control; the output level of port P4 3 is controlled by software.
CS
CLK
DATA
DO0
DO1
DO2
DO3
Note: When serial I/O1 is used, the level of the last bit is held. When serial
I/O2 is used, SOUT2 pin is in the high-impedance state after the transfer
is completed.
Fig. 2.4.25 Timing chart (Serial I/O1)
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APPLICATION
2.4 Serial I/O
Figure 2.4.26 shows registers setting relevant to Serial I/O1, and Figure 2.4.27 shows a setting of
serial I/O1 transmission data.
Serial I/O1 control register (Address : 1A16)
b7
SIOCON
b0
1 1 0 1 1 0 0 0
BRG count source : f(XIN)
Serial I/O1 synchronous clock : BRG/4
SRDY1 output disab led
Transmit interrupt source : Transmit shift operating completion
Transmit enabled
Receive disabled
Clock synchronous serial I/O
Serial I/O1 enabled
UART control register (Address : 1B16)
b7
b0
0
UARTCON
P25/TXD pin : CMOS output
Baud rate generator (Address : 1C16)
b7
b0
7
B RG
Set “division ratio – 1”.
Interrupt control register 2 (Address : 3F16)
b7
ICON2
b0
0
Serial I/O1 transmit interrupt : Disabled
Interrupt request register 2 (Address : 3D16)
b7
IREQ2
b0
0
Serial I/O1 transmit interrupt request
Confirm completion of transmitting
1-byte data by one unit.
“1” : Transmit shift completion
Fig. 2.4.26 Registers setting relevant to Serial I/O1
Transmit/Receive buffer register (Address : 1816)
b7
TB/RB
b0
Set a transmission data.
Confirm that transmission of the previous data is
completed (bit 3 of the Interrupt request register 2
is “1”) before writing data.
Fig. 2.4.27 Setting of serial I/O1 transmission data
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.4 Serial I/O
Example for using Serial I/O1
When the registers are set as shown in Figure 2.4.26, the Serial I/O1 can transmit 1-byte data by
writing data to the transmit buffer register.
Thus, after setting the CS signal to “L”, write the transmission data to the transmit buffer register by
each 1 byte, and return the CS signal to “H” when 4-byte data has been transmitted.
Figure 2.4.28 shows a control procedure of Serial I/O1.
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
....
SIOCON (Address : 1A16) 110110002
0
UARTCON (Address : 1B16), bit4
8–1
(Address : 1C16)
BRG
0
(Address : 3F16), bit3
ICON2
1
(Address : 0816), bit3
P4
(Address : 0916)
xxxx1xxx2
P4D
•Serial I/O1 set
•Serial I/O1 transmit interrupt : Disabled
....
•CS signal output port set
(“H” level output)
P4 (Address : 0816), bit3
IREQ2 (Address : 3D16), bit3
TB/RB (Address : 1816)
•CS signal output level to “L” set
0
•Serial I/O1 transmit interrupt
request bit set to “0”
0
•Transmission
data write
(Start of transmit 1-byte data)
a transmission
data
IREQ2 (Address : 3D16), bit3?
0
•Judgment of completion of transmitting
1-byte data
1
N
Complete to transmit 4-byte data?
Y
P4 (Address : 0816), bit3
1
•Use any of RAM area as a counter for
counting the number of transmitted bytes
•Judgment of completion of transmitting 4byte data
•Return the CS signal output level to “H”
when transmission of 4-byte data is
completed
Fig. 2.4.28 Control procedure of Serial I/O1
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APPLICATION
2.4 Serial I/O
Figure 2.4.29 shows registers setting relevant to Serial I/O2, and Figure 2.4.30 shows a setting of
serial I/O2 transmission data.
Serial I/O2 control register 1 (Address : 1516)
b7
SIO2CON1
b0
0 1 0 0 1 0 1 0
Synchronous clock : f(XIN)/32
Serial I/O2 used
SRDY2 output not used
LSB first
Internal clock
P01/SOUT2, P02/SCLK2 pin : CMOS output
Serial I/O2 control register 2 (Address : 1616)
b7
SIO2CON2
b0
0
1 1 1
Transfer bit : 8 bits
P43 : I/O port
Interrupt edge selection register (Address : 3A16)
b7
INTEDGE
b0
1
Serial I/O2/ INT3 interrupt source selection : Serial I/O2 interrupt
Interrupt control register 1 (Address : 3E16)
b7
ICON1
b0
0
Serial I/O2 interrupt : Disabled
Interrupt request register 1 (Address : 3C16)
b7
IREQ1
b0
0
Serial I/O2 interrupt request
Confirm completion of transmitting
1-byte data by one unit.
“1” : Transmit shift completion
Fig. 2.4.29 Registers setting relevant to Serial I/O2
Serial I/O2 register (Address : 1716)
b7
SIO2
b0
Set a transmission data.
Confirm that transmission of the previous data is
completed (bit 4 of the Interrupt request register 1
is “1”) before writing data.
Fig. 2.4.30 Setting of serial I/O2 transmission data
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.4 Serial I/O
Example for using Sreial I/O2
When the registers are set as shown in Fig. 2.4.29, the Serial I/O2 can transmit 1-byte data by writing
data to the serial I/O2 register.
Thus, after setting the CS signal to “L”, write the transmission data to Serial I/O2 by each 1 byte, and
return the CS signal to “H” when 4-byte data has been transmitted.
Figure 2.4.31 shows a control procedure of Serial I/O2.
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
....
•Serial I/O2 control register set
010010102
SIO2CON1(Address : 1516)
x0xxx1112
SIO2CON2(Address : 2616)
xxx0xxxx2
INTEDGE (Address : 3A16)
(Address : 3E16), bit4
0
ICON1
(Address : 0816), bit3
1
P4
xxxx1xxx2
(Address : 0916)
P4D
•Serial I/O2/INT3 interrupt source selection : Serial I/O2 interrupt
•Serial I/O2 interrupt : Disabled
•CS signal output port set
(“H” level output)
....
P4 (Address : 0816), bit3
0
IREQ1 (Address : 3C16), bit4
SIO2 (Address : 1716)
•CS signal output level set to “L”
•Serial I/O2 interrupt request bit set to “0”
0
•Transmission data write
(Start of transmit 1-byte data)
a transmission
data
0
IREQ1 (Address : 3C16), bit4?
•Judgment of completion of transmitting 1byte data
1
N
Complete to transmit 4-byte data?
•Use any of RAM area as a counter for
counting the number of transmitted bytes
•Judgment of completion of transmitting 4byte data
Y
P4 (Address : 0816), bit3
•Return the CS signal output level to “H”
when transmission of 4-byte data is
completed
1
Fig. 2.4.31 Control procedure of Serial I/O2
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3850 Group (Spec. H) User’s Manual
APPLICATION
2.4 Serial I/O
(3) Cyclic transmission or reception of block data (data of specified number of bytes) between
two microcomputers
Outline : When the clock synchronous serial I/O is used for communication, synchronization of the
clock and the data between the transmitting and receiving sides may be lost because of
noise included in the synchronous clock. It is necessary to correct that constantly, using
“heading adjustment”.
This “heading adjustment” is carried out by using the interval between blocks in this
example.
Figure 2.4.32 shows a connection diagram.
SCLK1
SCLK1
RXD
TXD
TXD
RXD
Master unit
Slave
Fig. 2.4.32 Connection diagram
Specifications :
•
•
•
•
•
•
•
•
The serial I/O is used (clock synchronous serial I/O is selected).
Synchronous clock frequency : 131 kHz (f(X IN) = 4.19 MHz is divided by 32)
Byte cycle: 488 µs
Number of bytes for transmission or reception : 8 byte/block
Block transfer cycle : 16 ms
Block transfer term : 3.5 ms
Interval between blocks : 12.5 ms
Heading adjustment time : 8 ms
Limitations of specifications :
• Reading of the reception data and setting of the next transmission data must be
completed within the time obtained from “byte cycle – time for transferring 1-byte
data” (in this example, the time taken from generating of the serial I/O1 receive
interrupt request to input of the next synchronous clock is 431 µs).
• “Heading adjustment time < interval between blocks” must be satisfied.
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APPLICATION
2.4 Serial I/O
The communication is performed according to the timing shown in Figure 2.4.33. In the slave unit,
when a synchronous clock is not input within a certain time (heading adjustment time), the next clock
input is processed as the beginning (heading) of a block.
When a clock is input again after one block (8 byte) is received, the clock is ignored.
Figure 2.4.34 shows relevant registers setting.
D O0
D O1
DO2
DO7
D O0
Byte cycle
Interval between blocks
Block transfer term
Block transfer cycle
Heading adjustment time
Processing for heading adjustment
Fig. 2.4.33 Timing chart
Master unit
Slave unit
Serial I/O1 control register (Address : 1A16)
b7
b0
SIOCON
Serial I/O1 control register (Address : 1A16)
b7
b0
1 1 1 1 1 0 0 0
SIOCON
1 1 1 1
0 1
BRG count source : f(XIN)
Synchronous clock : BRG/4
SRDY1 output disabled
Not affected by external clock
Synchronous clock : External clock
SRDY1 output disabled
Transmit interrupt source :
Transmit shift operating completion
Transmit enabled
Receive enabled
Not use the serial I/O1 transmit interrupt
Transmit enabled
Receive enabled
Clock synchronous serial I/O
Clock synchronous serial I/O
Serial I/O1 enabled
Serial I/O1 enabled
Both of units
UART control register (Address : 1B16)
b7
b0
0
UARTCON
P25/TXD pin : CMOS output
Baud rate generator (Address : 1C16)
b7
b0
7
BRG
Set “division ratio – 1”.
Fig. 2.4.34 Relevant registers setting
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APPLICATION
2.4 Serial I/O
Control procedure :
● Control in the master unit
After setting the relevant registers shown in Figure 2.4.34, the master unit starts transmission or
reception of 1-byte data by writing transmission data to the transmit buffer register.
To perform the communication in the timing shown in Figure 2.4.33, take the timing into account
and write transmission data. Additionally, read out the reception data when the serial I/O1 transmit
interrupt request bit is set to “1”, or before the next transmission data is written to the transmit
buffer register.
Figure 2.4.35 shows a control procedure of the master unit using timer interrupts.
Interrupt processing routine
executed every 488 µs
CLT (Note 1)
CLD (Note 2)
Push register to stack
Within a block
transfer term?
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
•Push the register used in the interrupt
processing routine into the stack
N
•Generation of a certain block interval
by using a timer or other functions
Y
Complete to transfer
a block?
Y
Start a block transfer?
Pop registers
N
Y
N
Write a transmission data
•Check the block interval counter and
determine to start a block transfer
Count a block interval counter
Read a reception data
Write the first transmission data
(first byte) in a block
•Pop registers which is pushed to stack
R TI
Fig. 2.4.35 Control procedure of master unit
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APPLICATION
2.4 Serial I/O
● Control in the slave unit
After setting the relevant registers as shown in Figure 2.4.34, the slave unit becomes the state
where a synchronous clock can be received at any time, and the serial I/O receive interrupt
request bit is set to “1” each time an 8-bit synchronous clock is received.
In the serial I/O receive interrupt processing routine, the data to be transmitted next is written to
the transmit buffer register after the received data is read out.
However, if no serial I/O receive interrupt occurs for a certain time (heading adjustment time or
more), the following processing will be performed.
1. The first 1-byte data of the transmission data in the block is written into the transmit buffer register.
2. The data to be received next is processed as the first 1 byte of the received data in the block.
Figure 2.4.36 shows a control procedure of the slave unit using the serial I/O receive interrupt and
any timer interrupt (for heading adjustment).
Timer interrupt processing
routine
Serial I/O receive interrupt
processing routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
Within a block
transfer term?
N
CLT (Note 1)
•Push the register used in the
CLD (Note 2)
interrupt processing routine into
Push register to stack
the stack
•Confirmation of the received
byte counter to judge the
block transfer term
Heading adjustment counter – 1
Y
Read a reception data
Heading adjustment
counter = 0?
A received byte counter +1
Write the first transmission
data (first byte) in a block
•Push the register used in
the interrupt processing
routine into the stack
N
Y
A received byte
counter ≥ 8?
A received byte counter
Y
0
N
Pop registers
Write a transmission data
Write dummy data (FF16)
•Pop registers which is
pushed to stack
RTI
Initial
value
(Note 3)
Heading
adjustment
counter
Pop registers
R TI
•Pop registers which is pushed to stack
Notes 1: When using the Index X mode flag (T).
2: When using the Decimal mode flag (D).
3: In this example, set the value which is equal to the
heading adjustment time divided by the timer interrupt
cycle as the initial value of the heading adjustment
counter.
For example: When the heading adjustment time is 8 ms
and the timer interrupt cycle is 1 ms, set 8
as the initial value.
Fig. 2.4.36 Control procedure of slave unit
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3850 Group (Spec. H) User’s Manual
APPLICATION
2.4 Serial I/O
(4) Communication (transmit/receive) using asynchronous serial I/O (UART)
Outline : 2-byte data is transmitted and received, using the asynchronous serial I/O.
Port P4 0 is used for communication control.
Figure 2.4.37 shows a connection diagram, and Figure 2.4.38 shows a timing chart.
Transmitting side
Receiving side
P40
P40
T XD
RXD
3850 group
3850 group
Fig. 2.4.37 Connection diagram
Specifications : • The Serial I/O1 is used (UART is selected).
• Transfer bit rate : 9600 bps (f(X IN) = 4.9152 MHz is divided by 512)
• Communication control using port P4 0
(The output level of port P4 0 is controlled by software.)
• 2-byte data is transferred from the transmitting side to the receiving side at intervals
of 10 ms generated by the timer.
ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2)
~
~
TXD
.....
~
~
P40
.
ST D0
.....
.
10 ms
Fig. 2.4.38 Timing chart (using UART)
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APPLICATION
2.4 Serial I/O
Table 2.4.1 and Table 2.4.2 show setting examples of the baud rate generator (BRG) values and
transfer bit rate values; Figure 2.4.39 shows registers setting relevant to the transmitting side; Figure
2.4.40 shows registers setting relevant to the receiving side.
Table 2.4.1 Setting examples of Baud rate generator values and transfer bit rate values (1)
BRG count source
(Note 1)
BRG setting value
Transfer bit rate (bps) (Note 2)
at f(X IN) = 4.9152 MH Z
at f(X IN ) = 8 MH Z
f(XIN)/4
255(FF 16)
300
488.28125
f(XIN)/4
127(7F 16)
600
976.5625
f(XIN)/4
63(3F16)
1200
1953.125
f(XIN)/4
31(1F16)
2400
3906.25
f(XIN)/4
15(0F16)
4800
7812.5
f(XIN)/4
7(07 16)
9600
15625
f(XIN)/4
3(03 16)
19200
31250
f(XIN)/4
1(01 16)
38400
62500
f(XIN)
3(03 16)
76800
125000
f(XIN)
1(01 16)
153600
250000
f(XIN)
0(00 16)
307200
500000
Table 2.4.2 Setting examples of Baud rate generator values and transfer bit rate values (2)
BRG count source
(Note 1)
BRG setting value
Transfer bit rate (bps) (Note 2)
at f(X IN) = 7.9872 MH Z
f(XIN)/4
207(CF16)
600
f(XIN)/4
103(6716)
1200
f(XIN)/4
51(3316)
2400
f(XIN)/4
25(1916)
4800
f(XIN)/4
12(0C 16)
9600
f(XIN)
25(1916)
19200
f(XIN)
12(0C 16)
38400
Notes 1: Select the BRG count source with bit 0 of the serial I/O1 control register (Address : 1A 16 ).
2: Equation of transfer bit rate:
Transfer bit rate (bps) =
f(XIN)
(BRG setting value + 1) ✕ 16 ✕ m✽
✽m: When bit 0 of the serial I/O1 control register (Address : 1A16 ) is set to “0”, a value of m
is 1.
When bit 0 of the serial I/O1 control register (Address : 1A 16 ) is set to “1”, a value of m
is 4.
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APPLICATION
2.4 Serial I/O
Transmitting side
Serial I/O1 status register (Address : 1916)
b7
b0
SIOSTS
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O1 control register (Address : 1A16)
b7
b0
SIOCON 1 0 0 1
0 0 1
BRG count source : f(XIN)/4
Serial I/O1 synchronous clock : BRG/16
SRDY1 output disabled
Transmit enabled
Receive disabled
Asynchronous serial I/O (UART)
Serial I/O1 enabled
UART control register (Address : 1B16)
b7
UARTCON
b0
0 1
0 0
Character length : 8 bits
Parity checking disabled
Stop bit length : 2 stop bits
TXD : CMOS output
Baud rate generator (Address : 1C16)
b7
BRG
b0
7
Set
f(XIN)
Transfer bit rate ✕ 16 ✕ m
✽
–1
✽ When bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “0” ,
a value of m is 1.
When bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “1” ,
a value of m is 4.
Fig. 2.4.39 Registers setting relevant to transmitting side
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APPLICATION
2.4 Serial I/O
Receiving side
Serial I/O1 status register (Address : 1916)
b7
b0
SIOSTS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : At completing reception
“0” : At reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Framing error flag
“1” : When stop bits cannot be detected at the specified timing.
Summing error flag
“1” : When any one of the following errors occurs.
• Overrun error
• Framing error
Serial I/O1 control register (Address : 1A16)
b7
SIOCON
b0
1 0 1 0
0 0 1
BRG count source : f(XIN)/4
Serial I/O1 synchronous clock : BRG/16
SRDY1 out disabled
Transmit disabled
Receive enabled
Asynchronous serial I/O(UART)
Serial I/O1 enabled
UART control register (Address : 1B16)
b7
b0
UARTCON
1
0 0
Character length selection bit : 8 bits
Parity enable bit : Parity checking disabled
Stop bit length selection bit : 2 stop bits
Baud rate generator (Address : 1C16)
b7
BRG
b0
7
f(XIN)
–1
Transfer bit rate ✕ 16 ✕ m ✽
✽ When bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “0” ,
a value of m is 1.
When bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “1” ,
a value of m is 4.
Set
Fig. 2.4.40 Registers setting relevant to receiving side
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APPLICATION
2.4 Serial I/O
Figure 2.4.41 shows a control procedure of the transmitting side, and Figure 2.4.42 shows a control
procedure of the receiving side.
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
1001x0012
SIOCON (Address : 1A16)
xxx01x002
UARTCON (Address : 1B16)
8–1
(Address : 1C16)
BRG
(Address : 0816), bit0
0
P4
(Address : 0916)
P4D
xxxxxxx12
• Port P40 set for communication control
N
Pass 10 ms?
• An interval of 10 ms generated by Timer
Y
P4 (Address : 0816), bit0
TB/RB (Address : 1816)
• Communication start
1
The first byte of a
transmission data
0
SIOSTS (Address : 1916), bit0?
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
1
TB/RB (Address : 1816)
The second byte of
a transmission data
SIOSTS (Address : 1916), bit0?
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
0
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
0
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
1
SIOSTS (Address : 1916), bit2?
1
P4 (Address : 0816), bit0
0
• Communication completion
Fig. 2.4.41 Control procedure of transmitting side
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APPLICATION
2.4 Serial I/O
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
.....
SIOCON (Address : 1A16)
UARTCON (Address : 1B16)
BRG
(Address : 1C16)
P4D
(Address : 0916)
1010x0012
xxxx1x002
8–1
xxxxxxx02
SIOSTS (Address : 1916), bit1?
0
• Judgment of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 1816)
SIOSTS (Address : 1916), bit6?
1
• Judgment of an error flag
0
• Judgment of completion of
receiving
(Receive buffer full flag)
0
SIOSTS (Address : 1916), bit1?
1
• Reception of the second byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 1816)
SIOSTS (Address : 1916), bit6?
1
• Judgment of an error flag
Processing for error
0
1
P4 (Address : 0816), bit0?
0
SIOCON (Address : 1A16)
SIOCON (Address : 1A16)
0000x0002
1010x0012
• Countermeasure for a bit slippage
Fig. 2.4.42 Control procedure of receiving side
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APPLICATION
2.4 Serial I/O
2.4.6 Notes on serial I/O
(1) Notes when selecting clock synchronous serial I/O (Serial I/O1)
➀ Stop of transmission operation
Clear the serial I/O1 enable bit and the transmit enable bit to “0” (Serial I/O1 and transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O1 enable bit to “0”
(Serial I/O1 disabled).
➂ Stop of transmit/receive operation
Clear the transmit enable bit and receive enable bit to “0” simultaneously (transmit and receive
disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O1 enable bit to
“0” (Serial I/O1 disabled) (refer to (1) ➀).
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APPLICATION
2.4 Serial I/O
(2) Notes when selecting clock asynchronous serial I/O (Serial I/O1)
➀ Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
➂ Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
(3) SRDY1 output of reception side
When signals are output from the SRDY1 pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY1 output enable bit, and
the transmit enable bit to “1” (transmit enabled).
(4) Setting serial I/O1 control register again (Serial I/O1)
Set the serial I/O1 control register again after the transmission and the reception circuits are reset
by clearing both the transmit enable bit and the receive enable bit to “0”.
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O1 control register
↓
Set both the transmit enable bit (TE) and
the receive enable bit (RE), or one of
them to “1”
Can be set with the LDM instruction at the same time
Fig. 2.4.43 Sequence of setting serial I/O1 control register again
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3850 Group (Spec. H) User’s Manual
APPLICATION
2.4 Serial I/O
(5) Data transmission control with referring to transmit shift register completion flag (Serial I/O1)
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(6) Transmission control when external clock is selected (Serial I/O1)
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the S CLK1 input level. Also, write the transmit data to the transmit buffer
register at “H” of the S CLK1 input level.
(7) Transmit interrupt request when transmit enable bit is set (Serial I/O1)
When the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as shown
in the following sequence.
➀ Set the interrupt enable bit to “0” (disabled) with CLB instruction.
➁ Prepare serial I/O for transmission/reception.
➂ Set the interrupt request bit to “0” with CLB instruction after 1 or more instruction has been
executed.
➃ Set the interrupt enable bit to “1” (enabled).
● Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”. The interrupt request is generated and the transmission
interrupt bit is set regardless of which of the two timings listed below is selected as the timing for
the transmission interrupt to be generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
(8) Transmit data writing (Serial I/O2)
In the clock synchronous serial I/O, when selecting an external clock as synchronous clock, write the
transmit data to the serial I/O2 register (serial I/O shift register) at “H” of the transfer clock input level.
3850 Group (Spec. H) User’s Manual
2-73
APPLICATION
2.5 PWM
2.5 PWM
This paragraph explains the registers setting method and the notes relevant to the PWM.
2.5.1 Memory map
Address
001D16
PWM control register (PWMCON)
001E16
PWM prescaler (PREPWM)
PWM register (PWM)
001F16
Fig. 2.5.1 Memory map of registers relevant to PWM
2.5.2 Relevant registers
PWM control register
b7 b6 b5 b4 b3 b2 b1 b0
PWM control register (PWMCON: address 1D16)
b
0
1
2
3
4
5
6
7
Name
Functions
PWM function
0 : PWM disabled
enable bit
1 : PWM enabled
Count source
0 : f(XIN)
selection bit
1 : f(XIN)/2
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
Fig. 2.5.2 Structure of PWM control register
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3850 Group (Spec. H) User’s Manual
At reset R W
0
0
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
APPLICATION
2.5 PWM
PWM prescaler
b7 b6 b5 b4 b3 b2 b1 b0
PWM prescaler
(PREPWM: address 1E16)
b
Functions
At reset R W
0 •Set the PWM period.
1 •The value set in this register is written to both
PWM prescaler pre-latch and PWM prescaler
2 latch at the same time.
3 • When data is written to this register during
PWM output, the pulse corresponding to
4 changed value is output at the next period.
5 • When this register is read out, the count value
of the PWM prescaler latch is read out.
6
Undefined
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Fig. 2.5.3 Structure of PWM prescaler
PWM register
b7 b6 b5 b4 b3 b2 b1 b0
PWM register
(PWM: address 1F16)
b
Functions
At reset R W
0 • Set the PWM “H” level output interval.
1 • The value set in this register is written to both
PWM register pre-latch and PWM register
2 latch at the same time.
3 • When data is written to this register during
PWM output, the pulse corresponding to
4 changed value is output at the next period.
5 • When this register is read out, the contents of
the PWM register latch is read out.
6
Undefined
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Fig. 2.5.4 Structure of PWM register
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APPLICATION
2.5 PWM
2.5.3 PWM output circuit application example
<Motor control>
Outline : The rotation speed of the motor is controlled by using PWM (pulse width modulation) output.
Figure 2.5.5 shows a connection diagram ; Figures 2.5.6 shows PWM output timing, and Figure 2.5.7
shows a setting of the related registers.
M
P44/PWM
D-A converter
Motor driver
3850 group
Fig. 2.5.5 Connection diagram
Specifications : • Motor is controlled by using the PWM output function of 8-bit resolution.
• Clock f(XIN) = 5.0 MHz
• “T”, PWM cycle : 102 µs
• “t”, “H” level width of output pulse : 40 µs (Fixed speed)
✽ A motor speed can be changed by modifying the “H” level width of output pulse.
t = 40 µs
PWM output
T = 102 µs
Fig. 2.5.6 PWM output timing
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APPLICATION
2.5 PWM
PWM control register (Address : 1D16)
b7
b0
0 1
PWMCON
PWM output: Enabled (Note)
Count source: f(XIN)
PWM prescaler (Address : 1E16)
b7
b0
n
PREPWM
Set “T”, PWM cycle
n=1
[Equation]
255 ✕ (n + 1)
T=
f(XIN)
Set “t”, “H” level width of PWM
m = 100
[Equation]
t= T✕m
255
PWM register (Address : 1F16)
b7
b0
m
PWM
Note: The PWM output function has priority even when bit 4 (corresponding bit to P44 pin)
of Port P4 direction register is set to “0” (input mode).
Fig. 2.5.7 Setting of relevant registers
<About PWM output>
1. Set the PWM function enable bit to “1” : The P44/PWM pin is used as the PWM pin.
The pulse beginning with “H” level pulse is output.
2. Set the PWM function enable bit to “0” : The P44/PWM pin is used as the port P44.
Thus, when fixing the output level, take the following procedure:
(1) Write an output value to bit 6 of the port P4 register.
(2) Write “000100002” to the port P4 direction register.
3. After data is set to the PWM prescaler and the PWM register, the PWM waveforms corresponding to updated
data will be output from the next repetitive cycle.
PWM output
Change PWM
output data
From the next repetitive cycle,
output modified data
Fig. 2.5.8 PWM output
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APPLICATION
2.5 PWM
Control procedure : By setting the related registers as shown by Figure 2.5.7, PWM waveforms are output to
the externals. This PWM output is integrated through the low pass filter, and that
converted into DC signals is used for control of the motor.
Figure 2.5.9 shows control procedure.
• X : This bit is not used here.
Set it to “0” or “1” arbitrarily.
P4 (Address : 0816), bit4
P4D (Address : 0916)
0
XXX1XXXX2
• “L” level output from P44/PWM pin
PREPWM (Address : 1E16)
PWM
(Address : 1F16)
PWMCON (Address : 1D16)
1
100
XXXXXX012
• PWM period setting
• “H” level width of PWM setting
• PWM count source selected, PWM output enabled
Fig. 2.5.9 Control procedure
2.5.4 Notes on PWM
The PWM starts after the PWM enable bit is set to enable and “L” level is output from the PWM pin.
The length of this “L“ level output is as follows:
2-78
n + 1
2 • f(XIN)
sec. (Count source selection bit = 0, where n is the value set in the prescaler)
n + 1
f(XIN)
sec. (Count source selection bit = 1, where n is the value set in the prescaler)
3850 Group (Spec. H) User’s Manual
APPLICATION
2.6 A-D converter
2.6 A-D converter
This paragraph explains the registers setting method and the notes relevant to the A-D converter.
2.6.1 Memory map
Address
003416
A-D control register (ADCON)
003516
A-D conversion register (low-order) (ADL)
003616
A-D conversion register (high-order) (ADH)
003D16
Interrupt request register 2 (IREQ2)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.6.1 Memory map of registers relevant to A-D converter
2.6.2 Relevant registers
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register
(ADCON: address 3416)
b
Name
0 Analog input pin
selection bits
1
2
Functions
b2 b1 b0
0 0 0: P30/AN0
0 0 1: P31/AN1
0 1 0: P32/AN2
0 1 1: P33/AN3
1 0 0: P34/AN4
3 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
4 AD conversion
0: Conversion in progress
1: Conversion completed
completion bit
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read
7 out, the contents are “0”.
At reset R W
0
0
0
0
1
0
0
0
Fig. 2.6.2 Structure of A-D control register
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APPLICATION
2.6 A-D converter
A-D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (high-order)
(ADH: address 3616)
b
Functions
At reset R W
0 This is A-D conversion result stored bits. This is Undefined
read exclusive register.
10-bit read b0
b7
1
Undefined
b9 b8
2 Nothing is arranged for these bits. These are
3 write disabled bits. When these bits are read out,
4 the contents are “0”.
5
6
7
0
0
0
0
0
0
Fig. 2.6.3 Structure of A-D conversion register (high-order)
A-D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (low-order)
(ADL: address 3516)
b
Functions
0 This is A-D conversion result stored bits. This is
1 read exclusive register.
2
8-bit read
b7
b0
3
b9 b8 b7 b6 b5 b4 b3 b2
4
5
10-bit read
b7
b0
6
b7 b6 b5 b4 b3 b2 b1 b0
7
Fig. 2.6.4 Structure of A-D conversion register (low-order)
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3850 Group (Spec. H) User’s Manual
At reset R W
Undefined
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
APPLICATION
2.6 A-D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
Name
0 Timer 1 interrupt
request bit
1 Timer 2 interrupt
request bit
2 Serial I/O1 receive
interrupt request bit
3 Serial I/O1 transmit
interrupt request bit
4 CNTR0 interrupt
request bit
5 CNTR1 interrupt
request bit
6 A-D converter
interrupt request bit
Functions
At reset R W
0 : No interrupt request issued
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
✽: “0” can be set by software, but “1” cannot be set.
0
Fig. 2.6.5 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
0
Timer 1 interrupt
enable bit
Timer 2 interrupt
enable bit
Serial I/O1 receive
interrupt enable bit
Serial I/O1 transmit
interrupt enable bit
CNTR0 interrupt
enable bit
CNTR1 interrupt
enable bit
A-D converter
interrupt enable bit
Fix this bit to “0”.
1
2
3
4
5
6
7
Functions
At reset R W
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
0
0
Fig. 2.6.6 Structure of Interrupt control register 2
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APPLICATION
2.6 A-D converter
2.6.3 A-D converter application examples
(1) Conversion of analog input voltage
Outline : The analog input voltage input from a sensor is converted to digital values.
Figure 2.6.7 shows a connection diagram, and Figure 2.6.8 shows the relevant registers setting.
Sensor
P30/AN0
3850 Group
Fig. 2.6.7 Connection diagram
Specifications : •The analog input voltage input from a sensor is converted to digital values.
•P3 0/AN0 pin is used as an analog input pin.
A-D control register (address 3416)
b7
ADCON
b0
0
0 0 0
Analog input pin : P30/AN0 selected
A-D conversion start
A-D conversion register (high-order); (address 3616)
b7
b0
(Read-only)
ADH
A-D conversion register (low-order); (address 3516)
b7
b0
(Read-only)
ADL
A result of A-D conversion is stored (Note).
Note: After bit 4 of ADCON is set to “1”, read out that contents.
When reading 10-bit data, read address 003616 before address 003516;
when reading 8-bit data, read address 003516 only.
Fig. 2.6.8 Relevant registers setting
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APPLICATION
2.6 A-D converter
An analog input signal from a sensor is converted to the digital value according to the relevant
registers setting shown by Figure 2.6.8. Figure 2.6.9 shows the control procedure for 8-bit read, and
Figure 2.6.10 shows the control procedure for 10-bit read.
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
ADCON (address 3416)
•P30/AN0 pin selected as analog input pin
•A-D conversion start
XXX0X0002
0
ADCON (address 3416), bit4 ?
•Judgment of A-D conversion completion
1
•Read out of conversion result
Read out ADL (address 3516)
Fig. 2.6.9 Control procedure for 8-bit read
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
ADCON (address 3416)
•P30/AN0 pin selected as analog input pin
•A-D conversion start
XXX0X0002
0
ADCON (address 3416), bit4 ?
•Judgment of A-D conversion completion
1
Read out ADH (address 3616)
•Read out of high-order digit (b9, b8) of conversion result
Read out ADL (address 3516)
•Read out of low-order digit (b7 – b0) of conversion result
Fig. 2.6.10 Control procedure for 10-bit read
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APPLICATION
2.6 A-D converter
2.6.4 Notes on A-D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the
user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
(2) A-D converter power source pin
The AVSS pin is A-D converter power source pin. Regardless of using the A-D conversion function
or not, connect it as following :
• AV SS : Connect to the VSS line
● Reason
If the AV SS pin is opened, the microcomputer may have a failure because of noise or others.
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D conversion.
• f(XIN) is 500 kHz or more in middle-/high-speed mode.
• Do not execute the STP instruction.
• When the A-D converter is operated at low-speed mode, f(X IN) do not have the lower limit of
frequency, because of the A-D converter has a built-in self-oscillation circuit.
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APPLICATION
2.7 Watchdog timer
2.7 Watchdog timer
This paragraph explains the registers setting method and the notes relevant to the watchdog timer.
2.7.1 Memory map
Address
003916
Watchdog timer control register (WDTCON)
003B16
CPU mode register (CPUM)
Fig. 2.7.1 Memory map of registers relevant to watchdog timer
2.7.2 Relevant registers
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register
(WDTCON: address 3916)
b
Name
Functions
0 Watchdog timer H
1 (for read-out of high-order 6 bit)
2
3
4
5
6 STP instruction
0: STP instruction enabled
1: STP instruction disabled
disable bit
7 Watchdog timer H 0: Watchdog timer L
underflow
count source selection
1: f(XIN)/16 or f(XCIN)/16
bit
At reset R W
1
✕
✕
1
1
✕
✕
1
1
✕
✕
1
0
0
Fig. 2.7.2 Structure of Watchdog timer control register
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.7 Watchdog timer
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
CPU mode register
(CPUM: address 3B16)
b
Name
0 Processor mode
bits
1
2 Stack page
selection bit
3 Fix this bit to “1”.
Functions
b1 b0
00 : Single-chip mode
01 :
10 :
Not available
11 :
0 : 0 page
1 : 1 page
0
0
0
1
4 Port Xc switch bit
0: I/O port function
(stop oscillating)
1: XCIN-XCOUT oscillation
function
0
5 Main clock (XINXOUT) stop bit
6 Main clock division
ratio selection bits
0: Oscillating
1: Stopped
0
b7 b6
1
7
0 0: φ=f(XIN)/2
(high-speed mode)
0 1: φ=f(XIN)/8
(middle-speed mode)
1 0: φ=f(XCIN)/2
(low-speed mode)
1 1: not available
Fig. 2.7.3 Structure of CPU mode register
2-86
At reset R W
3850 Group (Spec. H) User’s Manual
0
APPLICATION
2.7 Watchdog timer
2.7.3 Watchdog timer application examples
(1) Detection of program runaway
Outline: If program runaway occurs, let the microcomputer reset, using the internal timer for detection
of program runaway.
Specifications: •An underflow of watchdog timer H is judged to be program runaway, and the
microcomputer is returned to the reset status.
•Before the watchdog timer underflows, “0” is set into bits 6 and 7 of the watchdog
timer control register at every cycle in a main routine.
•High-speed mode is used as a main clock division ratio.
•An underflow signal of the watchdog timer L is supplied as the count source of
watchdog timer H.
Figure 2.7.4 shows a watchdog timer connection and division ratio setting; Figure 2.7.5 shows the
relevant registers setting; Figure 2.7.6 shows the control procedure.
Fixed
f(XIN) = 8 MHz
1/16
Watchdog timer L Watchdog timer H
1/256
1/256
Reset
circuit
Internal reset
RESET
STP instruction disable bit
STP instruction
Fig. 2.7.4 Watchdog timer connection and division ratio setting
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.7 Watchdog timer
CPU mode register (address 3B16)
b7
CPUM
0 0 0
b0
1
0 0
Processor mode: Single-chip mode
Fix to “1”
Main clock (XIN-XOUT): Operating
Main clock division ratio: f(XIN)/2 (high-speed mode)
Watchdog timer control register (address 3916)
b7
WDTCON
b0
0 0
Watchdog timer H (for read-out of high-order 6 bits)
Enable STP instruction
Watchdog timer H count source: Watchdog timer L underflow
Fig. 2.7.5 Relevant registers setting
RESET
Initialization
SEI
CLT
CLD
CPUM (address 3B16)
:
:
CLI
•All interrupts disabled
000X1X002
•Interrupts enabled
WDTCON (address 3916), bit7, bit6
Main processing
:
:
•Processor mode: Single-chip mode
•Main clock f(XIN): Operating
•High-speed mode selected as main clock division ratio
002
•Watchdog timer L underflow selected as Watchdog
timer H count source
•STP instruction enabled
(“FF16” is set to Watchdog timer H and Watchdog
timer L, respectively.)
Fig. 2.7.6 Control procedure
2.7.4 Notes on watchdog timer
●Make sure that the watchdog timer does not underflow while waiting Stop release, because the watchdog
timer keeps counting during that term.
●When the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program.
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3850 Group (Spec. H) User’s Manual
APPLICATION
2.8 Reset
2.8 Reset
2.8.1 Connection example of reset IC
VCC
1
Power source
M62022L
5
Output
RESET
Delay capacity
4
GND
0.1 µF
3
VSS
3850 Group
Fig. 2.8.1 Example of poweron reset circuit
Figure 2.8.2 shows the system example which switches to the RAM backup mode by detecting a drop of
the system power source voltage with the INT interrupt.
System power
source voltage
+5 V
VCC
+
7
VCC1
RESET 5
2
VCC2
INT
3
RESET
INT
VSS
1
V1
GND
4
Cd
6
3850 Group
M62009L,M62009P,M62009FP
Fig. 2.8.2 RAM backup system
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.8 Reset
2.8.2 Notes on RESET pin
(1) Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the V SS pin. Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
(2) Reset release after power on
When releasing the reset after power on, such as power-on reset, release reset after XIN passes more
than 20 cycles in the state where the power supply voltage is 2.7 V or more and the XIN oscillation
is stable.
● Reason
To release reset, the RESET pin must be held at an “L” level for 20 cycles or more of XIN in the
state where the power source voltage is between 2.7 V and 5.5 V, and X IN oscillation is stable.
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APPLICATION
2.9 Clock generating circuit
2.9 Clock generating circuit
This paragraph explains how to set the registers relevant to the clock generating circuit and describes an
application example.
2.9.1 Relevant registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
CPU mode register
(CPUM: address 3B16)
b
Name
0 Processor mode
bits
1
2 Stack page
selection bit
3 Fix this bit to “1”.
Functions
b1 b0
00 : Single-chip mode
01 :
10 :
Not available
11 :
0 : 0 page
1 : 1 page
At reset R W
0
0
0
1
4 Port Xc switch bit
0: I/O port function
(stop oscillating)
1: XCIN-XCOUT oscillation
function
0
5 Main clock (XINXOUT) stop bit
6 Main clock division
ratio selection bits
0: Oscillating
1: Stopped
0
b7 b6
1
7
0 0: φ=f(XIN)/2
(high-speed mode)
0 1: φ=f(XIN)/8
(middle-speed mode)
1 0: φ=f(XCIN)/2
(low-speed mode)
1 1: not available
0
Fig. 2.9.1 Structure of CPU mode register
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APPLICATION
2.9 Clock generating circuit
2.9.2 Clock generating circuit application example
(1) Status transition during power failure
Outline: The clock counts up every second by using the timer interrupt during a power failure.
Input port
(Note)
Power failure detection signal
3850 Group
Note: A signal is detected when input to input port, interrupt
input pin, or analog input pin.
Fig. 2.9.2 Connection diagram
Specifications: •Reducing power dissipation as low as possible while maintaining clock function
•Clock: f(X IN) = 8 MHz, f(X CIN) = 32.768 kHz
•Port processing
Input port: Fixed to “H” or “L” level externally.
Output port: Fixed to output level that does not cause current flow to the external.
(Example) Fix to “H” for an LED circuit that turns on at “L” output
level.
I/O port: Input port → Fixed to “H” or “L” level externally.
Output port → Output of data that does not consume current
VREF pin: Stop VREF current dissipation by terminating A-D conversion operation.
Figure 2.9.3 shows the status transition diagram during power failure and Figure 2.9.4 shows the
setting of relevant registers.
Reset released
Power failure detected
XIN
XCIN
Internal system clock
Middle-speed
mode
Low-speed mode
High-speed mode
Change internal system
clock to high-speed mode
After detection, change internal system clock to
low-speed mode and stop oscillating XIN-XOUT
XCIN-XCOUT oscillation function selected
Fig. 2.9.3 Status transition diagram during power failure
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2.9 Clock generating circuit
CPU mode register (address 3B16)
b7
b0
CPUM 0 0 0 0 1
0 0
Main clock: High-speed mode (f(XIN)/2) (Note 1)
CPU mode register (address 3B16)
b7
b0
CPUM 0 0 0 1 1
0 0
(Note 2)
Port XC: XCIN–XCOUT oscillation function
CPU mode register (address 3B16)
b7
b0
CPUM 1 0 0 1 1
0 0
Internal system clock: Low-speed mode (f(XCIN)/2)
CPU mode register (address 3B16)
b7
CPUM
b0
1 0 1 1 1
0 0
Main clock f(XIN): Stopped
Notes 1: This setting is necessary only when selecting the high-speed mode.
2: When selecting the middle-speed mode, bit 6 is “1”.
Fig. 2.9.4 Setting of relevant registers
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2.9 Clock generating circuit
Control procedure: To prepare for a power failure, set the relevant registers in the order shown
below.
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
••••
CPUM (address 3B16), bit7, bit 6
CPUM (address 3B16), bit 4
0, 0
1
When selecting main clock f(XIN)/2 (high-speed mode)
Port XC: XCIN-XCOUT oscillation function
••••
N
Detect power failure ?
≈
Y
CPUM (address 3B16), bit7, bit 6
CPUM (address 3B16), bit5
1, 0 (Note)
1 (Note)
Set timer interrupt to occurs every second.
Execute WIT instruction.
N
Internal system clock: f(XCIN)/2 (low-speed mode)
Main clock f(XIN) oscillation stopped
At power failure, clock count is performed during
timer interrupt processing (every second).
Return condition from power failure
completed ?
Y
Return processing from power failure
Note: Do not switch simultaneously.
≈
Fig. 2.9.5 Control procedure
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2.10 Standby function
2.10 Standby function
The 3850 group is provided with standby functions to stop the CPU by software and put the CPU into the
low-power operation.
The following two types of standby functions are available.
•Stop mode using STP instruction
•Wait mode using WIT instruction
2.10.1 Relevant registers
MISRG
b7 b6 b5 b4 b3 b2 b1 b0
MISRG
(MISRG: address 3816)
b
Name
Functions
0 Oscillation stabilizing 0: Automatically set (Note 1)
time set after STP
1: Autimatically set disabled
instruction released bit
1 Middle-speed mode 0: Not set automatically
automatic switch set 1: Automatic switching
enabled (Note 2)
bit
2 Middle-speed mode 0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
automatic switch
wait time set bit
3 Middle-speed mode 0: Invalid
1: Automatic switch start
automatic switch
(Note 2)
start bit
(Depending on
program)
4 Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
5
out, the contents are “0”.
6
At reset R W
0
0
0
0
0
0
0
✕
✕
✕
✕
0
7
Notes 1: “0116” is set to Timer 1, “FF16” is set to Prescaler 12.
2: When automatic switch to middle-speed mode from low-speed mode occurs,
the values of CPU mode register (003B16) change.
Fig. 2.10.1 Structure of MISRG
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2.10 Standby function
2.10.2 Stop mode
The stop mode is set by executing the STP instruction. In the stop mode, the oscillation of both clocks
(XIN–X OUT, XCIN–X COUT) stop and the internal clock φ stops at the “H” level. The CPU stops and peripheral
units stop operating. As a result, power dissipation is reduced.
(1) State in stop mode
Table 2.10.1 shows the state in the stop mode.
Table 2.10.1 State in stop mode
State in stop mode
Item
CPU
Stopped.
Stopped.
Internal clock φ
Stopped at “H” level.
I/O ports P0–P4
Retains the state at the STP instruction execution.
Timer
Stopped. (Timers 1, 2, X, Y)
Oscillation
However, Timers X and Y can be operated in the event counter
mode.
Watchdog timer
Stopped.
Stopped.
Serial I/O1, Serial I/O2
Stopped.
PWM
However, these can be operated only when an external clock
is selected.
A-D converter
2-96
Stopped.
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2.10 Standby function
(2) Release of stop mode
The stop mode is released by a reset input or by the occurrence of an interrupt request. Note the
differences in the restoration process according to reset input or interrupt request, as described
below.
■Restoration by reset input
The stop mode is released by holding the RESET pin to the “L” input level during the stop mode.
Oscillation is started when all ports are in the input state and the stop mode of the main clock (XINXOUT) is released.
Oscillation is unstable when restarted. For this reason, time for stabilizing of oscillation (oscillation
stabilizing time) (Note) is required. The input of the RESET pin should be held at the “L” level until
oscillation stabilizes.
When the RESET pin is held at the “L” level for 20 cycles or more of X IN after the oscillation has
stabilized, the microcomputer will go to the reset state. After the input level of the RESET pin is
returned to “H”, the reset state is released in approximately 10.5 to 18.5 cycles of the X IN input.
Figure 2.10.2 shows the oscillation stabilizing time at restoration by reset input.
At release of the stop mode by reset input, the internal RAM retains its contents previous to the
reset. However, the previous contents of the CPU register and SFR are not retained.
For more details concerning reset, refer to “2.8 Reset”.
Note: For the setting of oscillation stabilizing time, refer to MISRG (address 0038 16).
Stop mode
Oscillation
20 cycles or
stabilizing time more of XIN
Operating mode
Vcc
Time to hold internal reset state =
approximately 10.5 to 18.5 cycles of XIN input
RESET
XIN
(Note)
Execute Stop instruction
Note: Some cases may occur in which no waveform is input to XIN (in low-speed mode).
Fig. 2.10.2 Oscillation stabilizing time at restoration by reset input
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2.10 Standby function
■Restoration by interrupt request
The occurrence of an interrupt request in the stop mode releases the stop mode. As a result,
oscillation is resumed. The interrupts available for restoration are:
•INT 0–INT 3
•CNTR 0, CNTR1
•Serial I/O (1, 2) using an external clock
•Timer X, Y using an external event count
However, when using any of these interrupt requests for restoration from the stop mode, in order
to enable the selected interrupt, you must execute the STP instruction after setting the following
conditions.
[Necessary register setting]
➀ Interrupt disable flag I = “0” (interrupt enabled)
➁ Timer 1 interrupt enable bit = “0” (interrupt disabled)
➂ Interrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request
issued)
➃ Interrupt enable bit of interrupt source to be used for restoration = “1” (interrupts enabled)
For more details concerning interrupts, refer to “2.2 Interrupts”.
Oscillation is unstable when restarted. For this reason, time for stabilizing of oscillation (oscillation
stabilizing time) is required. For restoration by an interrupt request, waiting time prior to supplying
internal clock φ to the CPU is automatically generated ✽2 by Prescaler 12 and Timer 1 ✽1. This
waiting time is reserved as the oscillation stabilizing time on the system clock side. The supply of
internal clock φ to the CPU is started at the Timer 1 underflow.
Figure 2.10.3 shows an execution sequence example at restoration by the occurrence of an INT 0
interrupt request.
✽1: If the STP instruction is executed when the oscillation stabilizing time set after STP instruction
released bit is “0”, “FF16” and “0116” are automatically set in the Prescaler 12 counter/latch and
Timer 1 counter/latch, respectively. When the oscillation stabilizing time set after STP instruction
released bit is “1”, nothing is automatically set to either Prescaler 12 or Timer 1. For this
reason, any suitable value can be set to Prescaler 12 and Timer 1 for the oscillation stabilizing
time.
✽2: Immediately after the oscillation is started, the count source is supplied to the prescaler 12
so that a count operation is started.
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2.10 Standby function
●When restoring microcomputer from stop mode by INT0 interrupt (rising edge selected)
Stop mode
XIN or XCIN
(System clock)
Oscillation stabilizing time
XIN; “H”
XCIN; in high-impedance state
INT0 pin
512 counts
“FF16”
Prescaler 12 counter
“0116”
Timer 1 counter
INT0 interrupt request bit
Peripheral device
Operating
CPU
Operating
Operating
Stopped
Operating
Stopped
Execute STP
instruction
INT0 interrupt signal
input (INT0 interrupt
request occurs)
Oscillation start
Prescaler 12 count start
512 counts down by
prescaler 12
Start supplying internal
clock φ to CPU
Accept INT0 interrupt
request
Note: f(XIN)/16 or f(XCIN)/16 is input as the prescaler 12 count source.
Fig. 2.10.3 Execution sequence example at restoration by occurrence of INT0 interrupt request
(3) Notes on using stop mode
■Register setting
Since values of the prescaler 12 and Timer 1 are automatically reloaded when returning from the
stop mode, set them again, respectively. (When the oscillation stabilizing time set after STP
instruction released bit is “0”)
■Clock restoration
After restoration from the stop mode to the normal mode by an interrupt request, the contents of
the CPU mode register previous to the STP instruction execution are retained. Accordingly, if both
main clock and sub clock were oscillating before execution of the STP instruction, the oscillation
of both clocks is resumed at restoration.
In the above case, when the main clock side is set as a system clock, the oscillation stabilizing
time for approximately 8,000 cycles of the XIN input is reserved at restoration from the stop mode.
At this time, note that the oscillation on the sub clock side may not be stabilized even after the
lapse of the oscillation stabilizing time of the main clock side.
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2.10 Standby function
2.10.3 Wait mode
The wait mode is set by execution of the WIT instruction. In the wait mode, oscillation continues, but the
internal clock φ stops at the “H” level.
The CPU stops, but most of the peripheral units continue operating.
(1) State in wait mode
The continuation of oscillation permits clock supply to the peripheral units. Table 2.10.2 shows the
state in the wait mode.
Table 2.10.2 State in wait mode
State in wait mode
Item
Oscillation
Operating.
CPU
Internal clock φ
Stopped.
I/O ports P0–P4
Timer
Retains the state at the WIT instruction execution.
Operating.
PWM
Operating.
Watchdog timer
Operating.
Serial I/O1, Serial I/O2
A-D converter
Operating.
2-100
Stopped at “H” level.
Operating.
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2.10 Standby function
(2) Release of wait mode
The wait mode is released by reset input or by the occurrence of an interrupt request. Note the
differences in the restoration process according to reset input or interrupt request, as described
below.
In the wait mode, oscillation is continued, so an instruction can be executed immediately after the
wait mode is released.
■Restoration by reset input
The wait mode is released by holding the input level of the RESET pin at “L” in the wait mode.
Upon release of the wait mode, all ports are in the input state, and supply of the internal clock
φ to the CPU is started. To reset the microcomputer, the RESET pin should be held at an “L” level
for 20 cycles or more of XIN. The reset state is released in approximately 10.5 cycles to 18.5 cycles
of the X IN input after the input of the RESET pin is returned to the “H” level.
At release of wait mode, the internal RAM retains its contents previous to the reset. However, the
previous contents of the CPU register and SFR are not retained.
Figure 2.10.4 shows the reset input time.
For more details concerning reset, refer to “2.8 Reset”.
Operating mode
Wait mode
Vcc
20 cycles of XIN
Time to hold internal reset state =
approximately 10.5 to 18.5 cycles of XIN input
RESET
XIN
(Note)
Execute WIT instruction
Note: Some cases may occur in which no waveform is input to XIN (in low-speed mode).
Fig. 2.10.4 Reset input time
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2.10 Standby function
■Restoration by interrupt request
In the wait mode, the occurrence of an interrupt request releases the wait mode and supply of the
internal clock φ to the CPU is started. At the same time, the interrupt request used for restoration
is accepted, so the interrupt processing routine is executed.
However, when using an interrupt request for restoration from the wait mode, in order to enable
the selected interrupt, you must execute the WIT instruction after setting the following conditions.
[Necessary
➀ Interrupt
➁ Interrupt
issued)
➂ Interrupt
register setting]
disable flag I = “0” (interrupt enabled)
request bit of interrupt source to be used for restoration = “0” (no interrupt request
enable bit of interrupt source to be used for restoration = “1” (interrupts enabled)
For more details concerning interrupts, refer to “2.2 Interrupts”.
(3) Notes on wait mode
■Clock restoration
If the wait mode is released by a reset when XCIN is set as the system clock and XIN oscillation is
stopped during execution of the WIT instruction, X CIN oscillation stops, XIN oscillations starts, and
X IN is set as the system clock.
In the above case, the RESET pin should be held at “L” until the oscillation is stabilized.
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2.11 Flash memory mode
2.11 Flash memory mode
This paragraph explains the registers setting method and the notes relevant to the flash memory version.
2.11.1 Overview
The functions of the flash memory version are similar to those of the mask ROM version except that the
flash memory is built-in and some of the SFR area differ from that of the mask ROM version (refer to
“2.11.2 Memory map”).
In the flash memory version, the built-in flash memory can be programmed or erased by using the following
three modes.
• CPU rewrite mode
• Parallel I/O mode
• Standard serial I/O mode
2.11.2 Memory map
M38507F8FP/SP have 32 Kbytes of built-in flash memory.
Figure 2.11.1 shows the memory map of the flash memory version.
000016
SFR area
004016
Internal RAM
area
(1 Kbyte)
RA M
043F16
044016
User ROM area
Not used
800016
0FF016
SFR area
0FFF16
100016
Not used
32 Kbytes
800016
Reserved ROM area
808016
Built-in flash memory
area
(32 Kbytes)
FFFF16
FFFF16
Boot ROM area
F00016
4 Kbytes
FFFF16
Note: Access to boot ROM area
Pararell I/O mode
CPU rewrite mode
Standard serial mode
Read/Write avilable
Read only available
Read only available
Fig. 2.11.1 Memory map of flash memory version for 3850 Group
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2.11 Flash memory mode
2.11.3 Relevant registers
Address
0FFE16
Flash memory control register (FMCR)
Fig. 2.11.2 Memory map of registers relevant to flash memory
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Flash memory control register
(FMCR : address 0FFE16)
b
Name
0 RY/BY status flag
Functions
0 : Busy (being written or
erased)
1 : Ready
At reset R W
1
0
0 : Normal mode (Software
commands invalid)
1 : CPU rewrite mode
(Software commands
acceptable)
CPU rewrite mode
0: Normal mode
0
entry flag
1: CPU rewrite mode
Flash memory reset 0: Normal operation
0
bit (Note 2)
1: Reset
User area/Boot
0: User ROM area
0
area selection bit
1: Boot ROM area
Nothing is arranged for these bits. When write, Undefined
set “0”. When these bits are read out, the
Undefined
contents are undefined.
Undefined
1 CPU rewrite mode
select bit (Note 1)
2
3
4
5
6
7
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession.
2: In order to perform flash memory reset by setting of this bit, set
this bit to “1” in state of the CPU rewriting mode select bit = “1”,
and then set to “0” to release the reset state.
Fig. 2.11.3 Structure of Flash memory control register
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2.11 Flash memory mode
2.11.4 Parallel I/O mode
In the parallel I/O mode, program/erase to the built-in flash memory can be performed by a EPROM
programmer (EFP-I).
The memory area of program/erase is from 0F000 16 to 0FFFF 16 (boot ROM area) or from 08000 16 to
0FFFF16 (user ROM area). Be especially careful when erasing; if the memory area is not set correctly, the
products will be damaged eternally.
Table 2.11.1 shows the setting of programmers when programming in the parallel I/O mode.
•EFP-I provided by Suisei Electronics System Co., Ltd. (http://www.suisei.co.jp/index_e.htm)
(product available in Asia and Oceania only)
Table 2.11.1 Setting of programmers when parallel programming
Products
M38507F8FP
Parallel unit
EF3850F-42E
M38507F8SP
EF3850F-42S
Boot ROM area
User ROM area
0F00016 to 0FFFF16
08000 16 to 0FFFF16
2.11.5 Standard serial I/O mode
Table 2.11.2 shows a pin connection example (4 wires) between the programmer (EFP-I; Serial unit
EF1SRP-01U is required additionally) and the microcomputer when programming in the serial I/O mode.
•EFP-I provided by Suisei Electronics System Co., Ltd. (http://www.suisei.co.jp/index_e.htm)
(product available in Asia and Oceania only)
Table 2.11.2 Connection example to programmer when serial programming (4 wires)
Function
3850 Group flash memory version
EFP-I (EF1SRP-01U)
EF1RP-01U side
Signal name
Pin name
Pin number
connector Line number
T_SCLK1
9
P26/SCLK1
10
Serial data input
T_RXD
P25/TxD
11
Serial data output
T_TXD
11
10
P24/RxD
12
12
P27/CNTR0/SRDY1
9
3
14
CNVSS
RESET (Note 1)
15
18
4
VCC (Note 2)
Transfer clock input
Transmit/Receive enable output
5 V input
T_BUSY
T_VPP
T_RESET
Reset input
Target board power source monitor input T_VDD (Note 2)
GND (Note 3)
GND
1
VSS, AVSS (Note 3)
21, 3
Notes 1: Since reset release after write verification is not performed, when operating MCU after writing,
separate a target connection cable.
2: Supply Vcc of EFP-I side from user side so that the power supply voltage of the output buffer used
by the EFP-I side becomes the same as user side power supply voltage (Vcc).
3: Four pins (No. 1, 2, 15, and 16) of the EF1SRP-01U side connector are prepared for GND signal.
When connecting with a target board, although connection of only one pin does not have a
problem, we recommend connecting with two or more pins.
1, 2, 15, 16
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2.11 Flash memory mode
2.11.6 CPU rewrite mode
In the CPU rewrite mode, issuing software commands through the Central Processing Unit (CPU) can
rewrite the built-in flash memory. Accordingly, the contents of the built-in flash memory can be rewritten
with the microcomputer itself mounted on board, without using the programmer.
Store the rewrite control program to the built-in flash memory in advance. The built-in flash memory cannot
be read in the CPU rewrite mode. Accordingly, after transferring the rewrite control program to the internal
RAM, execute it on the RAM.
The following commands can be used in the CPU rewrite mode: read array, read status register, clear
status register, program, erase all block, and block erase. For details concerning each command, refer to
“CHAPTER 1 Flash memory mode (CPU rewrite mode)”.
(1) CPU rewrite mode beginning/release procedures
Operation procedure in the CPU rewrite mode for the built-in flash memory is described below.
As for the control example, refer to “2.11.7 (2) Control example in the CPU rewrite mode”.
[Beginning procedure]
➀ Apply 5 V±10 % to the CNVSS/VPP pin (at selecting boot ROM area).
➁ Release reset.
➂ Set bits 6 and 7 (main clock division ratio selection bits) of the CPU mode register.
➃ After CPU rewrite mode control program is transferred to internal RAM, jump to this control
program on RAM. (The following operations are controlled by this control program).
➄ Apply 5 V±10 % to the CNVSS/V PP pin (in single-chip mode).
➅ Set “1” to the CPU rewrite mode select bit (bit 1 of address 0FFE 16 ).
For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession.
➆ Read the CPU rewrite mode entry flag (bit 2 of address 0FFE16) to confirm that the CPU rewrite
mode is set to “1”.
➇ Flash memory operations are executed by using software commands.
Note: The following procedures are also necessary.
• Control for data which is input from the external (serial I/O etc.) and to be programmed
to the flash memory.
• Initial setting for ports, etc.
• Writing to the watchdog timer
[Release procedure]
➀ Execute the read command or set the flash memory reset bit (bit 3 of address 0FFE16).
➁ Set the CPU rewrite mode select bit (bit 0 of address 0FFE 16) to “0”.
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2.11 Flash memory mode
Also, execute the following processing before the CPU reprogramming mode is selected so that
interrupts will not occur during the CPU reprogramming mode.
• Set the interrupt disable flag (I) to “1”
When the watchdog timer has already started, write to the watchdog timer control register (address
1E 16) periodically during the CPU reprogramming mode in order not to generate the reset by the
underflow of the watchdog timer H.
During the program or erase execution, watchdog timer is automatically cleared. Accordingly, the
inernal reset by underflow does not occur.
When the interrupt request or reset occurs in the CPU reprogramming mode, the microcomputer
enters the following state;
• Interrupt occurs
This may cause a program runaway because the read from the flash memory which has the interrupt
vector area cannot be performed.
• Underflow of watchdog timer H, reset
This may cause a microcomputer reset; the built-in flash memory control circuit and the flash memory
control register are reset. When reset state is released with CNVss = “H”, CPU starts in the boot
mode.
Also, when the above interrupt and reset occur during program/erase, error data may still exist after
reset release because the reprogramming of the flash memory is not completed, so that reprogramming
of the flash memory in the parallel I/O mode or serial I/O mode is required.
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2.11 Flash memory mode
2.11.7 Flash memory mode application examples
The control pin processing example on the system board in the serial I/O mode and the control example
in the CPU rewrite mode are described below.
(1) Control pin connection example on the system board in serial I/O mode
As shown in Figure 2.11.4, in the serial I/O mode, the built-in flash memory can be rewritten with the
microcomputer mounted on board. Connection examples of control pins (P2 4 /RxD, P2 5 /TxD,
P2 6/SCLK1, P2 7/SRDY1, P4 1, CNVSS, and RESET pin) in the serial I/O mode are described below.
RS-232C
Serial programmer
M3
85
07
F8
FP
/S
P
Fig. 2.11.4 Rewrite example of built-in flash memory in serial I/O mode
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2.11 Flash memory mode
➀ When control signals are not affected to user system circuit
When the control signals in the serial I/O mode are not used or not affected to the user system
circuit, they can be connected as shown in Figure 2.11.5.
Target board
✽1
Not used or to user system circuit
M38507F8FP/SP
✽2
TXD(P25)
SCLK1(P26)
RXD(P24)
BUSY(P27)
(P41)
VPP(CNVSS)
RESET
VCC
AVSS
VSS
XIN XOUT
User reset signal (Low active)
✽1: When not used, set to input mode and pull up or pull down, or set to output mode and open.
✽2: It is necessary to apply Vcc to SCLK1 (P26) pin only when reset is released in the serial I/O mode.
Fig. 2.11.5 Connection example in serial I/O mode (1)
➁ When control signals are affected to user system circuit-1
Figure 2.11.6 shows an example that the jumper switch cut-off the control signals not to supply
to the user system circuit in the serial I/O mode.
Target board
To user system circuit
M38507F8FP/SP
TXD(P25)
✽
SCLK1(P26)
RXD(P24)
BUSY(P27)
(P41)
VPP(CNVSS)
RESET
VCC
AVSS
VSS
XIN XOUT
User reset signal (Low active)
✽: It is necessary to apply Vcc to SCLK1 (P26) pin only when reset is released in the serial I/O mode.
Fig. 2.11.6 Connection example in serial I/O mode (2)
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2.11 Flash memory mode
➂ When control signals are affected to user system circuit-2
Figure 2.11.7 shows an example that the analog switch (74HC4066) cut-off the control signals not
to supply to the user system circuit in the serial I/O mode.
Target board
74HC4066
To user system circuit
M38507F8FP/SP
✽
TXD(P25)
SCLK1(P26)
RXD(P24)
BUSY(P27)
VCC
(P41)
AVSS
VSS
VPP(CNVss)
RESET
XIN XOUT
User reset signal (Low active)
✽: It is necessary to apply Vcc to SCLK1 (P26) pin only when reset is released in the serial I/O mode.
Fig. 2.11.7 Connection example in serial I/O mode (3)
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2.11 Flash memory mode
(2) Control example in CPU rewrite mode
In this example, data is received by using serial I/O, and the data is programmed to the built-in flash
memory in the CPU rewrite mode.
Figure 2.11.8 shows an example of the reprogramming system for the built-in flash memory in the
CPU rewrite mode. Figure 2.11.9 shows the CPU rewrite mode beginning/release flowchart.
M38507F8FP/SP
P41
Clock input
BUSY output
Data input
Data output
SCLK1
SRDY1(BUSY)
R XD
VCC
AVSS
VSS
TXD
RESET
VPP power source input
CNVSS
User reset signal
(Note 1)
Note 1: Apply 4.5 to 5.5 V to the VPP power source.
Fig. 2.11.8 Example of rewrite system for built-in flash memory in CPU rewrite mode
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2.11 Flash memory mode
START
Single-chip mode or boot mode (Note 1)
Set CPU mode register (Note 2)
Transfer CPU rewrite mode control
program to built-in RAM
Jump to transferred control program on RAM
(The following operations are controlled by
the control program on this RAM)
Set “1” to CPU rewrite mode select bit (by
writing “0” and then “1” in succession)
Check CPU rewrite mode entry flag
Using software command execute erase,
program, or other operation
Execute read command or set flash
memory reset bit (by writing “0” and then
“1” in succession) (Note 3)
Set “0” to CPU rewrite mode select bit
END
Notes 1: When MCU starts in the single-chip mode, it is necessary to apply
5 V ± 10 % to dhe CNVss pin until confirming of the CPU rewrite
mode entry flag.
2: Set bits 6 and 7 (main clock division ratio selection bits) of the
CPU mode register (address 003B16).
3: Before releasing the CPU rewrite mode after completing erase or
program operation, always be sure to execute a read command or
reset the flash memory.
Fig. 2.11.9 CPU rewrite mode beginning/release flowchart
2-112
3850 Group (Spec. H) User’s Manual
APPLICATION
2.11 Flash memory mode
2.11.8 Notes on CPU rewrite mode
(1) Operation speed
During CPU rewrite mode, set the internal clock φ 4 MHz or less using the main clock division ratio
selection bits (bits 6 and 7 of address 003B 16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash memory cannot be used during the CPU
rewrite mode.
(3) Interrupts inhibited against use
The interrupts cannot be used during the CPU rewrite mode because they refer to the internal data
of the flash memory.
(4) Watchdog timer
In case of the watchdog timer has been running already, the internal reset generated by watchdog
timer underflow does not happen, because of watchdog timer is always clearing during program or
erase operation.
(5) Reset
Reset is always valid. In case of CNV SS = “H” when reset is released, boot mode is active. So the
program starts from the address contained in address FFFC16 and FFFD 16 in boot ROM area.
3850 Group (Spec. H) User’s Manual
2-113
APPLICATION
2.11 Flash memory mode
MEMORANDUM
2-114
3850 Group (Spec. H) User’s Manual
CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Standard characteristics
3.3 Notes on use
3.4 Countermeasures against noise
3.5 List of registers
3.6 Package outline
3.7 Machine instructions
3.8 List of instruction code
3.9 SFR memory map
3.10 Pin configurations
APPENDIX
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Symbol
Parameter
Power source voltage
VCC
Input voltage P00–P07, P10–P17, P20, P21,
VI
P24–P27, P30–P34, P40–P44,
VREF
VI
VI
VI
VO
VO
Pd
Topr
Tstg
Input voltage
Input voltage
Input voltage
Output voltage
P22, P23
RESET, XIN
CNVSS
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
XOUT
Output voltage P22, P23
Power dissipation
Operating temperature
Storage temperature
Conditions
All voltages are based on VSS.
Output transistors are cut off.
Ta = 25 °C
Note : The rating becomes 300mW at the 42P2R-A/E package.
3-2
3850 Group (Spec. H) User’s Manual
Ratings
–0.3 to 6.5
Unit
V
–0.3 to VCC +0.3
V
–0.3 to 5.8
–0.3 to VCC +0.3
–0.3 to VCC +0.3
V
V
V
–0.3 to VCC +0.3
V
–0.3 to 5.8
1000 (Note)
–20 to 85
–40 to 125
V
mW
°C
°C
APPENDIX
3.1 Electrical characteristics
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions (1)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
8 MHz (high-speed mode)
8 MHz (middle-speed mode), 4 MHz (high-speed mode)
VCC
Power source voltage
VSS
VREF
AVSS
VIA
VIH
VIH
VIL
VIL
VIL
Power source voltage
A-D convert reference voltage
Analog power source voltage
Analog input voltage
“H” input voltage
AN0–AN4
P00–P07, P10–P17, P20–P27, P30–P34, P40–P44
“H” input voltage
RESET, XIN, CNVSS
“L” input voltage
P00–P07, P10–P17, P20–P27, P30–P34, P40–P44
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
“H” total peak output current (Note)
“H” total peak output current (Note)
“L” total peak output current (Note)
“L” total peak output current (Note)
“L” total peak output current (Note)
“H” total average output current (Note)
“H” total average output current (Note)
“L” total average output current (Note)
“L” total average output current (Note)
“L” total average output current (Note)
Min.
4.0
2.7
Limits
Typ.
5.0
5.0
0
2.0
Max.
5.5
5.5
“L” input voltage
RESET, CNVSS
“L” input voltage
XIN
P00–P07, P10–P17, P30–P34
P20, P21, P24–P27, P40–P44
P00–P07, P30–P34
P10–P17
P20–P27,P40–P44
P00–P07, P10–P17, P30–P34
P20, P21, P24–P27, P40–P44
P00–P07, P30–P34
P10–P17
P20–P27,P40–P44
V
VCC
VCC
VCC
0.2VCC
0.2VCC
0.16VCC
V
V
V
V
V
V
V
V
V
–80
–80
80
120
80
–40
–40
40
60
40
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VCC
0
AVSS
0.8VCC
0.8VCC
0
0
0
Unit
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
3850 Group (Spec. H) User’s Manual
3-3
APPENDIX
3.1 Electrical characteristics
Table 3.1.3 Recommended operating conditions (2)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOL(avg)
IOL(avg)
f(XIN)
f(XIN)
Parameter
Min.
Limits
Typ.
“H” peak output current
P00–P07, P10–P17, P20, P21, P24–P27, P30–P34,
(Note 1)
P40–P44
“L” peak output current (Note 1) P00–P07, P20–P27, P30–P34, P40–P44
“L” peak output current (Note 1) P10–P17
“H” average output current
P00–P07, P10–P17, P20, P21, P24–P27, P30–P34,
(Note 2)
P40–P44
“L” average output current (Note 2) P00–P07, P20–P27, P30–P34, P40–P44
“L” average output current (Note 2) P10–P17
Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3)
Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3)
Max.
Unit
–10
mA
10
20
mA
mA
–5
mA
5
15
8
4
mA
mA
MHz
MHz
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50%.
3.1.3 Electrical characteristics
Table 3.1.4 Electrical characteristics (1)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
VOH
VOL
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIH
IIL
IIL
IIL
VRAM
Parameter
Test conditions
“H” output voltage
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44
(Note)
“L” output voltage
P00–P07, P20–P27, P30–P34,
P40–P44
“L” output voltage
P10–P17
Hysteresis
CNTR0, CNTR1, INT0–INT3
Hysteresis
RxD, SCLK1, SCLK2, SIN2
____________
Hysteresis
RESET
“H” input current
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44
____________
“H” input current RESET, CNVSS
“H” input current XIN
“L” input current
P00–P07, P10–P17, P20–P27
P30–P34, P40–P44
____________
“L” input current RESET,CNVSS
“L” input current XIN
RAM hold voltage
IOH = –10 mA
VCC = 4.0–5.5 V
IOH = –1.0 mA
VCC = 2.7–5.5 V
IOL = 10 mA
VCC = 4.0–5.5 V
IOL = 1.0 mA
VCC = 2.7–5.5 V
IOL = 20 mA
VCC = 4.0–5.5 V
IOL = 10 mA
VCC = 2.7–5.5 V
Min.
Typ.
V
VCC–1.0
V
2.0
V
1.0
V
2.0
V
1.0
V
0.4
V
0.5
V
0.5
VI = VCC
5.0
VI = VCC
VI = VCC
VI = VSS
4
VI = VSS
VI = VSS
When clock stopped
–4
3850 Group (Spec. H) User’s Manual
Unit
VCC–2.0
5.0
–5.0
–5.0
2.0
Note: P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
3-4
Max.
5.5
V
µA
µA
µA
µA
µA
µA
V
APPENDIX
3.1 Electrical characteristics
Table 3.1.5 Electrical characteristics (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
ICC
Parameter
Test conditions
Power source current
High-speed mode
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
High-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
Except
Low-speed mode
M38507F8FP/SP
f(XIN) = stopped
f(XCIN) = 32.768 kHz
M38507F8FP/SP
Output transistors “off”
Low-speed mode
Except
f(XIN) = stopped
M38507F8FP/SP
f(XCIN) = 32.768 kHz (in WIT state)
M38507F8FP/SP
Output transistors “off”
Except
Low-speed mode (VCC = 3 V)
M38507F8FP/SP
f(XIN) = stopped
f(XCIN) = 32.768 kHz
M38507F8FP/SP
Output transistors “off”
Except
Low-speed mode (VCC = 3 V)
M38507F8FP/SP
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
M38507F8FP/SP
Output transistors “off”
Middle-speed mode
f(XIN) = 8 MHz
f(XCIN) = stopped
Output transistors “off”
Middle-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = stopped
Output transistors “off”
Increment when A-D conversion is
executed
f(XIN) = 8 MHz
Limits
Min.
All oscillation stopped
(in STP state)
Output transistors “off”
Ta = 25 °C
Ta = 85 °C
3850 Group (Spec. H) User’s Manual
Typ.
Max.
6.8
13
200
40
55
10.0
µA
µA
20
4.0
µA
µA
150
5.0
µA
µA
70
20
µA
µA
250
20
mA
mA
1.6
60
Unit
7.0
mA
1.5
mA
800
µA
0.1
1.0
µA
10
µA
3-5
APPENDIX
3.1 Electrical characteristics
3.1.4 A-D converter characteristics
Table 3.1.6 A-D converter characteristics
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted)
Symbol
Parameter
–
–
tCONV
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
RLADDER
IVREF
Ladder resistor
Reference power source input current
II(AD)
A-D port input current
3-6
Test conditions
VREF “on”
VREF “off”
Limits
Min.
High-speed mode,
Middle-speed mode
Low-speed mode
VREF = 5.0 V
50
Typ.
40
35
150
0.5
3850 Group (Spec. H) User’s Manual
Max.
10
±4
61
200
5.0
5.0
Unit
bit
LSB
2tc(XIN)
µs
kΩ
µA
µA
APPENDIX
3.1 Electrical characteristics
3.1.5 Timing requirements and switching characteristics
Table 3.1.7 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
Limits
Min.
20
125
50
50
200
80
80
80
80
800
370
370
220
100
1000
400
400
200
200
Typ.
Max.
Unit
XIN cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Table 3.1.8 Timing requirements (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
Limits
Min.
20
250
100
100
500
230
230
230
230
2000
950
950
400
200
2000
950
950
400
300
Typ.
Max.
Unit
XIN cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is “0” (UART).
3850 Group (Spec. H) User’s Manual
3-7
APPENDIX
3.1 Electrical characteristics
Table 3.1.9 Switching characteristics (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tv (SCLK1-TXD)
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tv (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Parameter
Test conditions
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
Fig.3.1.1
Limits
Min.
Typ.
tC(SCLK1)/2–30
tC(SCLK1)/2–30
Max.
140
–30
30
30
tC(SCLK2)/2–160
tC(SCLK2)/2–160
200
0
10
10
30
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”.
3: The XOUT pin is excluded.
Table 3.1.10 Switching characteristics (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tv (SCLK1-TXD)
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tv (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Parameter
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
Test conditions
Fig.3.1.1
Limits
Typ.
Min.
tC(SCLK1)/2–50
tC(SCLK1)/2–50
Max.
350
–30
50
50
tC(SCLK2)/2–240
tC(SCLK2)/2–240
400
0
20
20
50
50
50
Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”.
3: The XOUT pin is excluded.
3-8
3850 Group (Spec. H) User’s Manual
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
APPENDIX
3.1 Electrical characteristics
Measurement output pin
100 pF
CMOS output
Fig. 3.1.1 Circuit for measuring output switching characteristics
3850 Group (Spec. H) User’s Manual
3-9
APPENDIX
3.1 Electrical characteristics
tC(CNTR)
tWH(CNTR)
CNTR0
CNTR1
tWL(CNTR)
0.8VCC
0.2VCC
tWL(INT)
tWH(INT)
0.8VCC
INT0 to INT3
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
SCLK1
SCLK2
tf
0.2VCC
tC(SCLK1), tC(SCLK2)
tWL(SCLK1), tWL(SCLK2)
tWH(SCLK1), tWH(SCLK2)
tr
0.8VCC
0.2VCC
tsu(RxD-SCLK1),
tsu(SIN2-SCLK2)
RXD
SIN2
th(SCLK1-RxD),
th(SCLK2-SIN2)
0.8VCC
0.2VCC
td(SCLK1-TXD),
td(SCLK2-SOUT2)
TXD
SOUT2
Fig. 3.1.2 Timing diagram
3-10
3850 Group (Spec. H) User’s Manual
tv(SCLK1-TXD),
tv(SCLK2-SOUT2)
APPENDIX
3.2 Standard characteristics
3.2 Standard characteristics
Standard characteristics described below are just examples of the 3850 Group (spec. H)’s characteristics
and are not guaranteed. For rated values, refer to “3.1 Electrical characteristics”.
3.2.1 Flash memory version power source current standard characteristics
Figure 3.2.1, Figure 3.2.2, Figure 3.2.3, Figure 3.2.4, and Figure 3.2.5 show flash memory version (M38507F8)
power source current standard characteristics.
Measuring conditions : 25 °C, f(X IN) = 8 MHz, in high-speed mode
6.0
Power source current Icc [mA]
5.0
4.0
Standard mode
3.0
2.0
Wait mode
1.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.1 Flash memory version power source current standard characteristics (in high-speed mode,
f(X IN) = 8 MHz)
Measuring conditions : 25 °C, f(X IN) = 4 MHz, in high-speed mode
3.0
Power source current Icc [mA]
2.5
2.0
Standard mode
1.5
1.0
Wait mode
0.5
0.0
2.0
2.5
3.0
3.5
4.0
Power source voltage Vcc [V]
4.5
5.0
5.5
Fig. 3.2.2 Flash memory version power source current standard characteristics (in high-speed mode,
f(X IN) = 4 MHz)
3850 Group (Spec. H) User’s Manual
3-11
APPENDIX
3.2 Standard characteristics
Measuring conditions : 25 °C, f(X IN) = 8 MHz, in middle-speed mode
1.8
1.6
Power source current Icc [mA]
1.4
1.2
Standard mode
1.0
0.8
0.6
0.4
Wait mode
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.3 Flash memory version power source current standard characteristics (in middle-speed
mode, f(X IN) = 8 MHz)
Measuring conditions : 25 °C, f(X IN) = 4 MHz, in middle-speed mode
1.6
1.4
Power source current Icc [mA]
1.2
1.0
Standard mode
0.8
0.6
0.4
Wait mode
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.4 Flash memory version power source current standard characteristics (in middle-speed
mode, f(X IN) = 4 MHz)
3-12
3850 Group (Spec. H) User’s Manual
APPENDIX
3.2 Standard characteristics
Measuring conditions : 25 °C, f(X IN) = 32 kHz, in low-speed mode
250
Power source current Icc [µA]
200
Standard mode
150
100
Wait mode
50
0
2.0
2.5
3.0
3.5
4.0
Power source voltage Vcc [V]
4.5
5.0
5.5
Fig. 3.2.5 Flash memory version power source current standard characteristics (in low-speed mode)
3850 Group (Spec. H) User’s Manual
3-13
APPENDIX
3.2 Standard characteristics
3.2.2 Mask ROM version power source current standard characteristics
Figure 3.2.6, Figure 3.2.7, Figure 3.2.8, Figure 3.2.9 and Figure 3.2.10 show mask ROM version (M38503M2H,
M38503M4H, M38504M6, M38507M8) power source current standard characteristics.
Measuring conditions : 25 °C, f(X IN) = 8 MHz, in high-speed mode
4.0
3.5
Power source current Icc [mA]
3.0
2.5
Standard mode
2.0
1.5
1.0
Wait mode
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.6 Mask ROM version power source current standard characteristics (in high-speed mode,
f(X IN) = 8 MHz)
Measuring conditions : 25 °C, f(X IN) = 4 MHz, in high-speed mode
2.5
Power source current Icc [mA]
2.0
1.5
Standard mode
1.0
Wait mode
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.7 Mask ROM version power source current standard characteristics (in high-speed mode,
f(X IN) = 4 MHz)
3-14
3850 Group (Spec. H) User’s Manual
APPENDIX
3.2 Standard characteristics
Measuring conditions : 25 °C, f(X IN) = 8 MHz, in middle-speed mode
1.8
1.6
Power source current Icc [mA]
1.4
1.2
Standard mode
1.0
0.8
0.6
0.4
Wait mode
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.8 Mask ROM version power source current standard characteristics (in middle-speed mode,
f(X IN) = 8 MHz)
Measuring conditions : 25 °C, f(X IN) = 4 MHz, in middle-speed mode
1.0
0.9
Power source current Icc [mA]
0.8
0.7
0.6
Standard mode
0.5
0.4
0.3
Wait mode
0.2
0.1
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.9 Mask ROM version power source current standard characteristics (in middle-speed mode,
f(X IN) = 4 MHz)
3850 Group (Spec. H) User’s Manual
3-15
APPENDIX
3.2 Standard characteristics
Measuring conditions : 25 °C, f(X IN) = 32 kHz, in low-speed mode
35
30
Power source current Icc [µA]
25
20
Standard mode
15
10
5
Wait mode
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.10 Mask ROM version power source current standard characteristics (in low-speed mode)
3-16
3850 Group (Spec. H) User’s Manual
APPENDIX
3.2 Standard characteristics
3.2.3 PROM version power source current standard characteristics
Figure 3.2.11, Figure 3.2.12, Figure 3.2.13, Figure 3.2.14, and Figure 3.2.15 show flash memory version
(M38504E6) power source current standard characteristics.
Measuring conditions : 25 °C, f(X IN) = 8 MHz, in high-speed mode
6.0
Power source current Icc [mA]
5.0
4.0
Standard mode
3.0
2.0
Wait mode
1.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.11 PROM version power source current standard characteristics (in high-speed mode, f(XIN)
= 8 MHz)
Measuring conditions : 25 °C, f(X IN) = 4 MHz, in high-speed mode
3.5
3
Power source current Icc [mA]
2.5
Standard mode
2
1.5
1
Wait mode
0.5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.12 PROM version power source current standard characteristics (in high-speed mode, f(XIN)
= 4 MHz)
3850 Group (Spec. H) User’s Manual
3-17
APPENDIX
3.2 Standard characteristics
Measuring conditions : 25 °C, f(XIN) = 8 MHz, in middle-speed mode
2.5
Power source current Icc [mA]
2.0
Standard mode
1.5
1.0
Wait mode
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.13 PROM version power source current standard characteristics (in middle-speed mode, f(XIN)
= 8 MHz)
Measuring conditions : 25 °C, f(XIN) = 4 MHz, in middle-speed mode
1.6
1.4
Power source current Icc [mA]
1.2
1.0
Standard mode
0.8
0.6
0.4
Wait mode
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.14 PROM version power source current standard characteristics (in middle-speed mode, f(XIN)
= 4 MHz)
3-18
3850 Group (Spec. H) User’s Manual
APPENDIX
3.2 Standard characteristics
Measuring conditions : 25 °C, f(XIN) = 32 kHz, in low-speed mode
70
60
Power source current Icc [µA]
50
40
Standard mode
30
20
Wait mode
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.15 PROM version power source current standard characteristics (in low-speed mode)
3850 Group (Spec. H) User’s Manual
3-19
APPENDIX
3.2 Standard characteristics
3.2.4 Flash memory version port standard characteristics
Figure 3.2.16, Figure 3.2.17, Figure 3.2.18 and Figure 3.2.19 show flash memory version (M38507F8) port
standard characteristics.
Port P00 IOH-VOH characteristics (P-channel drive) [Ta = 25 °C]
(Same characteristics pins : P0, P1, P20, P21, P24–P27, P3, P4)
–50
–45
–40
–35
Vcc = 5.0 V
IOH –30
[mA] –25
Vcc = 4.0 V
–20
–15
Vcc = 2.7 V
–10
–5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOH [V]
Fig. 3.2.16 CMOS output port P-channel side characteristics (Ta = 25 °C)
Port P00 IOL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P0, P20, P21, P24–P27, P3, P4)
100
90
80
70
IO L
[mA]
60
50
Vcc = 5 V
40
Vcc = 4.0 V
30
20
Vcc = 2.7 V
10
0
0
0 .5
1.0
1 .5
2 .0
2 .5
3.0
3 .5
4.0
4 .5
5.0
5.5
VOL [V]
Fig. 3.2.17 CMOS output port N-channel side characteristics (Ta = 25 °C)
3-20
3850 Group (Spec. H) User’s Manual
APPENDIX
3.2 Standard characteristics
Port P22 IOL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P22, P23)
100
90
80
70
IO L
[mA]
60
50
Vcc = 5 V
40
30
Vcc = 4.0 V
20
Vcc = 2.7 V
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOL [V]
Fig. 3.2.18 N-channel open-drain output port N-channel side characteristics (Ta = 25 °C)
Port P17 IOL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P1)
100
90
Vcc = 5 V
80
70
IOL
[mA]
60
Vcc = 4.0 V
50
40
30
Vcc = 2.7 V
20
10
0
0
0.5
1 .0
1 .5
2.0
2.5
3 .0
3 .5
4.0
4.5
5 .0
5.5
VOL [V]
Fig. 3.2.19 CMOS large current output port N-channel side characteristics (Ta = 25 °C)
3850 Group (Spec. H) User’s Manual
3-21
APPENDIX
3.2 Standard characteristics
3.2.5 Mask ROM version port standard characteristics
Figure 3.2.20, Figure 3.2.21, Figure 3.2.22 and Figure 3.2.23 show mask ROM version (M38503M2H,
M38503M4H, M38504M6, M38507M8) port standard characteristics.
Port P00 IOH-VOH characteristics (P-channel drive) [Ta = 25 °C]
(Same characteristics pins : P0, P1, P20, P21, P24–P27, P3, P4)
–50
–45
–40
–35
Vcc = 5.0 V
IOH –30
[mA] –25
Vcc = 4.0 V
–20
–15
Vcc = 2.7 V
–10
–5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOH [V]
Fig. 3.2.20 CMOS output port P-channel side characteristics (Ta = 25 °C)
Port P00 IOL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P0, P20, P21, P24–P27, P3, P4)
100
90
80
70
IOL
[mA]
60
50
Vcc = 5.0 V
40
Vcc = 4.0 V
30
20
Vcc = 2.7 V
10
0
0
0.5
1 .0
1 .5
2.0
2.5
3 .0
3.5
4.0
4.5
5 .0
5.5
VOL [V]
Fig. 3.2.21 CMOS output port N-channel side characteristics (Ta = 25 °C)
3-22
3850 Group (Spec. H) User’s Manual
APPENDIX
3.2 Standard characteristics
Port P22 IOL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P22, P23)
100
90
80
70
IOL
[mA]
60
50
Vcc = 5.0 V
40
30
Vcc = 4.0 V
20
Vcc = 2.7 V
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOL [V]
Fig. 3.2.22 N-channel open-drain output port N-channel side characteristics (Ta = 25 °C)
Port P17 IOL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P1)
100
90
Vcc = 5.0 V
80
70
IO L
[mA]
60
Vcc = 4.0 V
50
40
30
Vcc = 2.7 V
20
10
0
0
0 .5
1 .0
1 .5
2 .0
2.5
3 .0
3.5
4 .0
4 .5
5.0
5.5
VOL [V]
Fig. 3.2.23 CMOS large current output port N-channel side characteristics (Ta = 25 °C)
3850 Group (Spec. H) User’s Manual
3-23
APPENDIX
3.2 Standard characteristics
3.2.6 PROM version port standard characteristics
Figure 3.2.24, Figure 3.2.25, Figure 3.2.26 and Figure 3.2.27 show PROM version (M38504E6) port standard
characteristics.
Port P00 IOH-VOH characteristics (P-channel drive) [Ta = 25 °C]
(Same characteristics pins : P0, P1, P20, P21, P24–P27, P3, P4)
–50
–45
–40
–35
Vcc = 5.0 V
IOH –30
[mA] –25
Vcc = 4.0 V
–20
–15
Vcc = 2.7 V
–10
–5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOH [V]
Fig. 3.2.24 CMOS output port P-channel side characteristics (Ta = 25 °C)
Port P00 IOL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P0, P20, P21, P24–P27, P3, P4)
100
90
80
70
IOL
[mA]
60
50
Vcc = 5.0 V
40
Vcc = 4.0 V
30
20
Vcc = 2.7 V
10
0
0
0 .5
1 .0
1 .5
2.0
2 .5
3.0
3.5
4.0
4 .5
5.0
5.5
VOL [V]
Fig. 3.2.25 CMOS output port N-channel side characteristics (Ta = 25 °C)
3-24
3850 Group (Spec. H) User’s Manual
APPENDIX
3.2 Standard characteristics
Port P22 IOL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P22, P23)
100
Vcc = 5.0 V
90
80
70
IOL
[mA]
Vcc = 4.0 V
60
50
40
30
Vcc = 2.7 V
20
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOL [V]
Fig. 3.2.26 N-channel open-drain output port N-channel side characteristics (Ta = 25 °C)
Port P17 IOL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P1)
100
Vcc = 5.0 V
90
80
70
IOL
[mA]
Vcc = 4.0 V
60
50
40
30
Vcc = 2.7 V
20
10
0
0
0.5
1 .0
1 .5
2.0
2.5
3 .0
3 .5
4.0
4.5
5 .0
5.5
VOL [V]
Fig. 3.2.27 CMOS large current output port N-channel side characteristics (Ta = 25 °C)
3850 Group (Spec. H) User’s Manual
3-25
APPENDIX
3.2 Standard characteristics
3.2.7 A-D conversion standard characteristics
(1) Definition of A-D conversion accuracy
The A-D conversion accuracy is defined below.
●Relative accuracy
➀ Zero transition voltage (V 0T)
This means an analog input voltage when the actual A-D conversion output data changes from “0”
to “1”.
➁ Full-scale transition voltage (V FST)
This means an analog input voltage when the actual A-D conversion output data changes from
“1023” to “1022”.
➂ Linearity error
This means a deviation from the lone between V0T and VFST of a converted value between V 0T and
VFST.
➃ Differential non-linearity error
This means a deviation from the input potential difference required to change a converted value
between V 0T and V FST by 1 LSB of the 1 LSB at the relative accuracy.
●Absolute accuracy
This means a deviation from the ideal characteristics between 0 to V REF of actual A-D conversion
characteristics.
Output data
Full-scale transition voltage (VFST)
1023
1022
b
a
n+1
n
Actual A-D conversion
characteristics
c
Ideal line of A-D
conversion between
V0 to V1022
1
0
Vn
V0
V1
Zero transition voltage (V0T)
c
Linearity error = a [LSB]
VFST-V0T
1 LSB at absolute accuracy =
VREF
1022
VREF
1024
Vn : Analog input voltage when the output data changes
from “n” to “n + 1” (n = 0 to 1022)
a : 1 LSB at relative accuracy
b : Vn+1 –Vn
c : Difference between the aideal Vn and actual Vn
[LSB]
[LSB]
Fig. 3.2.28 Definition of A-D conversion accuracy
3-26
V1022
Analog voltage
Differential non-linearity error = b-a
a [LSB]
1 LSB at relative accuracy =
Vn+1
3850 Group (Spec. H) User’s Manual
APPENDIX
3.2 Standard characteristics
(2) A-D conversion standard characteristics
Figure 3.2.29, Figure 3.2.30, and Figure 3.2.31 show the A-D conversion standard characteristics of
flash memory version, mask ROM version, and PROM version, respectively.
The thick lines of the graph indicate the absolute precision errors, These are expressed as the
deviation from the ideal value when the output code changes. For example, the change in output
code from 256 to 257 should occur at 1280 mV, but the measured value is 2.5 mV. Accordingly, the
measured point of change is 1280 + 2.5 = 1282.5 mV.
The thin lines of the graph indicate the input voltage width for which the output code is constant. For
example, the measured input voltage width for which the output code is 256 is 5.0 mV, so that the
differential non-linear error is 5.0 – 5.0 = 0 mV (0 LSB).
3850 Group (Spec. H) User’s Manual
3-27
APPENDIX
3.2 Standard characteristics
M38507F8 A-D CONVERTER ERROR & STEP WIDTH MEASUREMENT
VCC = 5.12 [V], VREF = 5.12 [V]
XIN = 8 [MHz], Ta = 25 [deg.]
:
10.625 [mV]
: 5122.812 [mV]
:
1.719 [mV] :
:
—5.659 [mV] :
:
8.906 [mV] :
0.344 [LSB]
—1.131 [LSB]
1.781 [LSB]
15.0
15.0
10.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
1LSB WIDTH [mV]
ERROR [mV]
Zero transition voltage
Full-scale transition voltage
Differential non-linearity error
Linearity error
Absolute accuracy
256
15.0
15.0
10.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
256
272
288
304
320
336
352
368
384
400
416
432
448
464
480
496
1LSB WIDTH [mV]
ERROR [mV]
STEP No.
512
15.0
15.0
10.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
512
528
544
560
576
592
608
624
640
656
672
688
704
720
736
752
1LSB WIDTH [mV]
ERROR [mV]
STEP No.
768
15.0
15.0
10.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
768
784
800
816
832
848
864
880
896
912
928
944
960
976
992
1LSB WIDTH [mV]
ERROR [mV]
STEP No.
1008 1024
STEP No.
: ERROR (Absolute accuracy error)
: 1LSB WIDTH
Fig. 3.2.29 Flash memory version (M38507F8) A-D conversion standard characteristics
3-28
3850 Group (Spec. H) User’s Manual
APPENDIX
3.2 Standard characteristics
M38503M2H, M38503M4H, M38504M6, M38507M8 A-D CONVERTER ERROR & STEP WIDTH MEASUREMENT
VCC = 5.12 [V], VREF = 5.12 [V]
XIN = 8 [MHz], Ta = 25 [deg.]
:
:
:
:
:
10.31 [mV]
5118.12 [mV]
—1.41 [mV] :
—4.72 [mV] :
6.25 [mV] :
—0.28 [LSB]
—0.94 [LSB]
1.25 [LSB]
15.0
15.0
10.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
1LSB WIDTH [mV]
ERROR [mV]
Zero transition voltage
Full-scale transition voltage
Differential non-linearity error
Linearity error
Absolute accuracy
256
15.0
15.0
10.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
256
272
288
304
320
336
352
368
384
400
416
432
448
464
480
496
1LSB WIDTH [mV]
ERROR [mV]
STEP No.
512
15.0
15.0
10.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
512
528
544
560
576
592
608
624
640
656
672
688
704
720
736
752
1LSB WIDTH [mV]
ERROR [mV]
STEP No.
768
15.0
15.0
10.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
768
784
800
816
832
848
864
880
896
912
928
944
960
976
992
1LSB WIDTH [mV]
ERROR [mV]
STEP No.
1008 1024
STEP No.
: ERROR (Absolute accuracy error)
: 1LSB WIDTH
Fig. 3.2.30 Mask ROM version (M38503M2H, M38503M4H, M38504M6, M38507M8) A-D conversion standard
characteristics
3850 Group (Spec. H) User’s Manual
3-29
APPENDIX
3.2 Standard characteristics
M38504E6 A-D CONVERTER ERROR & STEP WIDTH MEASUREMENT
VCC = 5.12 [V], VREF = 5.12 [V]
XIN = 8 [MHz], Ta = 25 [deg.]
:
:
:
:
:
—0.62 [mV]
5112.19 [mV]
2.97 [mV] :
—3.41 [mV] :
—7.03 [mV] :
0.59 [LSB]
—0.68 [LSB]
—1.41[LSB]
15.0
15.0
10.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
1LSB WIDTH [mV]
ERROR [mV]
Zero transition voltage
Full-scale transition voltage
Differential non-linearity error
Linearity error
Absolute accuracy
256
15.0
15.0
10.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
256
272
288
304
320
336
352
368
384
400
416
432
448
464
480
496
1LSB WIDTH [mV]
ERROR [mV]
STEP No.
512
15.0
15.0
10.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
512
528
544
560
576
592
608
624
640
656
672
688
704
720
736
752
1LSB WIDTH [mV]
ERROR [mV]
STEP No.
768
15.0
15.0
10.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
768
784
800
816
832
848
864
880
896
912
928
944
960
976
992
1LSB WIDTH [mV]
ERROR [mV]
STEP No.
1008 1024
STEP No.
: ERROR (Absolute accuracy error)
: 1LSB WIDTH
Fig. 3.2.31 PROM version (M38504E6) A-D conversion standard characteristics
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APPENDIX
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on input and output ports
(1) Notes in standby state
In standby state ✽1, do not make input levels of an I/O port “undefined”, especially for I/O ports of the
N-channel open-drain. When setting the N-channel open-drain port as an output, do not make input
levels of an I/O port “undefined”, too.
Pull-up (connect the port to V CC ) or pull-down (connect the port to V SS ) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
● Reason
When setting as an input port with its direction register, the transistor becomes the OFF state,
which causes the ports to be the high-impedance state.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the
state that input levels of an I/O port are “undefined”. This may cause power source current.
In I/O ports of N-channel open-drain, when the contents of the port latch are “1”, even if it is set
as an output port with its direction register, it becomes the same phenomenon as the case of an
input port.
✽1 standby state: stop mode by executing STP instruction
wait mode by executing WIT instruction
(2) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction ✽2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
•As for bit which is set for input port:
The pin state is read in the CPU, and is written to this bit after bit managing.
•As for bit which is set for output port:
The bit value is read in the CPU, and is written to this bit after bit managing.
Note the following:
•Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
•As for a bit of which is set for an input port, its value may be changed even when not specified
with a bit managing instruction in case where the pin state differs from its port latch contents.
✽2 Bit managing instructions: SEB and CLB instructions
3850 Group (Spec. H) User’s Manual
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APPENDIX
3.3 Notes on use
3.3.2 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to V CC or V SS through each resistor of 1 kΩ to 10 kΩ.
As for pins whose potential affects to operation modes such as pins CNV SS, INT or others, select
the V CC pin or the V SS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to V CC or V SS through each resistor of
1 kΩ to 10 kΩ.
Set the I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
➃ The AVss pin when not using the A-D converter :
• When not using the A-D converter, handle a power source pin for the A-D converter, AVss pin
as follows:
AVss: Connect to the Vss pin.
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to V CC or V SS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or V SS ).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to V CC or VSS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
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3850 Group (Spec. H) User’s Manual
APPENDIX
3.3 Notes on use
3.3.3 Notes on interrupts
(1) Change of relevant register settings
When the setting of the following registers or bits is changed, the interrupt request bit may be set
to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following
sequence.
•Interrupt edge selection register (address 3A 16)
•Timer XY mode register (address 23 16)
Set the above listed registers or bits as the following sequence.
Set the corresponding interrupt enable bit to “0”
(disabled) .
↓
Set the interrupt edge select bit (active edge switch
bit) or the interrupt (source) select bit to “1”.
↓
NOP (one or more instructions)
↓
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
↓
Set the corresponding interrupt enable bit to “1”
(enabled).
Fig. 3.3.1 Sequence of changing relevant register
■ Reason
When setting the followings, the interrupt request bit may be set to “1”.
•When setting external interrupt active edge
Concerned register: Interrupt edge selection register (address 3A 16)
Timer XY mode register (address 23 16)
•When switching interrupt sources of an interrupt vector address where two or more interrupt
sources are allocated.
Concerned register: Interrupt edge selection register (address 3A 16)
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APPENDIX
3.3 Notes on use
(2) Check of interrupt request bit
● When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request
register immediately after this bit is set to “0” by using a data transfer instruction, execute one
or more instructions before executing the BBC or BBS instruction.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 3.3.2 Sequence of check of interrupt request bit
■ Reason
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt
request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
3.3.4 Notes on timer
● If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
● When switching the count source by the timer 12, X and Y count source selection bits, the value
of timer count is altered in unconsiderable amount owing to generating of thin pulses in the count
input signals.
Therefore, select the timer count source before set the value to the prescaler and the timer.
3.3.5 Notes on serial I/O
(1) Notes when selecting clock synchronous serial I/O (Serial I/O1)
➀ Stop of transmission operation
Clear the serial I/O1 enable bit and the transmit enable bit to “0” (Serial I/O1 and transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O1 enable bit to “0”
(Serial I/O1 disabled).
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3850 Group (Spec. H) User’s Manual
APPENDIX
3.3 Notes on use
➂ Stop of transmit/receive operation
Clear the transmit enable bit and receive enable bit to “0” simultaneously (transmit and receive
disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O1 enable bit to
“0” (Serial I/O1 disabled) (refer to (1) ➀).
➃ S RDY1 output of reception side (Serial I/O1)
When signals are output from the SRDY1 pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the S RDY1 output enable bit,
and the transmit enable bit to “1” (transmit enabled).
(2) Notes when selecting clock asynchronous serial I/O (Serial I/O1)
➀ Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
➂ Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
3850 Group (Spec. H) User’s Manual
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APPENDIX
3.3 Notes on use
(3) Setting serial I/O1 control register again (Serial I/O1)
Set the serial I/O1 control register again after the transmission and the reception circuits are reset
by clearing both the transmit enable bit and the receive enable bit to “0”.
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O1 control register
↓
Set both the transmit enable bit (TE) and
the receive enable bit (RE), or one of
them to “1”
Can be set with the LDM instruction at the same time
Fig. 3.3.3 Sequence of setting serial I/O1 control register again
(4) Data transmission control with referring to transmit shift register completion flag (Serial I/O1)
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(5) Transmit interrupt request when transmit enable bit is set (Serial I/O1)
When the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as shown
in the following sequence.
➀ Set the interrupt enable bit to “0” (disabled) with CLB instruction.
➁ Prepare serial I/O for transmission/reception.
➂ Set the interrupt request bit to “0” with CLB instruction after 1 or more instruction has been
executed.
➃ Set the interrupt enable bit to “1” (enabled).
● Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”. The interrupt request is generated and the transmission
interrupt request bit is set regardless of which of the two timings listed below is selected as the timing
for the transmission interrupt to be generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
(6) Transmission control when external clock is selected (Serial I/O1 clock synchronous mode)
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the S CLK1 input level. Also, write the transmit data to the transmit buffer
register (serial I/O shift register) at “H” of the S CLK1 input level.
(7) Transmit data writing (Serial I/O2)
In the clock synchronous serial I/O, when selecting an external clock as synchronous clock, write the
transmit data to the serial I/O2 register (serial I/O shift register) at “H” of the transfer clock input level.
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APPENDIX
3.3 Notes on use
3.3.6 Notes on PWM
The PWM starts after the PWM enable bit is set to enable and “L” level is output from the PWM pin.
The length of this “L“ level output is as follows:
n + 1
2 • f(X IN)
sec. (Count source selection bit = “0”, where n is the value set in the prescaler)
n + 1
f(X IN)
sec. (Count source selection bit = “1”, where n is the value set in the prescaler)
3.3.7 Notes on A-D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the
user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
(2) A-D converter power source pin
The AV SS pin is A-D converter power source pin. Regardless of using the A-D conversion function
or not, connect it as following :
• AV SS : Connect to the V SS line
● Reason
If the AV SS pin is opened, the microcomputer may have a failure because of noise or others.
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D conversion.
• f(X IN) is 500 kHz or more in middle-/high-speed mode.
• Do not execute the STP instruction.
• When the A-D converter is operated at low-speed mode, f(X IN) do not have the lower limit of
frequency, because of the A-D converter has a built-in self-oscillation circuit.
3.3.8 Notes on watchdog timer
●Make sure that the watchdog timer does not underflow while waiting Stop release, because the watchdog
timer keeps counting during that term.
●When the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program.
3850 Group (Spec. H) User’s Manual
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APPENDIX
3.3 Notes on use
3.3.9 Notes on RESET pin
(1) Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the V SS pin. Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
(2) Reset release after power on
When releasing the reset after power on, such as power-on reset, release reset after XIN passes more
than 20 cycles in the state where the power supply voltage is 2.7 V or more and the X IN oscillation
is stable.
● Reason
To release reset, the RESET pin must be held at an “L” level for 20 cycles or more of X IN in the
state where the power source voltage is between 2.7 V and 5.5 V, and X IN oscillation is stable.
3.3.10 Notes on using stop mode
■Register setting
Since values of the prescaler 12 and Timer 1 are automatically reloaded when returning from the
stop mode, set them again, respectively. (When the oscillation stabilizing time set after STP
instruction released bit is “0”)
When using the oscillation stabilizing time set after STP instruction released bit set to “1”, evaluate
time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12.
■Clock restoration
After restoration from the stop mode to the normal mode by an interrupt request, the contents of
the CPU mode register previous to the STP instruction execution are retained. Accordingly, if both
main clock and sub clock were oscillating before execution of the STP instruction, the oscillation
of both clocks is resumed at restoration.
In the above case, when the main clock side is set as a system clock, the oscillation stabilizing
time for approximately 8,000 cycles of the XIN input is reserved at restoration from the stop mode.
At this time, note that the oscillation on the sub clock side may not be stabilized even after the
lapse of the oscillation stabilizing time of the main clock side.
3.3.11 Notes on wait mode
■Clock restoration
If the wait mode is released by a reset when X CIN is set as the system clock and XIN oscillation is
stopped during execution of the WIT instruction, X CIN oscillation stops, X IN oscillations starts, and
X IN is set as the system clock.
In the above case, the RESET pin should be held at “L” until the oscillation is stabilized.
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APPENDIX
3.3 Notes on use
3.3.12 Notes on CPU rewrite mode of flash memory version
(1) Operation speed
During CPU rewrite mode, set the internal clock frequency 4MHz or less by using the main clock
division ratio selection bits (bits 6, 7 at address 003B 16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash memory cannot be used during CPU
rewrite mode .
(3) Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of
the flash memory.
(4) Watchdog timer
In case of the watchdog timer has been running already, the internal reset generated by watchdog
timer underflow does not happen, because of watchdog timer is always clearing during program or
erase operation.
(5) Reset
Reset is always valid. In case of CNV SS = “H” when reset is released, boot mode is active. So the
program starts from the address contained in addresses FFFC 16 and FFFD 16 in boot ROM area.
3.3.13 Notes on restarting oscillation
■Restarting oscillation
Usually, when the MCU stops the clock oscillation by STP instruction and the STP instruction has
been released by an external interrupt source, the fixed values of Timer 1 and Prescaler 12 (Timer
1 = “01 16”, Prescaler 12 = “FF16”) are automatically reloaded in order for the oscillation to stabilize.
The user can inhibit the automatic setting by writing “1” to bit 0 of MISRG (address 0038 16).
However, by setting this bit to “1”, the previous values, set just before the STP instruction was
executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate
value to each register, in accordance with the oscillation stabilizing time, before executing the STP
instruction.
● Reason
Oscillation will restart when an external interrupt is received. However, internal clock φ is supplied
to the CPU only when Timer 1 starts to underflow. This ensures time for the clock oscillation using
the ceramic resonators to be stabilized.
3850 Group (Spec. H) User’s Manual
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APPENDIX
3.3 Notes on use
3.3.14 Notes on programming
(1) Processor status register
➀ Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because they have an important effect
on calculations.
● Reason
After a reset, the contents of the processor status register (PS) are undefined except for the I
flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig. 3.3.4 Initialization of processor status register
➁ How to reference the processor status register
To reference the contents of the processor status register (PS), execute the PHP instruction once
then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its
original status.
A NOP instruction should be executed after every PLP instruction.
PLP instruction execution
↓
NOP
Fig. 3.3.5 Sequence of PLP instruction execution
(S)
(S)+1
Stored PS
Fig. 3.3.6 Stack memory contents after PHP
instruction execution
(2) BRK instruction
➀ Interrupt priority level
When the BRK instruction is executed with the following conditions satisfied, the interrupt execution
is started from the address of interrupt vector which has the highest priority.
• Interrupt request bit and interrupt enable bit are set to “1”.
• Interrupt disable flag (I) is set to “1” to disable interrupt.
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3850 Group (Spec. H) User’s Manual
APPENDIX
3.3 Notes on use
(3) Decimal calculations
➀ Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper decimal notation, set the
decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction,
execute another instruction before executing the SEC, CLC, or CLD instruction.
➁ Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in the status register (the N, V,
and Z flags) are invalid after a ADC or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared
to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C
flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be
initialized to “1” before each calculation.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 3.3.7 Status flag at decimal calculations
(4) JMP instruction
When using the JMP instruction in indirect addressing mode, do not specify the last address on a
page as an indirect address.
(5) Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register.
(6) Ports
The contents of the port direction registers cannot be read. The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register.
Use instructions such as LDM and STA, etc., to set the port direction registers.
(7) Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the
number of cycles needed to execute an instruction.
The number of cycles required to execute an instruction is shown in the list of machine instructions.
The frequency of the internal clock φ is half of the X IN frequency in high-speed mode.
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APPENDIX
3.3 Notes on use
3.3.15 EPROM Version/One Time PROM Version/Flash Memory Version
The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has
the multiplexed function to be a programmable power source pin (V PP pin) as well.
To improve the noise reduction, connect a track between CNVss pin and Vss pin or Vcc pin with 1 to 10
kΩ resistance.
The mask ROM version track of CNVss pin has no operational interference even if it is connected to Vss
pin or Vcc pin via a resistor.
3.3.16 Handling of Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass
capacitor between power source pin (VCC pin) and GND pin (VSS pin) and between power source pin (V CC
pin) and analog power source input pin (AV SS pin). Besides, connect the capacitor to as close as possible.
For bypass capacitor which should not be located too far from the pins to be connected, a ceramic
capacitor of 0.01 µF–0.1µF is recommended.
3.3.17 Differences between 3850 group (standard) and 3850 group (spec. H)
(1) The absolute maximum ratings of 3850 group (spec. H) is smaller than that of 3850 group (standard).
•Power source voltage Vcc = 0.3 to 6.5 V
•CNVss input voltage V I = –0.3 to Vcc +0.3 V
(2) The oscillation circuit constants of X IN-XOUT, XCIN-X COUT may be some differences between 3850 group
(standard) and 3850 group (spec. H).
(3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after
reset.)
(4) Fix bit 3 of the CPU mode register to “1”.
(5) Be sure to perform the termination of unused pins.
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3850 Group (Spec. H) User’s Manual
APPENDIX
3.4 Countermeasures against noise
3.4 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against
noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.
3.4.1 Shortest wiring length
The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Package
Select the smallest possible package to make the total wiring length short.
● Reason
The wiring length depends on a microcomputer package. Use of a small package, for example
QFP and not DIP, makes the total wiring length short to reduce influence of noise.
DIP
SDIP
SOP
QFP
Fig. 3.4.1 Selection of packages
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially,
connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within
20mm).
● Reason
The width of a pulse input into the RESET pin is determined by the timing necessary conditions.
If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is completely initialized. This may cause
a program runaway.
Noise
Reset
circuit
RESET
VSS
VSS
Reset
circuit
VSS
RESET
VSS
N.G.
O.K.
Fig. 3.4.2 Wiring for the RESET pin
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APPENDIX
3.4 Countermeasures against noise
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is
connected to an oscillator and the V SS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS patterns.
● Reason
If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program
failure or program runaway. Also, if a potential difference is caused by the noise between the V SS
level of a microcomputer and the V SS level of an oscillator, the correct clock will not be input in
the microcomputer.
Noise
XIN
XOUT
VSS
XIN
XOUT
VSS
O.K.
N.G.
Fig. 3.4.3 Wiring for clock I/O pins
(4) Wiring to CNV SS pin
Connect the CNV SS pin to the V SS pin with the shortest possible wiring.
● Reason
The processor mode of a microcomputer is influenced by a potential at the CNV SS pin. If a
potential difference is caused by the noise between pins CNVSS and VSS, the processor mode may
become unstable. This may cause a microcomputer malfunction or a program runaway.
Noise
CNVSS
CNVSS
VSS
VSS
N.G.
O.K.
Fig. 3.4.4 Wiring for CNV SS pin
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APPENDIX
3.4 Countermeasures against noise
(5) Wiring to VPP pin of One Time PROM version, EPROM version, and Flash memory version
Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series and also to the
VSS pin. When not connecting the resistor, make the length of wiring between the V PP pin and the
VSS pin the shortest possible.
Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM
version, the microcomputer operates correctly.
● Reason
The V PP pin of the One Time PROM, the EPROM version, and the flash memory version is the
power source input pin for the built-in PROM. When programming in the built-in PROM, the
impedance of the V PP pin is low to allow the electric current for writing flow into the PROM.
Because of this, noise can enter easily. If noise enters the V PP pin, abnormal instruction codes or
data are read from the built-in PROM, which may cause a program runaway.
Approximately
5kΩ
CNVSS/VPP
VSS
In the shortest
distance
Fig. 3.4.5 Wiring for the V PP pin of the One Time PROM version, the EPROM version, and the flash
memory version
3.4.2 Connection of bypass capacitor across V SS line and V CC line
Connect an approximately 0.1 µ F bypass capacitor across the V SS line and the V CC line as follows:
• Connect a bypass capacitor across the V SS pin and the VCC pin at equal length.
• Connect a bypass capacitor across the V SS pin and the V CC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for V SS line and V CC line.
• Connect the power source wiring via a bypass capacitor to the V SS pin and the V CC pin.
VCC
VCC
VSS
VSS
N.G.
O.K.
Fig. 3.4.6 Bypass capacitor across the V SS line and the V CC line
3850 Group (Spec. H) User’s Manual
3-45
APPENDIX
3.4 Countermeasures against noise
3.4.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the V SS pin and the analog input pin. Besides,
connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog
input pin and the V SS pin at equal length.
● Reason
Signals which is input in an analog input pin (such as an A-D converter/comparator input pin) are
usually output signals from sensor. The sensor which detects a change of event is installed far
from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer
necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer,
which causes noise to an analog input pin.
If a capacitor between an analog input pin and the VSS pin is grounded at a position far away from
the V SS pin, noise on the GND line may enter a microcomputer through the capacitor.
Noise
(Note)
Microcomputer
Analog
input pin
Thermistor
N.G.
O.K.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 3.4.7 Analog signal line and a resistor and a capacitor
3-46
3850 Group (Spec. H) User’s Manual
APPENDIX
3.4 Countermeasures against noise
3.4.4 Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected
by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a
current larger than the tolerance of current value flows.
● Reason
In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and
thermal heads or others. When a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
Microcomputer
Mutual inductance
M
XIN
XOUT
VSS
Large
current
GND
Fig. 3.4.8 Wiring for a large current signal line
(2) Installing oscillator away from signal lines where potential levels change frequently
Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential
levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect
other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a program runaway.
N.G.
Do not cross
CNTR
XIN
XOUT
VSS
Fig. 3.4.9 Wiring of RESET pin
3850 Group (Spec. H) User’s Manual
3-47
APPENDIX
3.4 Countermeasures against noise
(3) Oscillator protection using VSS pattern
As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the
position (on the component side) where an oscillator is mounted.
Connect the V SS pattern to the microcomputer V SS pin with the shortest possible wiring. Besides,
separate this V SS pattern from other V SS patterns.
An example of VSS patterns on the
underside of a printed circuit board
Oscillator wiring
pattern example
XIN
XOUT
VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.10 V SS pattern on the underside of an oscillator
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for checking whether input levels are
equal or not.
• As for an output port, since the output data may reverse because of noise, rewrite data to its port
latch at fixed periods.
• Rewrite data to direction registers at fixed periods.
Note: When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse
may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise
pulse.
O.K.
Noise
Data bus
Noise
Direction register
N.G.
Port latch
I/O port
pins
Fig. 3.4.11 Setup for I/O ports
3-48
3850 Group (Spec. H) User’s Manual
APPENDIX
3.4 Countermeasures against noise
3.4.6 Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ ( Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others,
the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with
counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program
initialization routine for recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the
initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization
routine for recovery processing in the following case:
If the SWDT contents are not initialized to the initial value N but continued to decrement and if
they reach 0 or less.
≠N
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
CLI
Interrupt processing
Main processing
(SWDT)
≤0?
(SWDT)
=N?
N
Interrupt processing
routine errors
>0
RTI
≤0
Return
Main routine
errors
Fig. 3.4.12 Watchdog timer by software
3850 Group (Spec. H) User’s Manual
3-49
APPENDIX
3.5 List of registers
3.5 List of registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (i = 0, 1, 2, 3, 4)
(Pi: addresses 0016, 0216, 0416, 0616, 0816)
b
Name
Functions
At reset R W
0 Port Pi0
0
●In output mode
Write •••••••• Port latch
1 Port Pi1
0
Read •••••••• Port latch
2 Port Pi2
0
●In input mode
3 Port Pi3
0
Write •••••••• Port latch
4 Port Pi4
0
Read •••••••• Value of pin
5 Port Pi5
0
6 Port Pi6
0
7 Port Pi7
0
Note: When reading bit 5, 6 or 7 of ports 3 and 4, the contents are undefined.
Fig. 3.5.1 Structure of Port Pi
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (i = 0, 1, 2, 3, 4)
(PiD: addresses 0116, 0316, 0516, 0716, 0916)
b
Name
0 Port Pi direction
register
1
2
3
4
5
6
7
Functions
0 : Port Pi0 input mode
1 : Port Pi0 output mode
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
Fig. 3.5.2 Structure of Port Pi direction register
3-50
3850 Group (Spec. H) User’s Manual
At reset R W
0
0
0
0
0
0
0
0
APPENDIX
3.5 List of registers
Serial I/O2 control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register 1 (SIO2CON1: address 1516)
b
Name
0 Internal
synchronous clock
1 selection bits
Functions
b2b1b0
0 0 0: f(XIN)/8
0 0 1: f(XIN)/16
0 1 0: f(XIN)/32
0 1 1: f(XIN)/64
1 1 0: f(XIN)/128
1 1 1: f(XIN)/256
0: I/O port (P01, P02)
1: SOUT2, SCLK2 signal output
0: I/O port (P03)
1: SRDY2 signal output
0: LSB first
1: MSB first
0: External clock
1: Internal clock
2
3 Serial I/O2 port
selection bit
4 SRDY2 output
enable bit
5 Transfer direction
selection bit
6 Serial I/O2
synchronous
clock selection bit
7 P01/SOUT2,
P02/SCLK2
P-channel output
disable bit
0: CMOS output
1: N-channel open-drain
output
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.3 Structure of Serial I/O2 control register 1
Serial I/O2 control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register 2
(SIO2CON2: address 1616)
b
Name
0 Optional transfer
bits
1
2
Functions
b2b1b0
0 0 0: 1 bit
0 0 1: 2 bit
0 1 0: 3 bit
0 1 1: 4 bit
1 0 0: 5 bit
1 0 1: 6 bit
1 1 0: 7 bit
1 1 1: 8 bit
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
3
4
5
6 Serial I/O2
I/O comparison
signal control bit
7 SOUT2 pin control
bit (P01)
0: P43 I/O
1: SCMP2 output
0: Output active
1: Output high-impedance
At reset R W
1
1
1
0
0
0
0
✕
✕
✕
0
Fig. 3.5.4 Structure of Serial I/O2 control register 2
3850 Group (Spec. H) User’s Manual
3-51
APPENDIX
3.5 List of registers
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register
(SIO2: address 1716)
b
0
1
2
3
4
5
6
7
Name
Functions
This register becomes shift register.
At transmit: Set transmit data to this register.
At receive: Received data is stored to this
register.
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Fig. 3.5.5 Structure of Serial I/O2 register
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB: address 1816)
b
Functions
0
1
2
3
4
5
6
7
The transmission data is written to or the
receive data is read out from this buffer register.
• At write: A data is written to the transmit buffer
register.
• At read: The contents of the receive buffer
register are read out.
Fig. 3.5.6 Structure of Transmit/Receive buffer register
3-52
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
3850 Group (Spec. H) User’s Manual
APPENDIX
3.5 List of registers
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 status register (SIOSTS: address 1916)
b
Name
0 Transmit buffer
empty flag (TBE)
1 Receive buffer full
flag (RBF)
2 Transmit shift
register shift
completion flag
(TSC)
Functions
0: Buffer full
1: Buffer empty
0: Buffer empty
1: Buffer full
0: Transmit shift in progress
1: Transmit shift completed
3 Overrun error flag 0: No error
(OE)
1: Overrun error
4 Parity error flag
0: No error
(PE)
1: Parity error
5 Framing error flag 0: No error
(FE)
1: Framing error
6 Summing error flag 0: (OE) U (PE) U (FE) = 0
(SE)
1: (OE) U (PE) U (FE) = 1
Nothing
is
arranged
for
this bit. This bit is a
7
write disabled bit. When this bit is read out, the
contents are “1”.
At reset R W
✕
0
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
1
✕
Fig. 3.5.7 Structure of Seial I/O1 status register
3850 Group (Spec. H) User’s Manual
3-53
APPENDIX
3.5 List of registers
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register
(SIOCON: address 1A16)
b
Name
Functions
0 BRG count source 0: f(XIN)
selection bit (CSS) 1: f(XIN)/4
When clock synchronous
1 Serial I/O1
synchronous clock serial I/O is selected,
selection bit (SCS) 0: BRG output divided by 4
1: External clock input
When UART is selected,
0: BRG output divided by 16
1: External clock input
divided by16
At reset R W
0
0
2 SRDY1 output
enable bit (SRDY)
0: I/O port (P27)
1: SRDY1 output pin
0
3 Transmit interrupt
source selection
bit (TIC)
0: Transmit buffer empty
1: Transmit shift operation
completion
0
4 Transmit enable bit
(TE)
5 Receive enable bit
(RE)
6 Serial I/O1 mode
selection bit (SIOM)
0: Transmit disabled
1: Transmit enabled
0: Receive disabled
1: Receive enabled
0: UART
1: Clock synchronous
serial I/O
0: Serial I/O1 disabled
(P24 to P27: normal I/O pins)
1: Serial I/O1 enabled
(P24 to P27: Serial I/O pins)
0
7 Serial I/O1 enable
bit (SIOE)
0
0
0
Fig. 3.5.8 Structure of Seial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register
(UARTCON: address 1B16)
b
Name
0 Character length
selection bit (CHAS)
1 Parity enable bit
(PARE)
2 Parity selection bit
(PARS)
3 Stop bit length
selection bit (STPS)
4 P25/TxD P-channel
output disable bit
(POFF)
Functions
0: 8 bits
1: 7 bits
0: Parity checking disabled
1: Parity checking enabled
0: Even parity
1: Odd parity
0: 1 stop bit
1: 2 stop bits
In output mode
0: CMOS output
1: N-channel open-drain
output
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read
7 out, the contents are “1”.
Fig. 3.5.9 Structure of UART control register
3-54
3850 Group (Spec. H) User’s Manual
At reset R W
0
0
0
0
0
1
1
1
✕
✕
✕
APPENDIX
3.5 List of registers
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator(BRG : address 1C16)
b
Functions
0 Set a count value of baud rate generator.
1
2
3
4
5
6
7
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Fig. 3.5.10 Structure of Baud rate generator
PWM control register
b7 b6 b5 b4 b3 b2 b1 b0
PWM control register (PWMCON: address 1D16)
b
Name
Functions
0 PWM function
0 : PWM disabled
enable bit
1 : PWM enabled
1 Count source
0 : f(XIN)
selection bit
1 : f(XIN)/2
2 Nothing is arranged for these bits. These are
3 write disabled bits. When these bits are read
4 out, the contents are “0”.
5
6
7
At reset R W
0
0
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
Fig. 3.5.11 Structure of PWM control register
PWM prescaler
b7 b6 b5 b4 b3 b2 b1 b0
PWM prescaler
(PREPWM: address 1E16)
b
Functions
At reset R W
0 •Set the PWM period.
1 •The value set in this register is written to both
PWM prescaler pre-latch and PWM prescaler
2 latch at the same time.
3 • When data is written to this register during
PWM output, the pulse corresponding to
4 changed value is output at the next period.
5 • When this register is read out, the count value
of the PWM prescaler latch is read out.
6
Undefined
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Fig. 3.5.12 Structure of PWM prescaler
3850 Group (Spec. H) User’s Manual
3-55
APPENDIX
3.5 List of registers
PWM register
b7 b6 b5 b4 b3 b2 b1 b0
PWM register
(PWM: address 1F16)
b
Functions
At reset R W
0 • Set the PWM “H” level output interval.
1 • The value set in this register is written to both
PWM register pre-latch and PWM register
2 latch at the same time.
3 • When data is written to this register during
PWM output, the pulse corresponding to
4 changed value is output at the next period.
5 • When this register is read out, the contents of
the PWM register latch is read out.
6
Undefined
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Fig. 3.5.13 Structure of PWM register
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY)
(addresses 2016, 2416, 2616)
b
Functions
0 • Set a count value of each prescaler.
1 • The value set in this register is written to both
2 each prescaler and the corresponding
3 prescaler latch at the same time.
• When this register is read out, the count value
4
of the corresponding prescaler is read out.
5
6
7
Fig. 3.5.14 Structure of Prescaler 12, Prescaler X, Prescaler Y
3-56
3850 Group (Spec. H) User’s Manual
At reset R W
1
1
1
1
1
1
1
1
APPENDIX
3.5 List of registers
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1
(T1: address 2116)
b
Functions
0 • Set timer 1 count value.
1 • The value set in this register is written to both
2 the timer 1 and the timer 1 latch at the same
3 time.
• When the timer 1 is read out, the count value
4
of the timer 1 is read out.
5
6
7
At reset R W
1
0
0
0
0
0
0
0
Fig. 3.5.15 Structure of Timer 1
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2
(T2: address 2216)
b
Functions
0 • Set timer 2 count value.
1 • The value set in this register is written to both
2 timer 2 and the timer 2 latch at the same time.
3 • When timer 2 is read out, the count value of
the timer 2 is read out.
4
5
6
7
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.16 Structure of Timer 2
3850 Group (Spec. H) User’s Manual
3-57
APPENDIX
3.5 List of registers
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY mode register
(TM: address 2316)
b
Name
0 Timer X operating
mode bits
1
2
3
4
5
6
7
Functions
b1 b0
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width
measurement mode
CNTR0 active edge Refer to Table 3.5.1
switch bit
Timer X count stop 0: Count start
1: Count stop
bit
b5
b4
Timer Y operating
0 0: Timer mode
mode bits
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width
measurement mode
CNTR1 active edge Refer to Table 3.5.1
switch bit
Timer Y count stop 0: Count start
1: Count stop
bit
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.17 Structure of Timer XY mode register
Table 3.5.1 CNTR 0/CNTR 1 active edge switch bit function
Timer X /Timer Y Set
Timer function
value
operation modes
“0”
Timer mode
No influence to timer count
“1”
No influence to timer count
“0”
Pulse output
Pulse output start: Beginning
mode
at “H” level
“1”
Pulse output start: Beginning
CNTR0 / CNTR 1 interrupt request
occurrence source
CNTR 0/CNTR1 input signal falling edge
CNTR 0/CNTR 1 input signal rising edge
Output signal falling edge count
Output signal rising edge count
at “L” level
Event counter
mode
Pulse width
measurement mode
3-58
“0”
“1”
“0”
“1”
Rising edge count
Falling edge count
“H” level width measurement
“L” level width measurement
Input signal falling edge count
Input signal rising edge count
Input signal falling edge count
Input signal rising edge count
3850 Group (Spec. H) User’s Manual
APPENDIX
3.5 List of registers
Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0
Timer X, Timer Y
(TX, TY: addresses 2516, 2716)
b
Functions
0 • Set each timer count value.
1 • The value set in this register is written to both
2 each timer and the corresponding timer latch
3 at the same time.
• When each timer is read out, the count value
4
of the corresponding timer is read out.
5
6
7
At reset R W
1
1
1
1
1
1
1
1
Fig. 3.5.18 Structure of Timer X, Timer Y
Timer count source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Timer count source selection register
(TCSS: address 2816)
b
Name
Functions
At reset R W
0: f(XIN)/16 (f(XCIN)/16 at
0 Timer X count
low-speed mode)
source selection bit
1: f(XIN)/2 (f(XCIN)/2 at lowspeed mode)
0
0: f(XIN)/16 (f(XCIN)/16 at
Timer Y count
low-speed mode)
source selection bit
1: f(XIN)/2 (f(XCIN)/2 at lowspeed mode)
0
1
2 Timer 12 count
0: f(XIN)/16 (f(XCIN)/16 at
low-speed mode)
source selection bit
1: f(XCIN)
0
3 Nothing is arranged for these bits. These are
4 write disabled bits. When these bits are read out,
5 the contents are “0”.
6
7
0
0
0
0
0
Fig. 3.5.19 Structure of Timer count source selection register
3850 Group (Spec. H) User’s Manual
3-59
APPENDIX
3.5 List of registers
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register
(ADCON: address 3416)
b
Name
0 Analog input pin
selection bits
1
2
Functions
b2 b1 b0
0 0 0: P30/AN0
0 0 1: P31/AN1
0 1 0: P32/AN2
0 1 1: P33/AN3
1 0 0: P34/AN4
3 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
4 AD conversion
0: Conversion in progress
1: Conversion completed
completion bit
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bist are read
7 out, the contents are “0”.
At reset R W
0
0
0
0
1
0
0
0
Fig. 3.5.20 Structure of A-D control register
A-D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (low-order)
(ADL: address 3516)
b
Functions
0 This is A-D conversion result stored bits. This is
1 read exclusive register.
2
8-bit read
b7
b0
3
b9 b8 b7 b6 b5 b4 b3 b2
4
5
10-bit read
b7
b0
6
b7 b6 b5 b4 b3 b2 b1 b0
7
Fig. 3.5.21 Structure of A-D conversion low-order register
3-60
3850 Group (Spec. H) User’s Manual
At reset R W
Undefined
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
APPENDIX
3.5 List of registers
A-D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (high-order)
(ADH: address 3616)
b
Functions
At reset R W
0 This is A-D conversion result stored bits. This is Undefined
read exclusive register.
10-bit read b0
b7
1
Undefined
b9 b8
2 Nothing is arranged for these bits. These are
3 write disabled bits. When these bits are read out,
4 the contents are “0”.
5
6
7
0
0
0
0
0
0
Fig. 3.5.22 Structure of A-D conversion high-order register
MISRG
b7 b6 b5 b4 b3 b2 b1 b0
MISRG
(MISRG: address 3816)
b
Name
Functions
0 Oscillatin stabilizing 0: Automatically set (Note 1)
time set after STP
1: Autimatically set disabled
instruction released bit
1 Middle-speed mode 0: Not set automatically
automatic switch set 1: Automatic switching
enabled (Note 2)
bit
2 Middle-speed mode 0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
automatic switch
wait time set bit
3 Middle-speed mode 0: Invalid
1: Automatic switch start
automatic switch
(Note 2)
start bit
(Depending on
program)
4 Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
5
out, the contents are “0”.
6
At reset R W
0
0
0
0
0
0
0
✕
✕
✕
✕
0
7
Notes 1: “0116” is set to Timer 1, “FF16” is set to Prescaler 12.
2: When automatic switch to middle-speed mode from low-speed mode occurs,
the values of CPU mode register (3B16) change.
Fig. 3.5.23 Structure of MISRG
3850 Group (Spec. H) User’s Manual
3-61
APPENDIX
3.5 List of registers
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register
(WDTCON: address 3916)
b
Name
Functions
0 Watchdog timer H
1 (for read-out of high-order 6 bit)
2
3
4
5
6 STP instruction
0: STP instruction enabled
1: STP instruction disabled
disable bit
7 Watchdog timer H 0: Watchdog timer L
underflow
count source selection
1: f(XIN)/16 or f(XCIN)/16
bit
At reset R W
1
✕
✕
1
1
✕
✕
1
1
✕
✕
1
0
0
Fig. 3.5.24 Structure of Watchdog timer control register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register
(INTEDGE: address 3A16)
b
Name
0 INT0 active edge
selection bit
1 INT1 active edge
selection bit
2 INT2 active edge
selection bit
3 INT3 active edge
selection bit
4 SeriaI/O2/INT3
interrupt source bit
Functions
0: Falling edge active
1: Rising edge active
0: Falling edge active
1: Rising edge active
0: Falling edge active
1: Rising edge active
0: Falling edge active
1: Rising edge active
0: INT3 interrupt selected
1: Serial I/O2 interrupt
selected
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read out,
7 the contents are “0”.
Fig. 3.5.25 Structure of Interrupt edge selection register
3-62
3850 Group (Spec. H) User’s Manual
At reset R W
0
0
0
0
0
0
0
0
0
APPENDIX
3.5 List of registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
CPU mode register
(CPUM: address 3B16)
b
Name
0 Processor mode
bits
1
2 Stack page
selection bit
3 Fix this bit to “1”.
Functions
b1 b0
00 : Single-chip mode
01 :
10 :
Not available
11 :
0 : 0 page
1 : 1 page
At reset R W
0
0
0
1
4 Port Xc switch bit
0: I/O port function
(stop oscillating)
1: XCIN-XCOUT oscillation
function
0
5 Main clock (XINXOUT) stop bit
6 Main clock division
ratio selection bits
0: Oscillating
1: Stopped
0
b7 b6
1
7
0 0: φ=f(XIN)/2
(high-speed mode)
0 1: φ=f(XIN)/8
(middle-speed mode)
1 0: φ=f(XCIN)/2
(low-speed mode)
1 1: not available
0
Fig. 3.5.26 Structure of CPU mode register
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
Name
Functions
At reset R W
0
✽
1 When writing to this bit, set “0” to this bit.
0
✽
2 INT1 interrupt
request bit
3 INT2 interrupt
request bit
4 INT3/Serial I/O2
interrupt request bit
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0 INT0 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
5 When writing to this bit, set “0” to this bit.
0 : No interrupt request issued
6 Timer X interrupt
1 : Interrupt request issued
request bit
Timer
Y
interrupt
0 : No interrupt request issued
7
request bit
1 : Interrupt request issued
✽: “0” can be set by software, but “1” cannot be set.
Fig. 3.5.27 Structure of Interrupt request register 1
3850 Group (Spec. H) User’s Manual
3-63
APPENDIX
3.5 List of registers
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
Name
0 Timer 1 interrupt
request bit
1 Timer 2 interrupt
request bit
2 Serial I/O1 receive
interrupt request bit
3 Serial I/O1 transmit
interrupt request bit
4 CNTR0 interrupt
request bit
5 CNTR1 interrupt
request bit
6 A-D converter
interrupt request bit
Functions
At reset R W
0 : No interrupt request issued
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
✽: “0” can be set by software, but “1” cannot be set.
0
Fig. 3.5.28 Structure of Interrupt request register 2
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Interrupt control register 1
(ICON1 : address 3E16)
b
Name
Functions
0 INT0 interrupt
enable bit
1 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
2 INT1 interrupt
enable bit
3 INT2 interrupt
enable bit
4 INT3/Serial I/O2
interrupt enable bit
5 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
6 Timer X interrupt
enable bit
7 Timer Y interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
0
Fig. 3.5.29 Structure of Interrupt control register 1
3-64
At reset R W
3850 Group (Spec. H) User’s Manual
0
0
APPENDIX
3.5 List of registers
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
0
Timer 1 interrupt
enable bit
Timer 2 interrupt
enable bit
Serial I/O1 receive
interrupt enable bit
Serial I/O1 transmit
interrupt enable bit
CNTR0 interrupt
enable bit
CNTR1 interrupt
enable bit
A-D converter
interrupt enable bit
Fix this bit to “0”.
1
2
3
4
5
6
7
Functions
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.30 Structure of Interrupt control register 2
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Flash memory control register
(FMCR : address 0FFE16)
b
Name
0 RY/BY status flag
Functions
0 : Busy (being written or
erased)
1 : Ready
At reset R W
1
0
0 : Normal mode (Software
commands invalid)
1 : CPU rewrite mode
(Software commands
acceptable)
CPU rewrite mode
0: Normal mode
0
entry flag
1: CPU rewrite mode
Flash memory reset 0: Normal operation
0
bit (Note 2)
1: Reset
User area/Boot
0: User ROM area
0
area selection bit
1: Boot ROM area
Nothing is arranged for these bits. When write, Undefined
set “0”. When these bits are read out, the
Undefined
contents are undefined.
Undefined
1 CPU rewrite mode
select bit (Note 1)
2
3
4
5
6
7
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then
a “1” to it in succession.
2: Effective only when the CPU rewrite mode select bit = “1”. Set this
bit to “0” subsequently after setting it to “1” (reset).
Fig. 3.5.31 Structure of Flash memory control register
3850 Group (Spec. H) User’s Manual
3-65
APPENDIX
3.6 Package outline
3.6 Package outline
MMP
42P4B
EIAJ Package Code
SDIP42-P-600-1.78
Plastic 42pin 600mil SDIP
Weight(g)
4.1
Lead Material
Alloy 42/Cu Alloy
22
1
21
E
42
e1
c
JEDEC Code
–
Symbol
L
A1
A
A2
D
e
b1
b2
b
SEATING PLANE
A
A1
A2
b
b1
b2
c
D
E
e
e1
L
42P2R-A/E
Dimension in Millimeters
Min
Nom
Max
–
–
5.5
0.51
–
–
–
3.8
–
0.35
0.45
0.55
0.9
1.0
1.3
0.63
0.73
1.03
0.22
0.27
0.34
36.5
36.7
36.9
12.85
13.0
13.15
–
1.778
–
–
15.24
–
3.0
–
–
0°
–
15°
Plastic 42pin 450mil SSOP
EIAJ Package Code
SSOP42-P-450-0.80
JEDEC Code
–
Weight(g)
0.63
e
b2
22
E
HE
e1
I2
42
Lead Material
Alloy 42
Recommended Mount Pad
F
Symbol
1
21
A
D
G
A2
e
b
L
L1
y
A1
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
y
c
z
Z1
3-66
Detail G
Detail F
3850 Group (Spec. H) User’s Manual
b2
e1
I2
Dimension in Millimeters
Min
Nom
Max
2.4
–
–
–
–
0.05
–
2.0
–
0.4
0.3
0.25
0.2
0.15
0.13
17.7
17.5
17.3
8.6
8.4
8.2
–
0.8
–
12.23
11.93
11.63
0.7
0.5
0.3
–
1.765
–
–
0.75
–
–
–
0.9
0.15
–
–
0°
–
10°
–
0.5
–
–
11.43
–
–
1.27
–
APPENDIX
3.6 Package outline
42S1B-A
Metal seal 42pin 600mil DIP
EIAJ Package Code
WDIP42-C-600-1.78
JEDEC Code
–
Weight(g)
1
21
e1
22
E
42
c
D
A1
L
A
A2
Symbol
Z
e
b
b1
SEATING PLANE
3850 Group (Spec. H) User’s Manual
A
A1
A2
b
b1
c
D
E
e
e1
L
Z
Dimension in Millimeters
Min
Nom
Max
–
–
5.0
–
–
1.0
3.44
–
–
0.38
0.54
0.46
0.7
0.8
0.9
0.17
0.33
0.25
–
–
41.1
–
15.8
–
–
–
1.778
–
–
15.24
3.05
–
–
–
–
3.05
3-67
APPENDIX
APPENDIX
3.7 Machine instructions
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
ADC
(Note 1)
(Note 5)
When T = 0
A←A+M+C
When T = 1
M(X) ← M(X) + M + C
AND
(Note 1)
When TV= 0
A←A M
When T = 1 V
M(X) ← M(X) M
7
ASL
C←
0
←0
IMM
# OP n
A
# OP n
Addressing mode
BIT,A,AR
BIT,
# OP n
ZP
# OP n
BIT,ZP,
ZPR
BIT,
# OP n
#
ZP, X
ZP, Y
OP n
# OP n
ABS
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
# OP n
# OP n
# OP n
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
When T = 0, this instruction adds the contents
M, C, and A; and stores the results in A and C.
When T = 1, this instruction adds the contents
of M(X), M and C; and stores the results in
M(X) and C. When T=1, the contents of A remain unchanged, but the contents of status
flags are changed.
M(X) represents the contents of memory
where is indicated by X.
69 2
2
65 3
2
75 4
2
6D 4
3 7D 5
3 79 5
3
61 6
2 71 6
2
N
V
•
•
•
•
Z
C
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise AND operation and stores the result
back in A.
When T = 1, this instruction transfers the contents M(X) and M to the ALU which performs a
bit-wise AND operation and stores the results
back in M(X). When T = 1 the contents of A remain unchanged, but status flags are
changed.
M(X) represents the contents of memory
where is indicated by X.
29 2
2
25 3
2
35 4
2
2D 4
3 3D 5
3 39 5
3
21 6
2 31 6
2
N
•
•
•
•
•
Z
•
06 5
2
16 6
2
0E 6
3 1E 7
3
N
•
•
•
•
•
Z
C
This instruction shifts the content of A or M by
one bit to the left, with bit 0 always being set to
0 and bit 7 of A or M always being contained in
C.
0A 2
1
BBC
(Note 4)
Ai or Mi = 0?
This instruction tests the designated bit i of M
or A and takes a branch if the bit is 0. The
branch address is specified by a relative address. If the bit is 1, next instruction is
executed.
13 4
+
20i
2
17 5
+
20i
3
•
•
•
•
•
•
•
•
BBS
(Note 4)
Ai or Mi = 1?
This instruction tests the designated bit i of the
M or A and takes a branch if the bit is 1. The
branch address is specified by a relative address. If the bit is 0, next instruction is
executed.
03 4
+
20i
2
07 5
+
20i
3
•
•
•
•
•
•
•
•
BCC
(Note 4)
C = 0?
This instruction takes a branch to the appointed address if C is 0. The branch address
is specified by a relative address. If C is 1, the
next instruction is executed.
90 2
2
•
•
•
•
•
•
•
•
BCS
(Note 4)
C = 1?
This instruction takes a branch to the appointed address if C is 1. The branch address
is specified by a relative address. If C is 0, the
next instruction is executed.
B0 2
2
•
•
•
•
•
•
•
•
BEQ
(Note 4)
Z = 1?
This instruction takes a branch to the appointed address when Z is 1. The branch
address is specified by a relative address.
If Z is 0, the next instruction is executed.
F0 2
2
•
•
•
•
•
•
•
•
BIT
A
M7 M6 •
•
•
•
Z
•
BMI
(Note 4)
N = 1?
This instruction takes a branch to the appointed address when N is 1. The branch
address is specified by a relative address.
If N is 0, the next instruction is executed.
30 2
2
•
•
•
•
•
•
•
•
BNE
(Note 4)
Z = 0?
This instruction takes a branch to the appointed address if Z is 0. The branch address
is specified by a relative address. If Z is 1, the
next instruction is executed.
D0 2
2
•
•
•
•
•
•
•
•
3-68
V
M
This instruction takes a bit-wise logical AND of
A and M contents; however, the contents of A
and M are not modified.
The contents of N, V, Z are changed, but the
contents of A, M remain unchanged.
3850 Group (Spec. H) User’s Manual
24 3
2
2C 4
3
3850 Group (Spec. H) User’s Manual
3-69
APPENDIX
APPENDIX
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
A
# OP n
Addressing mode
BIT, A
# OP n
ZP
# OP n
BIT, ZP
# OP n
#
ZP, X
OP n
ZP, Y
# OP n
ABS
# OP n
ABS, X
# OP n
ABS, Y
# OP n
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
REL
# OP n
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
BPL
(Note 4)
N = 0?
This instruction takes a branch to the appointed address if N is 0. The branch address
is specified by a relative address. If N is 1, the
next instruction is executed.
10 2
2
•
•
•
•
•
•
•
•
BRA
PC ← PC ± offset
This instruction branches to the appointed address. The branch address is specified by a
relative address.
80 4
2
•
•
•
•
•
•
•
•
BRK
B←1
(PC) ← (PC) + 2
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
M(S) ← PS
S←S–1
I← 1
PCL ← ADL
PCH ← ADH
When the BRK instruction is executed, the
CPU pushes the current PC contents onto the
stack. The BADRS designated in the interrupt
vector table is stored into the PC.
•
•
•
1
•
1
•
•
BVC
(Note 4)
V = 0?
This instruction takes a branch to the appointed address if V is 0. The branch address
is specified by a relative address. If V is 1, the
next instruction is executed.
50 2
2
•
•
•
•
•
•
•
•
BVS
(Note 4)
V = 1?
This instruction takes a branch to the appointed address when V is 1. The branch
address is specified by a relative address.
When V is 0, the next instruction is executed.
70 2
2
•
•
•
•
•
•
•
•
CLB
Ai or Mi ← 0
This instruction clears the designated bit i of A
or M.
•
•
•
•
•
•
•
•
CLC
C←0
This instruction clears C.
18 2
1
•
•
•
•
•
•
•
0
CLD
D←0
This instruction clears D.
D8 2
1
•
•
•
•
0
•
•
•
CLI
I←0
This instruction clears I.
58 2
1
•
•
•
•
•
0
•
•
CLT
T←0
This instruction clears T.
12 2
1
•
•
0
•
•
•
•
•
CLV
V←0
This instruction clears V.
B8 2
1
•
0
•
•
•
•
•
•
CMP
(Note 3)
When T = 0
A–M
When T = 1
M(X) – M
When T = 0, this instruction subtracts the contents of M from the contents of A. The result is
not stored and the contents of A or M are not
modified.
When T = 1, the CMP subtracts the contents
of M from the contents of M(X). The result is
not stored and the contents of X, M, and A are
not modified.
M(X) represents the contents of memory
where is indicated by X.
N
•
•
•
•
•
Z
C
COM
M←M
This instruction takes the one’s complement of
the contents of M and stores the result in M.
N
•
•
•
•
•
Z
•
CPX
X–M
This instruction subtracts the contents of M
from the contents of X. The result is not stored
and the contents of X and M are not modified.
E0 2
CPY
Y–M
This instruction subtracts the contents of M
from the contents of Y. The result is not stored
and the contents of Y and M are not modified.
C0 2
DEC
A ← A – 1 or
M←M–1
This instruction subtracts 1 from the contents
of A or M.
3-70
__
00 7
1
1B 2
+
20i
C9 2
3850 Group (Spec. H) User’s Manual
1
1F 5
+
20i
2
C5 3
2
44 5
2
2
E4 3
2
EC 4
3
N
•
•
•
•
•
Z
C
2
C4 3
2
CC 4
3
N
•
•
•
•
•
Z
C
C6 5
2
CE 6
3 DE 7
N
•
•
•
•
•
Z
•
2
1A 2
1
D5 4
D6 6
2
2
CD 4
3 DD 5
3 D9 5
3
C1 6
2 D1 6
2
3
3850 Group (Spec. H) User’s Manual
3-71
APPENDIX
APPENDIX
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
A
# OP n
BIT, A
# OP n
Addressing mode
ZP
# OP n
BIT, ZP
# OP n
#
ZP, X
OP n
ZP, Y
# OP n
ABS
# OP n
ABS, X
# OP n
ABS, Y
# OP n
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
REL
# OP n
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
DEX
X←X–1
This instruction subtracts one from the current CA 2
contents of X.
1
N
•
•
•
•
•
Z
•
DEY
Y←Y–1
This instruction subtracts one from the current
contents of Y.
88 2
1
N
•
•
•
•
•
Z
•
DIV
A ← (M(zz + X + 1),
M(zz + X )) / A
M(S) ← one's complement of Remainder
S←S–1
Divides the 16-bit data in M(zz+(X)) (low-order
byte) and M(zz+(X)+1) (high-order byte) by the
contents of A. The quotient is stored in A and
the one's complement of the remainder is
pushed onto the stack.
•
•
•
•
•
•
•
•
EOR
(Note 1)
When T = 0
–M
A←AV
When T = 0, this instruction transfers the contents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bitwise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
When T = 1
–M
M(X) ← M(X) V
E2 16 2
49 2
2
45 3
2
55 4
2
4D 4
3 5D 5
3 59 5
E6 5
2
F6 6
2
EE 6
3 FE 7
3
3
41 6
2 51 6
2
INC
A ← A + 1 or
M←M+1
This instruction adds one to the contents of A
or M.
INX
X←X+1
This instruction adds one to the contents of X.
E8 2
1
N
•
•
•
•
•
Z
•
INY
Y←Y+1
This instruction adds one to the contents of Y.
C8 2
1
N
•
•
•
•
•
Z
•
JMP
If addressing mode is ABS
PCL ← ADL
PCH ← ADH
If addressing mode is IND
PCL ← M (ADH, ADL)
PCH ← M (ADH, ADL + 1)
If addressing mode is ZP, IND
PCL ← M(00, ADL)
PCH ← M(00, ADL + 1)
This instruction jumps to the address designated by the following three addressing
modes:
Absolute
Indirect Absolute
Zero Page Indirect Absolute
4C 3
3
•
•
•
•
•
•
•
•
JSR
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
After executing the above,
if addressing mode is ABS,
PCL ← ADL
PCH ← ADH
if addressing mode is SP,
PCL ← ADL
PCH ← FF
If addressing mode is ZP, IND,
PCL ← M(00, ADL)
PCH ← M(00, ADL + 1)
This instruction stores the contents of the PC
in the stack, then jumps to the address designated by the following addressing modes:
Absolute
Special Page
Zero Page Indirect Absolute
20 6
3
•
•
•
•
•
•
•
•
LDA
(Note 2)
When T = 0
A←M
When T = 1
M(X) ← M
When T = 0, this instruction transfers the contents of M to A.
When T = 1, this instruction transfers the contents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
AD 4
3 BD 5
N
•
•
•
•
•
Z
•
LDM
M ← nn
This instruction loads the immediate value in
M.
•
•
•
•
•
•
•
•
LDX
X←M
This instruction loads the contents of M in X.
A2 2
N
•
•
•
•
•
Z
•
LDY
Y←M
This instruction loads the contents of M in Y.
A0 2
N
•
•
•
•
•
Z
•
3-72
3A 2
A9 2
3850 Group (Spec. H) User’s Manual
2
1
A5 3
2
3C 4
3
2
A6 3
2
2
A4 3
2
B5 4
2
B6 4
B4 4
2
2 AE 4
AC 4
6C 5
3 B9 5
3
3 BC 5
BE 5
3
3 B2 4
2
02 7
2
22 5
A1 6
2 B1 6
2
3
3
3850 Group (Spec. H) User’s Manual
2
3-73
APPENDIX
APPENDIX
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
LSR
7
0→
0
→C
Multiplies Accumulator with the memory specified by the Zero Page X address mode and
stores the high-order byte of the result on the
Stack and the low-order byte in A.
NOP
PC ← PC + 1
This instruction adds one to the PC but does EA 2
no otheroperation.
ORA
(Note 1)
When T = 0
A←AVM
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise “OR”, and stores the result in A.
When T = 1, this instruction transfers the contents of M(X) and the M to the ALU which
performs a bit-wise OR, and stores the result
in M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
PHP
PLA
PLP
ROL
S←S–1
1
# OP n
46 5
BIT, ZP
# OP n
2
#
ZP, X
ZP, Y
OP n
# OP n
56 6
2
ABS
ABS, X
ABS, Y
# OP n
# OP n
# OP n
4E 6
3 5E 7
3
IND
# OP n
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
# OP n
62 15 2
1
09 2
2
05 3
2
15 4
2
0D 4
3 1D 5
3 19 5
3
01 6
2 11 6
REL
2
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
0
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
1
M(S) ← PS
S←S–1
This instruction pushes the contents of PS to
the memory location designated by S and decrements the contents of S by one.
08 3
1
S←S+1
A ← M(S)
This instruction increments S by one and
stores the contents of the memory designated
by S in A.
68 4
1
S←S+1
PS ← M(S)
This instruction increments S by one and
stores the contents of the memory location
designated by S in PS.
28 4
1
7
←
This instruction shifts either A or M one bit left
through C. C is stored in bit 0 and bit 7 is
stored in C.
2A 2
1
26 5
2
36 6
2
2E 6
3 3E 7
3
N
•
•
•
•
•
Z
C
This instruction shifts either A or M one bit
right through C. C is stored in bit 7 and bit 0 is
stored in C.
6A 2
1
66 5
2
76 6
2
6E 6
3 7E 7
3
N
•
•
•
•
•
Z
C
82 8
2
•
•
•
•
•
•
•
•
0
←C ←
RRF
7
→
3-74
# OP n
ZP
48 3
7
C→
RTS
BIT, A
Processor status register
This instruction pushes the contents of A to
the memory location designated by S, and
decrements the contents of S by one.
ROR
RTI
# OP n
4A 2
M(S) • A ← A ✽ M(zz + X)
S←S–1
PHA
# OP n
A
This instruction shifts either A or M one bit to
the right such that bit 7 of the result always is
set to 0, and the bit 0 is stored in C.
MUL
When T = 1
M(X) ← M(X) V M
IMM
Addressing mode
0
→
0
→
This instruction rotates 4 bits of the M content
to the right.
S←S+1
PS ← M(S)
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
This instruction increments S by one, and
stores the contents of the memory location
designated by S in PS. S is again incremented
by one and stores the contents of the memory
location designated by S in PC L . S is again
incremented by one and stores the contents of
memory location designated by S in PCH.
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
(PC) ← (PC) + 1
This instruction increments S by one and
stores the contents of the memory location
d e s i g n a t e d b y S i n P C L. S i s a g a i n
incremented by one and the contents of the
memory location is stored in PC H . PC is
incremented by 1.
(Value saved in stack)
(Value saved in stack)
40 6
1
60 6
1
•
3850 Group (Spec. H) User’s Manual
3850 Group (Spec. H) User’s Manual
•
•
•
•
•
•
•
3-75
APPENDIX
APPENDIX
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
SBC
(Note 1)
(Note 5)
When T = 0 _
A←A–M–C
When T = 1
_
M(X) ← M(X) – M – C
IMM
# OP n
E9 2
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the contents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
A
# OP n
Addressing mode
BIT, A
# OP n
ZP
# OP n
2
E5 3
BIT, ZP
# OP n
#
2
ZP, X
ZP, Y
OP n
# OP n
F5 4
2
ABS
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
ED 4
3 FD 5
3 F9 5
3
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
# OP n
# OP n
# OP n
E1 6
2 F1 6
2
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
N
V
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
SEB
Ai or Mi ← 1
This instruction sets the designated bit i of A
or M.
SEC
C←1
This instruction sets C.
38 2
1
•
•
•
•
•
•
•
1
SED
D←1
This instruction set D.
F8 2
1
•
•
•
•
1
•
•
•
SEI
I←1
This instruction set I.
78 2
1
•
•
•
•
•
1
•
•
SET
T←1
This instruction set T.
32 2
1
•
•
1
•
•
•
•
•
STA
M←A
This instruction stores the contents of A in M.
The contents of A does not change.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
This instruction resets the oscillation control F/
F and the oscillation stops. Reset or interrupt
input is needed to wake up from this mode.
STP
0B 2
+
20i
1
0F 5
+
20i
85 4
42 2
2
M←X
This instruction stores the contents of X in M.
The contents of X does not change.
86 4
2
STY
M←Y
This instruction stores the contents of Y in M.
The contents of Y does not change.
84 4
2
TAX
X←A
This instruction stores the contents of A in X. AA 2
The contents of A does not change.
TAY
Y←A
This instruction stores the contents of A in Y.
The contents of A does not change.
TST
M = 0?
This instruction tests whether the contents of
M are “0” or not and modifies the N and Z.
TSX
X←S
This instruction transfers the contents of S in BA 2
X.
TXA
A←X
This instruction stores the contents of X in A.
TXS
S←X
TYA
A←Y
Notes 1
2
3
4
5
3-76
:
:
:
:
:
95 5
2
8D 5
3 9D 6
3 99 6
3
81 7
2 91 7
2
1
STX
WIT
2
2 8E 5
3
•
•
•
•
•
•
•
•
8C 5
3
•
•
•
•
•
•
•
•
1
N
•
•
•
•
•
Z
•
1
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
1
N
•
•
•
•
•
Z
•
8A 2
1
N
•
•
•
•
•
Z
•
This instruction stores the contents of X in S.
9A 2
1
•
•
•
•
•
•
•
•
This instruction stores the contents of Y in A.
98 2
1
N
•
•
•
•
•
Z
•
The WIT instruction stops the internal clock
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All registers or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
C2 2
1
•
•
•
•
•
•
•
•
A8 2
64 3
96 5
94 5
2
2
The number of cycles “n” is increased by 3 when T is 1.
The number of cycles “n” is increased by 2 when T is 1.
The number of cycles “n” is increased by 1 when T is 1.
The number of cycles “n” is increased by 2 when branching has occurred.
N, V, and Z flags are invalid in decimal operation mode.
3850 Group (Spec. H) User’s Manual
3850 Group (Spec. H) User’s Manual
3-77
APPENDIX
3.7 Machine instructions
Symbol
Contents
Symbol
IMP
IMM
A
BIT, A
BIT, A, R
ZP
BIT, ZP
BIT, ZP, R
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
Implied addressing mode
Immediate addressing mode
Accumulator or Accumulator addressing mode
Accumulator bit addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Z
I
D
B
T
V
N
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
Negative flag
+
–
✽
/
V
V
–
V
–
←
X
Y
S
PC
PS
PCH
PCL
ADH
ADL
FF
nn
zz
M
M(X)
M(S)
M(ADH, ADL)
M(00, ADL)
Ai
Mi
OP
n
#
3-78
3850 Group (Spec. H) User’s Manual
Contents
Addition
Subtraction
Multiplication
Division
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Zero page address
Memory specified by address designation of any addressing mode
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits.
Contents of address indicated by zero page ADL
Bit i (i = 0 to 7) of accumulator
Bit i (i = 0 to 7) of memory
Opcode
Number of cycles
Number of bytes
APPENDIX
3.8 List of instruction code
3.8 List of instruction code
D7 – D4
D3 – D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Hexadecimal
notation
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ORA
ABS
ASL
ABS
SEB
0, ZP
0000
0
BRK
BBS
ORA
JSR
IND, X ZP, IND 0, A
—
ORA
ZP
ASL
ZP
BBS
0, ZP
PHP
ORA
IMM
ASL
A
SEB
0, A
—
0001
1
BPL
ORA
IND, Y
CLT
BBC
0, A
—
ORA
ZP, X
ASL
ZP, X
BBC
0, ZP
CLC
ORA
ABS, Y
DEC
A
CLB
0, A
—
0010
2
JSR
ABS
AND
IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
PLP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
0011
3
BMI
AND
IND, Y
SET
BBC
1, A
—
AND
ZP, X
ROL
ZP, X
BBC
1, ZP
SEC
AND
ABS, Y
INC
A
CLB
1, A
ROL
CLB
LDM
AND
ZP ABS, X ABS, X 1, ZP
0100
4
RTI
EOR
IND, X
STP
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
PHA
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
0101
5
BVC
EOR
IND, Y
—
BBC
2, A
—
EOR
ZP, X
LSR
ZP, X
BBC
2, ZP
CLI
EOR
ABS, Y
—
CLB
2, A
—
0110
6
RTS
MUL
ADC
IND, X ZP, X
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
PLA
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
0111
7
BVS
ADC
IND, Y
—
BBC
3, A
—
ADC
ZP, X
ROR
ZP, X
BBC
3, ZP
SEI
ADC
ABS, Y
—
CLB
3, A
—
1000
8
BRA
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
DEY
—
TXA
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
1001
9
BCC
STA
IND, Y
—
BBC
4, A
STY
ZP, X
STA
ZP, X
STX
ZP, Y
BBC
4, ZP
TYA
STA
ABS, Y
TXS
CLB
4, A
—
STA
ABS, X
—
CLB
4, ZP
1010
A
LDY
IMM
LDA
IND, X
LDX
IMM
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
TAY
LDA
IMM
TAX
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
1011
B
BCS
JMP
BBC
LDA
IND, Y ZP, IND 5, A
LDY
ZP, X
LDA
ZP, X
LDX
ZP, Y
BBC
5, ZP
CLV
LDA
ABS, Y
TSX
CLB
5, A
1100
C
CPY
IMM
CMP
IND, X
WIT
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
INY
CMP
IMM
DEX
SEB
6, A
CPY
ABS
1101
D
BNE
CMP
IND, Y
—
BBC
6, A
—
CMP
ZP, X
DEC
ZP, X
BBC
6, ZP
CLD
CMP
ABS, Y
—
CLB
6, A
—
1110
E
CPX
IMM
DIV
SBC
IND, X ZP, X
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
INX
SBC
IMM
NOP
SEB
7, A
CPX
ABS
1111
F
BEQ
SBC
IND, Y
BBC
7, A
—
SBC
ZP, X
INC
ZP, X
BBC
7, ZP
SED
SBC
ABS, Y
—
CLB
7, A
—
—
ASL
CLB
ORA
ABS, X ABS, X 0, ZP
AND
ABS
EOR
ABS
ROL
ABS
LSR
ABS
SEB
1, ZP
SEB
2, ZP
LSR
CLB
EOR
ABS, X ABS, X 2, ZP
ADC
ABS
ROR
ABS
SEB
3, ZP
ROR
CLB
ADC
ABS, X ABS, X 3, ZP
LDX
CLB
LDY
LDA
ABS, X ABS, X ABS, Y 5, ZP
CMP
ABS
DEC
ABS
SEB
6, ZP
DEC
CLB
CMP
ABS, X ABS, X 6, ZP
SBC
ABS
INC
ABS
SEB
7, ZP
INC
CLB
SBC
ABS, X ABS, X 7, ZP
: 3-byte instruction
: 2-byte instruction
: 1-byte instruction
3850 Group (Spec. H) User’s Manual
3-79
APPENDIX
3.9 SFR memory map
3.9 SFR memory map
000016
Port P0 (P0)
002016
Prescaler 12 (PRE12)
000116
Port P0 direction register (P0D)
002116
Timer 1 (T1)
000216
Port P1 (P1)
002216
Timer 2 (T2)
000316
Port P1 direction register (P1D)
002316
Timer XY mode register (TM)
000416
Port P2 (P2)
002416
Prescaler X (PREX)
000516
Port P2 direction register (P2D)
002516
Timer X (TX)
000616
Port P3 (P3)
002616
Prescaler Y (PREY)
000716
Port P3 direction register (P3D)
002716
Timer Y (TY)
000816
Port P4 (P4)
002816
Timer count source selection register (TCSS)
000916
Port P4 direction register (P4D)
002916
000A16
002A16
000B16
002B16
Reserved ✽
000C16
002C16
Reserved ✽
000D16
002D16
Reserved ✽
000E16
002E16
Reserved ✽
000F16
002F16
Reserved ✽
001016
003016
Reserved ✽
003116
Reserved ✽
001116
001216
Reserved ✽
003216
001316
Reserved ✽
003316
001416
Reserved ✽
003416
A-D control register (ADCON)
001516
Serial I/O2 control register 1 (SIO2CON1)
003516
A-D conversion low-order register (ADL)
001616
Serial I/O2 control register 2 (SIO2CON2)
003616
A-D conversion high-order register (ADH)
001716
Serial I/O2 register (SIO2)
003716
Reserved ✽
001816
Transmit/Receive buffer register (TB/RB)
003816
MISRG
001916
Serial I/O1 status register (SIOSTS)
003916
Watchdog timer control register (WDTCON)
001A16
Serial I/O1 control register (SIOCON)
003A16
Interrupt edge selection register (INTEDGE)
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1 (IREQ1)
001D16
PWM control register (PWMCON)
003D16
Interrupt request register 2 (IREQ2)
001E16
PWM prescaler (PREPWM)
003E16
Interrupt control register 1 (ICON1)
001F16
PWM register (PWM)
003F16
Interrupt control register 2 (ICON2)
0FFE16
Flash memory control register (FMCR)
✽ Reserved : Do not write any data to this addresses, because these areas are reserved.
3-80
3850 Group (Spec. H) User’s Manual
APPENDIX
3.10 Pin configurations
3.10 Pin configurations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
M38503MXH-XXXFP/SP
VCC
VREF
AVSS
P44/INT3/PWM
P43/INT2/SCMP2
P42/INT1
P41/INT0
P40/CNTR1
P27/CNTR0/SRDY1
P26/SCLK1
P25/TxD
P24/RxD
P23
P22
CNVSS
VPP
P21/XCIN
P20/XCOUT
RESET
XIN
XOUT
VSS
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P30/AN0
P31/AN1
P32/AN2
P33/AN3
P34/AN4
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04
P05
P06
P07
P10/(LED0)
P11/(LED1)
P12/(LED2)
P13/(LED3)
P14/(LED4)
P15/(LED5)
P16/(LED6)
P17/(LED7)
: Flash memory version
3850 Group (Spec. H) User’s Manual
3-81
APPENDIX
3.10 Pin configurations
M38517RSS PIN CONFIGURATION (TOP VIEW)
VCC
1
42
P30/AN0
VREF
2
41
P31/AN1
AVSS
3
40
P32/AN2
P44/INT3/PWM
4
1
28
39
P33/AN3
P43/INT2/SCMP2
5
2
27
38
P34/AN4
P42/INT1
6
37
P00/SIN2
3
26
36
P01/SOUT2
4
25
35
P02/SCLK2
24
34
P03/SRDY2
P41/INT0
P40/CNTR1
7
8
P27/CNTR0/SRDY1
9
5
P26/SCLK1
10
6
23
33
P04
P25/TXD
11
7
22
32
P05
P24/RXD
12
8
21
31
P06
P23
13
30
P07
9
20
29
P10/(LED0)
10
19
28
P11/(LED1)
P22
14
CNVSS
15
P21/XCIN
16
11
18
27
P12/(LED2)
P20/XCOUT
17
12
17
26
P13/(LED3)
RESET
18
13
16
25
P14/(LED4)
XIN
19
14
15
24
P15/(LED5)
XOUT
20
23
P16/(LED6)
VSS
21
22
P17/(LED7)
Outline : 42S1M
3-82
3850 Group (Spec. H) User’s Manual
RENESAS 8-BIT CISC SINGLE-CHIP MICROCOMPUTER
USER’S MANUAL
3850 Group (Spec. H) Rev.1.03
Editioned by
Committee of editing of RENESAS Semiconductor User’s Manual
This book, or parts thereof, may not be reproduced in any form without permission
of Renesas Technology Corporation.
Copyright © 2003. Renesas Technology Corporation, All rights reserved.
3850 Group (Spec. H)
User’s Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan