Maxim DS1374C-33 I2c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output Datasheet

19-5484; Rev 4; 8/10
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
Features
The DS1374 is a 32-bit binary counter designed to continuously count time in seconds. An additional counter generates a periodic alarm or serves as a watchdog timer. If
disabled, this counter can be used as 3 bytes of nonvolatile (NV) RAM. Separate output pins are provided for
an interrupt and a square wave at one of four selectable
frequencies. A precision temperature-compensated reference and comparator circuit monitor the status of VCC to
detect power failures, provide a reset output, and automatically switch to the backup supply when necessary.
Additionally, the reset pin is monitored as a pushbutton
input for externally generating a reset. The device is programmed serially through an I2C serial interface.
♦ 32-Bit Binary Counter
♦ Second Binary Counter Provides Time-of-Day
Alarm, Watchdog Timer, or NV RAM
♦ Separate Square-Wave and Interrupt Output Pins
♦ I2C Serial Interface
♦ Automatic Power-Fail Detect and Switch Circuitry
♦ Single-Pin Pushbutton Reset Input/Open-Drain
Reset Output
♦ Low-Voltage Operation
♦ Trickle-Charge Capability
♦ -40°C to +85°C Operating Temperature Range
♦ 10-Pin µSOP, 16-Pin SO
♦ Available in a Surface-Mount Package with an
Integrated Crystal (DS1374C)
♦ Underwriters Laboratories (UL) Recognized
Applications
Portable Instruments
Typical Operating Circuit
Point-of-Sale Equipment
Medical Equipment
Telecommunications
RPU = tr/CB
VCC
VCC
CRYSTAL
RPU RPU
VCC
X1
VCC
X2
SQW
SCL
CPU
SDA
INT
RST
RST
N.O.
PUSHBUTTON
RESET
Pin Configurations appear at the end of the data sheet.
DS1374
INT
VBACKUP
GND
PRIMARY
BATTERY,
RECHARGEABLE
BATTERY, OR
SUPER CAPACITOR
Ordering Information
PART
TEMP RANGE
VOLTAGE (V)
PIN-PACKAGE
TOP MARK**
DS1374C-18#
-40°C to +85°C
1.8
16 SO (300 mils)
DS1374C-18
DS1374C-3#
-40°C to +85°C
3.0
16 SO (300 mils)
DS1374C-3
DS1374C-33#
-40°C to +85°C
3.3
16 SO (300 mils)
DS1374C-33
DS1374U-18+
-40°C to +85°C
1.8
10 μSOP
DS1374-18
DS1374U-3+
-40°C to +85°C
3.0
10 μSOP
DS1374-3
DS1374U-33+
-40°C to +85°C
3.3
10 μSOP
DS1374-33
#Denotes a RoHS-compliant device that may include lead that is exempt under RoHS requirements. The lead finish is JESD97 category
e3, and is compatible with both lead-based and lead-free soldering processes.
+Denotes a lead(Pb)-free/RoHS-compliant package.
**A "#" anywhere on the top mark denotes a RoHS-compliant package. A “+” anywhere on the top mark denotes a lead(Pb)-free
package.
______________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
DS1374
General Description
DS1374
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC Pin Relative to Ground .....-0.3V to +6.0V
Voltage Range on SDA or SCL
Relative to Ground ....................................-0.3V to VCC + 0.3V
Junction-to-Ambient Thermal Resistance (θJA) (Note 1)
16-Pin SO .....................................................................73°C/W
10-Pin µSOP ...............................................................221°C/W
Note 1:
Junction-to-Case Thermal Resistance (θJC) (Note 1)
16-Pin SO .....................................................................23°C/W
10-Pin µSOP .................................................................39°C/W
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +125°C
Lead Temperature (soldering, 10s) .................................+260°C
Soldering Temperature (reflow) .......................................+260°C
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
MIN
TYP
MAX
DS1374-33
CONDITIONS
2.97
3.3
5.50
DS1374-3
2.7
3.0
3.3
1.71
1.8
Supply Voltage
(Notes 3, 4)
VCC
Input Logic 1
VIH
(Note 3)
Input Logic 0
VIL
(Note 3)
Pullup Resistor Voltage (INT,
SQW, SDA, SCL), VCC = 0V
VPU
(Note 3)
DS1374-18
Power-Fail Voltage
(Note 3)
Backup Supply Voltage
(Notes 3, 4, 5)
2
VPF
VBACKUP
0.7 x VCC
-0.3
V
1.89
VCC + 0.3
V
+0.3 x
VCC
V
5.5
V
DS1374-33
2.70
2.88
DS1374-3
2.45
2.6
2.7
DS1374-18
1.51
1.6
1.71
DS1374-33
1.3
3.0
VCC
(MAX)
DS1374-3, DS1374-18
1.3
3.0
3.7
_____________________________________________________________________
UNITS
2.97
V
V
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
DS1374
DC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX) , TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
Trickle-Charge Current-Limiting
Resistors
SYMBOL
CONDITIONS
MIN
TYP
R1
(Note 6)
250
R2
(Note 7)
2000
MAX
R3
(Note 8)
Input Leakage
ILI
(Note 9)
-1
+1
I/O Leakage
ILO
(Note 10)
-1
+1
RST Pin I/O Leakage
ILORST
(Note 11)
-200
SDA Logic 0 Output (VOL = 0.4V)
I OLSDA
RST, SQW, and INT Logic 0
Outputs (Note 12)
I OL1
4000
VCC > 2V; VOL = 0.4V
1.71V < VCC < 2V; VOL = 0.2 VCC
3.0
3.0
250
DS1374-18
Standby Current (Notes 12, 14)
VBACKUP Leakage Current
(VBACKUP = 3.7V)
ICCA
ICCS
μA
+1
3.0
1.3V < VCC < 1.71V; VOL = 0.2 VCC
Active Supply Current
(Notes 12, 13)
UNITS
75
mA
μA
150
DS1374-3
110
200
DS1374-33
180
300
DS1374-18
60
100
DS1374-3
80
125
DS1374-33
115
175
IBACKUPLKG
mA
μA
μA
100
nA
TYP
MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
(VCC = 0V, VBACKUP = 3.7V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MAX
VBACKUP Current (OSC ON);
SQW OFF
IBKOSC1
(Note 15)
400
700
nA
VBACKUP Current (OSC ON);
SQW ON (32kHz)
IBKOSC2
(Notes 15, 16)
600
1000
nA
25
100
nA
VBACKUP Data-Retention Current
(OSC OFF)
IBACKUPDR
_____________________________________________________________________
3
DS1374
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
AC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted.) (Note 2) (Figure 1)
PARAMETER
SYMBOL
SCL Clock Frequency (Note 17)
f SCL
Bus Free Time Between STOP
and START Conditions
tBUF
Hold Time (Repeated) START
Condition (Note 18)
tHD:STA
Low Period of SCL Clock
tLOW
High Period of SCL Clock
tHIGH
Data Hold Time (Notes 19, 20)
tHD:DAT
Data Setup Time (Note 21)
t SU:DAT
Start Setup Time
t SU:STA
Rise Time of Both SDA and SCL
Signals (Note 17)
tR
Fall Time of Both SDA and SCL
Signals (Note 17)
tF
Setup Time for STOP Condition
t SU:STO
Capacitive Load for Each Bus Line
CONDITIONS
Fast mode
Standard mode
MIN
TYP
MAX
100
400
0
100
Fast mode
1.3
Standard mode
4.7
Fast mode
0.6
Standard mode
4.0
Fast mode
1.3
Standard mode
4.7
Fast mode
0.6
Standard mode
4.0
μs
μs
μs
0
0.9
Standard mode
0
0.9
100
Standard mode
250
Fast mode
0.6
Standard mode
4.7
Fast mode
Standard mode
Fast mode
Standard mode
μs
300
1000
300
20 +
0.1CB
0.6
Standard mode
4.7
μs
ns
20 +
0.1CB
Fast mode
kHz
μs
Fast mode
Fast mode
UNITS
300
ns
ns
μs
CB
(Note 17)
400
pF
I/O Capacitance (SDA, SCL)
CI/O
(Note 22)
10
pF
Pulse Width of Spikes That Must
be Suppressed by the Input Filter
t SP
Fast mode
30
ns
Pushbutton Debounce
PBDB
(Figure 2)
250
ms
Reset Active Time
tRST
(Figure 2)
250
ms
Oscillator Stop Flag (OSF) Delay
t OSF
(Note 23)
100
ms
4
_____________________________________________________________________
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
(TA = -40°C to +85°C) (Figure 3)
PARAMETER
VCC Detect to Recognize Inputs
(VCC Rising)
SYMBOL
tRPU
CONDITIONS
MIN
(Note 24)
TYP
250
MAX
UNITS
ms
VCC Fall Time; VPF(MAX) to
VPF(MIN)
tF
300
μs
VCC Rise Time; V PF(MIN) to
VPF(MAX)
tR
0
μs
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when the device is in write protection.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
Note 19:
Note 20:
Note 21:
Note 22:
Note 23:
Note 24:
Limits at -40°C are guaranteed by design and not production tested.
All voltages are referenced to ground.
VBACKUP should not exceed VCC MAX or 3.7V, whichever is greater.
The use of the 250Ω trickle-charge resistor is not allowed at VCC > 3.63V and should not be enabled.
Measured at VCC = typ, VBACKUP = 0V, register 09h = A5h.
Measured at VCC = typ, VBACKUP = 0V, register 09h = A6h.
Measured at VCC = typ, VBACKUP = 0V, register 09h = A7h.
SCL only.
SDA and SQW and INT.
The RST pin has an internal 50kΩ pullup resistor to VCC.
Trickle charger disabled.
ICCA—SCL clocking at max frequency = 400kHz.
Specified with I2C bus inactive.
Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
WDSTR = 1. BBSQW = 1 is required for operation when VCC is below the power-fail trip point (or absent).
CB—total capacitance of one bus line in pF.
After this period, the first clock pulse is generated.
The maximum tHD:DAT only has to be met if the device does not stretch the low period (tLOW) of the SCL signal.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL.
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must be met. This is
automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low
period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before
the SCL line is released.
Guaranteed by design. Not production tested.
The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
0V ≤ VCC ≤ VCC MAX and 1.3V ≤ VBACKUP ≤ 3.7V.
This delay applies only if the oscillator is enabled and running. If the EOSC bit is 1, the startup time of the oscillator is
added to this delay.
_____________________________________________________________________
5
DS1374
POWER-UP/POWER-DOWN CHARACTERISTICS
DS1374
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
SDA
tBUF
tSP
tHD:STA
tLOW
tR
tF
SCL
tHD:STA
STOP
tSU:STA
tHIGH
tSU:DAT
START
tSU:STO
REPEATED
START
tHD:DAT
Figure 1. Data Transfer on I2C Serial Bus
RST
PBDB
tRST
Figure 2. Pushbutton Reset Timing
VCC
VPF(MAX)
VPF
VPF
VPF(MIN)
tF
tR
tRPU
tRST
RST
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
Figure 3. Power-Up/Power-Down Timing
6
_____________________________________________________________________
VALID
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
IBAT0SC2 vs. VBAT
SQUARE-WAVE ON
VCC = 0V
SUPPLY CURRENT (nA)
750
450
400
475
VCC = 0V
700
650
600
550
500
450
425
400
450
350
400
350
2.8
3.3
3.8
4.3
4.8
5.3
375
1.3
1.8
2.3
2.8
VBAT (V)
3.3
3.8
4.3
4.8
5.3
-20
-40
VBAT (V)
0
20
40
60
80
TEMPERATURE (°C)
ICCA vs. VCC
(SQUARE-WAVE ON)
OSCILLATOR FREQUENCY vs. VBACKUP
275
32768.8
250
VCC = 0V
32768.7
225
FREQUENCY (Hz)
32768.6
200
175
150
125
32768.5
32768.4
32768.3
32768.2
100
32768.1
75
32768.0
50
1.8
2.3
2.8
3.3
3.8
4.3
4.8
1.3
5.3
1.8
2.3
2.8
3.3
3.8
4.3
4.8
5.3
VBACKUP (V)
VCC (V)
VCC FALLING vs. RST DELAY
1000
VCC = 3.0V TO 0V
DS1374 toc06
2.3
DS1374 toc04
1.8
100
RESET DELAY (μs)
1.3
DS1374 toc05
300
SUPPLY CURRENT (μA)
SUPPLY CURRENT (nA)
500
800
SUPPLY CURRENT (nA)
VCC = 0V
DS1374 toc03
DS1374 toc01
550
IBATOSC1 vs. TEMPERATURE
VBAT = 3.0V
DS1374 toc02
IBAT0SC1 vs. VBAT
SQUARE-WAVE OFF
10
1
0.1
0.01
0.10
1
10
100
VCC FALLING (V/ms)
_____________________________________________________________________
7
DS1374
Typical Operating Characteristics
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
DS1374
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
Pin Description
PIN
μSOP
1, 2
3
SO
—
13
NAME
FUNCTION
X1, X2
Connections for a Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed
for operation with a crystal having a specified load capacitance (CL) of 6pF. Pin X1 is the input to the
oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the
internal oscillator, pin X2, is left unconnected if an external oscillator is connected to pin X1.
Connection for a Secondary Power Supply. This supply is used to operate the oscillator and
counters when VCC is absent. Supply voltage must be held between 1.3V and 3.7V (-18 and -3) or
1.3V and 5.5V (-33) for proper operation. This pin can be connected to a primary cell such as a
VBACKUP
lithium cell. Additionally, this pin can be connected to a rechargeable cell or a super cap when
used with the trickle-charge feature. UL recognized to ensure against reverse charging when used
with a lithium battery. This pin must be grounded if not used.
4
14
RST
Active-Low, Open-Drain Output with a Debounced Pushbutton Input. This pin can be activated by a
pushbutton reset request, a watchdog alarm condition, or a power-fail event. It has an internal 50k
pullup resistor. No external resistors should be connected. If the crystal oscillator is disabled, the
startup time of the oscillator is added to the tRST delay.
5
15
GND
Ground
6
16
SDA
Serial Data Input/Output. SDA is the input/output for the 2-wire serial interface. The SDA pin is open
drain and requires an external pullup resistor.
7
1
SCL
Serial Clock Input. SCL is the clock input for the 2-wire serial interface and is used to synchronize
data movement on the serial interface.
8
2
INT
Interupt. This pin is used to output the alarm interrupt or the watchdog reset signal. It is active-low
open drain and requires an external pullup resistor.
9
3
SQW
Square-Wave Output. This pin is used to output the programmable square-wave signal. It is open
drain and requires an external pullup resistor.
10
4
VCC
DC Power for Primary Power Supply
—
5–12
N.C.
No Connection. Must be connected to ground.
X1
X2
VCC
VBACKUP
GND
SDA
SCL
CLOCK
DIVIDER
POWER
CONTROL
AND
TRICKLE
CHARGE
1Hz
4.096kHz
8.192kHz
32.768kHz
SQW
MUX
1Hz/4.096kHz
32-BIT
COUNTER
ALARM/
WATCHDOG
INT
RST
CONTROL
RST
24-BIT
COUNTER
STAT/CTRL/
TRICKLE
2-WIRE
INTERFACE
DS1374
Figure 4. Functional Diagram
8
INT
CONTROL
_____________________________________________________________________
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
PARAMETER
SYMBOL
Nominal
Frequency
fO
Series
Resistance
ESR
MIN
TYP
DS1374
Table 1. Crystal Specifications*
LOCAL GROUND PLANE (LAYER 2)
MAX
UNITS
32.768
X1
kHz
CRYSTAL
Load
Capacitance
45
CL
6
kΩ
X2
pF
*The crystal, traces, and crystal input pins should be isolated
from RF generating signals. Refer to Application Note 58:
Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
GND
NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED AREA (UPPER LEFT-HAND
QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE
SIGNAL LINE AND THE PACKAGE.
Figure 6. Layout Example
COUNTDOWN
CHAIN
DS1374
CL1
CL 2
RTC
REGISTERS
X2
X1
Oscillator Circuit
The DS1374 uses an external 32.768kHz crystal. The
oscillator circuit does not require any external resistors
or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 5 shows a
functional schematic of the oscillator circuit. The startup
time is usually less than 1 second when using a crystal
with the specified characteristics.
Clock Accuracy
CRYSTAL
Figure 5. Oscillator Circuit Showing Internal Bias Network
Detailed Description
The DS1374 is a real-time clock with an I2C serial interface. It provides elapsed seconds from a user-defined
starting point in a 32-bit counter (Figure 4). A 24-bit
counter can be configured as either a watchdog
counter or an alarm counter. An on-chip oscillator circuit uses a customer-supplied 32.768kHz crystal to
keep time. A power-control circuit switches operation
from VCC to VBACKUP and back when power on VCC is
cycled. The oscillator and counters continue to operate
when powered by either supply. If a rechargeable
backup supply is used, a trickle charger can be
enabled to charge the backup supply while VCC is on.
Clock accuracy is dependent upon the accuracy of the
crystal and the accuracy of the match between the
capacitive load of the oscillator circuit and the capacitive
load for which the crystal was trimmed. Additional error
is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 6
shows a typical PC board layout for isolating the crystal
and oscillator from noise. Refer to Application Note 58:
Crystal Considerations with Dallas Real-Time Clocks for
detailed information.
DS1374C Only
The DS1374C integrates a standard 32,768Hz crystal
into the package. Typical accuracy at nominal VCC and
25°C is approximately 10ppm. See Application Note 58
for information about crystal accuracy vs. temperature.
_____________________________________________________________________
9
DS1374
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
Power Control
Address Map
The power-control function is provided by a precise,
temperature-compensated voltage reference and a
comparator circuit that monitors the V CC level. The
device is fully accessible and data can be written and
read when VCC is greater than VPF. However, when
VCC falls below VPF, the internal clock registers are
blocked from any access. If VPF is less than VBACKUP,
the device power is switched from VCC to VBACKUP
when V CC drops below V PF . If V PF is greater than
VBACKUP, the device power is switched from VCC to
VBACKUP when VCC drops below VBACKUP. The registers are maintained from the VBACKUP source until VCC
is returned to nominal levels (Table 1). After V CC
returns above VPF, read and write access is allowed
after RST goes high (Figure 1).
Table 3 shows the address map for the DS1374 registers. During a multibyte access, the address pointer
wraps around to location 00h when it reaches the end of
the register space (08h). On an I2C START, STOP, or
address pointer incrementing to location 00h, the current
time is transferred to a second set of registers. These
secondary registers read the time information, while the
clock continues to run. This eliminates the need to reread
the registers in case of an update of the main registers
during a read.
Time-of-Day Counter
The time-of-day counter is a 32-bit up counter that
increments once per second when the oscillator is running. The contents can be read or written by accessing
the address range 00h–03h. When the counter is read,
the current time of day is latched into a register, which
is output on the serial data line while the counter continues to increment.
Note: Writing to any TOD register will reset the 1Hz
square wave output.
Table 2. Power Control
SUPPLY CONDITION
READ/WRITE
ACCESS
POWERED
BY
VCC < VPF, VCC < VBACKPUP
No
VBACKUP
VCC < VPF, VCC > VBACKUP
No
VCC
VCC > VPF, VCC < VBACKUP
Yes
VCC
VCC > VPF, VCC > VBACKUP
Yes
VCC
Table 3. Address Map
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TOD Counter Byte 0
Time-of-Day Counter
01H
TOD Counter Byte 1
Time-of-Day Counter
02H
TOD Counter Byte 2
Time-of-Day Counter
03H
TOD Counter Byte 3
Time-of-Day Counter
04H
WD/ALM Counter Byte 0
Watchdog/Alarm Counter
05H
WD/ALM Counter Byte 1
Watchdog/Alarm Counter
06H
WD/ALM Counter Byte 2
Watchdog/Alarm Counter
07H
EOSC
WACE
WD/ALM
BBSQW
WDSTR
RS2
RS1
AIE
Control
08H
OSF
0
0
0
0
0
0
AF
Status
09H
TCS3
TCS2
TCS1
TCS0
DS1
DS0
ROUT1
ROUT0
Trickle Charger
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied.
10
FUNCTION
00H
____________________________________________________________________
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
The contents of the watchdog/alarm counter, which is a
separate 24-bit down counter, are accessed in the
address range 04h–06h. When this counter is written, the
counter and a seed register are loaded with the desired
value. When the counter is to be reloaded, it uses the
value in the seed register. When the counter is read, the
current counter value is latched into a register, which is
output on the serial data line while the counter continues
to decrement.
IIf the counter is not needed, it can be disabled and
used as a 24-bit cache of NV RAM by setting the
WACE bit in the control register to logic 0. If all 24 bits
of the watchdog/alarm counter are written to zero, the
counter is disabled, independent of the WACE bit setting. When the watchdog counter is is written to a
nonzero value, and WACE is written to logic 1, the function of the counter is determined by the WD/ALM bit.
When the WD/ALM bit in the control register is set to
logic 0, the WD/ALM counter decrements every second
until it reaches zero. At this point, the AF bit in the status register is set to 1 and the counter is reloaded and
restarted. AF remains set until cleared by writing it to 0.
If AIE = 1, the INT pin goes active whenever AF = 1.
WDSTR does not affect operation when WD/ALM = 0.
When the WD/ALM bit is set to logic 1, the WD/ALM
counter decrements every 1/4096 of a second (approximately every 244us) until it reaches zero. When any of
the watchdog counters bytes are read, the seed value
is reloaded and the counter restarts. Writing to the
watchdog counter updates the seed value and reloads
the counter with the new seed value. When the counter
reaches zero, the AF bit is set and the counter stops.
If WDSTR = 0, the RST pin pulses low for 250ms, and
accesses to the device are inhibited. At the end of the
250ms pulse, the AF bit is cleared to zero, the RST pin
becomes high impedance, and read/write access to
the device is enabled.
If WDSTR = 1 and the counter reaches zero, the AF bit
is set and the counter stops. If AIE = 0, AF remains set
until cleared by writing it to 0. If AIE = 1, the INT pin
pulses low for 250ms. At the end of the 250ms pulse,
the AF bit is cleared and INT becomes high impedance.
The 250ms pulse on INT or RST cannot be truncated by
writing either AF or AIE to zero during the low time. If the
INT counter is written during the 250ms pulse, the
counter starts decrementing upon the pulse completion.
The watchdog and alarm function operates from VCC or
VBAT. When the AF bit is set, INT is pulled low when the
device is powered by VCC or VBAT.
Note: WACE must be toggled from logic 0 to logic 1
after the watchdog counter is written from a zero to a
nonzero value.
Power-Up/Power-Down Reset and
Pushbutton Reset Functions
A precision temperature-compensated reference and
comparator circuit monitors the status of VCC. When an
out-of-tolerance condition occurs, an internal power-fail
signal is generated that forces the RST pin low and
blocks read/write access to the DS1374. When VCC
returns to an in-tolerance condition, the RST pin is held
low for 250ms to allow the power supply to stabilize. If
the EOSC bit is set to a logic 1 (to disable the oscillator in
battery-backup mode), the reset signal is kept active for
250ms plus the startup time of the oscillator.
The DS1374 provides for a pushbutton switch to be connected to the RST output pin. When the DS1374 is not in
a reset cycle, it continuously monitors the RST signal for
a low-going edge. If an edge is detected, the DS1374
debounces the switch by pulling the RST pin low and
inhibits read/write access. After the internal 250ms timer
has expired, the device continues to monitor the RST
line. If the line is still low, the DS1374 continues to monitor the line, looking for a rising edge. Upon detecting
release, the DS1374 forces the RST pin low and holds it
low for an additional 250ms.
____________________________________________________________________
11
DS1374
Watchdog/Alarm Counter
DS1374
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
Bit 7
EOSC
Bit 6
WACE
Bit 5
WD/ALM
Bit 4
BBSQW
Special Purpose Registers
The DS1374 has two additional registers (07h–08h) that
control the WD/ALM counter and the square-wave, interrupt, and reset outputs.
Control Register (07h)
Bit 7/Enable Oscillator (EOSC). When set to logic 0,
the oscillator is started. When set to logic 1, the oscillator is stopped. When this bit is set to logic 1, the oscillator is stopped and the DS1374 is placed into a
low-power standby mode (IDDR). This bit is clear (logic
0) when power is first applied. When the DS1374 is
powered by VCC, the oscillator is always on regardless
of the state of the EOSC bit.
ALM Counter Enable (WACE). When set to
Bit 6/WD/A
logic 1, the WD/ALM counter is enabled. When set to
logic 0, the WD/ALM counter is disabled, and the 24
bits can be used as NV RAM. This bit is clear (logic 0)
when power is first applied.
ALM Counter Select (WD/ALM). When set to
Bit 5/WD/A
logic 0, the counter decrements every second until it
reaches zero and is then reloaded and restarted. When
set to logic 1, the WD/ALM counter decrements every
1/4096 of a second (approximately every 244µs) until it
reaches zero, sets the AF bit in the status register, and
stops. If any of the WD/ALM counter registers are
accessed before the counter reaches zero, the counter
is reloaded and restarted. This bit is clear (logic 0)
when power is first applied.
Bit 4/Battery-Backed Square-Wave Enable (BBSQW).
This bit, when set to logic 1, enables the square-wave
output when VCC is absent and when the DS1374 is
being powered by the VBACKUP pin. When BBSQW is
12
Bit 3
WDSTR
Bit 2
RS2
Bit 1
RS1
Bit 0
AIE
logic 0, the SQW pin goes high impedance when VCC
falls below the power-fail trip point. This bit is disabled
(logic 0) when power is first applied.
Bit 3/Watchdog Reset Steering Bit (WDSTR). This bit
selects which output pin the watchdog-reset signal
occurs on. When the WDSTR bit is set to logic 0, a
250ms pulse occurs on the RST pin if WD/ALM = 1 and
the WD/ALM counter reaches zero. The 250ms reset
pulse occurs on the INT pin when the WDSTR bit is set
to logic 1. This bit is logic 0 when power is first applied.
Bits 2, 1/Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the
square wave has been enabled. Table 4 shows the
square-wave frequencies that can be selected with the
RS bits. These bits are both set (logic 1) when power is
first applied.
Bit 0/Alarm Interrupt Enable (AIE). When set to logic
1, this bit permits the alarm flag (AF) bit in the status
register to assert INT (when WDSTR = 1). When set to
logic 0 or WDSTR is set to logic 0, the AF bit does not
initiate the INT signal. If the WD/ALM bit is set to logic 1
and the AF flag is set, writing AIE to zero does not truncate the 250ms pulse on the INT pin. The AIE bit is at
logic 0 when power is first applied. The INT output is
available while the device is powered by either supply.
Table 4. Square-Wave Output Frequency
RS2
RS1
SQUARE-WAVE OUTPUT FREQUENCY
0
0
1Hz
0
1
4.096kHz
1
0
8.192kHz
1
1
32.768kHz
____________________________________________________________________
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSF
0
0
0
0
0
0
AF
Status Register (08h)
Bit 7/Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator either is stopped or was
stopped for some period of time and can be used to
judge the validity of the timekeeping data. This bit is set
to logic 1 any time the oscillator stops. The following
are examples of conditions that can cause the OSF bit
to be set:
1) The first time power is applied.
2) The voltage present on both VCC and VBACKUP are
insufficient to support oscillation.
3) The EOSC bit is turned off.
4) External influences on the crystal (i.e., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0.
Bit 0/Alarm Flag (AF). A logic 1 in the alarm flag bit
indicates that the WD/ALM counter reached zero. If
WD/ALM is set to zero and the AIE bit = 1, the INT pin
goes low and stays low until AF is cleared. AF is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write logic 1 leaves the
value unchanged. If WD/ALM is set to 1 and the AIE
bit = 1, the INT pin pulses low for 250ms when the
WD/ALM counter reaches zero and sets AF = 1. At the
pulse completion, the DS1374 clears the AF bit to zero.
If the 250ms pulse is active, writing AF to zero does not
truncate the pulse.
Trickle-Charge Register (10h)
select (TCS) bits (bits 4–7) control the selection of the
trickle charger. To prevent accidental enabling, only a
pattern of 1010 enables the trickle charger. All other
patterns disable the trickle charger. The trickle charger
is disabled when power is first applied. The diode
select (DS) bits (bits 2, 3) select whether or not a diode
is connected between VCC and VBACKUP. If DS is 01,
no diode is selected; if DS is 10, a diode is selected.
The ROUT bits (bits 0, 1) select the value of the resistor
connected between VCC and VBACKUP. Table 5 shows
the resistor selected by the resistor select (ROUT) bits
and the diode selected by the diode select (DS) bits.
Warning: The ROUT value of 250Ω must not be selected whenever VCC is greater than 3.63V.
The user determines diode and resistor selection
according to the maximum current desired for battery or
super cap charging. The maximum charging current can
be calculated as illustrated in the following example.
Assume that a system power supply of 3.3V is applied
to VCC and a super cap is connected to VBACKUP. Also
assume the trickle charger has been enabled with a
diode and resistor R2 between VCC and VBACKUP. The
maximum current IMAX would therefore be calculated
as follows:
IMAX = (3.3V - diode drop) / R2 ≈ (3.3V - 0.7V) / 2kΩ ≈
1.3mA
As the super cap changes, the voltage drop between
VCC and VBACKUP decreases and therefore the charge
current decreases.
The simplified schematic in Figure 7 shows the basic
components of the trickle charger. The trickle-charge
Table 5. Trickle Charge Register
TCS3
TCS2
TCS1
TCS0
DS1
DS0
ROUT1
ROUT0
FUNCTION
X
X
X
X
0
0
X
X
Disabled
X
X
X
X
1
1
X
X
Disabled
X
X
X
X
X
X
0
0
Disabled
1
0
1
0
0
1
0
1
No diode, 250Ω resistor
1
0
1
0
1
0
0
1
One diode, 250Ω resistor
1
0
1
0
0
1
1
0
No diode, 2kΩ resistor
1
0
1
0
1
0
1
0
One diode, 2kΩ resistor
1
0
1
0
0
1
1
1
No diode, 4kΩ resistor
1
0
1
0
1
0
1
1
One diode, 4kΩ resistor
0
0
0
0
0
0
0
0
Power-on reset value
____________________________________________________________________
13
DS1374
Bit 7
DS1374
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
BIT 7
TCS3
BIT 6
TCS2
BIT 5
TCS1
BIT 4
TCS0
BIT 3
DS1
BIT 2
DS0
BIT 1
BIT 0
ROUT1 ROUT0
TCS0-3 = TRICKLE CHARGER SELECT
DS0-1 = DIODE SELECT
TOUT0-1 = RESISTOR SELECT
1 OF 16 SELECT
NOTE: ONLY 1010b
ENABLES CHARGER
1 OF 2
SELECT
1 OF 3
SELECT
R1
250Ω
R2
2kΩ
VCC
VBACKUP
R3
4kΩ
Figure 7. Programmable Trickle Charger
SDA
MSB
SLAVE ADDRESS
R/W
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
1
2
6
7
8
9
1
2
3–7
8
ACK
START
CONDITION
9
ACK
REPEATED IF MORE BYTES
ARE TRANSFERED
STOP
CONDITION
OR REPEATED
START
CONDITION
Figure 8. I2C Data Transfer Overview
I2C Serial Data Bus
The DS1374 supports the I2C bus protocol. A device
that sends data onto the bus is defined as a transmitter
and a device receiving data is a receiver. The device
that controls the message is called a master. The
devices that are controlled by the master are slaves. A
master device that generates the serial clock (SCL),
controls the bus access, and generates the START and
STOP conditions must control the bus. The DS1374
operates as a slave on the I2C bus. Connections to the
bus are made through the open-drain I/O lines SDA
14
and SCL. A standard mode (100kHz max clock rate)
and a fast mode (400kHz max clock rate) are defined
within the bus specifications. The DS1374 works in both
modes.
The following bus protocol has been defined (Figure 8):
• Data transfer can be initiated only when the bus is
not busy.
• During data transfer, the data line must remain stable whenever the clock line is high. Changes in the
data line while the clock line is high can be interpreted as control signals.
____________________________________________________________________
S 1101000
0 A XXXXXXXX A
S - START
A - ACKNOWLEDGE
P - STOP
R/W - READ/WRITE OR
DIRECTION BIT
DATA (n)
XXXXXXXX
DATA (n + 1)
A
SLAVE
ADDRESS
DATA (n + x)
XXXXXXXX A XXXXXXXX
P
DATA TRANSFERRED
(X+1 Bytes + Acknowledge)
S 1101000
R/W
REGISTER
ADDRESS (n)
DATA (n)
DATA (n + 1)
1 A XXXXXXXX A
S - START
A - ACKNOWLEDGE
P - STOP
/A - NOT ACKNOWLEDGE
R/W - READ/WRITE OR
DIRECTION BIT
XXXXXXXX
DATA (n + 2)
A
DS1374
SLAVE
ADDRESS
R/W
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
DATA (n + x)
XXXXXXXX A XXXXXXXX
/A
DATA TRANSFERRED
(X+1 Bytes + Acknowledge)
Figure 9. I2C Write Protocol
Figure 10. I2C Read Protocol
Accordingly, the following bus conditions have been
defined:
the slave must leave the data line high to enable
the master to generate the STOP condition.
Figures 9 and 10 detail how data transfer is accomplished on the 2-wire bus. Depending on the state of
the R/W bit, two types of data transfer are possible:
Data transfer from a master transmitter to a
slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number
of data bytes. The slave returns an acknowledge
bit after each received byte.
Data transfer from a slave transmitter to a master receiver. The master transmits the first byte
(the slave address). The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all
received bytes other than the last byte. At the end
of the last received byte, a “not acknowledge” is
returned.
Bus not busy: Both data and clock lines remain
high.
Start data transfer: A change in the state of the
data line from high to low, while the clock line is
high, defines a START condition.
Stop data transfer: A change in the state of the
data line from low to high, while the clock line is
high, defines a STOP condition.
Data valid: The state of the data line represents
valid data when, after a START condition, the data
line is stable for the duration of the high period of
the clock signal. The data on the line must be
changed during the low period of the clock signal.
There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between the
START and the STOP conditions is not limited, and
is determined by the master device. The information is transferred byte-wise and each receiver
acknowledges with a ninth bit. A standard mode
(100kHz clock rate) and a fast mode (400kHz clock
rate) are defined within the I2C bus specifications.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device
must generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the
SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable low during
the high period of the acknowledge-related clock
pulse. Setup and hold times must be considered. A
master must signal an end of data to the slave by
not generating an acknowledge bit on the last byte
that has been clocked out of the slave. In this case,
The master device generates the serial clock pulses and the START and STOP conditions. A transfer
is ended with a STOP condition or with a repeated
START condition. Since a repeated START condition is also the beginning of the next serial transfer,
the bus is not released.
The DS1374 can operate in the following two modes:
Slave Receiver Mode (Write Mode): Serial data
and clock data are received through SDA and SCL.
After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware
after reception of the slave address and direction
bit. The slave address byte is the first byte
received after the master generates a START condition. The slave address byte contains the 7-bit
DS1374 address, which is 1101000, followed by
the direction bit (R/W), which is zero for a write.
After receiving and decoding the slave address
byte, the DS1374 outputs an acknowledge on SDA.
____________________________________________________________________
15
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
DS1374
After the DS1374 acknowledges the slave address
+ write bit, the master transmits a register address
to the DS1374. This sets the register pointer on the
DS1374, with the DS1374 acknowledging the transfer. The master can then transmit zero or more
bytes of data, with the DS1374 acknowledging
each byte received. The register pointer increments
after each data byte is transferred. The master generates a STOP condition to terminate the data write.
Slave Transmitter Mode (Read Mode): The first
byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit
indicates that the transfer direction is reversed.
Serial data is transmitted on SDA by the DS1374,
while the serial clock is input on SCL. START and
STOP conditions are recognized as the beginning
and end of a serial transfer. Address recognition is
performed by hardware after reception of the slave
address and direction bit. The slave address byte
is the first byte received after the START condition
is generated by the master. The slave address byte
contains the 7-bit DS1374 address, which is
1101000, followed by the direction bit (R/W), which
is 1 for a read. After receiving and decoding the
slave address byte, the DS1374 outputs an
acknowledge on SDA. The DS1374 then begins to
transmit data starting with the register address
pointed to by the register pointer. If the register
pointer is not written to before the initiation of a
read mode, the first address that is read is the last
one stored in the register pointer. The DS1374 must
receive a not acknowledge to end a read.
16
Handling, PC Board Layout, and
Assembly
The DS1374C package contains a quartz tuning-fork
crystal. Pick-and-place equipment can be used, but
precautions should be taken to ensure that excessive
shocks are avoided. Ultrasonic cleaning should be
avoided to prevent damage to the crystal.
Avoid running signal traces under the package, unless
a ground plane is placed between the package and the
signal line. All no connect (N.C.) pins must be connected to ground.
Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package label must be followed to prevent damage during
reflow. Refer to the IPC/JEDEC J-STD-020 standard for
moisture-sensitive device (MSD) classifications.
____________________________________________________________________
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
TOP VIEW
SCL
1
16
SDA
INT
2
15
GND
SQW
3
14
RST
SCL
VCC
4
13
VBACKUP
SDA
N.C.
5
12
N.C.
N.C.
6
11
N.C.
N.C.
7
10
N.C.
N.C.
8
9
N.C.
X1 1
10 VCC
X2
2
9
SQW
VBACKUP
3
8
INT
RST
4
7
GND
5
6
DS1374
μSOP
DS1374C
SO (0.300")
Chip Information
PROCESS: CMOS
SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
16 SO (0.300”)
W16#H2
21-0042
90-0107
10 µSOP (3.0mm)
U10+2
21-0061
90-0330
____________________________________________________________________
17
DS1374
Pin Configurations
DS1374
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
Revision History
REVISION
NUMBER
3
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
8/10
Removed leaded parts from the Ordering Information table; in the Absolute Maximum
Ratings section, added the thermal information, lead information, and new Note 1, and
updated the soldering information; in the Control Register (07h) section, corrected the
references of INTCN to WDSTR in the AIE bit description; removed the section about
the SO package reflow in the Handling, PC Board Layout, and Assembly section;
added the land pattern no. to the Package Information table
1–5, 12, 16,
17
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Maxim Integrated Products, Inc.