June. 2001 Ver 1.2 8-BIT SINGLE-CHIP MICROCONTROLLERS GMS81C1404 GMS81C1408 User’s Manual Table of Contents OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . Development Tools . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . 1 1 2 2 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 3 PIN ASSIGNMENT . . . . . . . . . . . . . . . . . 4 PACKAGE DIAGRAM . . . . . . . . . . . . . . . 5 PIN FUNCTION . . . . . . . . . . . . . . . . . . . . 6 PORT STRUCTURES . . . . . . . . . . . . . . . 8 ELECTRICAL CHARACTERISTICS (GMS81C1404/GMS81C1408) . . . . . . . 12 Absolute Maximum Ratings . . . . . . . . Recommended Operating Conditions A/D Converter Characteristics . . . . . . DC Electrical Characteristics . . . . . . . AC Characteristics . . . . . . . . . . . . . . . Typical Characteristics . . . . . . . . . . . . 12 12 12 13 14 15 ELECTRICAL CHARACTERISTICS (GMS87C1404/GMS87C1408) . . . . . . . 17 Absolute Maximum Ratings . . . . . . . . Recommended Operating Conditions A/D Converter Characteristics . . . . . . DC Electrical Characteristics . . . . . . . AC Characteristics . . . . . . . . . . . . . . . Typical Characteristics . . . . . . . . . . . . 17 17 17 18 19 20 MEMORY ORGANIZATION . . . . . . . . . 22 Registers . . . . . . . . . . . . . . . . . . . . . . Program Memory . . . . . . . . . . . . . . . . Data Memory . . . . . . . . . . . . . . . . . . . Addressing Mode . . . . . . . . . . . . . . . . 22 24 27 31 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . 35 RA and RAIO registers . . . . . . . . . . . . 35 RB and RBIO registers . . . . . . . . . . . . 36 RC and RCIO registers . . . . . . . . . . . . 38 RD and RDIO registers . . . . . . . . . . . . 39 CLOCK GENERATOR . . . . . . . . . . . . . . 40 Oscillation Circuit . . . . . . . . . . . . . . . . . 40 BASIC INTERVAL TIMER . . . . . . . . . . . 41 TIMER / COUNTER . . . . . . . . . . . . . . . . 42 8-bit Timer/Counter Mode . . . . . . . . . . 43 16-bit Timer/Counter Mode . . . . . . . . . 45 8-bit Compare Output (16-bit) . . . . . . . 45 8-bit Capture Mode . . . . . . . . . . . . . . . 45 16-bit Capture Mode . . . . . . . . . . . . . . 48 PWM Mode . . . . . . . . . . . . . . . . . . . . . 48 SERIAL PERIPHERAL INTERFACE . . . 51 BUZZER OUTPUT FUNCTION . . . . . . . 53 ANALOG TO DIGITAL CONVERTER . . 54 INTERRUPTS . . . . . . . . . . . . . . . . . . . . 57 Interrupt Sequence . . . . . . . . . . . . . . . 59 BRK Interrupt . . . . . . . . . . . . . . . . . . . . 60 Multi Interrupt . . . . . . . . . . . . . . . . . . . . 60 External Interrupt . . . . . . . . . . . . . . . . . 62 WATCHDOG TIMER . . . . . . . . . . . . . . . 64 POWER SAVING MODE . . . . . . . . . . . . 65 Stop Mode . . . . . . . . . . . . . . . . . . . . . . 65 STOP Mode using Internal RCWDT . . 67 Wake-up Timer Mode . . . . . . . . . . . . . 68 Minimizing Current Consumption . . . . 69 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . 71 POWER FAIL PROCESSOR . . . . . . . . . 72 OTP PROGRAMMING (GMS87C1404/ GMS87C1408 ONLY) . . . . . . . . . . . . . . . 74 DEVICE CONFIGURATION AREA . . . 74 A. INSTRUCTION MAP . . . . . . . . . . . . . i B. INSTRUCTION SET . . . . . . . . . . . . . ii GMS81C1404/GMS81C1408 GMS81C1404 / GMS81C1408 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER 1. OVERVIEW 1.1 Description The GMS81C1404 and GMS81C1408 are an advanced CMOS 8-bit microcontroller with 4K/8K bytes of ROM. The Hynix semiconductor’s GMS81C1404 and GMS81C1408 are a powerful microcontroller which provides a highly flexible and cost effective solution to many small applications such as controller for battery charger. The GMS81C1404 and GMS81C1408 provide the following standard features: 4K/8K bytes of ROM, 192 bytes of RAM, 8-bit timer/counter, 8-bit A/D converter, 10-bit high speed PWM output, programmable buzzer driving port, 8-bit serial communication port, on-chip oscillator and clock circuitry. In addition, the GMS81C1404 and GMS81C1408 supports power saving modes to reduce power consumption. Device name ROM Size EPROM Size RAM Size Operatind Voltage Package GMS81C1404 4K bytes - 192bytes 2.2 ~ 5.5V 28 SKDIP or SOP GMS81C1408 8K bytes - 192bytes 2.2 ~ 5.5V 28 SKDIP or SOP GMS87C1404 - 4K bytes 192bytes 2.5 ~ 5.5V 28 SKDIP or SOP GMS87C1408 - 8K bytes 192bytes 2.5 ~ 5.5V 28 SKDIP or SOP 1.2 Features • 4K/8K Bytes On-chip Program Memory • One 8-bit Serial Peripheral Interface • 192 Bytes of On-chip Data RAM (Included stack memory) • Instruction Cycle Time: - 250nS at 8MHz • Twelve Interrupt sources - External input: 4 - A/D Conversion: 1 - Serial Peripheral Interface: 1 - Timer: 6 • 23 Programmable I/O pins (LED direct driving can be source and sink) • One Programmable Buzzer Driving port - 500Hz ~ 130kHz • 2.2V to 5.5V Wide Operating Range • Oscillator Type - Crystal - Ceramic Resonator • One 8-bit A/D Converter • One 8-bit Basic Interval Timer • Noise Immunity Circuit - Power Fail Processor • Four 8-bit Timer / Counters • Two 10-bit High Speed PWM Outputs • Power Down Mode - STOP mode - Wake-up Timer mode • Watchdog timer (can be operate with internal RC-oscillation) June. 2001 Ver 1.2 1 GMS81C1404/GMS81C1408 1.3 Development Tools The GMS81C1404 and GMS81C1408 are supported by a full-featured macro assembler, an in-circuit emulator CHOICE-DrTM. In Circuit Emulators Assembler OTP Writer CHOICE-Dr. HME Macro Assembler Single Writer : Dr. Writer 4-Gang Writer : Dr.Gang OTP Devices GMS87C1404 SK (Skinny DIP) GMS87C1404 D (SOP) GMS87C1408 SK (Skinny DIP) GMS87C1408 D (SOP) 1.4 Ordering Information ROM Size 4K bytes 8K bytes 4K bytes (OTP) 8K bytes (OTP) 2 Package Type Ordering Device Code 28SKDIP GMS81C1404 SK 28SOP GMS81C1404 D 28SKDIP GMS81C1404E SK 28SOP GMS81C1404E D 28SKDIP GMS81C1408 SK 28SOP GMS81C1408 D 28SKDIP GMS81C1408E SK 28SOP GMS81C1408E D 28SKDIP GMS87C1404 SK 28SOP GMS87C1404 D 28SKDIP GMS87C1408 SK 28SOP GMS87C1408 D Operating Temperature -20 ~ +85°C -40 ~ +85°C -20 ~ +85°C -40 ~ +85°C -20 ~ +85°C June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 2. BLOCK DIAGRAM PSW Accumulator ALU PC Stack Pointer Data Memory RESET Program Memory System controller System Clock Controller Timing generator 8-bit Basic Interval Timer Data Table Inte rrupt C ontroller Xin Xout Clock Generator Instruction Decoder Watch-dog Timer 8-bit A/D Converter 8-bit Timer/ Counter High Speed PWM Buzzer Driver SPI VDD VSS RA RB RC RD Power Supply RA0 / EC0 RA1 / AN1 RA2 / AN2 RA3 / AN3 RA4 / AN4 RA5 / AN5 RA6 / AN6 RA7 / AN7 June. 2001 Ver 1.2 RB0 / AN0 / Avref RB1 / BUZ RB2 / INT0 RB3 / INT1 RB4 / CMP0 / PWM0 RB5 / CMP1 / PWM1 RB6 / EC1 RB7 / TMR2OV RC3 / SRDY RC4 / SCK RC5 / SIN RC6 / SOUT RD0 / INT2 RD1 / INT3 RD2 3 GMS81C1404/GMS81C1408 3. PIN ASSIGNMENT 28 SKINNY DIP AN4 / RA4 1 28 RA3 / AN3 AN5 / RA5 2 27 RA2 / AN2 AN6 / RA6 3 26 RA1 / AN1 AN7 / RA7 4 25 RA0 / EC0 VDD 5 24 RD1 / INT3 AN0 / AVref / RB0 6 23 RD0 / INT2 BUZ / RB1 7 22 VSS INT0 / RB2 8 21 RESET INT1 / RB3 9 20 Xout PWM0 / COMP0 / RB4 10 19 Xin PWM1 / COMP1 / RB5 11 18 RD2 EC1 / RB6 12 17 RC6 / SOUT TMR2OV / RB7 13 16 RC5 / SIN SRDYIN / SRDYOUT / RC3 14 15 RC4 / SCK 28 SOP 4 AN4 / RA4 1 28 RA3 / AN3 AN5 / RA5 2 27 RA2 / AN2 AN6 / RA6 3 26 RA1 / AN1 AN7 / RA7 4 25 RA0 / EC0 VDD 5 24 RD1 / INT3 AN0 / AVref / RB0 6 23 RD0 / INT2 BUZ / RB1 7 22 VSS INT0 / RB2 8 21 RESET INT1 / RB3 9 20 Xout PWM0 / COMP0 / RB4 10 19 Xin PWM1 / COMP1 / RB5 11 18 RD2 EC1 / RB6 12 17 RC6 / SOUT TMR2OV / RB7 13 16 RC5 / SIN SRDYIN / SRDYOUT / RC3 14 15 RC4 / SCK June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 4. PACKAGE DIAGRAM 28 SKINNY DIP unit: inch MAX MIN TYP 0.300 1.375 0.300 0.275 0.120 0.140 MAX 0.180 MIN 0.020 1.355 4 0.01 8 0.00 0.021 0.055 0.0 15 0 ~ 15° TYP 0.100 0.045 June. 2001 Ver 1.2 0.414 0.398 0.293 0 ~ 8° TYP 0.050 0.008 0.019 0.013 0.012 0.106 0.096 0.708 0.608 0.012 0.006 0.299 28 SOP 0.042 0.022 5 GMS81C1404/GMS81C1408 5. PIN FUNCTION RC3~RC6: RC is a 4-bit, CMOS, bidirectional I/O port. RC pins can be used as outputs or inputs according to “1” or “0” written the their Port Direction Register(RCIO). VDD: Supply voltage. VSS: Circuit ground. RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. RA0~RA7: RA is an 8-bit, CMOS, bidirectional I/O port. RA pins can be used as outputs or inputs according to “1” or “0” written the their Port Direction Register(RAIO). Port pin Alternate function RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 EC0 ( Event Counter Input Source ) AN1 ( Analog Input Port 1 ) AN2 ( Analog Input Port 2 ) AN3 ( Analog Input Port 3 ) AN4 ( Analog Input Port 4 ) AN5 ( Analog Input Port 5 ) AN6 ( Analog Input Port 6 ) AN7 ( Analog Input Port 7 ) RC serves the functions of the serial interface following special features in Table 5-3 . Port pin RC3 RC4 RC5 RC6 Alternate function SRDYIN (SPI Ready Input) SRDYOUT (SPI Ready Output) SCKI (SPI CLK Input) SCKO (SPI CLK Output) SIN (SPI Serial Data Input) SOUT (SPI Serial Data Output) Table 5-3 RC Port RD0~RD2: RD is a 3-bit, CMOS, bidirectional I/O port. RC pins can be used as outputs or inputs according to “1” or “0” written the their Port Direction Register(RDIO). RD serves the functions of the external interrupt following special features in Table 5-4 Table 5-1 RA Port Port pin In addition, RA serves the functions of the various special features in Table 5-1 . RB0~RB7: RB is a 8-bit, CMOS, bidirectional I/O port. RB pins can be used as outputs or inputs according to “1” or “0” written the their Port Direction Register(RBIO). RD0 RD1 RD2 Alternate function INT2 (External Interrupt Input Port 2) INT3 (External Interrupt Input Port 3) Table 5-4 RD Port RB serves the functions of the various following special features in Table 5-2 Port pin Alternate function RB0 AN0 ( Analog Input Port 0 ) AVref ( External Analog Reference Pin ) BUZ ( Buzzer Driving Output Port ) INT0 ( External Interrupt Input Port 0 ) INT1 ( External Interrupt Input Port 1 ) PWM0 (PWM0 Output) COMP0 (Timer1 Compare Output) PWM1 (PWM1 Output) COMP1 (Timer3 Compare Output) EC1 (Event Counter Input Source) TMR2OV (Timer2 Overflow Output) RB1 RB2 RB3 RB4 RB5 RB6 RB7 Table 5-2 RB Port 6 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 PIN NAME Pin No. In/Out Function VDD 5 - Supply voltage VSS 22 - Circuit ground RESET 21 I Reset signal input XIN 19 I XOUT 20 O RA0 (EC0) 25 I/O (Input) External Event Counter input 0 RA1 (AN1) 26 I/O (Input) Analog Input Port 1 RA2 (AN2) 27 I/O (Input) Analog Input Port 2 RA3 (AN3) 28 I/O (Input) Analog Input Port 3 8-bit general I/O ports RA4 (AN4) 1 I/O (Input) Analog Input Port 4 RA5 (AN5) 2 I/O (Input) Analog Input Port 5 RA6 (AN6) 3 I/O (Input) Analog Input Port 6 RA7 (AN7) 4 I/O (Input) Analog Input Port 7 RB0 (AVref/AN0) 6 I/O (Input) Analog Input Port 0 / Analog Reference RB1 (BUZ) 7 I/O (Input) Buzzer Driving Output RB2 (INT0) 8 I/O (Input) External Interrupt Input 0 RB3 (INT1) 9 I/O (Output) External Interrupt Input 1 8-bit general I/O ports RB4 (PWM0/COMP0) 10 I/O (Output/Output) PWM0 Output or Timer1 Compare Output RB5 (PWM1/COMP1) 11 I/O (Output/Output) PWM1 Output or Timer3 Compare Output RB6 (EC1) 12 I/O (Output/Output) External Event Counter input 1 RB7 (TMR2OV) 13 I/O (Output/Output) Timer2 Overflow Output RC3 (SRDYIN/SRDYOUT) 14 I/O (Input/Output) SPI READY Input/Output RC4 (SCK) 15 I/O (Input/Output) SPI CLK Input/Output RC5 (SIN) 16 I/O (Input) RC6 (SOUT) 17 I/O (Output) RD0 (INT2) 23 I/O (Input) RD1 (INT3) 24 I/O (Input) RD2 18 I/O 4-bit general I/O ports SPI DATA Input SPI DATA Output External Interrupt Input 2 3-bit general I/O ports External Interrupt Input 3 Table 5-5 Pin Description June. 2001 Ver 1.2 7 GMS81C1404/GMS81C1408 6. PORT STRUCTURES • RESET Internal RESET VSS • Xin, Xout VDD Xout VSS STOP To System CLK Xin • RA0/EC0 Data Reg. Data Bus Direction Reg. Data Bus Data Bus Read EC0 8 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 • RA1/AN1 ~ RA7/AN7 VDD Data Reg. Data Bus Direction Reg. Data Bus VSS Data Bus Read To A/D Converter Analog Input Mode (ANSEL7 ~ 1) Analog CH. Selection (ADCM.4 ~ 2) • RB0 / AN0 / AVref VDD Data Reg. Data Bus AVREFS Direction Reg. Data Bus VSS Data Bus Read To A/D Converter Analog Input Mode (ANSEL0) Analog CH0 Selection (ADCM.4 ~ 2) Internal VDD 1 To Vref of A/D 0 AVREFS June. 2001 Ver 1.2 9 GMS81C1404/GMS81C1408 • RB1/BUZ, RB4/PWM0/COMP0, RB5/PWM1/COMP1, RB7/TMR2OV, RC6/SOUT PWM/COMP BUZ,TMR2OV,SOUT VDD Data Reg. 1 0 Data Bus Function Select Direction Reg. Data Bus VSS Data Bus Read • RB2/INT0, RB3/INT1, RD0/INT2, RD1/INT3 Pull-up Select Weak Pull-up VDD Data Reg. Data Bus Function Select Direction Reg. Data Bus VSS Data Bus Read INT0, INT1 INT2, INT3 Schmitt Trigger • RB6/EC1 Data Reg. Data Bus Direction Reg. Data Bus Data Bus Read EC1 10 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 • RD2 VDD Data Reg. Data Bus Direction Reg. Data Bus VSS Data Bus Read • RC5/SIN VDD Data Reg. Data Bus Function Select Direction Reg. Data Bus VSS Data Bus Read Schmitt Trigger SIN • RC3 / SRDYIN / SRDYOUT, RC4 / SCKIN / SCKOUT SRDYOUT SCKOUT Data Reg. 0 Data Bus Function Select VDD 1 Direction Reg. Data Bus VSS Data Bus Read SCKIN Schmitt Trigger SRDYIN June. 2001 Ver 1.2 11 GMS81C1404/GMS81C1408 7. ELECTRICAL CHARACTERISTICS (GMS81C1404/GMS81C1408) 7.1 Absolute Maximum Ratings Supply voltage ........................................... -0.3 to +6.0 V Storage Temperature ................................-40 to +125 °C Voltage on any pin with respect to Ground (VSS) ............................................................... -0.3 to VDD+0.3 Maximum current out of VSS pin ........................200 mA Maximum current into VDD pin ..........................150 mA Maximum current sunk by (IOL per I/O Pin) ........25 mA Maximum output current sourced by (IOH per I/O Pin) ...............................................................................15 mA Maximum current (ΣIOL) ....................................150 mA Maximum current (ΣIOH).................................... 100 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7.2 Recommended Operating Conditions Specifications Parameter Symbol Condition Max. fXIN=8MHz 4.5 5.5 V fXIN=4.2MHz 2.2 5.5 V VDD=4.5~5.5V 1 8 MHz VDD=2.2~5.5V 1 4.2 MHz -20 (-40 for GMS81C140XE) 85 °C VDD Supply Voltage fXIN Operating Frequency Operating Temperature Unit Min. TOPR 7.3 A/D Converter Characteristics (TA=25°C, VSS=0V, VDD=5.12V @fXIN =8MHz, VDD=3.072V @fXIN =4MHz) Specifications Parameter Analog Input Voltage Range Analog Power Supply Input Voltage Range Symbol VAIN VREF Condition Unit Min. Typ. Max. AVREFS=0 VSS - VDD AVREFS=1 VSS - VREF VDD=5V 3 - VDD V VDD=3V 2.4 - VDD V V Overall Accuracy NACC - ±1.0 ±1.5 LSB Non-Linearity Error NNLE - ±1.0 ±1.5 LSB Differential Non-Linearity Error NDNLE - ±1.0 ±1.5 LSB Zero Offset Error NZOE - ±0.5 ±1.5 LSB Full Scale Error NFSE - ±0.25 ±0.5 LSB Gain Error NNLE - ±1.0 ±1.5 LSB fXIN=8MHz - - 10 fXIN=4MHz - - 20 AVREFS=1 - 0.5 1.0 Conversion Time AVREF Input Current 12 TCONV IREF µS mA June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 7.4 DC Electrical Characteristics (TA=-20~85°C for GMS81C1404/1408 or TA=-40~85°C for GMS81C1404E/1408E, VDD=2.2~5.5V, VSS=0V), Specifications Parameter Symbol Pin Condition Unit Min. Typ. Max. VIH1 XIN, RESET 0.8 VDD - VDD VIH2 Hysteresis Input1 0.8 VDD - VDD VIH3 Normal Input 0.7 VDD - VDD VIL1 XIN, RESET 0 - 0.2 VDD VIL2 Hysteresis Input1 0 - 0.2 VDD VIL3 Normal Input 0 - 0.3 VDD Output High Voltage VOH All Output Port VDD=5V, IOH=-5mA VDD -1 - - V Output Low Voltage VOL All Output Port VDD=5V, IOL=10mA - - 1 V Input Pull-up Current IP -550 -320 -200 µA Input High Voltage Input Low Voltage RB2, RB3, RD0, RD1 VDD=5V V V Input High Leakage Current IIH1 All Pins (except XIN) VDD=5V - - 5 µA IIH2 XIN VDD=5V - - 15 µA Input Low Leakage Current IIL1 All Pins (except XIN) VDD=5V -5 - - µA IIL2 XIN VDD=5V -15 - - µA VDD=5V 0.5 - - V Hysteresis PFD Voltage | VT | Hysteresis VPFD1 VDD PFD Level = 0 2.5 3.0 3.5 VPFD2 VDD PFD Level = 1 2.0 2.5 3.0 VDD=5V 30 120 VDD=3V 60 280 Internal RC WDT Period TRCWDT Operating Current IDD VDD Wake-up Timer Mode Current IWKUP VDD RCWDT Mode Current at STOP Mode IRCWDT VDD ISTOP VDD Stop Mode Current Input1 V VDD=5.5V, fXIN=8MHz - 5 6 VDD=3.0V, fXIN=4MHz - 2 3 VDD=5.5V, fXIN=8MHz - 1 2 VDD=3.0V, fXIN=4MHz - 0.5 1 VDD=5.5V - - 200 VDD=3.0V - - 100 VDD=5.5V, fXIN=8MHz - 0.5 3 VDD=3.0V, fXIN=4MHz - 0.2 1 µS mA mA µA µA 1. Hysteresis Input: RB2, RB3, RB6, RC3, RC4, RC5, RD0, RD1 June. 2001 Ver 1.2 13 GMS81C1404/GMS81C1408 7.5 AC Characteristics (TA=-20~85°C for GMS81C1404/1408 or TA=-40~85°C for GMS81C1404E/1408E, VDD=5V±10%, VSS=0V) Specifications Parameter Symbol Pins Unit Min. Typ. Max. fCP XIN 1 - 8 MHz tCPW XIN 80 - - nS tRCP,tFCP XIN - - 20 nS Oscillation Stabilizing Time tST XIN, XOUT - - 20 mS External Input Pulse Width tEPW INT0, INT1, INT2, INT3 EC0, EC1 2 - - tSYS RESET Input Width tRST RESET 8 - - tSYS Operating Frequency External Clock Pulse Width External Clock Transition Time tCPW 1/fCP tCPW VDD-0.5V XIN 0.5V tSYS tRCP tFCP tRST RESET 0.2VDD tEPW tEPW 0.8VDD INT0, INT1 INT2, INT3 EC0, EC1 0.2VDD Figure 7-1 Timing Chart 14 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 7.6 Typical Characteristics This graphs and tables provided in this section are for design guidance only and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean − 3σ) respectively where σ is standard deviation Operating Area Normal Operation IDD−VDD fXIN (MHz) IDD (mA) Ta= 25°C 10 Ta=25°C 8 8 6 6 fXIN = 8MHz 4 4MHz 4 2 2 0 0 2 3 4 5 2 VDD (V) 6 STOP Mode ISTOP−VDD IDD (µA) 3 4 5 VDD 6 (V) Wake-up Timer Mode IWKUP−VDD fXIN = 8MHz 0.8 -40°C IDD (mA) 25°C 2.0 Ta=25°C 85°C 0.6 1.5 0.4 1.0 0.2 0.5 fXIN = 8MHz 0 2 3 4 5 VDD 6 (V) 4MHz 0 2 3 4 5 VDD 6 (V) RC-WDT in Stop Mode IRCWDT−VDD IDD (µA) Ta=25°C 20 15 TRCWDT = 80uS 10 5 0 2 June. 2001 Ver 1.2 3 4 5 VDD 6 (V) 15 GMS81C1404/GMS81C1408 IOL−VOL, VDD=5V IOH−VOH, VDD=5V IOL (mA) IOH (mA) -40°C 25°C 40 -40°C 25°C -20 85°C 85°C -15 30 -10 20 -5 10 0 1 VIH1 (V) 2 3 VDD−VIH1 XIN, RESET 0 VOL 5 (V) 2 VDD−VIH2 VIH2 (V) fXIN=4MHz Ta=25°C Hysteresis input f X IN =4kH z Ta=25°C 3 4 VIH3 (V) 4 3 3 3 2 2 2 1 1 1 1 VIL1 (V) 2 3 4 5 VDD 6 (V) VDD−VIL1 XIN, RESET 4 0 2 3 VDD−VIL2 VIL2 (V) fXIN=4MHz Ta=25°C 4 5 VDD 6 (V) Hysteresis input f X IN =4kH z Ta=25°C VIL3 (V) 3 3 2 2 2 1 1 1 3 4 5 VDD 6 (V) 4 0 2 3 4 5 VDD 6 (V) 3 VDD−VIL3 3 2 f X IN =4kH z Ta=25°C 2 4 1 Normal input 0 4 0 VOH 6 (V) 5 VDD−VIH3 4 0 16 4 4 5 VDD 6 (V) Normal input f X IN =4kH z Ta=25°C 0 2 3 4 5 VDD 6 (V) June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 8. ELECTRICAL CHARACTERISTICS (GMS87C1404/GMS87C1408) 8.1 Absolute Maximum Ratings Supply voltage ........................................... -0.3 to +6.0 V Storage Temperature ................................-40 to +125 °C Voltage on any pin with respect to Ground (VSS) ............................................................... -0.3 to VDD+0.3 Maximum current out of VSS pin ........................200 mA Maximum current into VDD pin ..........................150 mA Maximum current sunk by (IOL per I/O Pin) ........25 mA Maximum output current sourced by (IOH per I/O Pin) ...............................................................................15 mA Maximum current (ΣIOL) ....................................150 mA Maximum current (ΣIOH).................................... 100 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 8.2 Recommended Operating Conditions Specifications Parameter Symbol VDD Supply Voltage Operating Frequency Operating Temperature fXIN Condition Unit Min. Max. fXIN=8MHz 4.5 5.5 V fXIN=4.2MHz 2.5 5.5 V VDD=4.5~5.5V 1 8 MHz VDD=2.5~5.5V 1 4.2 MHz -20 85 °C TOPR 8.3 A/D Converter Characteristics (TA=25°C, VSS=0V, VDD=5.12V @fXIN =8MHz, VDD=3.072V @fXIN =4MHz) Specifications Parameter Analog Input Voltage Range Analog Power Supply Input Voltage Range Symbol VAIN VREF Condition Unit Min. Typ. Max. AVREFS=0 VSS - VDD AVREFS=1 VSS - VREF VDD=5V 3 - VDD V VDD=3V 2.4 - VDD V V Overall Accuracy NACC - ±1.0 ±1.5 LSB Non-Linearity Error NNLE - ±1.0 ±1.5 LSB Differential Non-Linearity Error NDNLE - ±1.0 ±1.5 LSB Zero Offset Error NZOE - ±0.5 ±1.5 LSB Full Scale Error NFSE - ±0.25 ±0.5 LSB Gain Error NNLE - ±1.0 ±1.5 LSB fXIN=8MHz - - 10 fXIN=4MHz - - 20 AVREFS=1 - 0.5 1.0 Conversion Time AVREF Input Current June. 2001 Ver 1.2 TCONV IREF µS mA 17 GMS81C1404/GMS81C1408 8.4 DC Electrical Characteristics (TA=-20~85°C, VDD=2.5~5.5V, VSS=0V), Specifications Parameter Symbol Pin Condition Unit Min. Typ. Max. VIH1 XIN, RESET 0.8 VDD - VDD VIH2 Hysteresis Input1 0.8 VDD - VDD VIH3 Normal Input 0.7 VDD - VDD VIL1 XIN, RESET 0 - 0.2 VDD VIL2 Hysteresis Input1 0 - 0.2 VDD VIL3 Normal Input 0 - 0.3 VDD Output High Voltage VOH All Output Port VDD=5V, IOH=-5mA VDD -1 - - V Output Low Voltage VOL All Output Port VDD=5V, IOL=10mA - - 1 V Input Pull-up Current IP -550 -420 -200 µA Input High Voltage Input Low Voltage RB2, RB3, RD0, RD1 VDD=5V V V Input High Leakage Current IIH1 All Pins (except XIN) VDD=5V - - 5 µA IIH2 XIN VDD=5V - - 15 µA Input Low Leakage Current IIL1 All Pins (except XIN) VDD=5V -5 - - µA IIL2 XIN VDD=5V -15 - - µA VDD=5V 0.5 - - V Hysteresis PFD Voltage | VT | Hysteresis VPFD1 VDD PFD Level = 0 2.5 3.0 3.5 VPFD2 VDD PFD Level = 1 2.0 2.5 3.0 VDD=5V 40 120 VDD=3V 95 280 Internal RC WDT Period TRCWDT Operating Current IDD VDD Wake-up Timer Mode Current IWKUP VDD RCWDT Mode Current at STOP Mode IRCWDT VDD ISTOP VDD Stop Mode Current Input1 V VDD=5.5V, fXIN=8MHz - 5 6 VDD=3.0V, fXIN=4MHz - 2 3 VDD=5.5V, fXIN=8MHz - 1 2 VDD=3.0V, fXIN=4MHz - 0.5 1 VDD=5.5V - - 200 VDD=3.0V - - 100 VDD=5.5V, fXIN=8MHz - 0.5 3 VDD=3.0V, fXIN=4MHz - 0.2 1 µS mA mA µA µA 1. Hysteresis Input: RB2, RB3, RB6, RC3, RC4, RC5, RD0, RD1 18 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 8.5 AC Characteristics (TA=-20~+85°C, VDD=5V±10%, VSS=0V) Specifications Parameter Symbol Pins Unit Min. Typ. Max. fCP XIN 1 - 8 MHz tCPW XIN 80 - - nS tRCP,tFCP XIN - - 20 nS Oscillation Stabilizing Time tST XIN, XOUT - - 20 mS External Input Pulse Width tEPW INT0, INT1, INT2, INT3 EC0, EC1 2 - - tSYS RESET Input Width tRST RESET 8 - - tSYS Operating Frequency External Clock Pulse Width External Clock Transition Time tCPW 1/fCP tCPW VDD-0.5V XIN 0.5V tSYS tRCP tFCP tRST RESET 0.2VDD tEPW tEPW 0.8VDD INT0, INT1 INT2, INT3 EC0, EC1 0.2VDD Figure 8-1 Timing Chart June. 2001 Ver 1.2 19 GMS81C1404/GMS81C1408 8.6 Typical Characteristics This graphs and tables provided in this section are for design guidance only and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean − 3σ) respectively where σ is standard deviation Operating Area Normal Operation IDD−VDD fXIN (MHz) IDD (mA) Ta= 25°C 10 Ta=25°C 8 8 6 6 fXIN = 8MHz 4 4MHz 4 2 2 0 0 2 3 4 5 2 VDD (V) 6 STOP Mode ISTOP−VDD IDD (µA) 3 4 5 VDD 6 (V) Wake-up Timer Mode IWKUP−VDD fXIN = 8MHz 0.8 -25°C IDD (mA) 25°C 2.0 Ta=25°C 85°C 0.6 1.5 0.4 1.0 0.2 0.5 fXIN = 8MHz 0 2 3 4 5 VDD 6 (V) 4MHz 0 2 3 4 5 VDD 6 (V) RC-WDT in Stop Mode IRCWDT−VDD IDD (µA) Ta=25°C 20 15 TRCWDT = 80uS 10 5 0 2 20 3 4 5 VDD 6 (V) June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 IOL−VOL, VDD=5V IOH−VOH, VDD=5V IOL (mA) IOH (mA) -25°C 25°C 40 -25°C 25°C -20 85°C 85°C -15 30 -10 20 -5 10 0 1 VIH1 (V) 2 3 4 VDD−VIH1 XIN, RESET 0 VOL 5 (V) 2 VDD−VIH2 VIH2 (V) fXIN=4MHz Ta=25°C Hysteresis input f X IN =4kH z Ta=25°C 3 4 VDD−VIH3 VIH3 (V) 4 4 3 3 3 2 2 2 1 1 1 0 1 VIL1 (V) 2 3 4 5 VDD 6 (V) VDD−VIL1 XIN, RESET 4 0 2 3 VDD−VIL2 VIL2 (V) fXIN=4MHz Ta=25°C 4 5 VDD 6 (V) Hysteresis input f X IN =4kH z Ta=25°C VIL3 (V) 3 3 2 2 2 1 1 1 3 June. 2001 Ver 1.2 4 5 VDD 6 (V) 4 0 2 3 4 5 VDD 6 (V) 3 VDD−VIL3 3 2 f X IN =4kH z Ta=25°C 2 4 1 Normal input 0 4 0 VOH 6 (V) 5 4 5 VDD 6 (V) Normal input f X IN =4kH z Ta=25°C 0 2 3 4 5 VDD 6 (V) 21 GMS81C1404/GMS81C1408 9. MEMORY ORGANIZATION The GMS81C1404 and GMS81C1408 have separate address spaces for Program memory and Data Memory. Program memory can only be read, not written to. It can be up to 4K /8K bytes of Program memory. Data memory can be read and written to up to 192 bytes including the stack area. 9.1 Registers This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register. A ACCUMULATOR X X REGISTER Y Y REGISTER SP PCH STACK POINTER PCL PROGRAM COUNTER PSW PROGRAM STATUS WORD Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 00H to BFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of “BFH” is used. Stack Address (000H ~ 0BFH) 15 8 0 Figure 9-1 Configuration of Registers Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below. Y Y A A Two 8-bit Registers can be used as a “YA” 16-bit Register Figure 9-2 Configuration of YA 16-bit Register X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed (save or restore). 22 7 0 SP Hardware fixed Note: The Stack Pointer must be initialized by software because its value is undefined after RESET. Example: To initialize the SP LDX #0BFH TXSP ; SP ← BFH Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 9-3 . It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is “0” and is cleared by any other result. June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 MSB PSW N LSB V - B H I Z C RESET VALUE: 00H CARRY FLAG RECEIVES CARRY OUT NEGATIVE FLAG OVERFLOW FLAG ZERO FLAG BRK FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS Figure 9-3 PSW (Program Status Word) Register [Interrupt disable flag I] dress. This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to “0”. This flag immediately becomes “0” when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Overflow flag V] [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector ad- June. 2001 Ver 1.2 This flag is set to “1” when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or -128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag. 23 GMS81C1404/GMS81C1408 9.2 Program Memory A 16-bit program counter is capable of addressing up to 64K bytes, but these devices have 4K/8K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Example: Usage of TCALL Figure 9-4 , shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 9-5 . ; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B As shown in Figure 9-4 , each area is assigned a fixed location in Program Memory. Program Memory area contains the user program. E000H LDA #5 TCALL 0FH : : ;1BYTE INSTR UCTIO N ;INSTEAD OF 3 BYTES ;NOR M AL C ALL 1 ;TCALL ADDRESS AREA GMS81C1408 F000H GMS81C1404 PROGRAM MEMORY FEFFH FF00H FFC0H FFDFH FFE0H FFFFH TCALL AREA PCALL AREA INTERRUPT VECTOR AREA Figure 9-4 Program Memory Map The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte interval: 0FFF8H and 0FFF9H for External Interrupt 1, 0FFFAH and 0FFFBH for External Interrupt 0, etc. As for the area from 0FF00H to 0FFFFH, if any area of them is not going to be used, its service location is available as general purpose Program Memory. Address 0FFE0H Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 9-6 . Vector Area Memory - E2 - E4 Serial Peripheral Interface Interrupt Vector Area E6 Basic Interval Interrupt Vector Area E8 Watchdog Timer Interrupt Vector Area EA A/D Converter Interrupt Vector Area EC Timer/Counter 3 Interrupt Vector Area EE Timer/Counter 2 Interrupt Vector Area F0 External Interrupt 3 Vector Area F2 External Interrupt 2 Vector Area F4 Timer/Counter 1 Interrupt Vector Area F6 Timer/Counter 0 Interrupt Vector Area F8 External Interrupt 1 Vector Area FA External Interrupt 0 Vector Area FC - FE RESET Vector Area NOTE: “-” means reserved area. Figure 9-5 Interrupt Vector Area 24 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 Address Address Program Memory 0FFC0H C1 TCALL 15 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF PCALL Area Memory 0FF00H PCALL Area (256 Bytes) 0FFFFH TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK * NOTE: * means that the BRK software interrupt is using same address with TCALL0. Figure 9-6 PCALL and TCALL Memory Area PCALL→ rel TCALL→ n 4F35 4A PCALL 35H TCALL 4 4A 4F 35 ~ ~ ~ ~ ~ ~ 0F125H ~ ~ NEXT 0FF00H 0FF35H 0FFFFH 01001010 ➊ PC: 11111111 11010110 FH FH DH 6H ➌ NEXT 0FF00H 0FFD6H 25 0FFD7H F1 Reverse ➋ 0FFFFH June. 2001 Ver 1.2 25 GMS81C1404/GMS81C1408 Example: The usage software example of Vector address and the initialize part. ORG 0FFE0H DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW NOT_USED NOT_USED SPI_INT BIT_INT WDT_INT AD_INT TMR3_INT TMR2_INT INT3 INT2 TMR1_INT TMR0_INT INT1 INT0 NOT_USED RESET ORG 0F000H ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; (0FFEO) (0FFE2) (0FFE4) (0FFE6) (0FFE8) (0FFEA) (0FFEC) (0FFEE) (0FFF0) (0FFF2) (0FFF4) (0FFF6) (0FFF8) (0FFFA) (0FFFC) (0FFFE) Serial Peripheral Interface Basic Interval Timer Watchdog Timer A/D Timer-3 Timer-2 Int.3 Int.2 Timer-1 Timer-0 Int.1 Int.0 Reset ;******************************************** ; MAIN PROGRAM * ;******************************************* ; RESET: DI ;Disable All Interrupts LDX #0 RAM_CLR: LDA #0 ;RAM Clear(!0000H->!00BFH) STA {X}+ CMPX #0C0H BNE RAM_CLR ; LDX #0BFH ;Stack Pointer Initialize TXSP ; CALL INITIAL ; ; LDM RA, #0 ;Normal Port A LDM RAIO,#1000_0010B ;Normal Port Direction LDM RB, #0 ;Normal Port B LDM RBIO,#1000_0010B ;Normal Port Direction : : LDM PFDR,#0 ;Enable Power Fail Detector : : 26 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 9.3 Data Memory Figure 9-7 shows the internal Data Memory space available. Data Memory is divided into two groups, a user RAM (including Stack) and control registers. 0000H USER MEMORY (including STACK) PAGE0 00BFH 00C0H CONTROL REGISTERS 00FFH Figure 9-7 Data Memory Map User Memory The GMS81C1404 and GMS81C1408 has 192 × 8 bits for the user memory (RAM). Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section. Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction. Example; To write at CKCTLR LDM CKCTLR,#09H ;Divide ratio ÷16 Address Symbol R/W RESET Value Addressing m ode 0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H 0C7H 0CAH 0CBH 0CCH 0CDH RA RAIO RB RBIO RC RCIO RD RDIO RAFUNC RBFUNC PUPSEL RDFUNC R/W R/W R/W R/W R/W R/W R/W W W W W W Undefined 0000_0000 Undefined 00000000 Undefined -000_0--Undefined ----_-000 0000_0000 0000_0000 ----_0000 ----_--00 byte, bit1 byte2 byte, bit byte byte, bit byte byte, bit byte byte byte byte byte 0D0H 0D1H 0D1H 0D1H 0D2H 0D3H 0D3H 0D4H 0D4H 0D4H 0D5H TM0 T0 TDR0 CDR0 TM1 TDR1 T1PPR T1 CDR1 T1PDR PWM0HR R/W R W R R/W W W R R R/W W --00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000 ----_0000 byte, bit byte byte byte byte, bit byte byte byte byte byte, bit byte 0D6H 0D7H 0D7H 0D7H 0D8H 0D9H 0D9H 0DAH 0DAH 0DAH 0DBH TM2 T2 TDR2 CDR2 TM3 TDR3 T3PPR T3 CDR3 T3PDR PWM1HR R/W R W R R/W W W R R R/W W --00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000 ----_0000 byte, bit byte byte byte byte, bit byte byte byte byte byte, bit byte 0DEH 0E0H 0E1H BUR SIOM SIOR W R/W R/W 1111_1111 0000_0001 Undefined byte byte, bit byte, bit 0E2H 0E3H 0E4H 0E5H 0E6H 0EAH 0EBH 0ECH 0ECH 0EDH 0EDH 0EFH IENH IENL IRQH IRQL IEDS ADCM ADCR BITR CKCTLR WDTR WDTR PFDR R/W R/W R/W R/W R/W R/W R R W R W R/W 0000_0000 0000_---0000_0000 0000_---0000_0000 --00_0001 Undefined 0000_0000 -001_0111 0000_0000 0111_1111 ----_-100 byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte byte byte byte, bit Table 9-1 Control Registers June. 2001 Ver 1.2 27 GMS81C1404/GMS81C1408 1. “byte, bit” means that register can be addressed by not only bit but byte manipulation instruction. 2. “byte” means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit. Note: Several names are given at same address. Refer to below table. When read When write Addr. Timer Mode Capture Mode PWM Mode Timer Mode PWM Mode D1H T0 CDR0 - TDR0 - TDR1 T1PPR D3H - D4H T1 CDR1 T1PDR - T1PDR D7H T2 CDR2 - TDR2 - TDR3 T3PPR - T3PDR D9H DAH ECH T3 CDR3 BITR T3PDR Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. CKCTLR Table 9-2 Various Register Name in Same Address 28 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C0H RA RA Port Data Register C1H RAIO RA Port Direction Register C2H RB RB Port Data Register C3H RBIO RB Port Direction Register C4H RC RC Port Data Register C5H RCIO RC Port Direction Register C6H RD RD Port Data Register C7H RDIO RD Port Direction Register CAH RAFUNC ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 CBH RBFUNC TMR2OV EC1I PWM1O PWM0O INT1I INT0I BUZO AVREFS CCH PUPSEL - - - - CDH RDFUNC - - - - - - INT3I INT2I D0H TM0 - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST D1H T0/TDR0/ CDR0 D2H TM1 T1CN T1ST D3H TDR1/ T1PPR Timer1 Data Register / PWM0 Period Register D4H T1/CDR1/ T1PDR Timer1 Register / Capture1 Data Register / PWM0 Duty Register D5H PWM0HR PWM0 High Register D6H TM2 T2CN T2ST D7H T2/TDR2/ CDR2 D8H TM3 T3CN T3ST D9H TDR3/ T3PPR Timer3 Data Register / PWM1 Period Register DAH T3/CDR3/ T3PDR Timer3 Register / Capture3 Data Register / PWM1Duty Register DBH PWM1HR PWM1 High Register DEH BUR BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0 E0H SIOM POL SRDY SM1 SM0 SCK1 SCK0 SIOST SIOSF E1H SIOR E2H IENH INT0E INT1E T0E T1E INT2E INT3E T2E T3E E3H IENL ADE WDTE BITE SPIE - - - - E4H IRQH INT0IF INT1IF T0IF T1IF INT2IF INT3IF T2IF T3IF E5H IRQL ADIF WDTIF BITIF SPIF - - - - E6H IEDS IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0L PUPSEL3 PUPSEL2 PUPSEL1 PUPSEL0 Timer0 Register / Timer0 Data Register / Capture0 Data Register POL - 16BIT - PWM0E CAP2 CAP1 T2CK2 T1CK1 T2CK1 T1CK0 T2CK0 Timer2 Register / Timer2 Data Register / Capture2 Data Register POL 16BIT PWM1E CAP3 T3CK1 T3CK0 SPI DATA REGISTER Table 9-3 Control Registers of GMS81C1404 and GMS81C1408 These registers of shaded area can not be accessed by bit manipulation instruction as “SET1, CLR1”, but should be accessed by register operation instruction as “LDM dp,#imm”. June. 2001 Ver 1.2 29 GMS81C1404/GMS81C1408 EAH ADCM - EBH ADCR ADC Result Data Register ECH BITR1 Basic Interval Timer Data Register ECH CKCTLR1 EDH WDTR WDTCL EFH PFDR2 - - - WAKEUP ADEN RCWDT ADS2 ADS1 ADS0 ADST ADSF WDTON BTCL BTS2 BTS1 BTS0 - PFDIS PFDM PFDS 7-bit Watchdog Counter Register - - - Table 9-3 Control Registers of GMS81C1404 and GMS81C1408 These registers of shaded area can not be accessed by bit manipulation instruction as “SET1, CLR1”, but should be accessed by register operation instruction as “LDM dp,#imm”. 1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR. 2.The register PFDR only be implemented on devices, not on In-circuit Emulator. 30 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 9.4 Addressing Mode The GMS81C1404 and GMS81C1408 uses six addressing modes; (3) Direct Page Addressing → dp • Register addressing Example; • Immediate addressing C535 In this mode, a address is specified within direct page. LDA ;A ←RAM[35H] 35H • Direct page addressing • Absolute addressing 0035H data ➋ • Indexed addressing ~ ~ • Register-indirect addressing ~ ~ 0F550H C5 0F551H 35 ➊ data → A (1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. (2) Immediate Addressing → #imm In this mode, second byte (operand) is accessed as a data immediately. Example: 0435 ADC #35H (4) Absolute Addressing → !abs Absolute addressing sets corresponding memory data to Data, i.e. second byte(Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. MEMORY ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY 04 A+35H+C → A 35 Example; 0735F0 E45535 LDM ADC data 0F035H 35H,#55H ~ ~ 0F100H ➊ 0F100H data ← 55H data 0035H ~ ~ ~ ~ ;A ←ROM[0F035H] !0F035H ➋ ~ ~ ➊ A+data+C → A 07 0F101H 35 0F102H F0 address: 0F035 ➋ E4 0F101H 55 0F102H 35 June. 2001 Ver 1.2 31 GMS81C1404/GMS81C1408 The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H. 983500 INC ;A ←RAM[035H] !0035H X indexed direct page, auto increment→ {X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; X=35H DB data 0035H ~ ~ LDA {X}+ ➌ ~ ~ ➋ data+1 → data 0F100H 98 ➊ 0F101H 35 address: 0035 0F102H 00 35H ➋ data ~ ~ ~ ~ data → A ➊ 36H → X DB (5) Indexed Addressing X indexed direct page (no offset) → {X} In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H D4 LDA {X} ;ACC←RAM[X]. X indexed direct page (8 bit offset) → dp+X This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; X=015H 15H ~ ~ 0E550H C645 data ~ ~ D4 LDA 45H+X ➋ data → A ➊ 5AH data ➌ ~ ~ 32 ➋ ~ ~ 0E550H C6 0E551H 45 data → A ➊ 45H+15H=5AH June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 Y indexed direct page (8 bit offset) → dp+Y 3F35 JMP [35H] This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. 35H 0A 36H E3 Y indexed absolute →!abs+Y ~ ~ Sets the value of 16-bit absolute address plus Y-register data as Memory. This addressing mode can specify memory in whole area. Example; Y=55H D500FA LDA ~ ~ D5 00 0F102H FA ~ ~ ~ ~ ➊ 3F 35 !0FA00H+Y 0F100H ➋ jump to address 0E30AH NEXT 0FA00H 0F101H 0FA55H 0E30AH ~ ~ ➊ X indexed indirect → [dp+X] 0FA00H+55H=0FA55H ~ ~ ➋ data ➌ data → A Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plus X-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; X=10H 1625 ADC [25H+X] (6) Indirect Addressing Direct page indirect → [dp] Assigns data address to use for accomplishing command which sets memory data(or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL 35H 05 36H E0 0E005H ~ ~ ➋ ~ ~ 0E005H ~ ~ Example; 0FA00H ~ ~ 16 25 June. 2001 Ver 1.2 ➊ 25 + X(10) = 35H data ➌ A + data + C → A 33 GMS81C1404/GMS81C1408 Y indexed indirect → [dp]+Y Absolute indirect → [!abs] Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Y-register data. The program jumps to address specified by 16-bit absolute address. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; Y=10H 1725 ADC JMP Example; 1F25E0 JMP [!0C025H] [25H]+Y PROGRAM MEMORY 25H 05 0E025H 25 26H E0 0E026H E7 ~ ~ 0E015H ~ ~ 0FA00H ~ ~ ➊ 0E725H ~ ~ 0FA00H 17 ➌ A + data + C → A ➋ jump to address 0E30AH NEXT ~ ~ ~ ~ 25 34 0E005H + Y(10) = 0E015H ➊ data ~ ~ ➋ ~ ~ 1F 25 E0 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 10. I/O PORTS The GMS81C1404 and GMS81C1408 has four ports, RA, RB, RC and RD. These ports pins may be multiplexed with an alternate function for the peripheral features on the device. In general, when a initial reset state, all ports are used as a general purpose input port. All pins have data direction registers which can set these ports as output or input. A “1” in the port direction register defines the corresponding port pin as output. Conversely, write “0” to the corresponding bit to specify as an input pin. For example, to use the even numbered bit of RA as output ports and the odd numbered bits as input ports, write “55H” to address C1H (RA direction register) during initial setting as shown in Figure 10-1 . Reading data register reads the status of the pins whereas writing to it will write to the port latch. WRITE “55H” TO PORT RA DIRECTION REGISTER C0H RA DATA C1H RA DIRECTION C2H RB DATA C3H RB DIRECTION 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 I O I BIT O I O I O 7 6 5 4 3 2 1 0 PORT I: INPUT PORT O: OUTPUT PORT Figure 10-1 Example of port I/O assignment 10.1 RA and RAIO registers RA is an 8-bit bidirectional I/O port (address C0H). Each port can be set individually as input and output through the RAIO register (address C1H). RA7~RA1 ports are multiplexed with Analog Input Port (AN7~AN1) and RA0 port is multiplexed with Event Counter Input Port (EC0). RA Data Register RA ADDRESS : C0H RESET VALUE : Undefined RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 INPUT / OUTPUT DATA RA Direction Register select alternate function. After reset, this value is “0”, port may be used as general I/O ports. To select alternate function such as Analog Input or External Event Counter Input, write “1” to the corresponding bit of RAFUNC.Regardless of the direction register RAIO, RAFUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features (RA0/EC0 is controlled by RBFUNC) PORT RAFUNC.7~0 Description 0 RA7 (Normal I/O Port) 1 AN7 (ADS2~0=111) 0 RA6 (Normal I/O Port) 1 AN6 (ADS2~0=110) 0 RA5 (Normal I/O Port) 1 AN5 (ADS2~0=101) 0 RA4 (Normal I/O Port) 1 AN4 (ADS2~0=100) 0 RA3 (Normal I/O Port) 1 AN3 (ADS2~0=011) 0 RA2 (Normal I/O Port) 1 AN2 (ADS2~0=010) 0 RA1 (Normal I/O Port) 1 AN1 (ADS2~0=001) RA7/AN7 ADDRESS : C1H RESET VALUE : 00000000 RA6/AN6 RAIO DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT RA5/AN5 RA4/AN4 RA Function Selection Register RAFUNC ADDRESS : CAH RESET VALUE : 00000000 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 0 : RA4 1 : AN4 0 : RA5 1 : AN5 0 : RA6 1 : AN6 0 : RA7 1 : AN7 0 : RB0 1 : AN0 0 : RA1 1 : AN1 0 : RA2 1 : AN2 0 : RA3 1 : AN3 RA3/AN3 RA2/AN2 RA1/AN1 RA0/EC01 Figure 10-2 Registers of Port RA The control register RAFUNC (address CAH) controls to June. 2001 Ver 1.2 RA0 (Normal I/O Port) EC0 (T0CK2~0=111) 1. This port is not an Analog Input port, but Event Counter clock source input port. ECO is controlled by setting TOCK2~0 = 111. The bit RAFUNC.0 (ANSEL0) controls the RB0/AN0/AVref port (Refer to Port RB). 35 GMS81C1404/GMS81C1408 10.2 RB and RBIO registers tion. After reset, this value is “0”, port may be used as general I/O ports. To select alternate function such as External interrupt or Timer compare output, write “1” to the corresponding bit of RBFUNC. RB is a 5-bit bidirectional I/O port (address C2H). Each pin can be set individually as input and output through the RBIO register (address C3H). In addition, Port RB is multiplexed with various special features. The control register RBFUNC (address CBH) controls to select alternate func- Pull-up Selection Register RB Data Register RB RB7 ADDRESS : C2H RESET VALUE : Undefined ADDRESS : CCH RESET VALUE : ----0000 PUPSEL RB6 RB5 RB4 RB3 RB2 RB1 RB0 - - - - PUP3 PUP2 RB3 / INT1 Pull-up 0 : No Pull-up 1 : With Pull-up INPUT / OUTPUT DATA PUP1 PUP0 RB2 / INT0 Pull-up 0 : No Pull-up 1 : With Pull-up Interrupt Edge Selection Register RB Direction Register RBIO ADDRESS : C3H RESET VALUE : 00000000 ADDRESS : E6H RESET VALUE : 00000000 IEDS IED3H IED3L IED2H INT3 IED2L INT2 DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT IED1H IED1L IED0H INT1 IED0L INT0 External Interrupt Edge Select 00 : Normal I/O port 01 : Falling (1-to-0 transition) 10 : Rising (0-to-1 transition) 11 : Both (Rising & Falling) RB Function Selection Register ADDRESS : CBH RESET VALUE : 00000000 RBFUNC TMR2OV EC1I PWM1O PWM0O INT1I INT0I BUZO AVREFS 0 : RB7 1 : TMR2OV 0 : RB0 when ANSEL0 = 0 AN0 when ANSEL0 = 1 1 : AVref 0 : RB6 1 : EC1 0 : RB1 1 : BUZ Output 0 : RB5 1 : PWM1 Output or Compare Output 0 : RB2 1 : INT0 0 : RB4 1 : PWM0 Output or Compare Output 0 : RB3 1 : INT1 Figure 10-3 Registers of Port RB Regardless of the direction register RBIO, RBFUNC is selected to use as alternate functions, port pin can be used as 36 a corresponding alternate features. June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 PORT RBFUNC.4~0 RB7/ TMR2OV 0 RB7 (Normal I/O Port) 1 Timer2 Overflow Output 0 RB6 (Normal I/O Port) 1 Event Counter 1 Input RB5/ PWM1/ COMP1 0 RB5 (Normal I/O Port) 1 PWM1 Output / Timer3 Compare Output RB4/ PWM0/ COMP0 0 RB4 (Normal I/O Port) 1 PWM0 Output / Timer1 Compare Output 0 RB3 (Normal I/O Port) 1 External Interrupt Input 1 0 RB2 (Normal I/O Port) 1 External Interrupt Input 0 0 RB1 (Normal I/O Port) 1 Buzzer Output 01 RB0 (Normal I/O Port)/ AN0 (ANSEL0=1) 12 External Analog Reference Voltage RB6/EC1 RB3/INT1 RB2/INT0 RB1/BUZ RB0/AN0/ AVref Description 1. When ANSEL0 = “0”, this port is defined for normal I/O port (RB0). When ANSEL0 = “1” and ADS2~0 = “000”, this port can be used Analog Input Port (AN0). 2. When this bit set to “1”, this port defined for AVref, so it can not be used Analog Input Port AN0 and Normal I/O Port RB0. June. 2001 Ver 1.2 37 GMS81C1404/GMS81C1408 10.3 RC and RCIO registers The control register SIOM (address E0 H) controls to select Serial Peripheral Interface function. RC is an 4-bit bidirectional I/O port (address C4H). Each pin can be set individually as input and output through the RCIO register (address C5H). After reset, the RCIO register value is “0”, port may be used as general I/O ports. To select Serial Peripheral Interface function, write “1” to the corresponding bit of SIOM. In addition, Port RC is multiplexed with Serial Peripheral Interface (SPI). ADDRESS : C4H RESET VALUE : Undefined RC Data Register - RC RC6 RC5 RC4 RC3 - - - ADDRESS : C5H RESET VALUE : -0000--- RC Direction Register RCIO INPUT / OUTPUT DATA DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT Figure 10-4 Registers of Port RC PORT Function RC6/ SOUT RC5/ SIN RC4/ SCK RC3/ SRDY SIOM Description SRDY SM [1:0] SCK [1:0] RC6 X X:0 X:X RC6 (Normal I/O Port) SOUT X X:1 X:X SPI Serial Data Output RC5 X 0:X X:X RC5 (Normal I/O Port) SIN X 1:X X:X SPI Serial Data Input RC4 X 0:0 X:X RC4 (Normal I/O Port) SCKO X 0:0 00, 01, 10 SCKI X 0:0 1:1 SPI Synchronous Clock Input RC3 0 X:X X:X RC3 (Normal I/O Port) SRDYIN 1 X:X 00, 01, 10 SPI Ready Input (Master Mode) SRDYOUT 1 X:X 1:1 SPI Ready Output (Slave Mode) SPI Synchronous Clock Output Table 10-1 Serial Communication Functions in RC Port 38 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 10.4 RD and RDIO registers RD is a 3-bit bidirectional I/O port (address C6H). Each pin can be set individually as input and output through the RD Data Register RD RDIO register (address C7H). Pull-up Selection Register ADDRESS : C6H RESET VALUE : Undefined RD2 RD1 RD0 - - - - RD1 / INT3 Pull-up 0 : No Pull-up 1 : With Pull-up INPUT / OUTPUT DATA PUP3 PUP2 PUP1 PUP0 RD0 / INT2 Pull-up 0 : No Pull-up 1 : With Pull-up Interrupt Edge Selection Register RD Direction Register RDIO ADDRESS : CCH RESET VALUE : ----0000 PUPSEL ADDRESS : C7H RESET VALUE : -----000 ADDRESS : E6H RESET VALUE : 00000000 IEDS IED3H IED3L IED2H INT3 IED2L INT2 DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT IED1L INT1 IED0H IED0L INT0 External Interrupt Edge Select 00 : Normal I/O port 01 : Falling (1-to-0 transition) 10 : Rising (0-to-1 transition) 1 1: Both (Rising & Falling) RD Function Selection Register ADDRESS : CDH RESET VALUE : 00000000 RDFUNC IED1H INT3I INT2I 0 : RD0 1 : INT2 0 : RD1 1 : INT3 Figure 10-5 Registers of Port RD In addition, Port RD is multiplexed with external interrupt input function. The control register RDFUNC (address CDH) controls to select alternate function. After reset, this value is “0”, port may be used as general I/O ports. To select alternate function, write “1” to the corresponding bit of June. 2001 Ver 1.2 RDFUNC. Regardless of the direction register RDIO, RDFUNC is selected to use as external interrupt input function, port pin can be used as a interrupt input feature. 39 GMS81C1404/GMS81C1408 11. CLOCK GENERATOR Xin and Xout pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the Xin pin and open the Xout pin. The clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and peripheral hardware. The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator connected to the OSCILLATION CIRCUIT fxin CLOCK PULSE GENERATOR Internal system clock PRESCALER STOP WAKEUP ÷1 ÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 ÷256 ÷512 ÷1024 ÷2048 Peripheral clock Figure 11-1 Block Diagram of Clock Pulse Generator 11.1 Oscillation Circuit XIN and XOUT are the input and output, respectively, a inverting amplifier which can be set for use as an on-chip oscillator, as shown in Figure 11-2 . should consult the crystal manufacturer for appropriate values of external components. OPEN C1 C2 Xout Xout R1 Xin External Clock Source Xin Vss Vss Recommended: C1, C2 = 30pF±10pF for Crystals R1 = 1MΩ Figure 11-2 Oscillator Connections To drive the device from an external clock source, Xout should be left unconnected while Xin is driven as shown in Figure 11-3 . There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user 40 Figure 11-3 External Clock Connections Note: When using a system clock oscillator, carry out wiring in the broken line area in Figure 11-2 to prevent any effects from wiring capacities. - Minimize the wiring length. - Do not allow wiring to intersect with other signal conductors. - Do not allow wiring to come near changing high current. - Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground to any ground pattern where high current is present. - Do not fetch signals from the oscillator. June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 12. Basic Interval Timer cillator, prescaler (only fxin÷2048) and Timer0. The GMS81C1404 and GMS81C1408 has one 8-bit Basic Interval Timer that is free-run, can not stop. Block diagram is shown in Figure 12-1 .The 8-bit Basic interval timer register (BITR) is increased every internal count pulse which is divided by prescaler. Since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. As the count overflows from FFH to 00H, this overflow causes to generate the Basic interval timer interrupt. The BITF is interrupt request flag of Basic interval timer. If the STOP instruction executed after writing “1” to bit RCWDT of CKCTLR, it goes into the internal RC oscillated watchdog timer mode. In this mode, all of the block is halted except the internal RC oscillator, Basic Interval Timer and Watchdog Timer. More detail informations are explained in Power Saving Function. The bit WDTON decides Watchdog Timer or the normal 7-bit timer Note: All control bits of Basic interval timer are in CKCTLR register which is located at same address of BITR (address ECH). Address ECH is read as BITR, written to CKCTLR. Therefore, the CKCTLR can not be accessed by bit manipulation instruction. When write “1” to bit BTCL of CKCTLR, BITR register is cleared to “0” and restart to count-up. The bit BTCL becomes “0” after one machine cycle by hardware. If the STOP instruction executed after writing “1” to bit WAKEUP of CKCTLR, it goes into the wake-up timer mode. In this mode, all of the block is halted except the os- . RCWDT BTS[2:0] fxin ÷8 ÷ 16 ÷ 32 ÷ 64 ÷ 128 ÷ 256 ÷ 512 ÷ 1024 BTCL 3 To Watchdog Timer Clear 8 MUX 0 BITIF BITR (8BIT) Basic Interval Timer Interrupt 1 Internal RC OSC Figure 12-1 Block Diagram of Basic Interval Timer Clock Control Register CKCTLR - WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0 ADDRESS : ECH RESET VALUE : -0010111 Bit Manipulation Not Available Basic Interval Timer Clock Selection Symbol WAKEUP Function Description 1 : Enables Wake-up Timer 0 : Disables Wake-up Timer RCWDT 1 : Enables Internal RC Watchdog Timer 0 : Disables Internal RC Watchdog Time WDTON 1 : Enables Watchdog Timer 0 : Operates as a 7-bit Timer BTCL 1 : BITR is cleared and BTCL becomes “0” automatically after one machine cycle, and BITR continue to count-up 000 : fxin ÷ 8 001 : fxin ÷ 16 010 : fxin ÷ 32 011 : fxin ÷ 64 100 : fxin ÷ 128 101 : fxin ÷ 256 110 : fxin ÷ 512 111 : fxin ÷ 1024 Figure 12-2 CKCTLR: Clock Control Register June. 2001 Ver 1.2 41 GMS81C1404/GMS81C1408 13. TIMER / COUNTER The GMS81C1404 and GMS81C1408 has four Timer/ Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and Timer 1 can be used either the two 8-bit Timer/Counter or one 16-bit Timer/Counter by combining them. Also Timer 2 and Timer 3 are same. In this document, explain Timer 0 and Timer 1 because Timer2 and Timer3 same with Timer 0 and Timer 1. In the “timer” function, the register is increased every internal clock input. Thus, one can think of it as counting internal clock input. Since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the oscillator frequency in Timer0. And Timer1 can use the same clock source too. In addition, Timer1 has more fast clock source (1/1 to 1/8). In the “counter” function, the register is increased in response to a 0-to-1 (rising edge) transition at its corresponding external input pin, EC0(Timer 0) or EC1(Timer 2). Note: In the external event counter function, the RA0/EC0 pin has not a schmitt trigger, but a normal input port. Therefore, it may be count more than input event signal if the noise interfere in slow transition input signal . In addition the “capture” function, the register is increased in response external interrupt same with timer function. When external interrupt edge input, the count register is captured into capture data register CDRx. Timer1 and Timer 3 are shared with “PWM” function and “Compare output” function It has seven operating modes: “8-bit timer/counter”, “16bit timer/counter”, “8-bit capture”, “16-bit capture”, “8-bit compare output”, “16-bit compare output” and “10-bit PWM” which are selected by bit in Timer mode register TMx as shown in Figure 13-1 and Table 13-1 . Timer 0(2) Mode Register TM0(2) - - CAPx TxCK2 TxCK1 TxCK0 TxCN ADDRESS : D0H (D6H for TM2) RESET VALUE : --000000 TxST CAP0 CAP2 Capture mode selection bit. 0 : Disables Capture 1 : Enables Capture T0CN T2CN Continue control bit 0 : Stop counting 1 : Start counting continuously T0CK[2:0] T2CK[2:0] Input clock selection 000 : fxin ÷ 2, 100 : fxin ÷ 128 T0ST T2ST Start control bit 0 : Stop counting 1 : Counter register is cleared and start again 001 : fxin ÷ 4, 010 : fxin ÷ 8, 101 : fxin ÷ 512 110 : fxin ÷ 2048 011 : fxin ÷ 32, 111 : External Event ( EC0(1) ) Timer 1(3) Mode Register TM1(3) POL 16BIT PWMxE CAPx TxCK1 TxCK0 TxCN ADDRESS : D2H (D8H for TM3) RESET VALUE : 00000000 TxST PWM Output Polarity 0 : Duty active low 1 : Duty active high T1CK[2:0] T3CK[2:0] 16BIT 16-bit mode selection 0 : 8-bit mode 1 : 16-bit mode T1CN T3CN Continue control bit 0 : Stop counting 1 : Start counting continuously PWM0E PWM1E PWM enable bit 0 : Disables PWM 1 : Enables PWM T1ST T3ST Start control bit 0 : Stop counting 1 : Counter register is cleared and start again CAP1 CAP3 Capture mode selection bit. 0 : Disables Capture 1 : Enables Capture POL Input clock selection 00 : fxin 10 : fxin ÷ 8 01 : fxin ÷ 2 11 : using the Timer 0 clock Figure 13-1 Timer Mode Register (TMx, x = 0~3) 42 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 16BIT CAP0 CAP1 PWME T0CK[2:0] T1CK[1:0] PWMO TIMER 0 TIMER1 0 0 0 0 XXX XX 0 8-bit Timer 8-bit Timer 0 0 1 0 111 XX 0 8-bit Event Counter 8-bit Capture 0 1 0 0 XXX XX 1 8-bit Capture 8-bit Compare output 0 X1 0 1 XXX XX 1 8-bit Timer/Counter 10-bit PWM 1 0 0 0 XXX 11 0 16-bit Timer 1 0 0 0 111 11 0 16-bit Event Counter 1 1 X 0 XXX 11 0 16-bit Capture 1 0 0 0 XXX 11 1 16-bit Compare output Table 13-1 Operating Modes of Timer 0 and Timer 1 1. X: The value “0” or “1” corresponding your operation. 13.1 8-bit Timer/Counter Mode The GMS81C1404 and GMS81C1408 has four 8-bit Timer/Counters, Timer 0, Timer 1, Timer 2 and Timer 3, as shown in Figure 13-2 . The “timer” or “counter” function is selected by mode reg- TM0 TM1 isters TMx as shown in Figure 13-1 and Table 13-1 . To use as an 8-bit timer/counter mode, bit CAP0 of TM0 is cleared to “0” and bits 16BIT of TM1 should be cleared to “0”(Table 13-1 ). - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST - - 0 X X X X X POL 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST X 0 0 0 X X X X ADDRESS : D0H RESET VALUE : --000000 ADDRESS : D2H RESET VALUE : 00000000 X: The value “0” or “1” corresponding your operation. T0CK[2:0] T0ST Edge Detector 0 : Stop 1 : Clear and Start 1 EC0 fxin ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 ÷1 ÷2 ÷8 T0 (8-bit) MUX CLEAR TIMER 0 INTERRUPT T0IF COMPARATOR T0CN TDR0 (8-bit) T1CK[1:0] T1ST 0 : Stop 1 : Clear and Start 1 MUX T1 (8-bit) CLEAR COMP0 PIN F/F T1IF T1CN TIMER 1 INTERRUPT COMPARATOR TDR1 (8-bit) Figure 13-2 8-bit Timer / Counter Mode June. 2001 Ver 1.2 43 GMS81C1404/GMS81C1408 (latched in T0F bit). As TDRx and Tx register are in same address, when reading it as a Tx, written to TDRx. These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option of 2, 4, 8, 32,128, 512, 2048 (selected by control bits T0CK2, T0CK1 and T0CK0 of register TM0) and 1, 2, 8 (selected by control bits T1CK1 and T1CK0 of register TM1). In the Timer 0, timer register T0 increases from 00H until it matches TDR0 and then reset to 00H. The match output of Timer 0 generates Timer 0 interrupt In counter function, the counter is increased every 0-to 1 (rising edge) transition of EC0 pin. In order to use counter function, the bit RA0 of the RA Direction Register RAIO is set to “0”. The Timer 0 can be used as a counter by pin EC0 input, but Timer 1 can not. TDR1 n n-1 nt -c ou ~~ PCP ~~ 9 8 ~~ up 7 6 5 4 3 2 1 0 Timer 1 (T1IF) Interrupt TIME Interrupt period = PCP x (n+1) Occur interrupt Occur interrupt Occur interrupt Figure 13-3 Counting Example of Timer Data Registers TDR1 disable t ~~ clear & start enable up -c o un stop ~~ TIME Timer 1 (T1IF) Interrupt Occur interrupt T1ST Start & Stop T1ST = 0 Occur interrupt T1ST = 1 T1CN Control count T1CN = 0 T1CN = 1 Figure 13-4 Timer Count Operation 44 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 13.2 16-bit Timer/Counter Mode The clock source of the Timer 0 is selected either internal or external clock by bit T0CK2, T0CK1 and T0SL0. The Timer register is being run with 16 bits. A 16-bit timer/ counter register T0, T1 are increased from 0000H until it matches TDR0, TDR1 and then resets to 0000 H . The match output generates Timer 0 interrupt not Timer 1 interrupt. - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST - - 0 X X X X X POL 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST X 1 0 0 1 1 X X TM0 TM1 In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1 should be set to “1” respectively. ADDRESS : D0H RESET VALUE : --000000 ADDRESS : D2H RESET VALUE : 00000000 X: The value “0” or “1” corresponding your operation. T0CK[2:0] T0ST 0 : Stop 1 : Clear and Start Edge Detector 1 EC0 fxin ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 T1 (8-bit) MUX T0 (8-bit) CLEAR T0IF T0CN TIMER 0 INTERRUPT COMPARATOR F/F TDR1 (8-bit) TDR0 (8-bit) COMP0 PIN Figure 13-5 16-bit Timer / Counter Mode 13.3 8-bit Compare Output (16-bit) The GMS81C1404 and GMS81C1408 has a function of Timer Compare Output. To pulse out, the timer match can goes to port pin(COMP0) as shown in Figure 13-2 and Figure 13-5 . Thus, pulse out is generated by the timer match. These operation is implemented to pin, RB4/COMP0/ PWM. This pin output the signal having a 50: 50 duty square wave, and output frequency is same as below equation. jvtw v m = ------------------------------------------------------------------------------------------Y × w } × ( {ky + X ) In this mode, the bit PWMO of RB function register (RBFUNC) should be set to “1”, and the bit PWME of timer1 mode register (TM1) should be set to “0”. In addition, 16-bit Compare output mode is available, also. 13.4 8-bit Capture Mode The Timer 0 capture mode is set by bit CAP0 of timer mode register TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as shown in Figure 13-6 . As mentioned above, not only Timer 0 but Timer 1 can also June. 2001 Ver 1.2 be used as a capture mode. The Timer/Counter register is increased in response internal or external input. This counting function is same with normal timer mode, and Timer interrupt is generated when 45 GMS81C1404/GMS81C1408 timer register T0 (T1) increases and matches TDR0 (TDR1). This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer. For example, in Figure 13-8 , the pulse width of captured signal is wider than the timer data value (FFH) over 2 times. When external interrupt is occurred, the captured value (13H) is more little than wanted value. It can be obtained correct value by counting the number of timer overflow occurrence. tured into registers CDRx (CDR0, CDR1), respectively. After captured, Timer x register is cleared and restarts by hardware. It has three transition modes: “falling edge”, “rising edge”, “both edge” which are selected by interrupt edge selection register IEDS (Refer to External interrupt section). In addition, the transition at INTx pin generate an interrupt. Note: The CDRx, TDRx and Tx are in same address. In the capture mode, reading operation is read the CDRx, not Tx because path is opened to the CDRx, and TDRx is only for writing operation. Timer/Counter still does the above, but with the added feature that a edge transition at external input INTx pin causes the current value in the Timer x register (T0,T1), to be cap- TM0 TM1 - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST - - 1 X X X X X POL 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST X 0 0 1 X X X X T0CK[2:0] ADDRESS : D0H RESET VALUE : --000000 ADDRESS : D2H RESET VALUE : 00000000 T0ST 0 : Stop 1 : Clear and Start Edge Detector 1 EC0 fxin ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 CLEAR T0 (8-bit) MUX T0IF T0CN CAPTURE COMPARATOR CDR0 (8-bit) TDR0 (8-bit) INT0IF INT0 TIMER 0 INTERRUPT INT 0 INTERRUPT T0ST 0 : Stop 1 : Clear and Start IEDS[1:0] ÷1 ÷2 ÷8 1 MUX CLEAR T1 (8-bit) T1IF T1CK[1:0] T1CN IEDS[3:2] TIMER 1 INTERRUPT COMPARATOR CDR1 (8-bit) TDR1 (8-bit) CAPTURE INT1IF INT 1 INTERRUPT INT1 Figure 13-6 8-bit Capture Mode 46 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 This value is loaded to CDR0 n T0 n-1 nt ou ~~ ~~ 9 up -c 8 7 6 5 4 ~~ 3 2 1 0 TIME Ext. INT0 Pin Interrupt Request (INT0F) Interrupt Interval Period Ext. INT0 Pin Interrupt Request (INT0F) Delay Capture (Timer Stop) Clear & Start Figure 13-7 Input Capture Operation Ext. INT0 Pin Interrupt Request (INT0F) Interrupt Interval Period = FFH + 01H + FFH +01H + 13H = 213H Interrupt Request (T0F) FFH FFH T0 13H 00H 00H Figure 13-8 Excess Timer Overflow in Capture Mode June. 2001 Ver 1.2 47 GMS81C1404/GMS81C1408 13.5 16-bit Capture Mode In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1 should be set to “1” respectively. 16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK2, T0CK1 and T0CK0. - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST - - 1 X X X X X POL 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST X 1 0 X 1 1 X X TM0 TM1 ADDRESS : D0H RESET VALUE : --000000 ADDRESS : D2H RESET VALUE : 00000000 X: The value “0” or “1” corresponding your operation. T0CK[2:0] T0ST Edge Detector 0 : Stop 1 : Clear and Start 1 EC0 fxin ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 CLEAR T0 + T1 (16-bit) MUX T0CN T0IF TIMER 0 INTERRUPT COMPARATOR CAPTURE CDR1 (8-bit) CDR0 (8-bit) TDR1 (8-bit) TDR0 (8-bit) INT0IF INT 0 INTERRUPT INT0 IEDS[1:0] Figure 13-9 16-bit Capture Mode 13.6 PWM Mode The GMS81C1404 and GMS81C1408 has a two high speed PWM (Pulse Width Modulation) functions which shared with Timer1 (Timer 3). In this document, it will be explained only PWM0. The user writes the lower 8-bit period value to the T1PPR and the higher 2-bit period value to the PWM0HR[3:2]. And writes duty value to the T1PDR and the PWM0HR[1:0] same way. In PWM mode, pin RB4/COMP0/PWM0 outputs up to a 10-bit resolution PWM output. This pin should be configure as a PWM output by setting “1” bit PWM0O in RBFUNC register. (PWM1 output by setting “1” bit PWM1O in RBFUNC) The T1PDR is configure as a double buffering for glitchless PWM output. In Figure 13-10 , the duty data is transferred from the master to the slave when the period data matched to the counted value. (i.e. at the beginning of next duty cycle) The period of the PWM output is determined by the T1PPR (PWM0 Period Register) and PWM0HR[3:2] (bit3,2 of PWM0 High Register) and the duty of the PWM output is determined by the T1PDR (PWM0 Duty Register) and PWM0HR[1:0] (bit1,0 of PWM0 High Register). PWM Period = [PWM0HR[3:2]T1PPR] X Source Clock 48 PWM Duty = [PWM0HR[1:0]T1PDR] X Source Clock The relation of frequency and resolution is in inverse proportion. Table 13-2 shows the relation of PWM frequency vs. resolution. June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 It can be changed duty value when the PWM output. However the changed duty value is output after the current period is over. And it can be maintained the duty value at present output when changed only period value shown as Figure 13-12 . As it were, the absolute duty time is not changed in varying frequency. But the changed period value must greater than the duty value. If it needed more higher frequency of PWM, it should be reduced resolution. Frequency Resolution T1CK[1:0] = 00(125nS) T1CK[1:0] = 01(250nS) T1CK[1:0] = 10(1uS) 10-bit 7.8KHz 3.9KHz 0.98KHZ 9-bit 15.6KHz 7.8KHz 1.95KHz 8-bit 31.2KHz 15.6KHz 3.90KHz 7-bit 62.5KHz 31.2KHz 7.81KHz Note: If changing the Timer1(3) to PWM function, it should be stop the timer clock firstly, and then set period and duty register value. If user writes register values while timer is in operation, these register could be set with certain values. Table 13-2 PWM Frequency vs. Resolution at 8MHz Ex) LDM LDM LDM LDM LDM LDM The bit POL of TM1 decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM output is determined by the bit POL (1: High, 0: Low). And if the duty value is set to “00H”, the PWM output is determined by the bit POL (1: Low, 0: High). TM1 PWM0HR POL 16BIT PW ME C A P1 T1C K 1 T1C K 0 T 1C N T 1S T X 0 1 0 X X X X - - - - - - - - PW M 0HR3 PW M0HR2 PW M0HR1 PW M0HR0 X X X Period High T1ST ADDRESS : D2H RESET VALUE : 00000000 ADDRESS : D5H RESET VALUE : ----0000 Bit Manipulation Not Available X Duty High X: The value “0” or “1” corresponding your operation. PWM0HR[3:2] T0 clock source TM1,#00H T1PPR,#00H T1PDR,#00H PWM0HR,#00H RBFUNC,#0001_1100B TM1,#1010_1011B T1PPR(8-bit) 0 : Stop 1 : Clear and Start COMPARATOR RB4/ PWM0 S Q CLEAR 1 fxin ÷1 ÷2 ÷8 MUX COMPARATOR T1CK[1:0] R T1 (8-bit) PWM0O [RBFUNC.4] POL T1CN Slave T1PDR(8-bit) PWM0HR[1:0] Master T1PDR(8-bit) Figure 13-10 PWM Mode June. 2001 Ver 1.2 49 GMS81C1404/GMS81C1408 ~ ~ ~ ~ fxin 02 03 04 05 80 81 3FF 00 01 02 03 ~ ~ ~ ~ PWM POL=1 7F ~ ~ ~ ~ 00 01 ~ ~ ~ ~ ~ ~ T1 ~ ~ PWM POL=0 Duty Cycle [80H x 125nS = 16uS] Period Cycle [3FFH x 125nS = 127.875uS, 7.8KHz] T1CK[1:0] = 00 (fxin) PWM0HR = 0CH Period PWM0HR3 PWM0HR2 1 1 T1PPR (8-bit) FFH T1PPR = FFH T1PDR = 80H Duty PWM0HR1 PWM0HR0 0 0 T1PDR (8-bit) 80H Figure 13-11 Example of PWM at 8MHz T 1 C K [1:0 ] = 10 (1 uS ) P W M 0 H R = 0 0H T1PPR = 0EH T 1 P D R = 0 5H Write T1PPR to 0AH Period changed Source clock T1 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 01 02 03 04 05 06 07 08 09 0A 01 02 03 04 05 PWM POL=1 Duty Cycle [05H x 1uS = 5uS] Period Cycle [0EH x 1uS = 14uS, 71KHz] Duty Cycle [05H x 1uS = 5uS] Duty Cycle [05H x 1uS = 5uS] Period Cycle [0AH x 1uS = 10uS, 100KHz] Figure 13-12 Example of Changing the Period in Absolute Duty Cycle (@8MHz) 50 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 14. Serial Peripheral Interface The Serial Peripheral Interface (SPI) module is a serial interface useful for communicating with other peripheral of microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. SPI Mode Control Register POL SIOM POL SRDY SM1 SM0 SCK1 SCK0 SIOST ADDRESS : E0H RESET VALUE : 00000001 SIOSF Serial Clock Polarity Selection bit. 0 : Data Transmission at falling edge (Received data latch at rising edge) 1 : Data Transmission at rising edge (Received data latch at falling edge) SCK[1:0] SRDY Serial Ready Enable bit 0 : Disable (RC3) 1 : Enable (SRDYIN / SRDYOUT) SIOST Serial Transmit Start bit 0 : Disable 1 : Start (After one SCK, becomes “0”) SM[1:0] Serial Operation Mode Selection bits 00 : Normal Port (RC4, RC5, RC6) 01 : Transmit Mode (SCK, RC5, SOUT) 10 : Receive Mode (SCK, SIN, RC6) 11 : Transmit & Receive Mode (SCK, SIN, SOUT) SIOSF Serial Transmit Status bit 0 : During Transmission 1 : Finished Serial Clock Selection bits 00 : fxin ÷ 4 01 : fxin ÷ 16 10 : TMR2OV (Overflow of Timer 2) 11 : External Clock SPI Data Register ADDRESS : E1H RESET VALUE : Undefined SIOR SOUT SM0 MSB LSB SIOR SIN SM1 SPIF (Interrupt Request) Octal Counter POL SCK fxin 01 fxin 10 TMR2OV 11 External Clock Polarity SCK1 SCK0 ÷4 ÷ 16 00 2 SCK[1:0] SM1 SM0 SRDY SRDY R SIOST S From Control Circuit Q To Control Circuit Figure 14-1 SPI Registers and Block Diagram June. 2001 Ver 1.2 51 GMS81C1404/GMS81C1408 The serial data transfer operation mode is decided by setting the SM1 and SM0 of SPI Mode Control Register, and the transfer clock rate is decided by setting the SCK1 and SCK0 of SPI Mode Control Register as shown in Figure 14-1 . And the polarity of transfer clock is selected by setting the POL. The SPI allows 8-bits of data to be synchronously transmitted and received. To accomplish communication, typically three pins are used: - Serial Data In - Serial Data Out - Serial Clock RC5/SIN RC6/SOUT RC4/SCK The bit SRDY is used for master / slave selection. If this bit is set to “1” and SCK[1:0] is set to “11”, the controller is performed to slave controller. As it were, the port RC3 is served for SRDYOUT. Additonarlly a fourth pin may be used when in a master or a slave mode of operation: - Serial Transfer Ready RC3/SRDYIN/SRDYOUT SIOST SCK (POL=1) SCK (POL=0) SOUT SIN D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 SPIF (SPI Int. Req) Figure 14-2 SPI Timing Diagram (without SRDY control) SRDY SIOST SCK (POL=1) SCK (POL=0) SOUT SIN D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 SPIF (SPI Int. Req) Figure 14-3 SPI Timing Diagram (with SRDY control) 52 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 15. Buzzer Output function The buzzer driver consists of 6-bit binary counter, the buzzer register BUR and the clock selector. It generates square-wave which is very wide range frequency (480 Hz~250 KHz at fxin = 4 MHz) by user programmable counter. Also, it is cleared by counter overflow and count up to output the square wave pulse of duty 50%. The bit 0 to 5 of BUR determines output frequency for buzzer driving. Frequency calculation is following as shown below. Pin RB1 is assigned for output port of Buzzer driver by setting the bit BUZO of RBFUNC to “1”. The 6-bit buzzer counter is cleared and start the counting by writing signal to the register BUR. It is increased from 00H until it matches 6-bit register BUR. BUR BUCK1 BUCK0 Input clock selection 00 : fxin ÷ 8 BUR5 BUR4 BUR3 i| ( o¡ ) Oscillator Frequency = ------------------------------------------------------------------------------------Y × Prescaler Ratio × ( i|y + X ) The bits BUCK1, BUCK0 of BUR selects the source clock from prescaler output. BUR2 BUR1 BUR0 ADDRESS : DEH RESET VALUE : 11111111 Bit Manipulation Not Available Buzzer Period Data 01 : fxin ÷ 16 10 : fxin ÷ 32 11 : fxin ÷ 64 fxin ÷8 ÷ 16 ÷ 32 ÷ 64 MUX COUNTER (6-bit) F/F COMPARATOR BUCK[1:0] RB1/BUZ PIN BUR (6-bit) BUZO [RBFUNC.1] Figure 15-1 Buzzer Driver June. 2001 Ver 1.2 53 GMS81C1404/GMS81C1408 16. ANALOG TO DIGITAL CONVERTER The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/D module has eight analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is selected to VDD or AVref by setting of the bit AVREFS in RBFUNC register. If external analog reference AVref is selected, the bit ANSEL0 should not be set to “1”, because this pin is used to an analog reference of A/D converter. The A/D module has two registers which are the control register ADCM and A/D result register ADCR. The ADCM register, shown in Figure 16-2 , controls the operation of the A/D converter module. The port pins can be configure as analog inputs or digital I/O. To use analog inputs, each port is assigned analog input port by setting the bit ANSEL[7:0] in RAFUNC register. And selected the corresponding channel to be converted by setting ADS[2:0]. The processing of conversion is start when the start bit ADST is set to “1”. After one cycle, it is cleared by hardware. The register ADCR contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCR, the A/D conversion status bit ADSF is set to “1”, and the A/D interrupt flag ADIF is set. The block diagram of the A/D module is shown in Figure 16-1 . The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 10 uS (at fxin=8 MHz). ADS[2:0] 111 RA7/AN7 ANSEL7 110 RA6/AN6 A/D Result Register ANSEL6 101 ADCR(8-bit) RA5/AN5 ADDRESS : EBH RESET VALUE : Undefined ANSEL5 100 RA4/AN4 ANSEL4 Sample & Hold S/H Successive Approximation Circuit 011 RA3/AN3 A D IF A/D Interrupt ANSEL3 010 RA2/AN2 ANSEL2 001 RA1/AN1 Resistor Ladder Circuit ANSEL1 000 RB0/AN0/AVref ANSEL0 (RAFUNC.0) 1 VDD Pin 0 ADEN AVREFS (RBFUNC.0) Figure 16-1 A/D Converter Block Diagram 54 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 A/D Control Register ADCM - - ADEN ADS2 ADS1 ADS0 ADST ADSF ADDRESS : EAH RESET VALUE : --000001 Reserved A/D Status bit 0 : A/D Conversion is in process 1 : A/D Conversion is completed Analog Channel Select 000 : Channel 0 (RB0/AN0) 001 : Channel 1 (RA1/AN1) 010 : Channel 2 (RA2/AN2) 011 : Channel 3 (RA3/AN3) 100 : Channel 4 (RA4/AN4) 101 : Channel 5 (RA5/AN5) 110 : Channel 6 (RA6/AN6) 111 : Channel 7 (RA7/AN7) A/D Start bit 1 : A/D Conversion is started After 1 cycle, cleared to “0” 0 : Bit force to zero A/D Enable bit 1 : A/D Conversion is enable 0 : A/D Converter module shut off and consumes no operation current A/D Result Data Register ADCR ADCR7 ADCR6 ADCR5 ADCR4 ADCR3 ADCR2 ADCR1 ADCR0 ADDRESS : EBH RESET VALUE : Undefined Figure 16-2 A/D Converter Registers A/D Converter Cautions ENABLE A/D CONVERTER (1) Input range of AN0 to AN7 The input voltage of AN0 to AN7 should be within the specification range. In particular, if a voltage above VDD (or AVref) or below VSS is input (even if within the absolute maximum rating range), the conversion value for that channel can not be indeterminate. The conversion values of the other channels may also be affected. A/D INPUT CHANNEL SELECT ANALOG REFERENCE SELECT (2) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AVref(or VDD)and AN0 to AN7. Since the effect A/D START (ADST = 1) increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 16-4 in order to reduce noise. NOP ADSF = 1 NO YES Analog Input AN0~AN7 100~1000pF READ ADCR Figure 16-3 A/D Converter Operation Flow June. 2001 Ver 1.2 Figure 16-4 Analog Input Pin Connecting Capacitor 55 GMS81C1404/GMS81C1408 (3) Pins AN0/RB0 and AN1/RA1 to AN7/RA7 The analog input pins AN0 to AN7 also function as input/ output port (PORT RA and RB0) pins. When A/D conversion is performed with any of pins AN0 to AN7 selected, be sure not to execute a PORT input instruction while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling 56 noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. (4) AVref pin input impedance A series resistor string of approximately 10KΩ is connected between the AVref pin and the VSS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the AVref pin and the VSS pin, and there will be a large reference voltage error. June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 17. INTERRUPTS The GMS81C1404 and GMS81C1408 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Interrupt Edge Selection Register (IEDS), priority circuit and Master enable flag(“I” flag of PSW). The configuration of interrupt circuit is shown in Figure 17-1 and Interrupt priority is shown in Table 17-1 . The External Interrupts INT0, INT1, INT2 and INT3 can each be transition-activated (1-to-0, 0-to-1 and both transition). The flags that actually generate these interrupts are bit INT0IF, INT1IF, INT2IF and INT3IF in Register IRQH. When an external interrupt is generated, the flag that gen- erated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transitionactivated. The Timer 0, Timer 1, Timer 2 and Timer 3 Interrupts are generated by T0IF, T1IF, T2IF and T3IF, which are set by a match in their respective timer/counter register. The AD converter Interrupt is generated by ADIF which is set by finishing the analog to digital conversion. The Watch dog timer Interrupt is generated by WDTIF which set by a match in Watch dog timer register (when the bit WDTON is set to “0”). The Basic Interval Timer Interrupt is generated by BITIF which is set by a overflowing of the Basic Interval Timer Register(BITR). Internal bus line IENH IRQH INT0IF IEDS External Int. 1 INT1IF Timer 0 T0IF Timer 1 T1IF External Int. 2 INT2IF IEDS External Int. 3 INT3IF Timer 2 T2IF Timer 3 T3IF A/D Converter ADIF WDT WDTIF BIT BITIF SPI SPIF IRQL 7 6 5 Release STOP 4 3 Priority Control External Int. 0 Interrupt Enable Register (Higher byte) I-flag is in PSW, it is cleared by “DI”, set by “EI” instruction.When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by “RETI” instruction, I-flag is set to “1” by hardware. 2 1 0 To CPU I Flag Interrupt Master Enable Flag Interrupt Vector Address Generator 7 6 5 5 IENL Interrupt Enable Register (Lower byte) Internal bus line Figure 17-1 Block Diagram of Interrupt Function June. 2001 Ver 1.2 57 GMS81C1404/GMS81C1408 The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL) and the interrupt request flags (in IRQH, IRQL) except Power-on reset and software BRK interrupt. Interrupt enable registers are shown in Figure 17-2 . These registers are composed of interrupt enable flags of each interrupt source, these flags determines whether an interrupt will be accepted or not. When enable flag is “0”, a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once. Reset/Interrupt Symbol Priority Vector Addr. Hardware Reset External Interrupt 0 External Interrupt 1 Timer 0 Timer 1 External Interrupt 2 External Interrupt 3 Timer 2 Timer 3 A/D Converter Watch Dog Timer Basic Interval Timer Serial Interface RESET INT0 INT1 Timer 0 Timer 1 INT2 INT3 Timer 2 Timer 3 A/D C WDT BIT SPI 1 2 3 4 5 6 7 8 9 10 11 12 FFFEH FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H Table 17-1 Interrupt Priority Interrupt Enable Register High IENH INT0E INT1E T0E T1E INT2E INT3E T2E T3E SPIE - - - - ADDRESS : E2H RESET VALUE : 00000000 Interrupt Enable Register Low IENL ADE WDTE BITE ADDRESS : E3H RESET VALUE : 0000---- Enables or disables the interrupt individually If flag is cleared, the interrupt is disabled. 0 : Disable 1 : Enable Interrupt Request Register High IRQH INT0IF INT1IF T0IF T1IF INT2IF INT3IF T2IF T3IF SPIF - - - - ADDRESS : E4H RESET VALUE : 00000000 Interrupt Request Register Low IRQL ADIF WDTIF BITIF ADDRESS : E5H RESET VALUE : 0000---- Shows the interrupt occurrence 0 : Not occurred 1 : Interrupt request is occurred Figure 17-2 Interrupt Enable Registers and Interrupt Request Registers When an interrupt is occurred, the I-flag is cleared and disable any further interrupt, the return address and PSW are pushed into the stack and the PC is vectored to. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt request flag bits. 58 The interrupt request flag bit(s) must be cleared by software before re-enabling interrupts to avoid recursive interrupts. The Interrupt Request flags are able to be read and written. June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 17.1 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 8 fOSC (2 µs at fXIN=4MHz) after the completion of the current instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction [RETI]. Interrupt acceptance 1. The interrupt master enable flag (I-flag) is cleared to “0” to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. Interrupt request flag for the interrupt source accepted is cleared to “0”. 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the interrupt service program is executed. System clock Instruction Fetch SP Address Bus PC Data Bus Not used SP-1 PCH PCL SP-2 PSW V.L. V.L. ADL V.H. ADH New PC OP code Internal Read Internal Write Interrupt Processing Step Interrupt Service Task V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents. Figure 17-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction Basic Interval Timer Vector Table Address 0FFE6H 0FFE7H 012H 0E3H Entry Address 0E312H 0E313H 0EH 2EH Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program. A interrupt request is not accepted until the I-flag is set to “1” even if a requested interrupt has higher priority than that of the current interrupt being serviced. June. 2001 Ver 1.2 When nested interrupt service is required, the I-flag should be set to “1” by “EI” instruction in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. Saving/Restoring General-purpose Register During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. These registers are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. 59 GMS81C1404/GMS81C1408 The following method is used to save/restore the generalpurpose registers. General-purpose register save/restore using push and pop instructions; Example: Register save using push and pop instructions INTxx: PUSH PUSH PUSH A X Y main task ;SAVE ACC. ;SAVE X REG. ;SAVE Y REG. acceptance of interrupt interrupt service task saving registers interrupt processing POP POP POP RETI Y X A ;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN restoring registers interrupt return 17.2 BRK Interrupt Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 17-4 . =0 B-FLAG BRK or TCALL0 =1 BRK INTERRUPT ROUTINE TCALL0 ROUTINE RETI RET Figure 17-4 Execution of BRK/TCALL0 17.3 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hardware which request is serviced. 60 However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But as user sets I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 Example: Even though Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend. Main Program service TIMER 1 service enable INT0 disable other INT0 service EI Occur TIMER1 interrupt Occur INT0 enable INT0 enable other TIMER1: PUSH PUSH PUSH LDM LDM EI : : : : : : LDM LDM POP POP POP RETI A X Y IENH,#80H IENL,#0 ;Enable INT0 only ;Disable other ;Enable Interrupt IENH,#0FFH ;Enable all interrupts IENL,#0F0H Y X A In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable “EI” in the TIMER1 routine. Figure 17-5 Execution of Multi Interrupt June. 2001 Ver 1.2 61 GMS81C1404/GMS81C1408 17.4 External Interrupt The external interrupt on INT0, INT1, INT2 and INT3 pins are edge triggered depending on the edge selection register IEDS (address 0E6H) as shown in Figure 17-6 . The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. INT0 pin INT0 INTERRUPT INT1IF edge selection INT1 pin INT0IF INT2 pin INT1 INTERRUPT INT2IF INT3 pin INT2 INTERRUPT INT3IF INT3 INTERRUPT IEDS [0E6H] Figure 17-6 External Interrupt Block Diagram Ext. Interrupt Edge Selection Register W W W W Example: To use as an INT0 and INT2 : : ;**** Set port as an input port RB2,RD0 LDM RBIO,#1111_1011B LDM RDIO,#1111_1110B ; ;**** Set port as an interrupt port LDM RBFUNC,#04H LDM RDFUNC,#01H ; ;**** Set Falling-edge Detection LDM IEDS,#0001_0001B : : : Response Time The INT0, INT1,INT2 and INT3 edge are latched into INT0IF, INT1IF, INT2IF and INT3IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. ADDRESS : 0E6H RESET VALUE : 00000000 W W W W IESR 62 INT2 edge select 00 : Int. disable 01 : falling 10 : rising 11 : both INT0 edge select 00 : Int. disable 01 : falling 10 : rising 11 : both INT3 edge select 00 : Int. disable 01 : falling 10 : rising 11 : both INT1 edge select 00 : Int. disable 01 : falling 10 : rising 11 : both June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 shows interrupt response timings. max. 12 fOSC Interrupt Interrupt goes latched active 8 fOSC Interrupt processing Interrupt routine Figure 17-7 Interrupt Response Timing Diagram June. 2001 Ver 1.2 63 GMS81C1404/GMS81C1408 18. WATCHDOG TIMER The purpose of the watchdog timer is to detect the malfunction (runaway) of program due to external noise or other causes and return the operation to the normal condition. The watchdog timer has two types of clock source. The first type is an on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the external oscillator of the Xin pin. It means that the watchdog timer will run, even if the clock on the Xin pin of the device has been stopped, for example, by entering the STOP mode. The other type is a prescaled system clock. The watchdog timer consists of 7-bit binary counter and the watchdog timer data register. When the value of 7-bit binary counter is equal to the lower 7 bits of WDTR, the interrupt request flag is generated. This can be used as WDT interrupt or reset the CPU in accordance with the bit WDTON. Note: Because the watchdog timer counter is enabled after clearing Basic Interval Timer, after the bit WDTON set to “1”, maximum error of timer is depend on prescaler ratio of Basic Interval Timer. The 7-bit binary counter is cleared by setting WDTCL(bit7 of WDTR) and the WDTCL is cleared automatically after 1 machine cycle. The RC oscillated watchdog timer is activated by setting the bit RCWDT as shown below. : LDM LDM STOP NOP NOP : CKCTLR,#3FH WDTR,#0FFH ; enable the RC-osc WDT ; set the WDT period ; enter the STOP mode ; RC-osc WDT running The RC oscillation period is vary with temperature, VDD and process variations from part to part (approximately, 40~120uS). The following equation shows the RC oscillated watchdog timer time-out. T R C W D T = C LK R C ×28×[W D T R .6~ 0 ]+ (C L K R C ×28)/2 w here, C L K R C = 40~ 12 0uS In addition, this watchdog timer can be used as a simple 7bit timer by interrupt WDTIF. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is as below. TWDT = [WDTR.6~0] × Interval of BIT Clock Control Register - CKCTLR WAKEUP RCWDT Watchdog Timer Register 0 BTCL BTS2 BTS1 BTS0 1 X X X X X WDTCL WDTR WDTON ADDRESS : ECH RESET VALUE : -0010111 Bit Manipulation Not Available ADDRESS : EDH RESET VALUE : 01111111 Bit Manipulation Not Available 7-bit Watchdog Counter Register RCWDT BTS[2:0] fxin ÷8 ÷ 16 ÷ 32 ÷ 64 ÷ 128 ÷ 256 ÷ 512 ÷ 1024 WDTR (8-bit) 3 BTCL WDTCL WDTON Clear 8 MUX Internal RC OSC 0 1 BITR (8-bit) 7-bit Counter CPU RESET OFD 1 0 Overflow Detection BITIF Basic Interval Timer Interrupt Watchdog Timer Interrupt Request Figure 18-1 Block Diagram of Watchdog Timer 64 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 19. Power Saving Mode For applications where power consumption is a critical factor, device provides two kinds of power saving functions, STOP mode and Wake-up Timer mode. STOP instruction after setting the corresponding status (WAKEUP) of CKCTLR. Table 19-1 shows the status of each Power Saving Mode. The power saving function is activated by execution of Peripheral STOP Wake-up Timer RAM Retain Retain Control Registers Retain Retain I/O Ports Retain Retain CPU Stop Stop Timer0, Timer2 Stop Operation Oscillation Stop Oscillation Prescaler Stop ÷ 2048 only Entering Condition [WAKEUP] 0 1 Release Sources RESET, RCWDT, INT0~3, EC0~1, SPI RESET, RCWDT, INT0~3, EC0~1, SPI, TIMER0, TIMER2 Table 19-1 Power Saving Mode 19.1 Stop Mode In the Stop mode, the on-chip oscillator is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. Oscillator stops and the systems internal operations are all held up. • The states of the RAM, registers, and latches valid immediately before the system is put in the STOP state are all held. • The program counter stop the address of the instruction to be executed after the instruction “STOP” which starts the STOP operating mode. The Stop mode is activated by execution of STOP instruction after clearing the bit WAKEUP of CKCTLR to “0”. (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example “set1” or “clr1” instruction, it may be undesired operation) In the Stop mode of operation, VDD can be reduced to minimize power consumption. Care must be taken, however, to ensure that VDD is not reduced before the Stop mode is invoked, and that VDD is restored to its normal operating level, before the Stop mode is terminated. June. 2001 Ver 1.2 The reset should not be activated before VDD is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. Note: After STOP instruction, at least two or more NOP instruction should be written Ex) LDM CKCTLR,#0000_1110B STOP NOP NOP In the STOP operation, the dissipation of the power associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level gets higher than the power voltage level (by approximately 0.3 to 0.5V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means. 65 GMS81C1404/GMS81C1408 Release the STOP mode The exit from STOP mode is hardware reset or external interrupt. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine. (refer to Figure 19-1 ) By reset, exit from Stop mode is shown in Figure 19-3 .When exit from Stop mode by external interrupt, enough oscillation stabilization time is required to normal operation. Figure 19-2 shows the timing diagram. When release the Stop mode, the Basic interval timer is activated on wake-up. It is increased from 00H until FFH . The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized.. STOP INSTRUCTION STOP Mode Interrupt Request =0 Corresponding Interrupt Enable Bit (IENH, IENL) IEXX =1 STOP Mode Release Master Interrupt Enable Bit PSW[2] I-FLAG =0 =1 Interrupt Service Routine Next INSTRUCTION Figure 19-1 STOP Releasing Flow by Interrupts ~ ~ ~ ~ Internal Clock ~ ~ External Interrupt ~ ~ STOP Instruction Execution Clear Basic Interval Timer ~ ~ N-2 N-1 N N+1 N+2 00 01 FE FF 00 00 ~ ~ BIT Counter ~ ~ ~ ~ ~ ~ Oscillator (XIN pin) Normal Operation STOP Mode Stabilizing Time tST > 20mS Normal Operation Figure 19-2 Timing of STOP Mode Release by External Interrupt 66 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 STOP Mode ~ ~ ~ ~ ~ ~ ~ ~ Internal Clock RESET ~ ~ ~ ~ Internal RESET ~~ ~ ~ ~ ~ Oscillator (XIN pin) STOP Instruction Execution Time can not be control by software Stabilizing Time tST = 64mS @4MHz Figure 19-3 Timing of STOP Mode Release by RESET 19.2 STOP Mode using Internal RCWDT In the STOP mode using Internal RC-Oscillated Watchdog Timer, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in this mode. The on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. The Internal RC-Oscillated Watchdog Timer mode is activated by execution of STOP instruction after setting the bit RCWDT of CKCTLR to “1”. ( This register should be written by byte operation. If this register is set by bit manipulation instruction, for example “set1” or “clr1” instruction, it may be undesired operation ) Note: After STOP instruction, at least two or more NOP instruction should be written LDM WDTR,#1111_1111B Ex) LDM CKCTLR,#0010_1110B STOP NOP NOP Release the STOP mode using internal RCWDT The exit from STOP mode using Internal RC-Oscillated Watchdog Timer is hardware reset or external interrupt. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts allow both June. 2001 Ver 1.2 on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. In this case, if the bit WDTON of CKCTLR is set to “0” and the bit WDTE of IENH is set to “1”, the device will execute the watchdog timer interrupt service routine.(Figure 19-4 ) However, if the bit WDTON of CKCTLR is set to “1”, the device will generate the internal RESET signal and execute the reset processing. (Figure 19-5 ) If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.( refer to Figure 19-1 ) When exit from STOP mode using Internal RC-Oscillated Watchdog Timer by external interrupt, the oscillation stabilization time is required to normal operation. Figure 194 shows the timing diagram. When release the Internal RC-Oscillated Watchdog Timer mode, the basic interval timer is activated on wake-up. It is increased from 00H until FFH . The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from STOP mode using internal RC-Oscillated Watchdog Timer is shown in Figure 19-5 . 67 GMS81C1404/GMS81C1408 ~ ~ ~ ~ ~ ~ Oscillator (XIN pin) Internal RC Clock ~ ~ ~ ~ Internal Clock ~ ~ External Interrupt (or WDT Interrupt) ~ ~ Clear Basic Interval Timer STOP Instruction Execution ~ ~ N-2 N-1 N N+1 N+2 00 01 FE FF 00 00 ~ ~ BIT Counter Normal Operation Stabilizing Time tST > 20mS STOP Mode Normal Operation Figure 19-4 STOP Mode Releasing by External Interrupt or WDT Interrupt(using RCWDT) STOP Mode ~ ~ ~ ~ ~ ~ Oscillator (XIN pin) Internal RC Clock ~ ~ ~ ~ Internal Clock ~ ~ ~ ~ RESET RESET by WDT ~ ~ Internal RESET ~ ~ STOP Instruction Execution Time can not be control by software Stabilizing Time tST = 64mS @4MHz Figure 19-5 STOP Mode Releasing by RESET(using RCWDT) 19.3 Wake-up Timer Mode In the Wake-up Timer mode, the on-chip oscillator is not stopped. Except the Prescaler(only 2048 devided ratio), Timer0 and Timer2, all functions are stopped, but the onchip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. 68 The Wake-up Timer mode is activated by execution of STOP instruction after setting the bit WAKEUP of CKCTLR to “1”. (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example “set1” or “clr1” instruction, it may be undesired operation) June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 Note: After STOP instruction, at least two or more NOP instruction should be written Ex) LDM TDR0,#0FFH LDM TM0,#0001_1011B LDM CKCTLR,#0100_1110B STOP NOP NOP In addition, the clock source of timer0 and timer2 should be selected to 2048 devided ratio. Otherwise, the wake-up function can not work. And the timer0 and timer2 can be operated as 16-bit timer with timer1 and timer3(refer to timer function). The period of wake-up function is varied by setting the timer data register0, TDR0 or timer data register2, TDR2. Release the Wake-up Timer mode The exit from Wake-up Timer mode is hardware reset, Timer0(Timer2) overflow or external interrupt. Reset redefines all the Control registers but does not change the onchip RAM. External interrupts and Timer0(Timer2) overflow allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If Iflag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.(refer to Figure 19-1 ) When exit from Wake-up Timer mode by external interrupt or timer0(Timer2) overflow, the oscillation stabilizing time is not required to normal operation. Because this mode do not stop the on-chip oscillator shown as Figure 19-6 . ~ ~ ~ ~ ~ ~ Oscillator (XIN pin) CPU Clock STOP Instruction Execution ~ ~ Interrupt Request Normal Operation Wake-up Timer Mode (stop the CPU clock) Normal Operation Do not need Stabilizing Time Figure 19-6 Wake-up Timer Mode Releasing by External Interrupt or Timer0(Timer2) Interrupt 19.4 Minimizing Current Consumption The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. Note: In the STOP operation, the power dissipation associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level becomes higher than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means. June. 2001 Ver 1.2 It should be set properly that current flow through port doesn't exist. First conseider the setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn’t flow. But input voltage level should be VSS or VDD. Be careful that if unspecified voltage, i.e. if uncertain voltage level (not VSSor VDD) is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low. 69 GMS81C1404/GMS81C1408 VDD INPUT PIN INPUT PIN VDD VDD internal pull-up VDD i=0 O OPEN O i i GND Very weak current flows VDD X X i=0 O OPEN Weak pull-up current flows GND O When port is configure as an input, input level should be closed to 0V or 5V to avoid power consumption. Figure 19-7 Application Example of Unused Input Port OUTPUT PIN OUTPUT PIN VDD ON OPEN OFF ON OFF OFF i VDD GND X ON O ON OFF L OFF ON i GND X O VDD L i=0 GND O In the left case, Tr. base current flows from port to GND. To avoid power consumption, there should be low output to the port. In the left case, much current flows from port to GND. Figure 19-8 Application Example of Unused Output Port 70 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 20. RESET The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, while the oscillator running. After reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 20-1 . Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before reading or testing it. Initial state of each register is shown as Table 9-1 . 1 ? ? 4 5 6 7 ~ ~ ? ? FFFE FFFF Start ~ ~ ~ ~ ? ? ? ? FE ADL ADH OP ~ ~ DATA BUS 3 ~ ~ RESET ADDRESS BUS 2 ~ ~ Oscillator (XIN pin) MAIN PROGRAM Stabilizing Time tST = 64mS at 4MHz RESET Process Step Figure 20-1 Timing Diagram after RESET June. 2001 Ver 1.2 71 GMS81C1404/GMS81C1408 21. POWER FAIL PROCESSOR cuit emulator, user can not experiment with it. Therefore, after final development of user program, this function may be experimented. The GMS81C1404 and GMS81C1408 has an on-chip power fail detection circuitry to immunize against power noise. A configuration register, PFDR, can enable (if clear/ programmed) or disable (if set) the Power-fail Detect circuitry. If VDD falls below 2.5~3.5V(2.0~3.0V) range for longer than 50 nS, the Power fail situation may reset MCU according to PFS bit of PFDR. And power fail detect level is selectable by mask option. On the other hand, in the OTP, power fail detect level is decided by setting the bit PFDLEVEL of CONFIG register when program the OTP. Note: Power fail detect level is decided by mask option checking the bit PFDLEVEL of MASK ORDER SHEET (refer to MASK ORDER SHEET) In thc case of OTP, Power fail detect level is decided by setting the bit PFDLEVEL of CONFIG register (refer to Figure 22-1 . As below PFDR register is not implemented on the in-cir- Power Fail Detector Register PFDR - - - - - PFDIS PFDM ADDRESS : EFH RESET VALUE : -----100 PFS Reserved Power Fail Status 0 : Normal Operate 1 : This bit force to “1” when Power fail was detected Operation Mode 0 : System Clock Freeze during power fail 1 : MCU will be reset during power fail Disable Flag 0 : Power fail detection enable 1 : Power fail detection disable Figure 21-1 Power Fail Detector Register RESET VECTOR PFS =1 YES NO RAM CLEAR INITIALIZE RAM DATA Skip the initial routine INITIALIZE ALL PORTS INITIALIZE REGISTERS FUNTION EXECUTION Figure 21-2 Example S/W of RESET by Power fail 72 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 VDD PFVDDMAX PFVDDMIN 64mS Internal RESET VDD When PFDM = 1 Internal RESET 64mS t < 64mS VDD Internal RESET PFVDDMAX PFVDDMIN PFVDDMAX PFVDDMIN 64mS VDD PFVDDMAX PFVDDMIN System Clock When PFDM = 0 VDD PFVDDMAX PFVDDMIN System Clock Figure 21-3 Power Fail Processor Situations June. 2001 Ver 1.2 73 GMS81C1404/GMS81C1408 22. OTP PROGRAMMING (GMS87C1404/GMS87C1408 only) 22.1 DEVICE CONFIGURATION AREA Customer ID recording locations where the user can store check-sum or other customer identification numbers. This area is not accessible during normal execution but is readable and writable during program / verify. The Device Configuration Area can be programmed or left unprogrammed to select device configuration such as security bit. Ten memory locations (0F50H ~ 0FE0H) are designated as 0F50H ID 0F50H ID 0F60H ID 0F70H ID 0F80H ID 0F90H ID 0FA0H ID 0FB0H ID 0FC0H ID 0FD0H ID 0FE0H CONFIG 0FF0H DEVICE CONFIGURATION AREA 0FF0H Configuration Register CONFIG - - - - - PFD LOCK LEVEL - ADDRESS : 0FF0H PFD Level Select 0 : PFD Level High (2.5~3.5V) 1 : PFD Level Low (2.0~3.0V) SECURITY BIT 0 Allow Code Read Out 1 : Prohibit Code Read Out Figure 22-1 Device Configuration Area A_D4 1 28 A_D3 A_D5 2 27 A_D2 A_D6 3 26 A_D1 A_D7 4 25 A_D0 5 24 CTL0 6 23 CTL1 7 22 CTL2 8 21 VDD 9 20 10 19 11 18 12 17 13 16 14 15 VSS VPP NC EPROM Enable Figure 22-2 Pin Assignment 74 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 User Mode EPROM MODE Pin No. Pin Name Pin Name Description 1 RA4 (AN4) A_D4 2 RA5 (AN5) A_D5 3 RA6 (AN6) A_D6 4 RA7 (AN7) A_D7 5 VDD VDD 6 RB0 (AVref/AN0) CTL0 7 RB1 (INT0) CTL1 8 RB2 (INT1) CTL2 RB3~7, RC3~6, RD2 VDD Connect to VDD (6.0V) 19 XIN EPROM Enable High Active, Latch Address in falling edge 20 XOUT NC No connection 21 RESET VPP Programming Power (0V, 12.75V) 22 VSS VSS Connect to VSS (0V) RC0, 1 VDD Connect to VDD (6.0V) 25 RA0 (EC0) A_D0 26 RA1 (AN1) A_D1 27 RA2 (AN2) A_D2 28 RA3 (AN3) A_D3 9~18 23, 24 Address Input Data Input/Output A12 A4 D4 A13 A5 D5 A14 A6 D6 A15 A7 D7 A8 A0 D0 A9 A1 D1 A10 A2 D2 A11 A3 D3 Connect to VDD (6.0V) Read/Write Control Address/Data Control Address Input Data Input/Output Table 22-1 Pin Description in EPROM Mode June. 2001 Ver 1.2 75 GMS81C1404/GMS81C1408 THLD1 TSET1 TDLY1 ~ ~ ~ ~ 0V ~ ~ CTL0 TVPPR ~ ~ ~ ~ TVDDS ~ ~ VPP VIHP ~ ~ TVPPS VDD1H TCD1 0V 0V TCD1 HA LA LA ~~ DATA OUT DATA IN ~ ~ DATA OUT DATA IN ~ ~ ~ ~ A_D7~ A_D0 ~ ~ TCD1 TCD1 ~ ~ VDD1H CTL2 TDLY2 ~ ~ EPROM Enable CTL1 THLD2 VDD1H VDD High 8bit Address Input Low 8bit Address Input Write Mode Verify Low 8bit Address Input Write Mode Verify Figure 22-3 Timing Diagram in Program (Write & Verify) Mode After input a high address, output data following low address input TSET1 THLD1 Another high address step TDLY1 EPROM Enable TVPPS VPP TVDDS CTL0 0V VIHP T VPPR VDD2H CTL1 0V CTL2 0V TCD2 VDD2H A_D7~ A_D0 TCD1 TCD2 TCD1 HA LA DATA LA DATA HA LA DATA High 8bit Address Input Low 8bit Address Input DATA Output Low 8bit Address Input DATA Output High 8bit Address Input Low 8bit Address Input DATA Output VDD2H VDD Figure 22-4 Timing Diagram in READ Mode 76 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 Parameter Symbol MIN TYP MAX Unit Programming Supply Current IVPP - - 50 mA Supply Current in EPROM Mode IVDDP - - 20 mA VPP Level during Programming VIHP 11.5 12.0 12.5 V VDD Level in Program Mode VDD1H 5 6 6.5 V VDD Level in Read Mode VDD2H - 2.7 - V CTL2~0 High Level in EPROM Mode VIHC 0.8VDD - - V CTL2~0 Low Level in EPROM Mode VILC - - 0.2VDD V A_D7~A_D0 High Level in EPROM Mode VIHAD 0.9VDD - - V A_D7~A_D0 Low Level in EPROM Mode VILAD - - 0.1VDD V VDD Saturation Time TVDDS 1 - - mS VPP Setup Time TVPPR - - 1 mS VPP Saturation Time TVPPS 1 - - mS EPROM Enable Setup Time after Data Input TSET1 200 nS EPROM Enable Hold Time after TSET1 THLD1 500 nS EPROM Enable Delay Time after THLD1 TDLY1 200 nS EPROM Enable Hold Time in Write Mode THLD2 100 nS EPROM Enable Delay Time after THLD2 TDLY2 200 nS CTL2,1 Setup Time after Low Address input and Data input TCD1 100 nS CTL1 Setup Time before Data output in Read and Verify Mode TCD2 100 nS Table 22-2 AC/DC Requirements for Program/Read Mode June. 2001 Ver 1.2 77 GMS81C1404/GMS81C1408 START Set VDD=VDD1H Report Programming failure Set VPP=VIHP Verify OK NO Verify blank Report Verify failure Verify for all address NO YES YES Report Programming OK First Address Location Next address location Report Programming failure N=1 VDD=Vpp=0v NO END YES EPROM Write 100uS program time Verify pass NO Verify pass YES Apply 3N program cycle NO Last address YES Figure 22-5 Programming Flow Chart 78 June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 START Set VDD=VDD2H Verify for all address Set VPP=VIHP First Address Location Next address location NO Last address YES Report Read OK VDD=0V VPP=0V END Figure 22-6 Reading Flow Chart June. 2001 Ver 1.2 79 APPENDIX GMS81C1404/GMS81C1408 A. INSTRUCTION MAP LOW 00000 HIGH 00 00001 01 SET1 dp.bit 00010 02 00011 03 BBS BBS A.bit,rel dp.bit,rel 00100 04 00101 05 00110 06 00111 07 01000 08 01001 09 ADC #imm ADC dp ADC dp+X ADC !abs ASL A ASL dp 01010 0A 01011 0B 01100 0C 01101 0D 01110 0E 01111 0F TCALL SETA1 0 .bit BIT dp POP A PUSH A BRK 000 - 001 CLRC SBC #imm SBC dp SBC dp+X SBC !abs ROL A ROL dp TCALL CLRA1 2 .bit COM dp POP X PUSH X BRA rel 010 CLRG CMP #imm CMP dp CMP dp+X CMP !abs LSR A LSR dp TCALL 4 NOT1 M.bit TST dp POP Y PUSH Y PCALL Upage 011 DI OR #imm OR dp OR dp+X OR !abs ROR A ROR dp TCALL 6 OR1 OR1B CMPX dp POP PSW PUSH PSW RET 100 CLRV AND #imm AND dp AND dp+X AND !abs INC A INC dp TCALL AND1 8 AND1B CMPY dp CBNE dp+X TXSP INC X 101 SETC EOR #imm EOR dp EOR dp+X EOR !abs DEC A DEC dp TCALL EOR1 10 EOR1B DBNE dp XMA dp+X TSPX DEC X 110 SETG LDA #imm LDA dp LDA dp+X LDA !abs TXA LDY dp TCALL 12 LDC LDCB LDX dp LDX dp+Y XCN DAS 111 EI LDM dp,#imm STA dp STA dp+X STA !abs TAX STY dp TCALL 14 STC M.bit STX dp STX dp+Y XAX STOP 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1A 11011 1B 11100 1C 11101 1D 11110 1E 11111 1F ADC {X} ADC !abs+Y ADC [dp+X] ADC [dp]+Y ASL !abs ASL dp+X TCALL 1 JMP !abs BIT !abs ADDW dp LDX #imm JMP [!abs] TEST !abs SUBW dp LDY #imm JMP [dp] TCLR1 CMPW !abs dp CMPX #imm CALL [dp] LOW 10000 HIGH 10 10001 11 10010 12 000 BPL rel 001 BVC rel SBC {X} SBC !abs+Y SBC [dp+X] SBC [dp]+Y ROL !abs ROL dp+X TCALL 3 CALL !abs 010 BCC rel CMP {X} CMP !abs+Y CMP [dp+X] CMP [dp]+Y LSR !abs LSR dp+X TCALL 5 MUL 011 BNE rel OR {X} OR !abs+Y OR [dp+X] OR [dp]+Y ROR !abs ROR dp+X TCALL 7 DBNE Y CMPX !abs LDYA dp CMPY #imm RETI 100 BMI rel AND {X} AND !abs+Y AND [dp+X] AND [dp]+Y INC !abs INC dp+X TCALL 9 DIV CMPY !abs INCW dp INC Y TAY 101 BVS rel EOR {X} EOR !abs+Y EOR [dp+X] EOR [dp]+Y DEC !abs DEC dp+X TCALL 11 XMA {X} XMA dp DECW dp DEC Y TYA 110 BCS rel LDA {X} LDA !abs+Y LDA [dp+X] LDA [dp]+Y LDY !abs LDY dp+X TCALL 13 LDA {X}+ LDX !abs STYA dp XAY DAA 111 BEQ rel STA {X} STA !abs+Y STA [dp+X] STA [dp]+Y STY !abs STY dp+X TCALL 15 STA {X}+ STX !abs CBNE dp XYX NOP CLR1 BBC BBC dp.bit A.bit,rel dp.bit,rel June. 2001 Ver 1.2 i GMS81C1404/GMS81C1408 B. INSTRUCTION SET 1. ARITHMETIC/ LOGIC OPERATION NO. ii MNEMONIC OP BYTE CYCLE CODE NO NO 04 2 2 1 ADC #imm 2 ADC dp 05 2 3 3 ADC dp + X 06 2 4 4 ADC !abs 07 3 4 5 ADC !abs + Y 15 3 5 6 ADC [ dp + X ] 16 2 6 7 ADC [ dp ] + Y 17 2 6 8 ADC { X } 14 1 3 9 AND #imm AND dp 84 2 2 10 85 2 3 11 AND dp + X 86 2 4 12 AND !abs 87 3 4 13 AND !abs + Y 95 3 5 14 AND [ dp + X ] 96 2 6 15 AND [ dp ] + Y 97 2 6 16 AND { X } 94 1 3 17 ASL A 08 1 2 18 19 ASL dp ASL dp + X 09 19 2 2 4 5 20 ASL !abs 18 3 5 21 CMP #imm 44 2 2 22 CMP dp 45 2 3 23 CMP dp + X 46 2 4 24 CMP !abs 47 3 4 25 CMP !abs + Y 55 3 5 26 CMP [ dp + X ] 56 2 6 27 CMP [ dp ] + Y 57 2 6 28 CMP { X } 54 1 3 29 CMPX #imm 5E 2 2 30 CMPX dp 6C 2 3 31 CMPX !abs 7C 3 4 32 CMPY #imm 7E 2 2 33 CMPY dp 8C 2 3 34 CMPY !abs 9C 3 4 FLAG NVGBHIZC OPERATION Add with carry. A←(A)+(M)+C NV--H-ZC Logical AND A← (A)∧(M) N-----Z- Arithmetic shift left C 7 6 5 4 3 2 1 N-----ZC 0 “0” Compare accumulator contents with memory contents (A) -(M) N-----ZC Compare X contents with memory contents (X)-(M) N-----ZC Compare Y contents with memory contents (Y)-(M) N-----ZC 35 COM dp 2C 2 4 1’S Complement : ( dp ) ← ~( dp ) N-----Z- 36 DAA DF 1 3 Decimal adjust for addition N-----ZC 37 DAS CF 1 3 Decimal adjust for subtraction N-----ZC 38 DEC A A8 1 2 Decrement N-----Z- 39 DEC dp A9 2 4 40 DEC dp + X B9 2 5 41 DEC !abs B8 3 5 42 DEC X AF 1 2 43 DEC Y BE 1 2 44 DIV 9B 1 12 M← (M)-1 N-----Z- Divide : YA / X Q: A, R: Y NV--H-Z- .June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 NO. MNEMONIC OP BYTE CYCLE OPERATION CODE NO NO A4 2 2 Exclusive OR A5 2 3 A← (A)⊕(M) 45 EOR #imm 46 EOR dp 47 EOR dp + X 48 EOR !abs A7 3 4 49 EOR !abs + Y B5 3 5 50 EOR [ dp + X ] B6 2 6 51 EOR [ dp ] + Y B7 2 6 52 EOR { X } B4 1 3 A6 2 FLAG NVGBHIZC 4 N-----Z- 53 INC A 88 1 2 54 INC dp 89 2 4 55 INC dp + X 99 2 5 56 INC !abs 98 3 5 57 INC X 8F 1 2 58 INC Y 9E 1 2 59 LSR A 48 1 2 60 LSR dp 49 2 4 61 LSR dp + X 59 2 5 62 LSR !abs 58 3 5 63 MUL 5B 1 9 Multiply : YA ← Y × A 64 OR #imm 64 2 2 Logical OR 65 OR dp 65 2 3 66 OR dp + X 66 2 4 67 OR !abs 67 3 4 68 OR !abs + Y 75 3 5 69 OR [ dp + X ] 76 2 6 70 OR [ dp ] + Y 77 2 6 71 OR { X } 74 1 3 72 ROL A 28 1 2 73 ROL dp 29 2 4 74 ROL dp + X 39 2 5 75 ROL !abs 38 3 5 76 ROR A 68 1 2 77 ROR dp 69 2 4 78 ROR dp + X 79 2 5 79 ROR !abs 78 3 5 Increment N-----Z- M← (M)+1 N-----Z- Logical shift right 7 6 5 4 3 2 1 0 C N-----ZC “0” N-----Z- A ← (A)∨(M) N-----Z- Rotate left through carry C 7 6 5 4 3 2 1 0 N-----ZC Rotate right through carry 7 6 5 4 3 2 1 0 C N-----ZC 80 SBC #imm 24 2 2 81 SBC dp 25 2 3 82 SBC dp + X 26 2 4 83 SBC !abs 27 3 4 84 SBC !abs + Y 35 3 5 85 SBC [ dp + X ] 36 2 6 86 SBC [ dp ] + Y 37 2 6 87 SBC { X } 34 1 3 88 TST dp 4C 2 3 Test memory contents for negative or zero ( dp ) - 00H N-----Z- 89 XCN CE 1 5 Exchange nibbles within the accumulator A7~A4 ↔ A3~A0 N-----Z- June. 2001 Ver 1.2 Subtract with carry A ← ( A ) - ( M ) - ~( C ) NV--HZC iii GMS81C1404/GMS81C1408 2. REGISTER / MEMORY OPERATION NO. iv MNEMONIC OP BYTE CYCLE CODE NO NO C4 2 2 1 LDA #imm 2 LDA dp C5 2 3 3 LDA dp + X C6 2 4 4 LDA !abs C7 3 4 5 LDA !abs + Y D5 3 5 6 LDA [ dp + X ] D6 2 6 7 LDA [ dp ] + Y D7 2 6 8 LDA { X } D4 1 3 FLAG NVGBHIZC OPERATION Load accumulator A←(M) N-----Z- 9 LDA { X }+ DB 1 4 X- register auto-increment : A ← ( M ) , X ← X + 1 10 LDM dp,#imm E4 3 5 Load memory with immediate data : ( M ) ← imm 11 LDX #imm 1E 2 2 Load X-register 12 LDX dp CC 2 3 13 LDX dp + Y CD 2 4 14 LDX !abs DC 3 4 15 LDY #imm 3E 2 2 16 LDY dp C9 2 3 17 LDY dp + X D9 2 4 18 LDY !abs D8 3 4 19 STA dp E5 2 4 20 STA dp + X E6 2 5 21 STA !abs E7 3 5 22 STA !abs + Y F5 3 6 23 STA [ dp + X ] F6 2 7 24 STA [ dp ] + Y F7 2 7 25 STA { X } F4 1 4 X ←(M) -------N-----Z- Load Y-register Y←(M) N-----Z- Store accumulator contents in memory (M)←A -------- 26 STA { X }+ FB 1 4 X- register auto-increment : ( M ) ← A, X ← X + 1 27 STX dp EC 2 4 Store X-register contents in memory 28 STX dp + Y ED 2 5 29 STX !abs FC 3 5 30 STY dp E9 2 4 31 STY dp + X F9 2 5 32 STY !abs F8 3 5 33 TAX E8 1 2 Transfer accumulator contents to X-register : X ← A 34 TAY 9F 1 2 Transfer accumulator contents to Y-register : Y ← A N-----Z- 35 TSPX AE 1 2 Transfer stack-pointer contents to X-register : X ← sp N-----Z- (M)← X -------- Store Y-register contents in memory (M)← Y -------N-----Z- 36 TXA C8 1 2 Transfer X-register contents to accumulator: A ← X N-----Z- 37 TXSP 8E 1 2 Transfer X-register contents to stack-pointer: sp ← X N-----Z- 38 TYA BF 1 2 Transfer Y-register contents to accumulator: A ← Y N-----Z- 39 XAX EE 1 4 Exchange X-register contents with accumulator :X ↔ A -------- 40 XAY DE 1 4 Exchange Y-register contents with accumulator :Y ↔ A -------- 41 XMA dp BC 2 5 Exchange memory contents with accumulator 42 XMA dp+X AD 2 6 43 XMA {X} BB 1 5 44 XYX FE 1 4 (M)↔A N-----Z- Exchange X-register contents with Y-register : X ↔ Y -------- .June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 3. 16-BIT OPERATION NO. MNEMONIC OP BYTE CYCLE CODE NO NO OPERATION FLAG NVGBHIZC 1 ADDW dp 1D 2 5 16-Bits add without carry YA ← ( YA ) + ( dp +1 ) ( dp ) NV--H-ZC 2 CMPW dp 5D 2 4 Compare YA contents with memory pair contents : (YA) − (dp+1)(dp) N-----ZC 3 DECW dp BD 2 6 Decrement memory pair ( dp+1)( dp) ← ( dp+1) ( dp) - 1 N-----Z- 4 INCW dp 9D 2 6 Increment memory pair ( dp+1) ( dp) ← ( dp+1) ( dp ) + 1 N-----Z- 5 LDYA dp 7D 2 5 Load YA YA ← ( dp +1 ) ( dp ) N-----Z- 6 STYA dp DD 2 5 Store YA ( dp +1 ) ( dp ) ← YA -------- 7 SUBW dp 3D 2 5 16-Bits substact without carry YA ← ( YA ) - ( dp +1) ( dp) NV--H-ZC 4. BIT MANIPULATION NO. MNEMONIC OP BYTE CYCLE OPERATION CODE NO NO 8B 3 4 Bit AND C-flag : C ← ( C ) ∧ ( M .bit ) FLAG NVGBHIZC -------C 1 AND1 M.bit 2 AND1B M.bit 8B 3 4 Bit AND C-flag and NOT : C ← ( C ) ∧ ~( M .bit ) -------C 3 BIT dp 0C 2 4 Bit test A with memory : MM----Z- 4 BIT !abs 1C 3 5 Z ← ( A ) ∧ ( M ) , N ← ( M7 ) , V ← ( M6 ) 5 CLR1 dp.bit y1 2 4 Clear bit : ( M.bit ) ← “0” -------- 6 CLRA1 A.bit 2B 2 2 Clear A bit : ( A.bit )← “0” -------- 7 CLRC 20 1 2 Clear C-flag : C ← “0” -------0 8 CLRG 40 1 2 Clear G-flag : G ← “0” --0----- 9 -0--0--- CLRV 80 1 2 Clear V-flag : V ← “0” 10 EOR1 M.bit AB 3 5 Bit exclusive-OR C-flag : C ← ( C ) ⊕ ( M .bit ) 11 EOR1B M.bit AB 3 5 12 LDC M.bit CB 3 4 13 LDCB M.bit CB 3 4 Load C-flag with NOT : C ← ~( M .bit ) -------C 14 NOT1 M.bit 4B 3 5 Bit complement : ( M .bit ) ← ~( M .bit ) -------- 15 OR1 M.bit 6B 3 5 Bit OR C-flag : C ← ( C ) ∨ ( M .bit ) -------C 16 OR1B M.bit 6B 3 5 Bit OR C-flag and NOT : C ← ( C ) ∨ ~( M .bit ) -------C -------C Bit exclusive-OR C-flag and NOT : C ← ( C ) ⊕ ~(M .bit) -------C Load C-flag : C ← ( M .bit ) -------C 17 SET1 dp.bit x1 2 4 Set bit : ( M.bit ) ← “1” -------- 18 SETA1 A.bit 0B 2 2 Set A bit : ( A.bit ) ← “1” -------- 19 -------1 SETC A0 1 2 Set C-flag : C ← “1” 20 SETG C0 1 2 Set G-flag : G ← “1” --1----- 21 STC M.bit EB 3 6 Store C-flag : ( M .bit ) ← C -------- 22 TCLR1 !abs 5C 3 6 Test and clear bits with A : A - ( M ) , ( M ) ← ( M ) ∧ ~( A ) N-----Z- 23 TSET1 !abs 3C 3 6 Test and set bits with A : A-(M), (M)← (M)∨(A) N-----Z- June. 2001 Ver 1.2 v GMS81C1404/GMS81C1408 5. BRANCH / JUMP OPERATION NO. vi MNEMONIC 1 BBC A.bit,rel 2 BBC dp.bit,rel OP BYTE CYCLE OPERATION CODE NO NO y2 2 4/6 Branch if bit clear : y3 3 5/7 if ( bit ) = 0 , then pc ← ( pc ) + rel FLAG NVGBHIZC -------- 3 BBS A.bit,rel x2 2 4/6 Branch if bit set : 4 BBS dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ← ( pc ) + rel 5 BCC rel 50 2 2/4 Branch if carry bit clear if ( C ) = 0 , then pc ← ( pc ) + rel -------- 6 BCS rel D0 2 2/4 Branch if carry bit set if ( C ) = 1 , then pc ← ( pc ) + rel -------- 7 BEQ rel F0 2 2/4 Branch if equal if ( Z ) = 1 , then pc ← ( pc ) + rel -------- 8 BMI rel 90 2 2/4 Branch if minus if ( N ) = 1 , then pc ← ( pc ) + rel -------- 9 BNE rel 70 2 2/4 Branch if not equal if ( Z ) = 0 , then pc ← ( pc ) + rel -------- 10 BPL rel 10 2 2/4 Branch if minus if ( N ) = 0 , then pc ← ( pc ) + rel -------- 11 BRA rel 2F 2 4 Branch always pc ← ( pc ) + rel -------- 12 BVC rel 30 2 2/4 Branch if overflow bit clear if (V) = 0 , then pc ← ( pc) + rel -------- 13 BVS rel B0 2 2/4 Branch if overflow bit set if (V) = 1 , then pc ← ( pc ) + rel -------- 14 CALL !abs 3B 3 8 Subroutine call M( sp)←( pcH ), sp←sp - 1, M(sp)← (pcL), sp ←sp - 1, -------if !abs, pc← abs ; if [dp], pc L← ( dp ), pcH← ( dp+1 ) . 15 CALL [dp] 5F 2 8 16 -------- CBNE dp,rel FD 3 5/7 17 CBNE dp+X,rel 8D 3 6/8 18 DBNE dp,rel AC 3 5/7 Decrement and branch if not equal : 19 DBNE Y,rel 7B 2 4/6 if ( M ) ≠ 0 , then pc ← ( pc ) + rel. 20 JMP !abs 1B 3 3 21 JMP [!abs] 1F 3 5 22 JMP [dp] 3F 2 4 23 PCALL upage 4F 2 6 U-page call M(sp) ←( pcH ), sp ←sp - 1, M(sp) ← ( pcL ), sp ← sp - 1, pcL ← ( upage ), pcH ← ”0FFH” . -------- 24 TCALL n nA 1 8 Table call : (sp) ←( pcH ), sp ← sp - 1, M(sp) ← ( pcL ),sp ← sp - 1, pcL ← (Table vector L), pcH ← (Table vector H) -------- Compare and branch if not equal : -------- if ( A ) ≠ ( M ) , then pc ← ( pc ) + rel. -------- Unconditional jump pc ← jump address -------- .June. 2001 Ver 1.2 GMS81C1404/GMS81C1408 6. CONTROL OPERATION & etc. NO. 1 MNEMONIC BRK OP BYTE CYCLE CODE NO NO 0F 1 8 OPERATION FLAG NVGBHIZC Software interrupt : B ← ”1”, M(sp) ← (pcH), sp ←sp-1, M(s) ← (pcL), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, ---1-0-pcL ← ( 0FFDEH ) , pcH ← ( 0FFDFH) . 2 DI 60 1 3 Disable interrupts : I ← “0” -----0-- 3 EI E0 1 3 Enable interrupts : I ← “1” -----1-- 4 -------- NOP FF 1 2 No operation 5 POP A 0D 1 4 sp ← sp + 1, A ← M( sp ) 6 POP X 2D 1 4 sp ← sp + 1, X ← M( sp ) 7 POP Y 4D 1 4 sp ← sp + 1, Y ← M( sp ) 8 sp ← sp + 1, PSW ← M( sp ) POP PSW 6D 1 4 9 PUSH A 0E 1 4 M( sp ) ← A , sp ← sp - 1 10 PUSH X 2E 1 4 M( sp ) ← X , sp ← sp - 1 11 PUSH Y 4E 1 4 M( sp ) ← Y , sp ← sp - 1 12 PUSH PSW 6E 1 4 M( sp ) ← PSW , sp ← sp - 1 -------restored -------- 13 RET 6F 1 5 Return from subroutine -------sp ← sp +1, pcL ← M( sp ), sp ← sp +1, pcH ← M( sp ) 14 RETI 7F 1 6 Return from interrupt sp ← sp +1, PSW ← M( sp ), sp ← sp + 1, pcL ← M( sp ), sp ← sp + 1, pcH ← M( sp ) restored 15 STOP EF 1 3 Stop mode ( halt CPU, stop oscillator ) -------- June. 2001 Ver 1.2 vii MASK ORDER SHEET MASK ORDER & VERIFICATION SHEET GMS81C1404-HG Customer should write inside thick line box. 1. Customer Information 2. Device Information Package Company Name Application YYYY MM DD Order Date Tel: 28SKDIP 28SOP PFD Use YES NO PFD Level HIGH LOW Mask Data File Name: ( Fax: Name & Signature: Hitel .OTP) Check Sum: ( ) 0000H Chollian Set “00” in this area Internet EFFFH F000H .OTP file data FFFFH 3. Marking Specification (Please check mark into G M S81C 1404-H G xxx YYW W KO R EA #1 index mark 4. Delivery Schedule Quantity Date YYYY MM DD Customer Sample pcs YYYY MM DD pcs Risk Order 5. ROM Code Verification YYYY This box is written after “5.Verification”. MM DD Approval Date: Verification D ate: Please confirm our verification data. Fax: YYYY MM DD I agree w ith your verification data and confirm you to m ake m ask set. Fax: Tel: Check Sum: Tel: Name & Signature: Hynix Confirmation Name & Signature: Hynix Semiconductor 2001.6 ) MASK ORDER SHEET MASK ORDER & VERIFICATION SHEET GMS81C1408-HG Customer should write inside thick line box. 1. Customer Information 2. Device Information Package Company Name Application YYYY MM DD Order Date Tel: 28SKDIP 28SOP PFD Use YES NO PFD Level HIGH LOW Mask Data File Name: ( Fax: Name & Signature: Hitel .OTP) Check Sum: ( ) 0000H Chollian Set “00” in this area Internet DFFFH E000H .OTP file data FFFFH 3. Marking Specification (Please check mark into G M S81C 1408-H G xxx YYW W KO R EA #1 index mark 4. Delivery Schedule Quantity Date YYYY MM DD Customer Sample pcs YYYY MM DD pcs Risk Order 5. ROM Code Verification YYYY This box is written after “5.Verification”. MM DD Approval Date: Verification D ate: Please confirm our verification data. Fax: YYYY MM DD I agree w ith your verification data and confirm you to m ake m ask set. Fax: Tel: Check Sum: Tel: Name & Signature: Hynix Confirmation Name & Signature: Hynix Semiconductor 2001.6 ) MASK ORDER SHEET MASK ORDER & VERIFICATION SHEET GMS81C1404E-HG Customer should write inside thick line box. 1. Customer Information 2. Device Information Package Company Name Application YYYY MM DD Order Date Tel: 28SKDIP 28SOP PFD Use YES NO PFD Level HIGH LOW Mask Data File Name: ( Fax: Name & Signature: Hitel .OTP) Check Sum: ( ) 0000H Chollian Set “00” in this area Internet EFFFH F000H .OTP file data FFFFH 3. Marking Specification (Please check mark into G M S81C 1404E-H G xxx YYW W KO R EA #1 index mark 4. Delivery Schedule Quantity Date YYYY MM DD Customer Sample pcs YYYY MM DD pcs Risk Order 5. ROM Code Verification YYYY This box is written after “5.Verification”. MM DD Approval Date: Verification D ate: Please confirm our verification data. Fax: YYYY MM DD I agree w ith your verification data and confirm you to m ake m ask set. Fax: Tel: Check Sum: Tel: Name & Signature: Hynix Confirmation Name & Signature: Hynix Semiconductor 2001.6 ) MASK ORDER SHEET MASK ORDER & VERIFICATION SHEET GMS81C1408E-HG Customer should write inside thick line box. 1. Customer Information 2. Device Information Package Company Name Application YYYY MM DD Order Date Tel: 28SKDIP 28SOP PFD Use YES NO PFD Level HIGH LOW Mask Data File Name: ( Fax: Name & Signature: Hitel .OTP) Check Sum: ( ) 0000H Chollian Set “00” in this area Internet DFFFH E000H .OTP file data FFFFH 3. Marking Specification (Please check mark into G M S81C 1408E-H G xxx YYW W KO R EA #1 index mark 4. Delivery Schedule Quantity Date YYYY MM DD Customer Sample pcs YYYY MM DD pcs Risk Order 5. ROM Code Verification YYYY This box is written after “5.Verification”. MM DD Approval Date: Verification D ate: Please confirm our verification data. Fax: YYYY MM DD I agree w ith your verification data and confirm you to m ake m ask set. Fax: Tel: Check Sum: Tel: Name & Signature: Hynix Confirmation Name & Signature: Hynix Semiconductor 2001.6 )