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DRV3202-Q1
SLVSBJ4B – OCTOBER 2012 – REVISED JULY 2016
DRV3202-Q1 3-Phase Brushless Motor Driver
Not Recommended for New Designs
1 Features
3 Description
•
The DRV3202-Q1 device is a field effect transistor
(FET) pre-driver designed for 3-phase motor control
and its application such as an oil pump or a water
pump. It is equipped with three high-side pre-FET
drivers and three low-side drivers which are
controlled by an external microcontroller (MCU). The
power for the high side is supplied by a charge pump
and no bootstrap cap is needed. For commutation,
this integrated circuit (IC) sends a conditional motor
drive signal and output to the MCU. Diagnostics
provide undervoltage, overvoltage, overcurrent,
overtemperature and power bridge faults. The motor
current can be measured using an integrated current
sense amplifier and comparator in a battery commonmode range, which allows the motor current to be
used in a high-side current sense application. Gain is
attained by external resistors. If the MCU does not
have enough bandwidth, the phase monitoring
sample and hold amplifiers can hold phase
information until the MCU is ready to process it. The
interfaces include SPI and CAN. The pre-driver and
other internal settings can be configured through the
SPI. The CAN is used to communicate with other
electronic control units (ECUs).
1
•
•
•
•
•
•
•
•
•
•
•
3-Phase Pre-drivers for N-channel MOS Field
Effect Transistors (MOSFETs)
Pulse Width Modulation (PWM) Frequency up to
20 kHz
Fault Diagnostics
Charge Pump
Phase Comparators
Phase Monitoring Sample and Hold Op-Amps
Central Processing Unit (CPU) Reset Generator
Serial Port I/F (SPI)
Motor Current Sense
80-pin HTQFP
Controller Area Network (CAN)
5-V Regulator
2 Applications
Automotive
Device Information(1)
PART NUMBER
DRV3202-Q1
PACKAGE
BODY SIZE (NOM)
HTQFP (80)
12.00 mm × 12.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Not Recommended for New Designs
DRV3202-Q1
SLVSBJ4B – OCTOBER 2012 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision history .....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
7
1
1
1
2
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Supply Voltage and Current.................................... 12
Detailed Description ............................................ 19
7.1
7.2
7.3
7.4
8
19
19
31
31
Device and Documentation Support.................. 35
8.1
8.2
8.3
8.4
8.5
9
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Register Maps .........................................................
Receiving Notification of Documentation Updates.. 35
Community Resources............................................ 35
Trademarks ............................................................. 35
Electrostatic Discharge Caution .............................. 35
Glossary .................................................................. 35
Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision history
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2012) to Revision B
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..... 1
•
Changed device status to NRND............................................................................................................................................ 1
Changes from Original (October, 2012) to Revision A
Page
•
Changed max rating for PHTM, PH1M, PH2M, and PH3M from -2 –40 V to -1–40 V. ......................................................... 4
•
Changed O to IO for pin 44 and 45. ....................................................................................................................................... 5
•
Deleted Table 1 Pin Equivalent Circuits. ................................................................................................................................ 6
•
Changed VCANH and VCANL to VCAN_H and VCAN_L in CAN receiver section............................................................... 7
•
Added 3 new parameters to VCC and VDD Electrical Characteristics table. Changed min, typ, and max values
VLRVCC, CVCC, TVCC1, TVCC2, VDDOV, TVDD. Added table note. ............................................................................... 8
•
Changed VCANH and VCANL to VCAN_H and VCAN_L in CAN AC characteristic section. ............................................... 8
•
Changed CANH_D to VCANH_D, CANL_D to VCANL_D, and VCANH - VCANL to VCAN_H - VCAN_L in CAN
timing chart. ............................................................................................................................................................................ 8
•
Changed Vchv1_12 to Vchv1_1, Vchv1_20 to Vchv1_2, Vchv2_12 to Vchv2_1, Vchv2_20 to Vchv2_2, Vchv3_12 to Vchv3_1, Vchv3_20 to
Vchv3_2. .................................................................................................................................................................................... 9
•
Added min and typ values to Vchvmax parameter..................................................................................................................... 9
•
Changed min, typ and max values for Vchv1_0 through Vchv3_2; changed typ Ron value from 10 to 8...................................... 9
•
Removed RONH_H row, removed cross-references from RONH_HP and RONH_HN, added conditions to RONH_HP and
RONH_HN, changed typ and max values for RONH_HN................................................................................................................ 9
•
Removed "side" from VOH_L and VOL_L description, changed high side and low side to pull up and pull down
respectively for RONH_L and RONL_L. Changed values for RONL_L from 10 typ to 7 typ and from 20 max to 14 max in
pre-driver electrical characteristics table. ............................................................................................................................... 9
•
Changed Turn-off time from Toff_h to Toff_I ............................................................................................................................... 9
•
Changed min value for Vinm from -2 to -1. ............................................................................................................................ 10
•
Added C1 = 4.7 pF to Tset_TR1, Tset_TR2, Tset_TF1, and Tset_TF2 conditions in motor current sense electrical characteristics... 10
•
Changed max current limit from 500 to 550. ........................................................................................................................ 12
•
Added typ and max values to VB monitor electrical characteristics table. ........................................................................... 12
•
Changed max IVB from 40 to 35 mA. .................................................................................................................................... 12
•
Changed ICANH to IA_CANH and ICANL to IA_CANL in CAN testing condition image..................................................... 14
2
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Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: DRV3202-Q1
Not Recommended for New Designs
DRV3202-Q1
www.ti.com
SLVSBJ4B – OCTOBER 2012 – REVISED JULY 2016
•
Changed CANTX to CAN_TX and CANH and CANL to CAN_H and CAN_L in CAN reset function image. ...................... 15
•
Changed CANH and CANL to CAN_H and CAN_L in description section; changed CANH, CANL, and CANM to
CAN_H, CAN_L, and CAN_M in block diagram................................................................................................................... 22
•
Changed charge pump description....................................................................................................................................... 22
•
Changed pre-driver description and updated block diagram................................................................................................ 23
•
Updated phase comparator description. .............................................................................................................................. 24
•
Changed motor current sense description and motor current sense block diagram............................................................ 25
•
Updated Sample and Hold Mode Block Diagram................................................................................................................. 25
•
Changed VCC Block Diagram................................................................................................................................................ 27
•
Changed VB Monitor description.......................................................................................................................................... 28
•
Changed thermal shutdown description. .............................................................................................................................. 29
•
Changed location of EN in Figure 34. .................................................................................................................................. 30
•
Changed MCU RESET column to RES column; changed values........................................................................................ 31
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Product Folder Links: DRV3202-Q1
3
Not Recommended for New Designs
DRV3202-Q1
SLVSBJ4B – OCTOBER 2012 – REVISED JULY 2016
www.ti.com
5 Pin Configuration and Functions
VCCB
VCFB
VBPD
UL
VL
WL
N/C
TEST1
GFB
TEST3
TEST2
UH
VH
WH
PDCPV
CPDR4
CPDR3
CPDR2
CPDR1
VBCP
PFP PACKAGE
80-PINS HTQFP
TOP VIEW
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
AOUT
1
60
VCCT
PHTM
2
59
VLVD
PH1M
3
58
N/C
PH2M
4
57
ALP
PH3M
5
56
ALM
PMV1
6
55
ALFB
PMV2
7
54
AREF
PMV3
8
53
ALV
GND
9
52
AMPG
PH1T
10
51
ADTH
PSC1
11
50
GND
AMPG
12
49
S_GND
PH2T
13
48
CAN_TX
PSC2
14
47
CAN_RX
PH3T
15
46
N/C
PSC3
16
45
CAN_L
PTV1
17
44
CAN_H
PTV2
18
43
CAN_M
PTV3
19
42
CAN_PW
GND
20
41
OVCR
DRV3202-Q1
FAULT
WDEN
PRN
RES
CTLUH
CTLUL
CTLVH
CTLVL
CTLWH
CTLWL
CTLEN
DGND
DIN
VDD
SCK
DOUT
CS
PSS3
PSS2
PSS1
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Pin Functions
PIN
MAX RATING
FUNCTION
NO.
NAME
TYPE
1
AOUT
O
–0.3–6 V
Test mode output
2
PHTM
I
–1–40 V
Phase comparator reference input
3
PH1M
I
–1–40 V
Phase comparator input
4
PH2M
I
–1–40 V
Phase comparator input
5
PH3M
I
–1–40 V
Phase comparator input
6
PMV1
O
–0.3–6 V
Phase comparator output
7
PMV2
O
–0.3–6 V
Phase comparator output
8
PMV3
O
–0.3–6 V
Phase comparator output
9, 20, 50
GND
I
–0.3–0.3 V
10
PH1T
I
–2–40 V
Phase amplifier input
11
PSC1
O
–0.3–6 V
Sample and hold filter output
12
AMPG
I
–0.3–0.3 V
13
PH2T
I
–2–40 V
Phase amplifier input
14
PSC2
O
–0.3–6 V
Sample and hold filter output
15
PH3T
I
–2–40 V
Phase amplifier input
16
PSC3
O
–0.3–6 V
Sample and hold filter output
17
PTV1
O
–0.3–6 V
Phase amplifier output
18
PTV2
O
–0.3–6 V
Phase amplifier output
19
PTV3
O
–0.3–6 V
Phase amplifier output
21
PSS1
I
–0.3–6 V
Sample and hold control signal input
22
PSS2
I
–0.3–6 V
Sample and hold control signal input
23
PSS3
I
–0.3–6 V
Sample and hold control signal input
4
GND
Quiet GND
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Product Folder Links: DRV3202-Q1
Not Recommended for New Designs
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SLVSBJ4B – OCTOBER 2012 – REVISED JULY 2016
Pin Functions (continued)
PIN
TYPE
MAX RATING
FUNCTION
NO.
NAME
24
CS
I
–0.3–6 V
SPI chip select
25
DOUT
O
–0.3–6 V
SPI data output
26
SCK
I
–0.3–6 V
SPI clock
27
VDD
O
–0.3–3.6 V
28
DIN
I
–0.3–6 V
29
DGND
I
–0.3–0.3 V
30
CTLEN
I
–0.3–6 V
Pre-driver parallel enable input
31
CTLWL
I
–0.3–6 V
Pre-driver parallel input
32
CTLWH
I
–0.3–6 V
Pre-driver parallel input
33
CTLVL
I
–0.3–6 V
Pre-driver parallel input
34
CTLVH
I
–0.3–6 V
Pre-driver parallel input
35
CTLUL
I
–0.3–6 V
Pre-driver parallel input
36
CTLUH
I
–0.3–6 V
Pre-driver parallel input
37
RES
O
–0.3–6 V
Reset output
38
PRN
I
–0.3–6 V
Pulse input
39
WDEN
I
–0.3–6 V
Reset generator enable input
40
FAULT
O
–0.3–6 V
Diagnosis output
41
OVCR
I
–0.3–6 V
Over current reset input
42
CAN_PW
I
–0.3–6 V
CAN supply input
43
CAN_M
O
–27–40 V
CAN transceiver middle point terminal
44
CAN_H
IO
–27–40 V
CAN transceiver positive terminal
45
CAN_L
IO
–27–40 V
CAN transceiver negative terminal
46, 58, 67
N/C
—
—
47
CAN_RX
O
–0.3–6 V
CAN digital output
48
CAN_TX
I
–0.3–6 V
CAN digital input
49
S_GND
I
–0.3–0.3 V
51
ADTH
I
–0.3–6 V
52
AMPG
I
–0.3–0.3 V
53
ALV
O
–0.3–6 V
Motor current sense amp output
54
AREF
O
–0.3–40 V
Motor current sense reference output
55
ALFB
O
–0.3–40 V
Motor current sense amp feedback
56
ALM
I
–0.3–40 V
Motor current sense amp negative input
57
ALP
I
–0.3–40 V
Motor current sense amp positive input
59
VLVD
I
–0.3–6 V
VCC undervoltage threshold input
60
VCCT
I
–0.3–6 V
VCC supply input
61
VCCB
O
–0.3–40 V
VCC regulator base drive for PNP external transistor
62
VCFB
I
–0.3–40 V
VCC regulator current sense input
63
VBPD
I
–0.3–40 V
VB input
64
UL
O
-0.3–20 V
Pre-driver output
65
VL
O
-0.3–20 V
Pre-driver output
66
WL
O
-0.3–20 V
Pre-driver output
68
TEST1
I
–0.3–6 V
Test input
69
GFB
I
–0.3–0.3 V
Power GND
70
TEST3
I
-0.3–20 V
Test input
71
TEST2
I
–0.3–6 V
Test input
72
UH
O
–0.3–40 V
Pre-driver output
Digital supply output
SPI data input
Digital GND
Not connected
CAN GND
Motor overcurrent threshold input
Quiet GND
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SLVSBJ4B – OCTOBER 2012 – REVISED JULY 2016
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Pin Functions (continued)
PIN
MAX RATING
TYPE
FUNCTION
NO.
NAME
73
VH
O
–0.3–40 V
Pre-driver output
74
WH
O
–0.3–40 V
Pre-driver output
75
PDCPV
O
–0.3–40 V
Charge pump output
76
CPDR4
O
–0.3–40 V
Charge pump output
77
CPDR3
O
–0.3–40 V
Charge pump output
78
CPDR2
O
–0.3–40 V
Charge pump output
79
CPDR1
O
–0.3–40 V
Charge pump output
80
VBCP
I
–0.3–4 0V
VB input
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
TA
Operating temperature range
-40
125
degree
TJ
Junction temperature
-40
150
degree
Ts
Storage temperature
–55
150
degree
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge (1)
Human-body model (HBM)
±2000
Charged-device model (CDM)
±500
UNIT
V
ESD testing is performed according to the ACE-Q100 standard.
6.3 Thermal Information
DRV3202-Q1
THERMAL METRIC (1)
PFP (HTQFP )
UNIT
80 PINS
θJA
Junction-to-ambient thermal resistance
23.0
°C/W
θJCtop
Junction-to-case (top) thermal resistance
7.5
°C/W
θJB
Junction-to-board thermal resistance
7.6
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
7.4
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance
0.3
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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Not Recommended for New Designs
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SLVSBJ4B – OCTOBER 2012 – REVISED JULY 2016
6.4 Electrical Characteristics
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WATCHDOG
VSTN
Function start VCC voltage RES
–
0.8
1.3
V
tON
Power-on time RES
32
40
48
ms
tOFF
Clock off reset time RES
64
80
96
ms
tRL
Reset pulse low time RES
16
20
24
ms
tRH
Reset pulse high time RES
64
80
96
ms
tRES
Reset delay time RES
30
71.5
90
µs
Pwth
Pulse width PRN
200
–
–
ns
Fop
Operating frequency
DC
–
4
MHz
Tlead
Enable lead time
100
–
–
ns
Twait
Wait time between two successive
communications
5
–
–
µs
Tlag
Enable lag time
100
–
–
ns
Tpw
SCLK pulse width
100
–
–
ns
Tsu
Data setup time
80
–
–
ns
Th
Data hold time
80
–
–
ns
Tdis
Disable time
–
–
80
ns
Tdel
Data delay time (SCK to DOUT)
–
–
80
ns
2
2.5
3
V
2
2.5
3
V
–500
0
50
mV
2.25
2.5
2.75
V
2.25
2.5
2.75
V
2.75
3.5
4.5
V
0.5
1.5
2.25
V
CAN_TX = 0 V, RL = 60 Ω between
CAN_H and CAN_L
1.5
2
3
V
Refer to Figure 1
SPI
Refer to Figure 2
CL = 50 pF, Refer to Figure 2
CAN (TRANSMITTER SECTION)
VCAN_H
VCAN_L
Bus voltage recessive
CAN_TX = VCC, ICANH = ICANL = 0,
see Figure 3
VDIFF =
(VCAN_H
–
VCAN_L)
Differential output voltage
VCAN_H
Bus voltage recessive 2
VCAN_L
Bus voltage recessive 2
VCANH_D
Dominant state CAN_H output
voltage
VCANL_D
Dominant state CAN_L output
voltage
VDIFF =
(VCANH_ Differential output voltage
D–
VCANL_D)
CAN_TX = VCCRL = 60 Ω between
CAN_H and CAN_L, see Figure 3
and Figure 4
CAN_TX = 0 V, RL = 60 Ω between
CAN_H and CAN_L, see Figure 3
IA_CANH
CAN_H short circuit threshold
current
CAN_TX = 0 V
70
–
160
mA
IA_CANL
CAN_L short circuit threshold
current
CAN_TX = 0 V
70
–
160
mA
tOVCAN
Overcurrent to output switch-off
delay
Refer to Figure 6
200
TRESCAN
Self recovery time
Refer to Figure 6
8
ns
25
50
µs
CAN (RECEIVER SECTION)
VDOM
Differential input voltage for
dominant state
(VDIFF = VCAN_H – VCAN_L)
VCAN_L = –12 V to 12 V, CAN_TX
= VCC
VREC
Differential input voltage for
recessive state
(VDIFF = VCAN_H – VCAN_L)
VCAN_L = –12 V to 12 V, CAN_TX
= VCC
Vhys
Differential input hysteresis
900
80
mV
150
500
mV
–
mV
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SLVSBJ4B – OCTOBER 2012 – REVISED JULY 2016
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Electrical Characteristics (continued)
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
Vcom =
(VCAN_H
Input common mode voltage range
- VCAN_L)
/2
MIN
TYP
MAX
UNIT
–12
–
12
V
RIN
Input resistance CAN_H, CAN_L
CAN_TX = VCC
5
–
50
kΩ
RDIFF
Differential input resistance
CAN_TX = VCC
10
–
100
kΩ
CIN (1)
Input capacitance to ground CAN_H,
CAN_TX = VCC
CAN_L
–
20
46
pF
CDIFF (1)
Differential input capacitance to
ground
CAN_TX = VCC
–
10
–
pF
CIN (1)
Input capacitance between CAN_H
and CAN_L
CAN_TX = VCC
–
-
46
pF
Refer to Figure 3
–
–
100
ns
CAN (AC CHARACTERISTIC)
Delay time from CAN_TX to VDIFF
= VCAN_H - VCAN_L
tTDhHS
tTDlHS
Refer to Figure 3
–
–
100
ns
tDRHS
Delay time from VDIFF = VCAN_H VCAN_L to CAN_RX
Refer to Figure 3
–
–
150
ns
tTRlHS
Delay time from CAN_TX to
CAN_RX
Refer to Figure 3
–
–
300
ns
Refer to Figure 3
–
tTRhHS
–
300
ns
SRHS_R
Slew rate, CAN_H, rise
Threshold set to 20%–80%
20
85
ns
SRHS_F
Slew rate, CAN_H, fall
Threshold set to 80%–20%
20
85
ns
SRLS_R
Slew rate, CAN_L, rise
Threshold set to 20%–80%
20
85
ns
SRLS_F
Slew rate, CAN_L, fall
Threshold set to 80%–20%
20
85
ns
0.3
0.5
0.7
VCC
0.45
0.5
0.55
VCC
10
–
100
kΩ
CAN (SPLIT, OPTIONAL)
VCAN_M_l Output voltage
Isource, Isink = 500 µA
VCAN_M_
u
Rmeasure > 1 MΩ
Output voltage, unloaded condition
CAN (POWER OFF CONDITION)
RIN
(1)
8
Input resistance CAN_H, CAN_L
VB = 0 V
Specified by design
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Not Recommended for New Designs
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SLVSBJ4B – OCTOBER 2012 – REVISED JULY 2016
Electrical Characteristics (continued)
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
CHARGE PUMP
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
Vchv1_0
VB = 5.3 V, Iload = 0 mA, C1 = C2 =
47 nF, CCP = 2.2 µF
VB + 7
VB + 8
VB + 9
V
Vchv1_1
VB = 5.3 V, Iload = 5 mA, C1 = C2 =
47 nF, CCP = 2.2 µF
VB + 6
VB + 7
VB + 8
V
Vchv1_2
VB = 5.3 V, Iload = 8 mA, C1 = C2 =
47 nF, CCP = 2.2 µF
VB + 5
VB + 6
VB + 7
V
Vchv2_0
VB = 12 V, Iload = 0 mA, C1 = C2 =
47 nF,
CCP = 2.2 µF
VB + 13
VB + 14
VB + 15
V
VB = 12 V, Iload = 11 mA, C1 = C2 =
47 nF, CCP = 2.2 µF
VB + 13
VB + 14
VB + 15
V
Vchv2_2
VB = 12 V, Iload = 18 mA, C1 = C2 =
47 nF, CCP = 2.2 µF
VB + 12.5
VB + 13.5
VB + 15
V
Vchv3_0
VB = 18 V, Iload = 0 mA, C1 = C2 =
47 nF,
CCP = 2.2 µF
VB + 13
VB + 14
VB + 15
V
Vchv3_1
VB = 18 V, Iload = 13 mA, C1 = C2 =
47 nF, CCP = 2.2 µF
VB + 13
VB + 14
VB + 15
V
Vchv3_2
VB = 18 V, Iload = 22 mA, C1 = C2 =
47 nF, CCP = 2.2 µF
VB + 13
VB + 14
VB + 15
V
Vchv2_1
Output voltage
Vchvmax
Maximum voltage
VchvUV
Undervoltage detection threshold
Tchv (1)
Rise time
Ron
On resistance S1~S4
35
37.5
40
V
VB + 4
VB + 4.5
VB + 5
V
1
2
VB = 5.3 V, C1 = C2 = 47 nF, CCP
= 2.2 µF, VchvUV released
8
ms
Ω
HIGH SIDE PRE-DRIVER
VOH_H
Output voltage high
Isink = 10 mA, U(V/W)H – GFB
VOL_H
Output voltage low
Isource = 10 mA, U(V/W)H – GFB
RONH_HP
ON resistance pull up (Pch)
U(V/W)H = PDCPV - 1 V
RONH_HN
ON resistance pull up (Nch)
U(V/W)H = PDCPV - 2.5 V
RONL_H
ON resistance pull down
Vchv – 2.7 Vchv – 1.35
V
60
120
mV
135
270
Ω
8
16
Ω
6
12
Ω
Turn-on time
VB = 5.3 ~ 18 V, CL = 11 nF, RL = 0
Ω from 20% to 80%
100
300
500
ns
Toff_h (1)
Turn-off time
VB = 5.3 ~ 18 V, CL = 11 nF, RL = 0
Ω from 80% to 20%
100
300
500
ns
Th-ondly (1)
Output delay time
VB = 5.3 ~ 18 V, CL = 11 nF, RL = 0
Ω to 20%,
see Figure 7
100
200
400
ns
Th-offdly (1)
Output delay time
VB = 5.3 ~ 18 V, CL = 11 nF, RL = 0
Ω to 80%,
see Figure 7
100
200
400
ns
VB – 0.14
VB-0.07
70
140
mV
7
14
Ω
7
14
Ω
Ton_h
(1)
LOW SIDE PRE-DRIVER
VOH_L
Output voltage high
Isink = 10 mA, U(V/W)L – GFB
VOL_L
Output voltage low
Isource = 10 mA, U(V/W)L – GFB
RONH_L
ON resistance pull up
RONL_L
ON resistance pull down
Ton_l
(1)
Toff_I (1)
V
Turn-on time
VB = 5.3 ~ 18 V, CL = 22 nF, RL = 0
Ω from 20% to 80%
100
300
800
ns
Turn-off time
VB = 5.3 ~ 18 V, CL = 22 nF, RL = 0
Ω from 80% to 20%
100
300
800
ns
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Electrical Characteristics (continued)
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Tl-ondly (1)
Output delay time
VB = 5.3 ~ 18 V, CL = 22 nF, RL = 0
Ω to 20%,
see Figure 7
100
200
400
ns
Tl-offdly (1)
Output delay time
VB = 5.3 ~ 18 V, CL = 22 nF, RL = 0
Ω to 80%,
see Figure 7
100
200
400
ns
VCLAMP
VGS protection voltage
16
18
20
V
(1)
Tdiff2 (1)
Tdiff1
Differential time 1
VB = 5.3 ~ 18 V (Th-on)–(Tl-off), see
Figure 7
–300
300
ns
Differential time 2
VB = 5.3 ~ 18 V (Tl-on)–(Th-off), see
Figure 7
–300
300
ns
PHASE COMPARATOR
Viofs
Input offset voltage
–15
–
15
mV
Vinp
Input voltage range (PHTM)
Vinm
Input voltage range (PHxM)
1.325
–
4.5
V
–1
–
VB
Vihys
Input hysteresis voltage
V
100
200
400
mV
VOH
Output high voltage
Isink = 2.5 mA
VOL
Output low voltage
Isource = 2.5 mA
0.9 × VCC
–
–
–
–
0.1 × VCC
Tres_tr (1)
Response time (rising)
V
CL = 100 pF
–
0.2
0.5
µs
Tres_tf (1)
Response time (falling)
CL = 100 pF
–
0.4
1
µs
5
mV
VB = 5.3 ~18 V
V
MOTOR CURRENT SENSE (2)
VOfs
Input offset voltage
–5
Output voltage (ALV)
VB = 5.3 ~ 18 V,
Imotor = 0 A
VLine
Linearity (ALV)
VB = 5.3 ~ 18 V,
Rshunt = 1 mΩ,
R11 = R12 = 1 kΩ, R21 = R22 = 30
kΩ
VGain
Gain
VO_0
Tset_TR1
Tset_TR2
Tset_TF1
Tset_TF2
(2)
10
1
–2%
30
10
V
2%
mV/A
30
Settling time (Rise) ALV ±1%
VB = 5.3 ~ 18 V,
Rshunt = 1 mΩ, C1 = 4.7 pF, CL =
100 pF,
R11 = R12 = 1 kΩ, R21 = R22 = 30
kΩ,
Imotor = 0 → 30 A, (ALV : 1→1.9 V)
–
1
2.5
µs
Settling time (Rise) ALV ±1%
VB = 5.3 ~ 18 V,
Rshunt = 1 mΩ, C1 = 4.7 pF, CL =
100 pF,
R11 = R12 = 1 kΩ, R21 = R22 = 30
kΩ,
Imotor = 0 → 100 A, (ALV : 1 → 4 V)
–
1
2.5
µs
Settling time (Fall) ALV ±1%
VB = 5.3 ~ 18 V,
Rshunt = 1 mΩ, C1 = 4.7 pF, CL =
100 pF,
R11 = R12 = 1 kΩ, R21 = R22 = 30
kΩ,
Imotor = 30 → 0 A, (ALV : 1.9 → 1 V)
–
1
2.5
µs
Settling time (Fall) ALV ±1%
VB = 5.3 ~ 18 V,
Rshunt = 1 mΩ, C1 = 4.7 pF, CL =
100 pF,
R11 = R12 = 1 kΩ, R21 = R22 = 30
kΩ,
Imotor = 100 → 0 A, (ALV : 4 → 1 V)
–
1
2.5
µs
Motor current is converted to voltage in test
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Electrical Characteristics (continued)
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
OVAD
Overcurrent threshold
TDEL_OV
AD (1)
Propagation delay (Rise or fall)
TEST CONDITIONS
150-A detection,
Rshunt = 1 mΩ,
R11 = R12 = 1 kΩ, R21 = R22 = 30
kΩ,
R3 = 8.2 kΩ, R4 = 10 kΩ
MIN
TYP
MAX
UNIT
–10%
150
10%
A
–
–
1.5
µs
50
mV
50
mV
PHASE AMPLIFIER
Vofs_SH
Output offset voltage, sample and
hold mode
VB = 5.3–18 V, Gain = 1
–50
–
Vofs_TH
Output offset voltage, through mode
VB = 5.3–18 V, Gain = 1
–50
–
Vin_cm
Common mode input range
VB = 5.3–18 V, Gain = 1–4
1.5
Vout_max
Maximum output voltage
VB = 5.3–18 V, Gain = 1–4
4.5
Vout_min
Minimum output voltage
VB = 5.3–18 V, Gain = 1–4
–
VB – 1.5
V
–
–
V
–
0.5
V
–
1
2
3
4
–
Vgain (3)
Gain
Vout_SH0
Output voltage, sample and hold
mode
VB = 5.3–18 V, Gain = 1–4, PHxT =
VB / 2
–
2.5
–
V
Vout_TH0
Output voltage, through mode
VB = 5.3–18 V, Gain = 1–4 PHxT =
VB / 2
–
2.5
–
V
Vout_SH1
Output voltage, sample and hold
mode
VB = 12 V, Gain = 1, PHxT = 1.5 V
–
1.375
–
V
Vout_TH1
Output voltage, through mode
VB = 12 V, Gain = 1, PHxT = 1.5 V
–
1.375
–
V
Vout_SH2
Output voltage, sample and hold
mode
VB = 12 V, Gain = 1, PHxT = 10.5 V
–
3.625
–
V
Vout_TH2
Output voltage, through mode
VB = 12 V, Gain = 1, PHxT = 10.5 V
–
3.625
–
V
Settling time (rise), sample and hold
mode PTVx ±1%
VB = 12 V, Gain = 1, PSC = 470 pF,
PTVx = 100 pF, PHxT = 1.5 V ≥
10.5 V,
(PTVx = 1.375 V → 3.625 V), see
Figure 12
1.5
3
µs
Settling time (rise), through mode
PTVx ±1%
VB = 12 V, Gain = 1, PTVx = 100
pF,
PHxT = 1.5 V ≥ 10.5 V,
(PTVx = 1.375 V → 3.625 V), see
Figure 13
1.5
3
µs
Settling time (fall), sample and hold
mode PTVx ±1%
VB = 12 V, Gain = 1, PSC = 470 pF,
PTVx = 100 pF, PHxT = 10.5 V ≥
1.5 V,
(PTVx = 3.625 V → 1.375 V), see
Figure 12
1.5
3
µs
Settling time (fall), through mode
STL_THTF
PTVx ±1%
VB = 12 V, Gain = 1, PTVx = 100
pF,
PHxT = 10.5 V ≥ 1.5V,
(PTVx = 3.625 V → 1.375 V), see
Figure 13
1.5
3
µs
SH Error
Voltage
Falling voltage
VB = 5.3–18 V, PSC = 470 pF, TH =
1 mS, see Figure 11
5
75
mV
VCC
Output voltage
VB = 5.3–18 V, Iload = 5–150 mA
5
5.1
V
IBVCC
Base current
1.5
hfePNP
DC current gain of external VCC
100
STL_SHT
R
STL_THT
R
STL_SHT
F
VCC
(3)
4.9
mA
Vgain is an SPI setting
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Electrical Characteristics (continued)
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
VLRVCC
Load regulation
CVCC
Load capacitance
VB = 5.3–18 V, Iload = 5–150 mA
RVCC
ESR of external capacitance
VCCUV
Undervoltage detection threshold
MIN
TYP
–50
–
MAX
50
22
R1 = 7.5 kΩ, R2 = 10 kΩ,
VCCUV > 4 V
3.97
4.07
VCCUVHY Undervoltage detection threshold
S
hysteresis
Overvoltage detection threshold
ICLVCC
Current limit
Rsns = 0.51 Ω
TVCC1
Rise time
VCC > UVVCC, CVCC = 22 µF
TVCC2
Rise time
VCC > UVVCC, CVCC = 100 µF
VDD
Output voltage
VB = 5.3–18 V, Iload = 0–2 mA
CVDD
Load capacitance
VDDUV
VDDOV
mV
100
µF
300
mΩ
4.17
V
100
VCCOV
UNIT
mV
6
6.5
7
300
400
550
mA
V
0.3
0.5
ms
1
1.5
ms
3
3.3
3.6
V
Undervoltage detection threshold
2.2
2.3
2.4
V
Overvoltage detection threshold
4.1
4.3
4.5
V
75
150
µs
26.5
27.5
28.5
V
155
175
195
°C
9
10
11
MHz
VDD
Tvdd
(1)
1
Rise time
VDD > VDDUV, CVDD = 1 µF
µF
VB MONITOR
Vstop
Pre-driver stop VB voltage
THERMAL SHUT DOWN
TSD (1)
Thermal shut down threshold
OSCILLATOR
OSC
OSC frequency
INPUT BUFFER 1
VIH
Input threshold logic high
VIL
Input threshold logic low
0.7 × VCC
Ru
Input pullup resistance
50
Ru
(CAN_TX)
Input pullup resistance
Rd
Input pulldown resistance
V
0.3 × VCC
V
100
150
kΩ
12.5
25
37.5
kΩ
50
100
150
kΩ
OUTPUT BUFFER 1 AND 2
VOH
Output level logic high
Isink = 2.5 mA
VOL
Output level logic low
Isource = 2.5 mA
0.9 × VCC
V
0.1 × VCC
V
4.5
kΩ
0.1 × VCC
V
OUTPUT BUFFER 3
R_RES
Pullup resistor
VOL
Output level logic low
1.5
3
Isource = 2 mA
6.5 Supply Voltage and Current
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5.3
12
18
V
20
35
mA
SUPPLY INPUT
VB
VB Supply voltage
IVB
VB Operating current
12
VB = 5.3 ~18 V, CAN_TX = High, No PWM
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VB
Do not switch to RES LOW
when the VCC LOW time
is less than tRES.
VNMI+VHS
VNMI
VCC
tRES
VSTN
tRES
Ignore transient voltage falling
NMI
(Internal signal)
Switch to NMI-LOW after tRES delay
when VCC is lower than VNMIL
tRES
RES is HIGH after tON from NMI-HIGH
if internal clock is not generated
(In case of malfunction).
RES signal should remain in low voltage
(< -0.4 V) and in this case, controlled CPU
should be in
RES is HIGH after tON from of NMI-HIGH.
tRH
RES
tRL
RES is LOW at NMI-LOW.
tON
tON
RES is LOW at NMI-LOW.
Pwth
tOFF
PRN
Detecting only rising edge of PRN signal
Switch to RES LOW if PRN stays at a High or LOW
level.
If WDEN is LOW (or OPEN),
and there is abnormal PRN:
RES is active.
If WDEN is HIGH,
and there is abnormal PRN:
no operation.
WDEN
NOTE: WDEN = High, VCC undervoltage condition sets RES = Low
Figure 1. Watchdog Timing Chart
Tlead
Tpw
Tlag
Tpw
Twait
CS
SCK
MSB
DIN
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
Th
Tsu
MSB
DOUT Hi-Z
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
Hi-Z
Tdel
Ten
Tdis
Figure 2. SPI AC Timing Definition
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CAN_TX
0.5 VCC
0.5 VCC
VCANH_D
CAN_H
2.5 V
CAN_L
VCANL_D
VDIFF =
VCAN_H ± VCAN_L
0.9 V
0.5 V
0V
tTDHS
CAN_RX
tTDHS
0.5 VCC
0.5 VCC
tDRHS
tDRHS
tTRHS
tTRHS
Figure 3. CAN Timing Chart
IA_CANH
CAN_H
30 Ÿ
CAN_M
RL
30 Ÿ
10 nF
CAN_L
IA_CANL
Test circuit for measurement of AC characteristics and slew rate.
NOTE: If CAN_L is shorted to GND, try to keep transmission (no overcurrent event).
Figure 4. CAN Testing Condition
14
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VCC
CAN_TX
0V
RES
Signal
3.5 V
CAN_H
CAN_L
1.5 V
Figure 5. CAN Reset Function
CAN_TX
IA
Current of CAN_H, CAN_L
tOVCAN
TRESCAN
CAN_H_CAN_L
The CANOC in CANFLAG is set high if overcurrent condition exists.
Figure 6. Overcurrent Event
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CTLUH
CTLVH
CTLWH
CTLUL
CTLVL
CTLWL
Th-ondly
Th-offdly
80%
UH
VH
WH
80%
20%
20%
Th-on(Th-ondly + Ton)
Th-off(Th-offdly + Toff)
80%
UL
VL
WL
GFB
80%
20%
GFB
20%
TI-ondly
TI-offdly
TI-off(TI-offdly + Toff)
TI-on(TI-ondly + Ton)
Figure 7. Delay Time from Input to Output
Motor
Overcurrent
OVAD
OVCR
PreDRV
Enable
Disable
Enable
Figure 8. Motor Overcurrent Event
16
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ALV
ALFB / 2
VCC
ADTH
VLine
= ûY / ûX
ûY
ûX
VO_0
0A
Imotor
OVAD
0A
Imotor
*ALFB up to VB
Figure 9. Motor Current Sense and Overcurrent
PHxT
PSSx
Sampling Time
PTVx
Figure 10. Sampling Timing Chart
TH
PSSx
PTVx
SH Error Voltage
Figure 11. Holding Timing Chart
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PHxT
50%
PSSx
50%
PTVx
STL_SHTRx_XXX
STL_SHTFx_XXX
Figure 12. Settling Time Timing Chart (Sample and Hold Mode)
PHxT
PTVx
STL_THTRx_XXX
STL_THTFx_XXX
Figure 13. Settling Time Timing Chart (Through Mode)
18
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7 Detailed Description
1
2
VCFB
VCCB
66
VBPD
67
VL
68
UL
GFB
69
WL
70
NC
71
TEST1
72
TEST3
UH
73
TEST2
VH
CPDR4
74
65
64
63
62
61
TEST I/F
GFB
GFB
PDCPV
VB
58
5
PMV1 6
VB
56
UHS
51
PTV1
PSS1
EEPROM
49
PSS2
Control Logic
CAN_PW
AMP
PSC3
UH
VH
AMPG
VCCT
16
PTV3
PSS3
VHS
S_GND
47
CAN_RX
46
NC
PSS3
M
UHS
UL
44 CAN_H
S_GND
PTV2 18
PSS1
WHS
VL
45 CAN_L
CAN
PTV1 17
PSS2
WH
ADTH
PTV2
14
GND
VMS
48 CAN_TX
13
PSC2
15
Battery
50
AMP
PTV3 19
VM
ALM
GND
OSC
VB
Monitor
TSD
12
PH3T
NC
ALP
53 ALV
52
AMPG
WHS
VB
(VBCP,
VBPD)
AREF
AMP
10
VM
54
COMP
Through Mode or
Sample and Hold Mode
VB
11
PH2T
VMS
VLVD
55
PSC1
VHS
VCCT
VCCT
ALFB
PMV3 8
9
57
AMP
PMV2 7
PH1T
VCCB
59
3
4
PH3M
GND
VCFB
60
5V
Reg
ADTH
WHS
PH2M
75
76
COMP
VHS
COMP
UHS
PH1M
77
Charge
Pump
PHTM
VCOM
CPDR3
CPDR2
78
COMP
AOUT
79
VB
PDCPV
WH
80
CPDR1
VBCP
VB
7.1 Functional Block Diagram
43 CAN_M
42 CAN_PW
3.3 V
Reg
20
WL
CAN_H
CAN_M
41 OVCR
33
34
35
36
37
38
39
40
CTLUH
RES
PRN
WDEN
FAULT
SCK
32
CTLUL
DOUT
31
CTLVH
CS
30
CTLVL
PSS3
29
CTLWH
PSS2
28
27
CTLWL
26
DGND
25
CTLEN
24
DIN
23
VDD
22
PSS1
CAN_L
21
7.2 Feature Description
7.2.1 Watchdog
The watchdog monitors the PRN signal and VCC supply level and generates a reset to the MCU through the RES
pin if the status of the PRN is not normal or the VCC is lower than the specified threshold level. The watchdog
can be disabled if WDEN is set high.
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Feature Description (continued)
Vbgr = 2.325 V
(+0.75 V / ± 0.25 V)
VDD Undervoltage
Detection
Band Gap VHS = 0.1 V
Regulator (+0.75 V / ± 0.05 V)
VCC
R1
VCC
VCC Low
Voltage Detection
(NMI)
R_RES
Reset Logic
3k
VLVD
RES
R2
100 pF
Option
Clock
Monitor
Watch Dog Timer
WDEN
WDEN
Open: Enable
High: Disable
PRN
From CPU
Disable During
Power On Reset
Power On Reset
VNMI: Lower Threshold Voltage
VHS: Hysteresis Voltage
Figure 14. Watchdog Block Diagram
7.2.2 Serial Port I/F
The SPI is used to receive an input byte from CPU and to transmit an output byte to CPU. Four signals are
utilized according to the timing chart of Figure 15.
LSB
CS
CK
MSB
Register
Parallel Output
Parallel Input
/16
DIN
MSB First
Parallel Output
Serial input
Shift Register
(16 bits)
SCK
Serial Output
CK
DOUT
MSB First
Parallel Input
/16
Parallel Output
EN
LSB
Parallel Input
Output Latch
(Transparent if EN = High)
Internal
Diagnosis Register
MSB
Figure 15. Block Diagram of SPI
20
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Feature Description (continued)
•
•
•
•
CS – Chip Select
– This input signal is utilized to select this IC by CPU.
– This input signal is normally high and the communication is possible only when it is forced low.
– When this input signal falls, the communication between this IC and the CPU starts.
– Transmitted data is latched and the DOUT pin comes out of high impedance.
– When this input signal rises, the communication stops.
– The DOUT pin goes into high impedance. Then, the internal input register updates with the received bits
(only if the clock pulse numbers are right and the key bit of the DIN signals is correct).
– The next falling edge starts another communication.
– There is a minimum waiting time between two communications (Twait).
– The pin has an internal pullup.
SCK – Synchronization Serial Clock
– This input signal is utilized to synchronize the communication by CPU.
– It is normally high and the correct clock pulse number is 16.
– At each falling edge, the CPU writes a new bit on the DIN input and this IC writes a new bit on the DOUT
pin. At each rising edge, this IC reads the new bit on the DIN pin and the CPU reads the new bit on the
DOUT pin.
– The maximum clock frequency is 4 MHz.
– The pin has an internal pullup.
DIN – Serial Input Data
– This input signal is used to receive 16-bit data.
– The bits are received in order from the MSB (first) to the LSB (last).
– The pin has an internal pullup.
DOUT – Serial Output Data
– This output signal is used to transmit 16-bit data.
– It is a 3-state output and it is in high impedance mode when CS is high.
– The serial data bits are transmitted in order from the MSB (first) to the LSB (last).
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Feature Description (continued)
7.2.3 CAN
The CAN data from CAN control logic is transmitted to other systems through the CAN bus. The receiver
compares the CAN_H–CAN_L voltage levels against an internally generated reference and the result is output
through CAN_TX. It has overcurrent protection, shown in Figure 6.
CAN_PW
VCCT
R = 0~5 , C = 10 µF
(Optional)
CANH_OC
CAN_RX
CANL_OC
CAN_H
CAN_OC
FAULT_OC
CAN_L
TX_Drive
S_GND
RES
CAN_TX
Split Control
CAN SPLIT
CAN_M
Figure 16. CAN Block Diagram
7.2.4 Charge Pump
The charge pump block generates the supply for high-side and low-side pre-drivers to maintain the gate voltage
on the external FETs. External storage cap (CCP) and bucket caps (C1, C2) are used to support pre-driver slope
and switching frequency requirements. R1 and R2 can reduce switching current if required. The charge pump
has a voltage supervisor for over and undervoltage, and a selectable stop condition for pre-drivers.
22
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Feature Description (continued)
VB
PDCPV
CP
Supervisor
CP Logic
CP14
CPCLK
MAX
S2
VF
UV
CPDR2
C2
CPDR1
S1
GFB
PDCPV
S4
VF
CCP
VF
CPDR4
C1
CPDR3
S3
GFB
Figure 17. Charge Pump Block Diagram
7.2.5 Pre-Driver
The pre-driver block provides three high-side pre-drivers and three low-side pre-drivers to drive external Nchannel MOSFETs. The turn on side of the high-side pre-drivers supply the large N-channel transistor current to
quickly charge and PMOS support output voltage up to PDCPV. The turn off side supplies the large N-channel
transistor current to quickly discharge, while the low-side pre-drivers supply the large N-channel transistor current
for charge and discharge. The output voltage of the low-side pre-driver is controlled by VB and it has VGS
protection to make less than 18 V. The pre-driver has a stop condition in some fault conditions ($16 Error
Detection).
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Feature Description (continued)
Figure 18. Pre-Driver Block Diagram
7.2.6 Phase Comparator
A 3-channel comparator module monitors the external FET by detecting voltage across the drain-source for highside and low-side FETs. PHTM is the threshold level of comparators usable for sensorless communication.
Figure 19 shows an example of the threshold level. There is no detection when CTLEN = Low.
UHS,
VHS,
WHS
CTLEN
VCOM
VCC
PHxM
+
Clamp
PHTM
PMVx
-
Clamp
Figure 19. Phase Comparator Block Diagram
24
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Feature Description (continued)
7.2.7 Motor Current Sense
The operational amplifier is operating with an external resistor network for higher flexibility to adjust the current
measurement to application requirements. The first stage amplifier is operating with the external resistor and the
output voltage up to VB at ALFB. The gain of the amplifier is adjustable by external resistors from x10 to x30.
The second stage amplifier is a buffer to MCU at ALV. Current sense has a comparator for motor overcurrent
(OVAD). ADTH is the overcurrent threshold level and sets the value by the external resistor as well. Figure 9
shows the curve of the detection level. ALFB is divided by 2, compare this value with ADTH. In the
recommended application, zero-point adjustment is required as a large error offset in the initial condition.
OVAD
+
VCC
-
R3
ADTH
½ ALFB
CLAMP
R4
VCC
CLAMP
+
ALV
-
VB
-
ALFB
+
R22
C1
Battery
R11
ALP
ALM
*R11, R12, R21, R22 # 0.1%
*VGain
X10: R11 = R12 = 3 k , R21 = R22 = 30 k
1V
X20: R11 = R12 = 1.5 k , R21 = R22 = 30 k
X30: R11 = R12 = 1 k , R21 = R22 = 30 k
C2 = 10 n ~ 20 nF
C1 = 0 ~ 10 pF
*ALV = VGain x (Rshunt x lmotor) + AREF
*ADTH = {R4 / (R3 + R4)} x VCC
*OVAD = (2 x ADTH ± AREF) / (Rshunt x VGain)
+
R12
R21
VCC
Imotor
Rshunt
M
AREF
-
C2
CLAMP
Figure 20. Motor Current Sense Block Diagram
7.2.8 Phase Amplifier (Sample and Hold Mode and Through Mode)
The 3-channel amplifier module monitors the drain-source for high-side and low-side FETs. Two modes (selected
by the SPI) are provided: sample and hold mode, and through mode. Sample and hold is controlled by PSSx at
the external pins and PSCx connects the charging capacitor. Through mode is real-time detection and the
amplifier has x1–x4 gain control.
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Feature Description (continued)
SH_MODE
High: Sample and Hold Mode
Low: Through Mode
VB
R2
CLAMP
open
VCC
VCC
R1
-
7:1
+
+
PH1T
PH2T
PH3T
VCC
-
-
+
CAL_MODE
PTV1
PTV2 PTVx = ¼ x (R2 / R1) x (PHxT-½ x VB) + 2.5 V
PTV3
Sample
and
Hold
PSC
CLAMP
VCC
-
R1
PSC1
PSC2
PSC3
+
3:1
R2
CAL_MODE
VCC
-
PSS1
PSS2
PSS3
+
2.5 V
Figure 21. Sample and Hold Mode Block Diagram
SHORT_MODE
High: Sample and Hold Mode
Low: Through Mode
VB
R2
CLAMP
Short
VCC
7:1
VCC
R1
PH1T
PH2T
PH3T
SHORT_MODE
CLAMP
VCC
Open
PTVx = ¼*(R2 / R1)*(PHxT ± ½*VB) + 2.5 V
Disable
PTV1
PTV2
PTV3
VCC
R1
PSC1
PSC2
PSC3
3:1
R2
SHORT_MODE
VCC
PSS1
PSS2
PSS3
2.5 V
Figure 22. Through Mode Block Diagram
26
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Feature Description (continued)
SH_MODE
High: Sample and Hold Mode
Low: Through Mode
VB
R2
CLAMP
Open/Short
VCC
Short/Open
2.5 V
7:1
VCC
VCC
R1
PTVX = 2.5 V
PTV1
PTV2
PTV3
SHORT_MODE
PH1T
PH2T
PH3T
PSC
CLAMP
VCC
R1
2.5 V
3:1
PSC1
PSC2
PSC3
SHORT_MODE
R2
VCC
PSS1
PSS2
PSS3
2.5 V
Figure 23. Short Mode (Optional) Block Diagram
7.2.9 Regulators
The regulator block offers a 5-V LDO and a 3.3-V LDO. The VCC LDO regulates VB down to 5 V with an external
PNP controlled by the regulator block. The 5-V LDO is supplied to the MCU and other components. The 5-V LDO
is protected against a short to GND fault, and the external resistors R1 and R2 set the undervoltage. The VDD
regulator regulates VB down to 3.3-V with an internal FET and a controller.
The regulators detect the overvoltage and undervoltage events of both supplies.
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Feature Description (continued)
VB
Current
Limit
OC
Rsns
VCF
B
BG
+
AMP
VCC
B
-
PNP Tr
CVCC
Trim
VCCT(VCC)
AMPG
VLVD
Supervisor
R1
Supervisor
R2
OV
UV
* Rsns = 0.2 V / ICLVCC
* VCCUV = 2.325 x {(R1+R2) / R2}
Figure 24. VCC Block Diagram
VB
BG
+
AMP
-
VDD
CVDD
AMPG
OV
UV
Supervisor
Figure 25. VDD Block Diagram
7.2.10 VB Monitor
The block monitors VB overvoltage.
28
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Feature Description (continued)
VB
+
VB_OV
BG
-
Figure 26. VB Monitor Block Diagram
7.2.11 Thermal Shutdown
The device has temperature sensors that produce a pre-driver stop condition if the chip temperature exceeds
175°.
IPTAT
TSD
Figure 27. Thermal Shutdown Block Diagram
7.2.12 Oscillator
Oscillator block generates two 10-MHZ clock signals. OSC1 is the main clock used for internal logic
synchronization and timing control. OSC2 is the secondary clock which is used to monitor the status of OSC1.
OSC1(OSC2)
VREF
Figure 28. Oscillator Block Diagram
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Feature Description (continued)
7.2.13 I/O
VCC
VDD
VCC
VCC
VDD
VDD
PSS1 CTLEN
PSS2 CTLUH
PSS3 CTLUL
PRN CTLVH
WDEN CTLVL
TEST1 CTLWH
TEST2 CTLWL
VDD
OVCR
CAN_TX
DIN
SCK
CS
Level Shift
Rd
Ru
Level Shift
Figure 29. Input Buffer 1 Block Diagram
VDD
VCC
VCC
FAULT
CAN_RX
Level Shift
Figure 30. Output Buffer 1 Block Diagram
VDD
VCC
VCC
Level Shift
DOUT
EN
Figure 31. Output Buffer 2 Block Diagram
VCC
VDD
VCC
R_RES
VCC
RES
Level Shift
Figure 32. Output Buffer 3 Block Diagram
7.2.14 Error Detection
Table 1. Error Detection
ITEMS
30
SPI
PRE-DRIVER
FAULT SIGNAL
RES
VB – Overvoltage
–
STOP
L
H
CP – Overvoltage
–
STOP
L
H
CP – Undervoltage
Error Bit (CPLV)
–
L
H
VCC – Overvoltage
Error Bit (VCO)
–
L
H
VCC – Undervoltage
–
STOP
L
L
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Table 1. Error Detection (continued)
ITEMS
VCC – Overcurrent
Motor – Overcurrent
SPI
PRE-DRIVER
FAULT SIGNAL
RES
Error Bit (VCC)
–
H
H
Error Bit (OVAD)
STOP
H
H
VDD – Overvoltage
Error Bit (VDO)
–
L
H
VDD – Undervoltage
–
STOP
L
L
Thermal Shut Down
Error Bit (TD)
STOP
H
H
–
–
L
L
Error Bit (EEP)
–
L
H
Watchdog
EEPROM Data Check
Clock Monitor
–
–
L
L
CAN Overcurrent
Error Bit (CCD)
–
L
H
SPI
Error Bit (SPI)
–
L
H
7.3 Device Functional Modes
Table 2. Motor Overcurrent Truth Table
RES
OVCR
MOTOR OVERCURRENT
OVAD
PRE-DRIVER ENABLE OR DISABLE
0
–
–
0 (Clear)
Disable (1)
1
(1)
(2) (3)
0
–
0 (Clear)
1
0
Keep
Enable
Enable
1
1 (Set)
Disable
The CTLEN goes to Hi-Z because the external CPU will not drive it when RES = 0, then all the pre-drivers are turned off because
CTLEN is internally pulled down.
The OVAD is not set, even if a motor overcurrent error is generated during OVCR = 0.
The OVAD is cleared if OVCR = 0 even when the motor overcurrent error is generated.
(2)
(3)
7.4 Register Maps
Waiting Time From b9 Through b8
CS
DIN
b15~b10
b7~b0
b9~b8
Select Diagnosis or Command Register
From b15 Through b10
Command Input or Diagnosis Result Output From b7 Through b0
DOUT
b7~b0
Echo Back of b14~b9
Figure 33. SPI Bit Sequence
Table 3. SPI Bit Map (DIN)
ITEM
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
COMMAND1
0
0
0
0
0
1
–
–
SHM
SRT
–
–
–
–
–
–
COMMAND2
0
0
0
0
1
0
–
–
AG1
AG0
–
–
–
–
–
–
COMMAND3
0
0
0
0
1
1
–
–
–
–
–
–
–
–
–
–
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Register Maps (continued)
Table 3. SPI Bit Map (DIN) (continued)
ITEM
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
DIAG_READ1
0
0
1
0
0
0
–
–
–
–
–
–
–
–
–
–
DIAG_READ2
0
1
0
0
0
0
–
–
–
–
–
–
–
–
–
–
DIAG_READ3
0
1
1
0
0
0
–
–
–
–
–
–
–
–
–
–
In Table 3, the B15–B10 are the control bits, so the each command depends on them (listed below).
1. B15-B10 = 0 0 0 0 0 1
These are the commands:
1) Phase AMP Sampling Hold Mode (B7 bit)
MM0: OFF (through) (INITIAL VALUE)
MM1: ON (use sample hold mode)
2) Phase AMP Short Mode [Short_Mode] (B6 bit)
MM0: OFF (no calibration) (INITIAL VALUE)
MM1: ON (use calibration mode)
2. B15-B10 = 0 0 0 0 1 0
These are the commands:
1) Phase AMP Gain (B7 bit and B6 bit)
MMB7:0 B6:0; Gain x1 (INITIAL VALUE)
MMB7:0 B6:1; Gain x2
MMB7:1 B6:0; Gain x3
MMB7:1 B6:1; Gain x4
3. B15-B10 = 0 0 0 0 1 1
Not used
4. B15-B10 = 0 0 1 0 0 0
This command is to read the diagnosis of the current regulator,
SPI communication, overvoltage detection, and input diagnosis.
5. B15-B10 = 0 1 0 0 0 0
This command is to read the diagnosis of SPI communication.
6. B15-B10 = 0 1 1 0 0 0
Not used
7. B15-B10 = Other command
This command sets the SPI-NG (DOUT, B7) bit.
Table 4. SPI Bit Map (DOUT)
ITEM
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
–
–
–
–
–
–
–
–
0
0
0
0
0
1
1
0
–
–
–
–
–
–
–
–
DIAG_READ1
0
0
0
1
0
0
0
0
VCC
OCD
CCD
VCO
VDO
CPLV
TD
EEP
DIAG_READ2
0
0
1
0
0
0
0
0
SPI
–
–
–
–
–
–
–
DIAG_READ3
0
0
1
1
0
0
0
0
–
–
–
–
–
–
–
–
ON/OFF COMMAND
ECHO BACK
1. B14-B9 = 0 0 1 0 0 0
This flag is cleared after the register is read by the CPU.
1) VCC Current Detection (B7)
MM0: NORMAL
MM1: Fail (Short to GND or open)
2) Overcurrent Detection (B6)
MM0: NORMAL
MM1: Fail (Overcurrent)
3) CAN Current Detection (B5)
MM0: NORMAL
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MM1: Fail (Overcurrent)
4) VCC Overvoltage Detection (B4)
MM0: NORMAL
MM1: Fail (VCC overvoltage)
5) VDD Overvoltage Detection (B3)
MM0: NORMAL
MM1: Fail (VDD overvoltage)
6) CPV Low Voltage Detection (B2)
MM0: NORMAL
MM1: Fail (CPV low voltage)
7) Thermal Detection (B1)
MM0: NORMAL
MM1: Fail (Overtemperature)
8) EEPROM* Data Consistency Check (B0)
MM0: NORMAL
MM1: Fail (EEPROM DATA CRC error)
*ASIC calibration EEPROM
NOTE
Just after power-on of the IC, some of the bits listed above may be set depending on the
apply sequence of VB. It is recommended to issue a DIAG_READ1 to clear these bits
prior to all S/W sequences.
2. B14-B9 = 0 1 0 0 0 0
This flag is cleared after the register is read by the CPU.
1) SPI-NG (B7)
MM0: NORMAL
MM1: Fail (SPI read and write command is wrong)
Diag happen!
Twait > 5 µs
CS
CLK
MSB
~
bit10 bit9 bit8 bit7
~
bit0
MSB
~
bit10 bit9 bit8
bit7
~
bit0
DOUT Command Data for Diagnosis
DOUT Command Data for Diagnosis
DIN
New Diagnosis Data
During bit7 ~ bit0
Internal Diagnosis
Shadow Register
Internal Diagnosis
Status Register
DOUT
Diagnosis Data Against DIN Command
DIN ECHO
Diagnosis
New Diagnosis Data
Hi-Z
'RQ¶W FDUH
DIN ECHO
Hi-Z
New
'RQ¶W FDUH
Figure 34. DIAG_READ
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7.4.1 Internal Diagnosis Register (Status Register and Shadow Register)
If the diagnosis happens during the SPI communication, the function follows this protocol:
The diagnosis information is stored in the shadow register when the diagnosis happens.
After the output of the previous information a new diagnosis is sent from the shadow to the status register,
and both registers are output through the DOUT pin.
In this case, a FAULT signal continues to be output until a new diagnosis is read by the CPU.
All diagnosis bits read by the DIAG_READ1 command happen before the CS falling edge. So, all the diagnosis
events that happen right after the CS falling edge are not read by the current DIAG_READ1 command, instead
they are read by the next DIAG_READ1 command.
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8 Device and Documentation Support
8.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
8.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
8.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Jun-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
DRV3202QPFPQ1
NRND
Package Type Package Pins Package
Drawing
Qty
HTQFP
PFP
80
96
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
DRV3202
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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Addendum-Page 1
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PACKAGE OPTION ADDENDUM
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27-Jun-2016
Addendum-Page 2
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