TI1 LMV831MGE Operational amplifier Datasheet

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LMV831, LMV832, LMV834
SNOSAZ6C – AUGUST 2008 – REVISED NOVEMBER 2015
LMV831 Single / LMV832 Dual / LMV834 Quad 3.3-MHz Low-Power CMOS, EMI-Hardened
Operational Amplifiers
1 Features
3 Description
•
TI’s LMV83x devices are CMOS input, low-power
operation amplifier ICs, providing a low input bias
current, a wide temperature range of −40°C to 125°C,
and exceptional performance, making them robust
general-purpose parts. Additionally, the LMV83x are
EMI-hardened to minimize any interference, making
them ideal for EMI-sensitive applications.
1
•
•
•
•
•
•
•
•
•
•
•
Unless Otherwise Noted, Typical Values at
TA= 25°C, V+ = 3.3 V
Supply Voltage 2.7 V to 5.5 V
Supply Current (per Channel) 240 µA
Input Offset Voltage 1-mV Maximum
Input Bias Current 0.1 pA
GBW 3.3 MHz
EMIRR at 1.8 GHz 120 dB
Input Noise Voltage at 1 kHz 12 nV/√Hz
Slew Rate 2 V/µs
Output Voltage Swing Rail-to-Rail
Output Current Drive 30 mA
Operating Ambient Temperature Range −40°C to
125°C
2 Applications
•
•
•
•
•
Photodiode Preamps
Piezoelectric Sensors
Portable/Battery-Powered Electronic Equipment
Filters and Buffers
PDAs and Phone Accessories
The unity gain stable LMV83x feature 3.3-MHz of
bandwidth while consuming only 0.24 mA of current
per channel. These parts also maintain stability for
capacitive loads as large as 200 pF. The LMV83x
provide superior performance and economy in terms
of power and space usage.
This family of parts has a maximum input offset
voltage of 1 mV, a rail-to-rail output stage and an
input common-mode voltage range that includes
ground. Over an operating range from 2.7 V to 5.5 V,
the LMV83x provide a PSRR of 93 dB, and a CMRR
of 91 dB. The LMV831 is offered in the space-saving
5-pin SC70 package, the LMV832 in the 8-pin
VSSOP and the LMV834 is offered in the 14--in
TSSOP package.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMV831
SC70 (5)
1.25 mm × 2.00 mm
LMV832
VSSOP (8)
3.00 mm × 3.00 mm
LMV834
TSSOP (14)
4.40 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
R1
V
+
NO RF RELATED
DISTURBANCES
-
PRESSURE
SENSOR
+
-
R2
+
ADC
+
EMI HARDENED
EMI HARDENED
INTERFERING
RF SOURCES
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV831, LMV832, LMV834
SNOSAZ6C – AUGUST 2008 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics, 3.3 V ............................... 5
Electrical Characteristics, 5 V .................................. 7
Typical Characteristics ............................................ 10
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 20
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application .................................................. 22
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2013) to Revision C
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision A (March 2013) to Revision B
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 23
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SNOSAZ6C – AUGUST 2008 – REVISED NOVEMBER 2015
5 Pin Configuration and Functions
DCK Package
5-Pin SC70
Top View
DGK Package
8-Pin VSSOP
Top View
PW Package
14-Pin TSSOP
Top View
Pin Functions
PIN
NAME
TYPE
DESCRIPTION
SC70
VSSOP
TSSOP
IN+
1
—
—
I
Noninverting Input
IN–
3
—
—
I
Inverting Input
+
IN A
—
3
3
I
Noninverting Input, Channel A
IN A–
—
2
2
I
Inverting Input, Channel A
IN B+
—
5
5
I
Noninverting Input, Channel B
–
IN B
—
6
6
I
Inverting Input, Channel B
IN C+
—
—
10
I
Noninverting Input, Channel C
IN C–
—
—
9
I
Inverting Input, Channel C
IN D+
—
—
12
I
Noninverting Input, Channel D
–
IN D
—
—
13
I
Inverting Input, Channel D
OUT A
—
1
1
O
Output, Channel A
OUT B
—
7
7
O
Output, Channel B
OUT C
—
—
8
O
Output, Channel C
OUT D
—
—
14
O
Output, Channel D
OUTPUT
4
—
—
O
Output
+
V
5
8
4
P
Positive (highest) Power Supply
V–
2
4
11
P
Negative (lowest) Power Supply
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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
See
MIN
VIN differential
MAX
−
+
Supply voltage (VS = V – V )
Junction temperature (3)
Soldering information
Infrared or Convection (20 sec)
−65
Storage temperature, Tstg
(2)
(3)
V
6
V− − 0.4
Voltage at input/output pins
(1)
UNIT
±Supply Voltage
V
V+ + 0.4
V
150
°C
260
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
6.2 ESD Ratings
VALUE
Electrostatic discharge (1)
V(ESD)
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101
±1000
Machine Model (MM)
±200
UNIT
V
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
6.3 Recommended Operating Conditions
Temperature range (1)
+
−
Supply voltage (VS = V – V )
(1)
MIN
MAX
UNIT
−40
125
°C
2.7
5.5
V
The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) – TA)/ θJA . All numbers apply for packages soldered directly onto a PCB.
6.4 Thermal Information
THERMAL METRIC (1)
(2)
LMV831
LMV832
LMV834
DCK (SC70)
DGK (VSSOP)
PW (TSSOP)
5 PINS
8 PINS
14 PINS
267.7
177.1
UNIT
RθJA
Junction-to-ambient thermal resistance
118.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
96.6
67.1
44.4
°C/W
RθJB
Junction-to-board thermal resistance
48.8
97.5
60.5
°C/W
ψJT
Junction-to-top characterization parameter
2.5
9.9
4.5
°C/W
ψJB
Junction-to-board characterization parameter
47.9
96.1
59.9
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
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6.5 Electrical Characteristics, 3.3 V
Unless otherwise specified, all limits are specified for at TA = 25°C, V+ = 3.3 V, V− = 0 V, VCM = V+/2, and RL = 10 kΩ to
V+/2. (1)
PARAMETER
VOS
Input offset voltage (4)
TCVOS
Input offset voltage
temperature drift (4) (5)
TEST CONDITIONS
TA = 25°C
±0.5
±1.7
TA = 25°C
0.1
Common-mode
rejection ratio (4)
0.2 V ≤ VCM ≤ V+ – 1.2 V
PSRR
Power supply
rejection ratio (4)
2.7 V ≤ V+ ≤ 5.5 V,
VOUT = 1 V
–40°C ≤ TA ≤ +125°C
(3)
(4)
(5)
(6)
(7)
μV/°C
10
500
TA = 25°C
76
–40°C ≤ TA ≤ +125°C
75
TA = 25°C
76
–40°C ≤ TA ≤ +125°C
75
VRF_PEAK = 100 mVP (−20 dBP),
f = 900 MHz
90
VRF_PEAK = 100 mVP (−20 dBP),
f = 1800 MHz
110
VRF_PEAK = 100 mVP (−20 dBP),
f = 2400 MHz
120
CMRR ≥ 65 dB
Large signal
voltage gain (7)
dB
93
80
pA
pA
91
VRF_PEAK = 100 mVP (−20 dBP),
f = 400 MHz
RL = 10 kΩ,
VOUT = 0.1 V to 1.65 V,
VOUT = 3.2 V to 1.65 V
(2)
mV
1
RL = 2 kΩ,
VOUT = 0.15 V to 1.65 V,
VOUT = 3.15 V to 1.65 V
(1)
UNIT
±1.23
LMV834
CMRR
AVOL
±1
±1.5
Input offset current
Input common-mode
voltage range
±0.25
±0.5
IOS
CMVR
MAX (2)
LMV831,
LMV832
Input bias current (5)
EMIRR
TYP (3)
–40°C ≤ TA ≤ +125°C
IB
EMI rejection ratio,
IN+ and IN– (6)
MIN (2)
dB
dB
−0.1
LMV831,
LMV832
102
LMV831,
LMV832,
–40°C ≤ TA ≤ +125°C
102
LMV834
102
LMV834
–40°C ≤ TA ≤ +125°C
102
LMV831,
LMV832
104
LMV831,
LMV832,
–40°C ≤ TA ≤ +125°C
104
LMV834
104
LMV834
–40°C ≤ TA ≤ +125°C
103
2.1
V
121
121
dB
126
123
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
The typical value is calculated by applying absolute value transform to the distribution, then taking the statistical average of the resulting
distribution.
This parameter is specified by design and/or characterization and is not tested in production.
The EMI Rejection Ratio is defined as EMIRR = 20log ( VRF_PEAK/ΔVOS).
The specified limits represent the lower of the measured values for each output range condition.
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LMV831 LMV832 LMV834
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Electrical Characteristics, 3.3 V (continued)
Unless otherwise specified, all limits are specified for at TA = 25°C, V+ = 3.3 V, V− = 0 V, VCM = V+/2, and RL = 10 kΩ to
V+/2.(1)
PARAMETER
MIN (2)
TEST CONDITIONS
LMV831,
LMV832
+
RL = 2 kΩ to V /2
TYP (3)
MAX (2)
29
36
LMV831,
LMV832,
–40°C ≤ TA ≤ +125°C
43
LMV834
31
LMV834
–40°C ≤ TA ≤ +125°C
Output voltage
swing high
RL = 10 kΩ to V+/2
6
LMV831,
LMV832,
–40°C ≤ TA ≤ +125°C
7
LMV834
–40°C ≤ TA ≤ +125°C
Output voltage
swing low
Output short circuit
current
IOUT
RL = 10 kΩ to V+/2
Sourcing, VOUT = VCM,
VIN = 100 mV
Sinking, VOUT = VCM,
VIN = −100 mV
TA = 25°C
25
–40°C ≤ TA ≤ +125°C
5
–40°C ≤ TA ≤ +125°C
27
LMV831,
LMV832,
–40°C ≤ TA ≤ +125°C
22
LMV834
24
LMV834
–40°C ≤ TA ≤ +125°C
19
TA = 25°C
27
–40°C ≤ TA ≤ +125°C
21
mA
28
32
0.27
0.3
0.46
LMV832,
–40°C ≤ TA ≤ +125°C
0.51
0.58
0.9
LMV834,
–40°C ≤ TA ≤ +125°C
GBW
8
28
0.24
LMV834
Slew rate (8)
34
10
LMV831,
LMV832
LMV832
SR
9
43
TA = 25°C
LMV831,
–40°C ≤ TA ≤ +125°C
Supply current
mV from
either rail
10
LMV831
IS
8
9
LMV834
R = 2 kΩ to V+/2
38
44
LMV831,
LMV832
VOUT
UNIT
mA
1
1.16
AV = +1, VOUT = 1 VPP,
10% to 90%
2
V/μs
Gain bandwidth
product
3.3
MHz
Φm
Phase margin
65
deg
en
Input referred
voltage noise
in
Input referred
current noise
f = 1 kHz
ROUT
Closed-loop
output impedance
f = 2 MHz
(8)
6
f = 1 kHz
12
f = 10 kHz
10
0.005
500
nV/√Hz
pA/√Hz
Ω
Number specified is the slower of positive and negative slew rates.
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Electrical Characteristics, 3.3 V (continued)
Unless otherwise specified, all limits are specified for at TA = 25°C, V+ = 3.3 V, V− = 0 V, VCM = V+/2, and RL = 10 kΩ to
V+/2.(1)
PARAMETER
CIN
THD+N
TEST CONDITIONS
MIN (2)
TYP (3)
Common-mode
input capacitance
15
Differential-mode
input capacitance
20
Total harmonic
distortion + noise
MAX (2)
UNIT
pF
f = 1 kHz, AV = 1, BW ≥ 500 kHz
0.02%
6.6 Electrical Characteristics, 5 V
Unless otherwise specified, all limits are specified for at TA = 25°C, V+ = 5 V, V− = 0 V, VCM = V+/2, and RL = 10 kΩ to V+/2.
PARAMETER
VOS
Input offset voltage (4)
TCVOS
Input offset voltage
temperature drift (4) (5)
TEST CONDITIONS
TA = 25°C
±0.25
LMV834
±0.5
±1.7
TA = 25°C
0.1
Input offset current
CMRR
Common-mode
rejection ratio (4)
0 V ≤ VCM ≤ V+ −1.2 V
PSRR
Power supply
rejection ratio (4)
2.7 V ≤ V+ ≤ 5.5 V,
VOUT = 1 V
(1)
(2)
(3)
(4)
(5)
(6)
Input common-mode
voltage range
±1
±1.5
–40°C ≤ TA ≤ +125°C
mV
μV/°C
10
500
1
TA = 25°C
77
–40°C ≤ TA ≤ +125°C
77
TA = 25°C
76
–40°C ≤ TA ≤ +125°C
75
VRF_PEAK = 100 mVP (−20 dBP),
f = 900 MHz
90
VRF_PEAK = 100 mVP (−20 dBP),
f = 1800 MHz
110
VRF_PEAK=100 mVP (−20 dBP),
f = 2400 MHz
120
CMRR ≥ 65 dB
dB
93
80
pA
pA
93
VRF_PEAK = 100 mVP (−20 dBP),
f = 400 MHz
(1)
UNIT
±1.23
±0.5
IOS
CMVR
MAX
(2)
LMV831,
LMV832
Input bias current (5)
EMIRR
TYP
(3)
–40°C ≤ TA ≤ +125°C
IB
EMI rejection ratio,
IN+ and IN– (6)
MIN
(2)
dB
dB
–0.1
3.8
V
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
The typical value is calculated by applying absolute value transform to the distribution, then taking the statistical average of the resulting
distribution.
This parameter is specified by design and/or characterization and is not tested in production.
The EMI Rejection Ratio is defined as EMIRR = 20log ( VRF_PEAK/ΔVOS).
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LMV831 LMV832 LMV834
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Electrical Characteristics, 5 V (continued)
Unless otherwise specified, all limits are specified for at TA = 25°C, V+ = 5 V, V− = 0 V, VCM = V+/2, and RL = 10 kΩ to V+/2.
PARAMETER
RL = 2 kΩ,
VOUT = 0.15 V to 2.5 V,
VOUT = 4.85 V to 2.5 V
AVOL
MIN (2)
TYP (3)
LMV831,
LMV832
107
127
LMV831,
LMV832,
–40°C ≤ TA ≤ +125°C
106
LMV834
104
LMV834,
–40°C ≤ TA ≤ +125°C
104
LMV831,
LMV832
107
LMV831,
LMV832,
–40°C ≤ TA ≤ +125°C
107
LMV834
105
LMV834,
–40°C ≤ TA ≤ +125°C
104
TEST CONDITIONS
Large signal voltage
gain (7)
RL = 10 kΩ,
VOUT = 0.1 V to 2.5 V,
VOUT = 4.9 V to 2.5 V
127
130
127
32
LMV831,
LMV832,
–40°C ≤ TA ≤ +125°C
35
LMV834,
–40°C ≤ TA ≤ +125°C
RL = 10 kΩ to V+/2
6
LMV831,
LMV832,
–40°C ≤ TA ≤ +125°C
7
LMV834,
–40°C ≤ TA ≤ +125°C
Output voltage
swing low
RL = 10 kΩ to V+/2
Sourcing VOUT = VCM
VIN = 100 mV
IOUT
Output short
circuit current
Sinking VOUT = VCM
VIN = −100 mV
(7)
8
9
10
LMV834
RL = 2 kΩ to V+/2
45
52
LMV831,
LMV832
VOUT
42
49
LMV834
Output voltage
swing high
UNIT
dB
LMV831,
LMV832
RL = 2 kΩ to V+/2
MAX (2)
(1)
mV from
either rail
10
11
TA = 25°C
27
–40°C ≤ TA ≤ +125°C
43
52
TA = 25°C
6
–40°C ≤ TA ≤ +125°C
10
12
LMV831,
LMV832
59
LMV831,
LMV832,
–40°C ≤ TA ≤ +125°C
49
LMV834
57
LMV834,
–40°C ≤ TA ≤ +125°C
45
LMV831,
LMV832
50
LMV831,
LMV832,
–40°C ≤ TA ≤ +125°C
41
LMV834
53
LMV834,
–40°C ≤ TA ≤ +125°C
41
66
63
mA
64
63
The specified limits represent the lower of the measured values for each output range condition.
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LMV831, LMV832, LMV834
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Electrical Characteristics, 5 V (continued)
Unless otherwise specified, all limits are specified for at TA = 25°C, V+ = 5 V, V− = 0 V, VCM = V+/2, and RL = 10 kΩ to V+/2.
PARAMETER
TEST CONDITIONS
LMV831
MIN (2)
TYP (3)
MAX (2)
0.25
0.27
LMV831,
–40°C ≤ TA ≤ +125°C
LMV832
IS
Supply current
LMV832,
–40°C ≤ TA ≤ +125°C
Slew rate (8)
0.92
GBW
AV = +1, VOUT = 2 VPP,
10% to 90%
0.52
mA
0.6
LMV834,
–40°C ≤ TA ≤ +125°C
SR
UNIT
0.31
0.47
LMV834
1.02
1.18
2
V/μs
Gain bandwidth
product
3.3
MHz
Φm
Phase margin
65
deg
en
Input referred
voltage noise
in
Input referred
current noise
f = 1 kHz
ROUT
Closed-loop
output impedance
f = 2 MHz
CIN
THD+N
(8)
f = 1 kHz
12
f = 10 kHz
10
0.005
nV/√Hz
pA/√Hz
500
Common-mode
input capacitance
14
Differential-mode
input capacitance
20
Total harmonic
distortion + noise
(1)
Ω
pF
f = 1 kHz, AV = 1, BW ≥ 500 kHz
0.02%
Number specified is the slower of positive and negative slew rates.
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6.7 Typical Characteristics
At TA = 25°C, RL = 10 kΩ, V+ = 3.3 V, V− = 0 V, Unless otherwise specified.
0.3
0.3
125°C
0.2
0.2
0.1
0.1
VOS (mV)
VOS (mV)
85°C
25°C
0
-40°C
-0.1
125°C
85°C
25°C
0
-40°C
-0.1
-0.2
-0.2
+
+
V = 3.3V
-0.3
-0.5 0.0 0.5
1.0
1.5
2.0
2.5
3.0
V = 5.0V
-0.3
-0.5
0.5
1.5
3.5
2.5
3.5
4.5
5.5
VCM (V)
VCM (V)
Figure 2. VOS vs VCM at V+ = 5 V
Figure 1. VOS vs VCM at V+ = 3.3 V
200
0.3
125°C
85°C
150
0.2
3.3V
100
25°C
0
5.0V
0
-50
-40°C
-0.1
50
VOS (µV)
VOS (mV)
0.1
-100
-0.2
-150
-200
-50
-0.3
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-25
0
75
5
+
V = 5.0V, RL = 2k
100
125
TA = 25°C
4
4
3
2
IB (pA)
2
VOS (µV)
50
Figure 4. VOS vs Temperature
Figure 3. VOS vs Supply Voltage
6
25
TEMPERATURE (°C)
VSUPPLY (V)
0
5V
1
0
-1
-2
-2
3.3V
-3
-4
-4
-6
0
1
2
3
VOUT (V)
4
5
-5
-1
0
1
2
3
4
5
6
VCM (V)
Figure 5. VOS vs VOUT
Figure 6. Input Bias Current vs VCM at 25°C
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Typical Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, V+ = 3.3 V, V− = 0 V, Unless otherwise specified.
50
500
TA = 85°C
40
30
300
20
200
10
5.0V
IBIAS (pA)
IBIAS (pA)
TA = 125°C
400
0
-10
3.3V
-20
100
0
-200
-30
-300
-40
-400
-50
-1
0
1
5.0V
-100
2
3
4
5
-500
-1
6
3.3V
0
1
2
5
6
Figure 7. Input Bias Current vs VCM at 85°C
Figure 8. Input Bias Current vs VCM at 125°C
0.4
0.4
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
4
VCM (V)
VCM (V)
85°C
125°C
0.3
0.2
25°C
-40°C
0.1
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.2
25°C
-40°C
0.1
2.5
6.0
85°C
125°C
0.3
3.0
SUPPLY VOLTAGE (V)
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
Figure 9. Supply Current vs Supply Voltage Single LMV831
Figure 10. Supply Current vs Supply Voltage Dual LMV832
1.4
0.4
125°C
85°C
1.2
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
3
1.0
0.8
25°C
-40°C
0.6
0.4
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0.3
5.0V
3.3V
0.2
0.1
-50
-25
SUPPLY VOLTAGE (V)
Figure 11. Supply Current vs Supply Voltage Quad LMV834
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 12. Supply Current vs Temperature Single LMV831
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Typical Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, V+ = 3.3 V, V− = 0 V, Unless otherwise specified.
1.4
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
0.7
0.6
5.0V
0.5
3.3V
0.4
0.3
-50
-25
0
25
50
75
100
1.2
5.0V
1.0
3.3V
0.8
0.6
0.4
-50
125
-25
TEMPERATURE (°C)
Figure 13. Supply Current vs Temperature Dual LMV832
100
90
90
80
80
ISINK (mA)
ISOURCE (mA)
25°C
-40°C
60
50
40
85°C
125°C
100
125
60
50
20
3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
10
6.0
125°C
85°C
40
20
10
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
Figure 15. Sinking Current vs Supply Voltage
Figure 16. Sourcing Current vs Supply Voltage
12
60
RL = 10k
VOUT FROM RAIL HIGH (mV)
RL = 2k
VOUT FROM RAIL HIGH (mV)
75
-40°C
30
3.0
50
25°C
70
30
2.5
25
Figure 14. Supply Current vs Temperature Quad LMV834
100
70
0
TEMPERATURE (°C)
50
125°C
85°C
40
30
25°C
20
10
125°C
85°C
8
6
4
25°C
2
-40°C
-40°C
10
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.5
3.0
RL = 2 kΩ
4.0
4.5
5.0
5.5
6.0
RL = 10 kΩ
Figure 17. Output Swing High vs Supply Voltage
12
3.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
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Figure 18. Output Swing High vs Supply Voltage
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Typical Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, V+ = 3.3 V, V− = 0 V, Unless otherwise specified.
60
12
RL = 10k
125°C
VOUT FROM RAIL LOW (mV)
VOUT FROM RAIL LOW (mV)
RL = 2k
50
85°C
40
30
25°C
20
125°C
10
85°C
8
6
25°C
4
-40°C
2
-40°C
10
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
6.0
2.5
3.0
3.5
SUPPLY VOLTAGE (V)
RL = 2 kΩ
5.0
5.5
6.0
Figure 20. Output Swing Low vs Supply Voltage
2.0
SINK
1.6
1.2
VOUT FROM RAIL (V)
0.4
+
-40°C
0
V = 3.3V
-0.4
-0.8
-1.2
-2.0
125°C
1.2
0.8
-1.6
SINK
1.6
125°C
0
10
15
20
25
30
35
-0.4
-2.0
40
125°C
SOURCE
0
10
20
ILOAD (mA)
50
40
-40°C
GAIN
30
25°C
85°C
125°C
10
CL = 5 pF
0
10k
100k
60
100
80
50
60
40
60
70
80
100
PHASE
20 pF 5 pF
80
100 pF
50 pF
GAIN
60
40
20
20
20
0
10
-40°C
-20
10M
1M
50
30
40
20
40
Figure 22. Output Voltage Swing vs Load Current at V+ = 5 V
GAIN (dB)
25°C, 85°C, 125°C
PHASE (°)
PHASE
30
ILOAD (mA)
Figure 21. Output Voltage Swing vs Load Current at V+ = 3.3
V
60
+
V = 5.0V
-40°C
-0.8
-1.6
SOURCE
SOURCE
5
0.4
-1.2
125°C
0
0.8
CL = 5 pF
20 pF
50 pF
100 pF
0
10k
FREQUENCY (Hz)
Figure 23. Open-Loop Frequency Response vs Temperature
5 pF
100 pF
100k
1M
PHASE (°)
2.0
VOUT FROM RAIL (V)
4.5
RL = 10 kΩ
Figure 19. Output Swing Low vs Supply Voltage
GAIN (dB)
4.0
SUPPLY VOLTAGE (V)
0
-20
10M
FREQUENCY (Hz)
Figure 24. Open-Loop Frequency Response vs Load
Conditions
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Typical Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, V+ = 3.3 V, V− = 0 V, Unless otherwise specified.
70
120
60
100
50
3.3V
40
PSRR (dB)
PHASE(°)
80
5.0V
30
5.0V
-PSRR
60
3.3V
5.0V
40
20
3.3V
20
10
0
1
10
100
+PSRR
0
100
1000
1k
10k
CLOAD (pF)
100k
1M
10M
FREQUENCY (Hz)
Figure 25. Phase Margin vs Capacitive Load
Figure 26. PSRR vs Frequency
100
160
CMRR (dB)
80
DC
CMRR
60
40
V+ = 3.3V, 5.0V
20
100
1k
10k
100k
1M
CHANNEL SEPARATION (dB)
AC CMRR
140
120
100
80
60
1k
10M
V+ = 3.3V, 5.0V
10k
FREQUENCY (Hz)
10M
Figure 28. Channel Separation vs Frequency
200 mV/DIV
100 mV/DIV
1M
FREQUENCY (Hz)
Figure 27. CMRR vs Frequency
f = 100 kHz
AV = +10
VIN = 100 mVPP
f = 100 kHz
AV = +1
VIN = 500 mVPP
1 µs/DIV
1 us/DIV
Figure 29. Large Signal Step Response With Gain = 1
14
100k
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Figure 30. Large Signal Step Response With Gain = 10
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Typical Characteristics (continued)
20 mV/DIV
20 mV/DIV
At TA = 25°C, RL = 10 kΩ, V+ = 3.3 V, V− = 0 V, Unless otherwise specified.
f = 100 kHz
f = 100 kHz
AV = +1
VIN = 100 mVPP
AV = +10
VIN = 10 mVPP
1 µs/DIV
1 µs/DIV
Figure 31. Small Signal Step Response With Gain = 1
Figure 32. Small Signal Step Response With Gain = 10
2.0
100
FALLING EDGE
NOISE (nV/ Hz)
SLEW RATE (V/µs)
1.9
1.8
RISING EDGE
1.7
10
1.6
AV = +1
+
CL = 5 pF
1.5
2.5
3.0
V = 3.3V, 5.0V
3.5
4.0
4.5
5.0
5.5
1
6.0
10
100
10
AV = 10x
BW = >500 kHz
10k
100k
Figure 34. Input Voltage Noise vs Frequency
Figure 33. Slew Rate vs Supply Voltage
0.1
1k
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
V+ = 5.0V
AV = 10x
+
+
V = 3.3V
V = 3.3V
VIN = 300 mVPP
THD + N (%)
THD + N (%)
1
0.01
VIN = 480 mVPP
VIN = 2.3 VPP
0.001
AV = 1x
VIN = 3.8 VPP
AV = 1x
0.1
0.01
+
V = 5.0V
0.0001
10
f = 1 kHz
BW = >500 kHz
100
1k
FREQUENCY (Hz)
Figure 35. THD+N vs Frequency
10k
0.001
1m
10m
100m
VOUT (VPP)
1
10
Figure 36. THD+N vs Amplitude
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Typical Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, V+ = 3.3 V, V− = 0 V, Unless otherwise specified.
1k
140
130
100
AV = 100x
120
EMIRRV_PEAK (dB)
ROUT (:)
110
10
1
AV = 10x
125°C
85°C
90
80
70
60
25°C
-40°C
50
AV = 1x
0.1
100
40
30
0.01
100
1k
10k
100k
1M
fRF = 400 MHz
20
-40
-30
-20
10M
Figure 37. ROUT vs Frequency
140
130
130
120
125°C
EMIRRV_PEAK (dB)
110
100
90
80
25°C
70
-40°C
60
90
80
60
50
40
30
30
0
25°C
-40°C
70
40
-10
85°C
100
50
fRF = 900 MHz
20
-40
-30
-20
fRF = 1800 MHz
20
-40
-30
-20
10
10
140
130
130
125°C
85°C
120
120
EMIRR V_PEAK (dB)
110
EMIRRV_PEAK (dB)
0
Figure 40. EMIRR IN+ vs Power at 1800 MHz
Figure 39. EMIRR IN+ vs Power at 900 MHz
140
100
90
25°C
-40°C
80
70
60
50
40
110
125°C
100
85°C
90
80
70
60
25°C
50
-40°C
40
fRF = 2400 MHz
-30
-20
-10
0
10
Figure 41. EMIRR IN+ vs Power at 2400 MHz
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+
V = 3.3V, 5.0V
VPEAK = -20 dBVp
30
20
10
100
1000
FREQUENCY (MHz)
RF INPUT PEAK VOLTAGE (dBVp)
16
-10
RF INPUT PEAK VOLTAGE (dBVp)
RF INPUT PEAK VOLTAGE (dBVp)
20
-40
10
125°C
110
85°C
EMIRRV_PEAK (dB)
120
0
Figure 38. EMIRR IN+ vs Power at 400 MHz
140
30
-10
RF INPUT PEAK VOLTAGE (dBVp)
FREQUENCY (Hz)
10000
Figure 42. EMIRR IN+ vs Frequency
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7 Detailed Description
7.1 Overview
The LMV831, LMV832, and LMV834 are operational amplifiers with excellent specifications, such as low offset,
low noise and a rail-to-rail output. The EMI hardening makes the LMV831, LMV832 or LMV834 a must for almost
all operational amplifier applications that are exposed to Radio Frequency (RF) signals such as the signals
transmitted by mobile phones or wireless computer peripherals. The LMV831, LMV832, and LMV834 will
effectively reduce disturbances caused by RF signals to a level that will be hardly noticeable. This again reduces
the need for additional filtering and shielding. Using this EMI resistant series of operational amplifiers will thus
reduce the number of components and space needed for applications that are affected by EMI, and will help
applications, not yet identified as possible EMI sensitive, to be more robust for EMI.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Input Characteristics
The input common-mode voltage range of the LMV831, LMV832, and LMV834 includes ground, and can even
sense well below ground. The CMRR level does not degrade for input levels up to 1.2 V below the supply
voltage. For a supply voltage of 5 V, the maximum voltage that should be applied to the input for best CMRR
performance is thus 3.8 V.
When not configured as unity gain, this input limitation will usually not degrade the effective signal range. The
output is rail-to-rail and therefore will introduce no limitations to the signal range.
The typical offset is only 0.25 mV, and the TCVOS is 0.5 μV/°C, specifications close to precision operational
amplifiers.
7.3.2 EMIRR
With the increase of RF transmitting devices in the world, the electromagnetic interference (EMI) between those
devices and other equipment becomes a bigger challenge. The LMV831, LMV832, and LMV834 are EMIhardened operational amplifiers which are specifically designed to overcome electromagnetic interference. Along
with EMI-hardened operational amplifiers, the EMIRR parameter is introduced to unambiguously specify the EMI
performance of an operational amplifier. This section presents an overview of EMIRR. A detailed description on
this specification for EMI-hardened operational amplifiers can be found in AN-1698 (SNOA497).
The dimensions of an operational amplifier IC are relatively small compared to the wavelength of the disturbing
RF signals. As a result the operational amplifier itself will hardly receive any disturbances. The RF signals
interfering with the operational amplifier are dominantly received by the PCB and wiring connected to the
operational amplifier. As a result the RF signals on the pins of the operational amplifier can be represented by
voltages and currents. This representation significantly simplifies the unambiguous measurement and
specification of the EMI performance of an operational amplifier.
RF signals interfere with operational amplifiers through the non-linearity of the operational amplifier circuitry. This
non-linearity results in the detection of the so called out-of-band signals. The obtained effect is that the amplitude
modulation of the out-of-band signal is downconverted into the base band. This base band can easily overlap
with the band of the operational amplifier circuit. As an example Figure 43 depicts a typical output signal of a
unity-gain connected operational amplifier in the presence of an interfering RF signal. Clearly the output voltage
varies in the rhythm of the on-off keying of the RF carrier.
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Feature Description (continued)
RF
RF SIGNAL
VOUT OPAMP
(AV = 1)
NO RF
VOS + VDETECTED
VOS
Figure 43. Offset Voltage Variation Due to an Interfering RF Signal
7.3.3 EMIRR Definition
To identify EMI-hardened operational amplifiers, a parameter is needed that quantitatively describes the EMI
performance of operational amplifiers. A quantitative measure enables the comparison and the ranking of
operational amplifiers on their EMI robustness. Therefore the EMI Rejection Ratio (EMIRR) is introduced. This
parameter describes the resulting input-referred offset voltage shift of an operational amplifier as a result of an
applied RF carrier (interference) with a certain frequency and level. The definition of EMIRR is given by
Equation 1:
§ VRF_PEAK·
¸
EMIRRV RF_PEAK = 20 log ¨
¨ 'VOS ¸
©
¹
In which
•
•
VRF_PEAK is the amplitude of the applied un-modulated RF signal (V)
ΔVOS is the resulting input-referred offset voltage shift (V)
(1)
The offset voltage depends quadratically on the applied RF level, and therefore, the RF level at which the EMIRR
is determined should be specified. The standard level for the RF signal is 100 mVP. AN-1698 (SNOA497)
addresses the conversion of an EMIRR measured for an other signal level than 100 mVP. The interpretation of
the EMIRR parameter is straightforward. When two operational amplifiers have an EMIRR which differ by 20 dB,
the resulting error signals when used in identical configurations, differ by 20 dB as well. So, the higher the
EMIRR, the more robust the operational amplifier.
7.3.3.1 Coupling an RF Signal to the IN+ Pin
Each of the operational amplifier pins can be tested separately on EMIRR. In this section, the measurements on
the IN+ pin (which, based on symmetry considerations, also apply to the IN– pin) are discussed. In AN-1698
(SNOA497) the other pins of the operational amplifier are treated as well. For testing the IN+ pin the operational
amplifier is connected in the unity gain configuration. Applying the RF signal is straightforward as it can be
connected directly to the IN+ pin. As a result the RF signal path has a minimum of components that might affect
the RF signal level at the pin. The circuit diagram is shown in Figure 44. The PCB trace from RFIN to the IN+ pin
should be a 50-Ω stripline in order to match the RF impedance of the cabling and the RF generator. On the PCB
a 50-Ω termination is used. This 50-Ω resistor is also used to set the bias level of the IN+ pin to ground level. For
determining the EMIRR, two measurements are needed: one is measuring the DC output level when the RF
signal is off; and the other is measuring the DC output level when the RF signal is switched on. The difference of
the two DC levels is the output voltage shift as a result of the RF signal. As the operational amplifier is in the
unity-gain configuration, the input referred offset voltage shift corresponds one-to-one to the measured output
voltage shift.
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Feature Description (continued)
C2
10 µF
+
VDD
C3
100 pF
RFin
+
R1
50:
Out
C4
100 pF
C1
22 pF
+
VSS
C5
10 µF
Figure 44. Circuit for Coupling the RF Signal to IN+
7.3.3.2 Cell Phone Call
The effect of electromagnetic interference is demonstrated in a set-up where a cell phone interferes with a
pressure sensor application. The application is shown in Figure 49.
This application needs two operational amplifiers and therefore a dual operational amplifier is used. The
operational amplifier configured as a buffer and connected at the negative output of the pressure sensor prevents
the loading of the bridge by resistor R2. The buffer also prevents the resistors of the sensor from affecting the
gain of the following gain stage. The operational amplifiers are placed in a single-supply configuration.
The experiment is performed on two different dual operational amplifiers: a typical standard operational amplifier
and the LMV832, EMI-hardened dual operational amplifier. A cell phone is placed on a fixed position a couple of
centimeters from the operational amplifiers in the sensor circuit.
VOUT (0.5V/DIV)
When the cell phone is called, the PCB and wiring connected to the operational amplifiers receive the RF signal.
Subsequently, the operational amplifiers detect the RF voltages and currents that end up at their pins. The
resulting effect on the output of the second operational amplifier is shown in Figure 45.
Typical Opamp
LMV832
TIME (0.5s/DIV)
Figure 45. Comparing EMI Robustness
The difference between the two types of dual operational amplifiers is clearly visible. The typical standard dual
operational amplifier has an output shift (disturbed signal) larger than 1 V as a result of the RF signal transmitted
by the cell phone. The LMV832, EMI-hardened operational amplifier does not show any significant disturbances.
This means that the RF signal will not disturb the signal entering the ADC when using the LMV832.
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7.4 Device Functional Modes
7.4.1 Output Characteristics
As already mentioned the output is rail-to-rail. When loading the output with a 10-kΩ resistor the maximum swing
of the output is typically 6 mV from the positive and negative rail.
The output of the LMV83x can drive currents up to 30 mA at 3.3 V and even up to 65 mA at 5 V.
The LMV83x can be connected as noninverting unity-gain amplifiers. This configuration is the most sensitive to
capacitive loading. The combination of a capacitive load placed at the output of an amplifier along with the output
impedance of the amplifier creates a phase lag, which reduces the phase margin of the amplifier. If the phase
margin is significantly reduced, the response will be under damped which causes peaking in the transfer and,
when there is too much peaking, the operational amplifier might start oscillating. The LMV83x can directly drive
capacitive loads up to 200 pF without any stability issues. In order to drive heavier capacitive loads, an isolation
resistor, RISO, should be used, as shown in Figure 46. By using this isolation resistor, the capacitive load is
isolated from the output of the amplifier, and hence, the pole caused by CL is no longer in the feedback loop. The
larger the value of RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback
loop will be stable, independent of the value of CL. However, larger values of RISO result in reduced output swing
and reduced output current drive.
RISO
VIN
VOUT
+
CL
Figure 46. Isolating Capacitive Load
A resistor value of around 150 Ω would be sufficient. As an example some values are given in Table 1, for 5 V.
Table 1. Resistor Values
CLOAD
RISO
300 pF
165 Ω
400 pF
175 Ω
500 pF
185 Ω
7.4.2 CMRR Measurement
The CMRR measurement results may need some clarification. This is because different set-ups are used to
measure the AC CMRR and the DC CMRR.
The DC CMRR is derived from ΔVOS versus ΔVCM. This value is stated in the tables, and is tested during
production testing. The AC CMRR is measured with the test circuit shown in Figure 47.
R2
1 k:
V+
R1
1 k:
-
VIN
LMV83x
+
R11
1 k:
R12 V995:
V+ BUFFER
Buffer
+
VOUT
V- BUFFER
P1
10:
Figure 47. AC CMRR Measurement Set-Up
20
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The configuration is largely the usually applied balanced configuration. With potentiometer P1, the balance can
be tuned to compensate for the DC offset in the DUT. The main difference is the addition of the buffer. This
buffer prevents the open-loop output impedance of the DUT from affecting the balance of the feedback network.
Now the closed-loop output impedance of the buffer is a part of the balance. As the closed-loop output
impedance is much lower, and by careful selection of the buffer also has a larger bandwidth, the total effect is
that the CMRR of the DUT can be measured much more accurately. The differences are apparent in the larger
measured bandwidth of the AC CMRR.
One artifact from this test circuit is that the low frequency CMRR results appear higher than expected. This is
because in the AC CMRR test circuit the potentiometer is used to compensate for the DC mismatches. So,
mainly AC mismatch is all that remains. Therefore, the obtained DC CMRR from this AC CMRR test circuit tends
to be higher than the actual DC CMRR based on DC measurements.
The CMRR curve in Figure 48 shows a combination of the AC CMRR and the DC CMRR.
100
AC CMRR
CMRR (dB)
80
DC
CMRR
60
40
V+ = 3.3V, 5.0V
20
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 48. CMRR Curve
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMV83x family of amplifiers is specified for operation from 2.7 V to 5.5 V (±1.35 V to ±2.25 V). Parameters
that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical
Characteristics.
8.2 Typical Application
V+
5 NŸ
R1
2.4 k
R2
100
5 NŸ
V+
+
5 NŸ
+
ADC
VOUT
RX
Figure 49. Pressure Sensor Application
8.2.1 Design Requirements
The LMV83x can be used for pressure sensor applications. Because of their low power the LMV83x are ideal for
portable applications, such as blood pressure measurement devices, or portable barometers. This example
describes a universal pressure sensor that can be used as a starting point for different types of sensors and
applications.
The pressure sensor used in this example functions as a Wheatstone bridge. The value of the resistors in the
bridge change when pressure is applied to the sensor. This change of the resistor values will result in a
differential output voltage, depending on the sensitivity of the sensor and the applied pressure.
8.2.2 Detailed Design Procedure
The difference between the output at full-scale pressure and the output at zero pressure is defined as the span of
the pressure sensor. A typical value for the span is 100 mV. A typical value for the resistors in the bridge is 5 kΩ.
Loading of the resistor bridge could result in incorrect output voltages of the sensor. Therefore the selection of
the circuit configuration, which connects to the sensor, should take into account a minimum loading of the
sensor.
The configuration shown in Figure 49 is simple, and is very useful for the read out of pressure sensors. With two
operational amplifiers in this application, the dual LMV832 fits very well. The operational amplifier configured as a
buffer and connected at the negative output of the pressure sensor prevents the loading of the bridge by resistor
R2. The buffer also prevents the resistors of the sensor from affecting the gain of the following gain stage. Given
the differential output voltage VS of the pressure sensor, the output signal of this operational amplifier
configuration, VOUT, equals Equation 2:
22
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Typical Application (continued)
VOUT =
VDD
2
-
VS §
R1·
¨1+ 2× ¸¸
2 ¨©
R2¹
(2)
To align the pressure range with the full range of an ADC, the power supply voltage and the span of the pressure
sensor are needed. For this example a power supply of 5 V is used and the span of the sensor is 100 mV. When
a 100-Ω resistor is used for R2, and a 2.4-kΩ resistor is used for R1, the maximum voltage at the output is 4.95
V and the minimum voltage is 0.05 V. This signal is covering almost the full input range of the ADC. Further
processing can take place in the microprocessor following the ADC.
8.2.3 Application Curve
Figure 50 shows the resulting output voltage as RX is varied between 4.5 kΩ and 5.5 kΩ.
5.0
4.5
4.0
Output Voltage (V)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4500
4600
4700
4800
4900
5000
5100
5200
5300
5400
5500
Rx Resistance (Ohms)
C001
Figure 50. Output Voltage vs RX
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9 Power Supply Recommendations
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI
recommends that 10-nF capacitors be placed as close as possible to the operational amplifier power supply pins.
For single-supply, place a capacitor between V+ and V− supply leads. For dual supplies, place one capacitor
between V+ and ground, and one capacitor between V– and ground.
CAUTION
Supply voltages larger than 6 V can permanently damage the device.
The internal RFI filters shunt the received EMI energy to the supply pins. To maximize the effectiveness of the
built-in EMI filters, the power supply pin bypassing should have a low impedance, low inductance path to RF
ground.
The normally suggested 0.1-µF and larger capacitors tend to be inductive over the effective frequency range of
the EMI filters and are not effective at filtering high frequencies (> 50 MHz). Capacitors with high self-resonance
frequencies near the GHz range should be placed at the supply pins. This can be accomplished with small (0805
or less) 10 pF to 100 pF SMT ceramic capacitors placed directly at the supply pins to a solid RF ground. These
capacitors will provide a direct AC path for the high-frequency EMI to ground. These capacitors are in addition to,
and not a replacement for, the recommended low-frequency supply bypassing capacitors.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
•
Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply
applications.
For single-supply, place a capacitor between V+ and V−.
For dual supplies, place one capacitor between V+ and the board ground, and a second capacitor between
ground and V−.
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and operational
amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pick-up. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
Circuit Board Layout Techniques, SLOA089.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular
as opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible, keeping RF and RG close to the inverting
input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Even with the LMV83x inherent hardening against EMI, TI still recommends to keep the input traces short and as
far as possible from RF sources. Then the RF signals entering the chip are as low as possible, and the
remaining EMI can be, almost, completely eliminated in the chip by the EMI reducing features of the LMV83x.
10.2 Layout Example
Figure 51. SOT-23 Noninverting Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LMV831 PSPICE Model, SNOM049
LMV832 PSPICE Model, SNOM050
LMV834 PSPICE Model, SNOM038
TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
TI Filterpro Software, http://www.ti.com/tool/filterpro
DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• AN-028 Feedback Plots Define Op Amp AC Performance, SBOA015
• Circuit Board Layout Techniques, SLOA089
• Capacitive Load Drive Solution using an Isolation Resistor, TIPD128
• Handbook of Operational Amplifier Applications, SBOA092
• EMI-Hardened Operational Amplifiers for Robust Circuit Design, SNOA817
• AN-1698 A Specification for EMI Hardened Operational Amplifiers, SNOA497
• AN-1867 EMIRR Evaluation Boards for LMV831/LMV832/LMV834 (Boards are no longer available - for
reference only), SNOA530
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LMV831
Click here
Click here
Click here
Click here
Click here
LMV832
Click here
Click here
Click here
Click here
Click here
LMV834
Click here
Click here
Click here
Click here
Click here
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
26
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www.ti.com
SNOSAZ6C – AUGUST 2008 – REVISED NOVEMBER 2015
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2008–2015, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMV831MG/NOPB
ACTIVE
SC70
DCK
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AFA
LMV831MGE/NOPB
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AFA
LMV831MGX/NOPB
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AFA
LMV832MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AU5A
LMV832MME/NOPB
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AU5A
LMV832MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AU5A
LMV834MT/NOPB
ACTIVE
TSSOP
PW
14
94
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV834
MT
LMV834MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV834
MT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
2-Oct-2015
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LMV831MG/NOPB
SC70
DCK
5
LMV831MGE/NOPB
SC70
DCK
LMV831MGX/NOPB
SC70
DCK
LMV832MM/NOPB
VSSOP
LMV832MME/NOPB
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
5
250
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
5
3000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
VSSOP
DGK
8
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMV832MMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMV834MTX/NOPB
TSSOP
PW
14
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMV831MG/NOPB
SC70
DCK
5
1000
210.0
185.0
35.0
LMV831MGE/NOPB
SC70
DCK
5
250
210.0
185.0
35.0
LMV831MGX/NOPB
SC70
DCK
5
3000
210.0
185.0
35.0
LMV832MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMV832MME/NOPB
VSSOP
DGK
8
250
210.0
185.0
35.0
LMV832MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LMV834MTX/NOPB
TSSOP
PW
14
2500
367.0
367.0
35.0
Pack Materials-Page 2
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