IMP IMP1232LPCMA 5v î¼p power suppl er supply monit y monitor and or and reset cir eset circuit Datasheet

IMP1 232LP/LPS
POWER MANAGEMENT
5V µP Power Supply Monitor and
Reset Circuit
Key Features
◆ Pin compatible with the Dallas Semiconductor
DS1232LP/1232LPS
— 40% lower supply current
◆ 5V supply monitor
◆ Selectable watchdog period
◆ Debounce manual push-button reset input
◆ Precision temperature-compensated voltage
reference and comparator
◆ Power-up, power-down and brownout detection
◆ 250ms reset time
◆ Active LOW open-drain reset and active HIGH
push-pull output
◆ Selectable trip point tolerance: 5% or 10%
◆ Low-cost, surface mount packages: 8/16-pin
SO, 8-pin DIP and 8-pin MicroSO
◆ Wide operating temperature – 40°C to +85°C
(N/EPA suffixed devices)
– Selectable Trip -Point Tolerance
and Watchdog Period
– Push-Button Reset
The IMP1232LP/LPS microprocessor supervisor can halt and restart a
“hung-up” or “stalled” microprocessor, restart a microprocessor after a
power failure, and debounce and interface a manual push-button microprocessor reset switch. The low-power supervisors feature 40% lower
supply current than the pin compatible Dallas Semiconductor
DS1232LP/LPS.
Precision temperature compensated reference and comparator circuits
monitor the 5V, VCC input voltage. During power-up or when the VCC
power supply falls outside selectable tolerance limits, both the RESET
and RESET become active. When VCC rises above the threshold voltage,
the reset signals remain active for an additional 250ms minimum,
allowing the power supply and system microprocessor to stabilize. The
trip point tolerance signal, TOL, selects the trip level tolerance to be
either 5- or 10-percent.
Each device has both a push-pull, active HIGH reset output and an open
drain, active LOW reset output.
150ms, 610ms and 1,200ms. If the ST input is not strobed
A debounced manual reset input activates the reset outputs for a mini- LOW before the time-out period expires, a reset is issued.
mum period of 250ms.
Devices are available in 8-pin DIP, 8/16-pin SO and comAlso included is a watchdog timer to stop and restart a microprocessor pact 8-pin MicroSO packages.
that is “hung-up”. Three watchdog time-out periods are selectable:
Block Diagram
VCC
TOL
8 (15)
IMP1232LP/LPS
3 (6)
6 (11)
RESET
(16-Pin Package)
5%/10% Tolerance
Selection
+
5 (9)
Reference
VCC
–
RESET
40kΩ
PBRST
TD
ST
1 (2)
Push Button
Debounce
2 (4)
Watchdog
Timebase Selection
7 (13)
Watchdog
Transition Detector
Reset &
Watchdog Timer
4 (8)
1232_03.eps
GND
© 1999 IMP, Inc.
408-432-9100/www.impweb.com
1
IMP1 232LP/LPS
Pin Configuration
DIP/SO/MicroSO
SO
NC 1
PBRST 1
8 VCC
16 NC
PBRST 2
IMP1232LP
7 ST
IMP1232LPS-2
TOL 3 IMP1232LPCMA 6 RESET
IMP1232LPEMA
5 RESET
GND 4
TD 2
NC 3
15 VCC
IMP1232LPSN
14 NC
TD 4
13 ST
NC 5
12 NC
1232_01.eps
TOL 6
NC 7
GND 8
11 RESET
10 NC
9 RESET
1232_02.eps
Pin Descriptions
Pin Number
8-Pin Pac k ag e
Pin Number
16-Pin Pac k ag e
N ame
F unction
1
2
2
4
PBRST
TD
3
6
TOL
4
5
8
9
GND
RESET
6
7
8
—
11
13
15
1, 3, 5, 7, 10,
12, 14, 16
RESET
ST
VCC
NC
Debounced manual pushbutton RESET input
Watchdog time delay selection. (tTD = 150ms for TD = GND, tTD = 610ms
for TD = Open, and tTD =1200ms for TD = VCC)
Selects 5% (TOL connected to GND) or 10% (TOL connected to VCC) trip
point tolerance
Ground
Active HIGH reset output. RESET is active:
1. If VCC falls below the reset voltage trip point.
2. If PBRST is LOW.
3. If ST is not strobed LOW before the timeout period set by TD expires.
4. During power-up.
Active LOW reset output. (See RESET)
Strobe Input
5V power
No internal connection
Ordering Information
Package
Operating Temperature
Range
Maximum Supply
Current (µA)
Voltage Monitoring
Application
IMP1232LP
8-DIP
0°C to 70°C
30
5V
IMP1232LPS
16-SO
0°C to 70°C
30
5V
IMP1232LPS-2
8-SO
0°C to 70°C
30
5V
IMP1232LPCMA
8-MicroSO
0°C to 70°C
30
5V
IMP1232LPEMA
8-MicroSO
–40°C to 85°C
30
5V
IMP1232LPN
8-DIP
–40°C to 85°C
30
5V
IMP1232LPSN-2
8-SO
–40°C to 85°C
30
5V
IMP1232LPSN
16-SO
–40°C to 85°C
30
5V
Part Number
1232_t01.eps
2
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© 1999 IMP, Inc.
IMP1 232LP/LPS
Absolute Maximum Ratings
Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to 7V
Voltage on ST, TD . . . . . . . . . . . . . . . . . . . . . –0.5V to VCC + 0.5V
Voltage on PBRST, RESET, RESET . . . . . . . . –0.5V to VCC + 0.5V
Operating Temperature Range . . . . . . . . . . . –40°C to 85°C
(N/EMA version)
0°C to 70°C
Soldering Temperature . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Storage Temperature . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Voltages measured with respect to ground.
These are stress ratings only and functional operation is not implied.
Electrical Characteristics
Unless otherwise stated, 4.5V ≤ VCC ≤ 5.5V and over the operating temperature range of 0°C to +70°C (–40°C to +85°C for N/EMA
devices). All voltages are referenced to ground.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply Voltage (VCC)
VCC
4.5
5.5
V
ST and PBRST Input High Level
VIH
2
VCC + 0.3V
V
ST and PBRST Input Low Level
VIL
– 0.3
0.8
V
VCC Trip Point (TOL = GND)
VCCTP
4.50
4.62
4.74
V
VCC Trip Point (TOL = VCC)
VCCTP
4.25
4.37
4.49
V
Watchdog Time-Out Period
tTD
TD = GND
62.5
150
250
ms
Watchdog Time-Out Period
tTD
TD = VCC
500
1200
2000
ms
Watchdog Time-Out Period
tTD
TD floating
250
610
1000
ms
Output Voltage
VOH
I = –500µA, Note 3
VCC - 0.5V
VCC - 0.1V
V
Output Current
IOH
Output = 2.4V , Note 2
–8
–10
mA
Output Current
IOL
Output = 0.4V,
Input Leakage
IIL
Note 1
RESET Low Level
10
mA
–1.0
1.0
VOL
Internal Pull-Up Resistor
0.4
Note 1
40
µA
V
kΩ
Operating Current (CMOS)
ICC1
30
µA
Input Capacitance
CIN
5
pF
Output Capacitance
COUT
PBRST Manual Reset
Minimum Low Time
tPB
Reset Active Time
tRST
ST Pulse Width
tST
VCC Fail Detect to
RESET or RESET
tRPD
VCC Slew Rate
tF
PBRST Stable LOW to
RESET and RESET Active
tPDLY
VCC Detect to RESET or
RESET Inactive
tRPU
VCC Slew Rate
tR
10
PBRST = VIL
20
250
Note 4
610
tRISE = 5µs
4.25V to 4.75V
1000
20
8
µs
20
ms
1000
ms
µs
300
250
0
ms
ns
5
4.75V to 4.25V
pF
ms
610
ns
Notes: 1. PBRST is internally pulled HIGH to VCC through a nominal 40kΩ resistor.
2. RESET is an open drain output.
3. RESET remains within 0.5V of VCC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down
until VCC falls below 2.0V.
4. Must not exceed the minimum watchdog time-out period (tTD). The watchdog circuit cannot be disabled. To avoid a reset, ST must be
strobed.
© 1999 IMP, Inc.
408-432-9100/www.impweb.com
3
IMP1 232LP/LPS
Application Information
Supply Voltage Monitor
TRIP Point Voltage (V)
Tolerance
Select
Reset Signal Polarity and Output Stage Structure
RESET is an active LOW signal. It is developed with an open
drain driver. If a pullup resistor is required, typical values are
10kΩ to 50kΩ.
RESET is an active High signal developed by a CMOS push-pull
output stage and is the logical opposite to RESET.
Trip Point Tolerance Selection
With TOL connected to VCC, RESET and RESET become active
whenever VCC falls below 4.5V. RESET and RESET become active
when VCC falls below 4.75V if TOL is connected to ground.
After VCC has risen above the trip point set by TOL, RESET and
RESET remain active for a minimum time period of 250ms.
On power-down, once VCC falls below the reset threshold RESET
stays LOW and is guaranteed to be 0.4V or less until VCC drops
below 1.2V. The active HIGH reset signal is valid down to a VCC
level of 1.2V also.
Tolerance
Min
Nominal
Max
TOL = VCC
10%
4.25
4.37
4.49
TOL = GND
5%
4.5
4.62
4.74
1232_t02.eps
Manual Reset Operation
Push-button switch input, PBRST, allows the user to override the
internal trip point detection circuits and issue reset signals. The
pushbutton input is debounced and is normally pulled HIGH
through an internal 40kΩ resistor.
When PBRST is held LOW for the minimum time tPB , both resets
become active and remain active for approximately a minimum
time period of 250ms after PBRST returns HIGH.
The debounced input is guaranteed to recognize pulses greater
than 20ms. No external pull-up resistor is required, since PBRST
is pulled HIGH by an internal 40kΩ resistor.
The PBRST can be driven from a TTL or CMOS logic line or shorted to ground with a mechanical switch.
tR
4.25V
tPB
PBRST
4.75V
VCCTP
tPDLY
VIH
VIL
tRST
VCC
tRPU
RESET
RESET
VOH
VOL
VOH
RESET
1232_08.eps
Figure 3. Timing Diagram: Pushbutton Reset
VOL
RESET
1232_05.eps
5V
Figure 1. Timing Diagram: Power Up
IMP1232LP/LPS
1
tF
VCC
2
4.75V
VCCTP
3
4.25V
4
PBRST
TD
VCC
ST
TOL
RESET
GND
RESET
8
7
6
5
µP
RESET
1232_06.eps
RESET
Figure 4. Application Circuit: Pushbutton Reset
tRPD
RESET
VOH
VOL
1232_04.eps
Figure 2. Timing Diagram: Power Down
4
408-432-9100/www.impweb.com
© 1999 IMP, Inc.
IMP1 232LP/LPS
Application Information
Watchdog Timer and ST Input
A watchdog timer stops and restarts a microprocessor that is
“hung-up”. Through the time delay input, TD, three watchdog
time-out periods are selectable: 150ms, 610ms and 1,200ms. If the
strobe input, ST, is not strobed LOW prior to timeout, reset signals
become active. On power-up or after the supply voltage returns to
an in-tolerance condition, the reset signal remains active for
250ms minimum, allowing the power supply and system microprocessor to stabilize.
ST
Timeouts periods of approximately 150ms, 610ms or 1,200ms are
selected through the TD pin.
Watchdog Time-Out Period (ms)
TD Voltage Level
ST Pulses as short as 20ns can be detected.
Valid
Strobe
A HIGH-to-LOW ST signal transition must be regularly issued
no later than the minimum time-out period defined by the state of
the TD signal. This guarantees the watchdog timer does not
time-out.
Valid
Strobe
Invalid
Strobe
GND
Floating
VCC
Min
Nominal
Max
62.5
250
500
150
610
1200
250
1000
2000
tST
tRST
1232_t03.eps
tTD
(Min)
RESET
The watchdog timer cannot be disabled. It must be strobed with a
high-to-low transition to avoid a watchdog timeout.
tTD
(Max)
1232_09.eps
Note: ST is ignored whenever a reset is active.
Figure 5. Timing Diagram: Strobe Input
5V
IMP1232LP/LPS
1
2
3
4
PBRST
TD
TOL
GND
VCC
ST
RESET
RESET
8
7
6
MREQ
10kΩ
µP
RESET
Address
Bus
Decoder
5
1232_07.eps
Figure 6. Application Circuit: Watchdog Timer
© 1999 IMP, Inc.
408-432-9100/www.impweb.com
5
IMP1 232LP/LPS
Package Dimensions
MicroSO (8-Pin)
Inches
Min
a
+
L
D
C
D
A
e
0.10mm
0.004in
Max
A
A1
A2
b
C
D
e
E
E1
L
a
–––––
0.0433
0.0020
0.0059
0.0295
0.0374
0.0098
0.0157
0.0051
0.0091
0.1142
0.1220
0.0256 BSC
0.193 BSC
0.1142
0.1220
0.0157
0.0276
0°
6°
A
A1
B
C
e
E
H
L
D
0.053
0.004
0.013
0.007
SO (8-Pin)
0°– 8°
L
E
Max
––––
1.10
0.050
0.15
0.75
0.95
0.25
0.40
0.13
0.23
2.90
3.10
0.65 BSC
4.90 BSC
2.90
3.10
0.40
0.70
0°
6°
SO (8-Pin)**
MicroSO (8-Pin).eps
A1
b
Min
MicroSO (8-Pin)*
E1 E
A2
Millimeters
H
0.069
0.010
0.020
0.010
1.35
0.10
0.33
0.19
0.050
0.150
0.228
0.016
0.189
1.75
0.25
0.51
0.25
1.27
0.157
0.244
0.050
0.197
3.80
5.80
0.40
4.80
4.00
6.20
1.27
2.00
Plastic DIP (8-Pin)***
C
D
A
e
B
A1
SO (8-Pin).eps
Plastic DIP (8-Pin)
D1
E
D
E1
A
–––––
0.210
A1
0.015
–––––
A2
0.115
0.195
b
0.014
0.022
b2
0.045
0.070
b3
0.030
0.045
D
0.355
0.400
D1
0.005
–––––
E
0.300
0.325
E1
0.240
0.280
e
0.100
–––––
eA
0.300
–––––
eB
–––––
0.430
eC
–––––
0.060
L
0.115
0.150
*** JEDEC Drawing MO-187AA
*** JEDEC Drawing MS-112AA
*** JEDEC Drawing MS-001BA
––––
0.38
2.92
0.36
1.14
0.80
9.02
0.13
7.62
6.10
5.33
–––––
4.95
0.56
1.78
1.14
10.16
–––––
8.26
7.11
2.54
7.62
–––––
10.92
2.92
3.81
1232_t04.at3
A A2
L A1
0°–15°
e
C
b2
b
eA
eB
Plastic DIP (8-Pin)a.eps
6
408-432-9100/www.impweb.com
© 1999 IMP, Inc.
IMP1 232LP/LPS
Package Dimensions
SO (16-Pin)
Inches
Min
Millimeters
Max
Min
Max
SO (16-Pin)*
E
H
D
0°– 8°
A
C
e
L
B
A1
SO (14-Pin).eps
IMP, Inc.
Corporate Headquarters
2830 N. First Street
San Jose, CA 95134-2071
Tel: 408-432-9100
Tel: 800-438-3722
Fax: 408-434-0335
e-mail: [email protected]
http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc.
All other company and product names are trademarks of their respective owners.
A
0.926
0.1043
A1
0.0040
0.0118
B
0.013
0.020
C
0.0091
0.0125
D
0.3977
0.4133
E
0.2914
0.2662
e
0.050 BSC
H
0.394
0.419
L
0.016
0.050
* JEDEC Drawing MS-013AA
2.35
2.65
0.10
0.30
0.33
0.51
0.23
0.32
10.10
10.50
7.40
7.60
1.27 BSC
10.00
10.65
0.40
1.27
2524/26_t03.at3
© 1999 IMP, Inc.
Printed in USA
Publication #: 1011
Revision:
B
Issue Date:
11/08/99
Type:
Preliminary
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