Ramtron FM25L512 512kb fram serial 3v memory Datasheet

Preliminary
FM25L512
512Kb FRAM Serial 3V Memory
Features
512K bit Ferroelectric Nonvolatile RAM
• Organized as 65,536 x 8 bits
• Unlimited Read/Write Cycles
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Write Protection Scheme
• Hardware Protection
• Software Protection
Low Power Consumption
• Low Voltage Operation 3.0V – 3.6V
• 20 µA Standby Current
Very Fast Serial Peripheral Interface - SPI
• Up to 20 MHz Frequency
• Direct Hardware Replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Industry Standard Configurations
• Industrial Temperature -40°C to +85°C
• 8-pin “Green”/RoHS TDFN Package
• Footprint Compatible with SOIC-8 (see pg 12)
Description
Pin Configuration
The FM25L512 is a 512-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
Unlike serial EEPROMs, the FM25L512 performs
write operations at bus speed. No write delays are
incurred. The next bus cycle may commence
immediately without the need for data polling. The
next bus cycle may start immediately. In addition, the
product offers virtually unlimited write endurance.
Also, FRAM exhibits much lower power
consumption than EEPROM.
These capabilities make the FM25L512 ideal for
nonvolatile memory applications requiring frequent
or rapid writes or low power operation. Examples
range from data collection, where the number of
write cycles may be critical, to demanding industrial
controls where the long write time of EEPROM can
cause data loss.
Top View
/CS
1
8
VDD
SO
2
7
/HOLD
/WP
3
6
SCK
VSS
4
5
SI
Pin Name
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage (3.0 to 3.6V)
Ground
Ordering Information
FM25L512-DG
8-pin “Green”/RoHS TDFN
The FM25L512 provides substantial benefits to users
of serial EEPROM as a hardware drop-in
replacement. The FM25L512 uses the high-speed SPI
bus, which enhances the high-speed write capability
of FRAM technology. Device specifications are
guaranteed over an industrial temperature range of
-40°C to +85°C.
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.2
Aug. 2007
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 1 of 13
FM25L512
WP
Instruction Decode
Clock Generator
Control Logic
Write Protect
CS
HOLD
SCK
8192 x 64
FRAM Array
Instruction Register
Address Register
Counter
SI
16
8
Data I/O Register
SO
3
Nonvolatile Status
Register
Figure 1. Block Diagram
Pin Descriptions
Pin Name
/CS
I/O
Input
SCK
Input
/HOLD
Input
/WP
Input
SI
Input
SO
Output
VDD
VSS
Supply
Supply
Rev. 1.2
Aug. 2007
Description
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the SCK signal. A falling edge on /CS must occur
prior to every op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 20 MHz and may be interrupted at
any time.
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while
SCK is low.
Write Protect: This active low pin prevents write operations to the Status Register
only. A complete explanation of write protection is provided on pages 6 and 7.
Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet IDD specifications.
* SI may be connected to SO for a single pin data interface.
Serial Output: This is the data output pin. It is driven during a read and remains tristated at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* SO may be connected to SI for a single pin data interface.
Power Supply (3.0V to 3.6V)
Ground
Page 2 of 13
FM25L512
Overview
The FM25L512 is a serial FRAM memory. The
memory array is logically organized as 65,536 x 8
and is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the FRAM is similar to serial EEPROMs. The
major differences between the FM25L512 and a
serial EEPROM with the same pinout are the
FRAM’s superior write performance, unlimited
endurance, and lower power consumption.
Memory Architecture
When accessing the FM25L512, the user addresses
64K locations of 8 data bits each. These data bits are
shifted serially. The addresses are accessed using the
SPI protocol, which includes a chip select (to permit
multiple devices on the bus), an op-code, and a twobyte address. The complete address of 16-bits
specifies each byte address uniquely.
Most functions of the FM25L512 either are
controlled by the SPI interface or are handled
automatically by on-board circuitry. The access time
for memory operation is essentially zero, beyond the
time needed for the serial protocol. That is, the
memory is read or written at the speed of the SPI bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. So, by the time a new bus transaction can be
shifted into the device, a write operation will be
complete. This is explained in more detail in the
interface section.
Users expect several obvious system benefits from
the FM25L512 due to its fast write cycle and high
endurance as compared to EEPROM. In addition
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
Note that the FM25L512 contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to
ensure that VDD is within datasheet tolerances to
prevent incorrect operation.
Serial Peripheral Interface – SPI Bus
The FM25L512 employs a Serial Peripheral Interface
(SPI) bus. It is specified to operate at speeds up to
20MHz. This high-speed serial bus provides high
performance serial communication to a host
Rev. 1.2
Aug. 2007
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25L512 operates in SPI Mode 0 and 3.
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. A typical system
configuration uses one or more FM25L512 devices
with a microcontroller that has a dedicated SPI port,
as Figure 2 illustrates. Note that the clock, data-in,
and data-out pins are common among all devices.
The Chip Select and Hold pins must be driven
separately for each FM25L512 device.
For a microcontroller that has no dedicated SPI bus, a
general purpose port may be used. To reduce
hardware resources on the controller, it is possible to
connect the two data pins together and tie off the
Hold pin. Figure 3 shows a configuration that uses
only three pins.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data pins. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25L512 will begin monitoring
the clock and data lines. The relationship between the
falling edge of /CS, the clock and data is dictated by
the SPI mode. The device will make a determination
of the SPI mode on the falling edge of each chip
select. While there are four such modes, the
FM25L512 supports only modes 0 and 3. Figure 4
shows the required signal relationships for modes 0
and 3. For both modes, data is clocked into the
FM25L512 on the rising edge of SCK and data is
expected on the first rising edge after /CS goes
active. If the clock starts from a high state, it will fall
prior to the first data transfer in order to create the
first rising edge.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the device. After
/CS is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred.
Certain op-codes are commands with no subsequent
data transfer. The /CS must go inactive after an
operation is complete and before a new op-code can
be issued. There is one valid op-code only per active
chip select.
Page 3 of 13
FM25L512
Figure 2. 1Mbit System Configuration with SPI port
Figure 3. System Configuration without SPI port
SPI Mode 0: CPOL=0, CPHA=0
7
6
5
4
3
2
1
0
SPI Mode 3: CPOL=1, CPHA=1
7
6
5
4
3
2
1
0
Figure 4. SPI Modes 0 & 3
Rev. 1.2
Aug. 2007
Page 4 of 13
FM25L512
Power Up to First Access
The FM25L512 is not accessible for a period of time
(10 ms) after power up. Users must comply with the
timing parameter tPU, which is the minimum time
from VDD (min) to the first /CS low.
WREN - Set Write Enable Latch
The FM25L512 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the Status
Register and writing the memory.
Data Transfer
All data transfers to and from the FM25L512 occur in
8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the Status
Register, called WEL, indicates the state of the
latch. WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the Status
Register has no effect on the state of this bit. The
WEL bit will be automatically cleared on the rising
edge of /CS following a WRDI, a WRSR, or a
WRITE operation. This prevents further writes to
the Status Register or the FRAM array without
another WREN command. Figure 5 below illustrates
the WREN command bus configuration.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25L512. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the Status
Register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
Table 1. Op-code Commands
Name
Description
Set Write Enable Latch
WREN
Write Disable
WRDI
Read Status Register
RDSR
Write Status Register
WRSR
Read Memory Data
READ
WRITE Write Memory Data
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the Status Register and verifying that WEL=0.
Figure 6 illustrates the WRDI command bus
configuration.
Op-code
0000
0000
0000
0000
0000
0000
0110b
0100b
0101b
0001b
0011b
0010b
CS
0
1
2
3
4
5
6
7
0
1
1
0
SCK
SI
SO
0
0
0
0
Hi-Z
Figure 5. WREN Bus Configuration
Rev. 1.2
Aug. 2007
Page 5 of 13
FM25L512
CS
0
1
2
3
4
5
6
7
0
1
0
0
SCK
SI
0
0
0
0
Hi-Z
SO
Figure 6. WRDI Bus Configuration
RDSR - Read Status Register
The RDSR command allows the bus master to verify
the contents of the Status Register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR opcode, the FM25L512 will return one byte with the
contents of the Status Register. The Status Register is
described in detail in a later section.
WRSR – Write Status Register
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status Register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive.
Prior to sending the WRSR command, the user must
send a WREN command to enable writes. Note that
executing a WRSR command is a write operation
and therefore clears the Write Enable Latch. The bus
configuration of RDSR and WRSR are shown
below.
Figure 7. RDSR Bus Configuration
Figure 8. WRSR Bus Configuration
Status Register & Write Protection
The write protection features of the FM25L512 are
multi-tiered. A WREN op-code must be issued prior
to writing the memory (WRITE) or Status Register
(WRSR). Protecting the Status Register can be
accomplished via software using the WPEN bit or
hardware using the /WP pin. Status Register write
operations are blocked when /WP is low and
WPEN=1. Memory write operations are protected by
Rev. 1.2
Aug. 2007
the block protect (BP) bits in the Status Register. The
state of the /WP pin has no effect on memory writes.
As described above, writes to the Status Register are
performed using the WRSR command and subject to
the WPEN bit and /WP pin. The Status Register is
organized as follows.
Table 2. Status Register
Bit
Name
7
6
5
4
3
2
1
0
WPEN
1
0
0
BP1
BP0
WEL
0
Page 6 of 13
FM25L512
Bits 0, 4, 5 are fixed at 0 and bit 6 is fixed at 1, and
none of these bits can be modified. Note that bit 0
(“Ready” in EEPROMs) is unnecessary as the FRAM
writes in real-time and is never busy, so it reads out
as a ‘0’. The BP1 and BP0 control software write
protection features. They are nonvolatile (shaded
yellow). The WEL flag indicates the state of the
Write Enable Latch. Attempting to directly write the
WEL bit in the Status Register has no effect on its
state. This bit is internally set and cleared via the
WREN and WRDI commands, respectively.
BP1 and BP0 are memory block write protection bits.
They specify portions of memory that are writeprotected as shown in the following table.
Table 3. Block Memory Write Protection
BP1
BP0 Protected Address Range
0
0
None
0
1
C000h to FFFFh (upper ¼)
1
0
8000h to FFFFh (upper ½)
1
1
0000h to FFFFh (all)
Table 4. Write Protection
WEL
WPEN
/WP
0
X
X
1
0
X
1
1
0
1
1
1
Protected Blocks
Protected
Protected
Protected
Protected
Memory Operation
The SPI interface, which is capable of a relatively
high clock frequency, highlights the fast write
capability of the FRAM technology. Unlike SPI-bus
EEPROMs, the FM25L512 can perform sequential
writes at bus speed. No page register is needed and
any number of sequential writes may be performed.
Write Operation
All writes to the memory array begin with a WREN
op-code. The next op-code is the WRITE instruction.
This op-code is followed by a two-byte address
value, which specifies the 16-bit address of the first
data byte of the write operation. Subsequent bytes are
data and they are written sequentially. Addresses are
incremented internally as long as the bus master
continues to issue clocks. If the last address of FFFFh
is reached, the counter will roll over to 0000h. Data is
written MSB first. A write operation is shown in
Figure 9.
Rev. 1.2
Aug. 2007
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes. The remaining write protection features
protect inadvertent changes to the block protect bits.
The WPEN bit controls the effect of the hardware pin
/WP. When WPEN=0, the /WP pin is ignored. When
WPEN=1, the /WP pin controls write access to the
Status Register. Thus the Status Register is writeprotected only when WPEN=1 and the /WP pin is
low.
This scheme provides a write protection mechanism,
which can prevent software from writing the memory
under any circumstances. This occurs if the BP1 and
BP0 are set to 1, the WPEN bit is set to 1, and the
/WP pin is low. This occurs because the block
protect bits prevent writing memory and the /WP
signal in hardware prevents altering the block protect
bits (if WPEN is high). Therefore in this condition,
hardware must be involved in allowing a write
operation. The following table summarizes the write
protection conditions.
Unprotected Blocks
Protected
Unprotected
Unprotected
Unprotected
Status Register
Protected
Unprotected
Protected
Unprotected
Unlike EEPROMs, any number of bytes can be
written sequentially and each byte is written to
memory immediately after it is clocked in (after the
8th clock). The rising edge of /CS terminates a
WRITE op-code operation. Asserting /WP active in
the middle of a write operation will have no effect
until the next falling edge of /CS.
Read Operation
After the falling edge of /CS, the bus master can issue
a READ op-code. Following this instruction is a twobyte address value, 16-bits specifying the address of
the first data byte of the read operation. After the opcode and address are complete, the SI line is ignored.
The bus master issues 8 clocks, with one bit read out
for each. Addresses are incremented internally as
long as the bus master continues to issue clocks. If
the last address of FFFFh is reached, the counter will
roll over to 0000h. Data is read MSB first. The rising
edge of /CS terminates a READ op-code operation.
A read operation is shown in Figure 10.
Page 7 of 13
FM25L512
while SCK is low will resume an operation. The
transitions of /HOLD must occur while SCK is low,
but the SCK and /CS pins can toggle during a hold
state.
Hold
The /HOLD pin can be used to interrupt a serial
operation without aborting it. If the bus master pulls
the /HOLD pin low while SCK is low, the current
operation will pause. Taking the /HOLD pin high
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
4
5
6
7
0
1
2
3
4
5
6
7
16-bit Address
15 14 13 12 11 10 9
3
2
1
0
7
6
Data
5 4
3
2
1
0
SCK
op-code
SI
0
0
0
0
0
0
1
0
MSB
LSB MSB
LSB
SO
Figure 9. Memory Write
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
4
5
6
16-bit Address
15 14 13 12 11 10 9
3
2
1
7
0
1
2
3
4
5
6
3
2
1
7
SCK
op-code
SI
0
0
0
0
0
0
1
1
0
LSB
MSB
SO
Data
MSB
7
6
5
4
LSB
0
Figure 10. Memory Read
Rev. 1.2
Aug. 2007
Page 8 of 13
FM25L512
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
VDD
Power Supply Voltage with respect to VSS
VIN
Voltage on any pin with respect to VSS
TSTG
TLEAD
Ratings
-1.0V to +5.0V
-1.0V to +5.0V
and VIN < VDD+1.0V
-55°C to + 125°C
300° C
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40°C to + 85°C, VDD = 3.0V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Typ
Max
Units
VDD
Power Supply Voltage
3.0
3.6
V
IDD
Power Supply Current
@ SCK = 1 MHz
0.6
mA
@ SCK = 20 MHz
12
ISB
Standby Current
20
µA
ILI
Input Leakage Current
µA
±1
ILO
Output Leakage Current
µA
±1
VIH
Input High Voltage
0.7 VDD
VDD + 0.5
V
VIL
Input Low Voltage
-0.3
0.3 VDD
V
VOH
Output High Voltage
V
VDD – 0.8
@ IOH = -2 mA
0.4
V
VOL
Output Low Voltage
@ IOL = 2 mA
VHYS
Input Hysteresis (/CS and SCK only)
0.05 VDD
V
Notes
1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.
2. SCK = SI = /CS=VDD. All inputs VSS or VDD.
3. VSS ≤ VIN ≤ VDD and VSS ≤ VOUT ≤ VDD.
4. This parameter is characterized but not 100% tested.
Data Retention (VDD = 3.0V to 3.6V)
Parameter
Data Retention
Rev. 1.2
Aug. 2007
Min
10
Max
-
Units
Years
Notes
1
2
3
3
4
Notes
Page 9 of 13
FM25L512
AC Parameters (TA = -40°C to + 85°C, VDD = 3.0V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Max
fCK1
SCK Clock Frequency
0
20
tCH1
Clock High Time
22
tCL1
Clock Low Time
22
tCSU
Chip Select Setup
10
tCSH
Chip Select Hold
10
tOD
Output Disable Time
20
tODV
Output Data Valid Time
20
tOH
Output Hold Time
0
tD
Deselect Time
60
tR
Data In Rise Time
50
tF
Data In Fall Time
50
tSU
Data Setup Time
5
tH
Data Hold Time
5
tHS
/Hold Setup Time
10
tHH
/Hold Hold Time
10
tHZ
/Hold Low to Hi-Z
20
tLZ
/Hold High to Data Active
20
Notes
1.
2.
3.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
2
1,3
1,3
2
2
tCH + tCL = 1/fCK.
This parameter is characterized but not 100% tested.
Rise and fall times measured between 10% and 90% of waveform.
AC Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing levels
Output Load Capacitance
10% and 90% of VDD
3 ns
0.5 VDD
30 pF
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V)
Symbol
Parameter
CO
Output Capacitance (SO)
CI
Input Capacitance
Notes
1. This parameter is characterized and not 100% tested.
Rev. 1.2
Aug. 2007
Min
-
Max
8
6
Units
pF
pF
Notes
1
1
Page 10 of 13
FM25L512
Serial Data Bus Timing
/Hold Timing
tHS
CS
tHH
SCK
tHH
tHS
HOLD
SO
tHZ
tLZ
Power Cycle Timing
Power Cycle Timing (TA = -40° C to + 85° C, VDD = 3.0V to 3.6V)
Symbol
Parameter
tPU
Power Up (VDD min) to First Access (/CS low)
tPD
Last Access (/CS high) to Power Down (VDD min)
tVR
VDD Rise Time
tVF
VDD Fall Time (applies only to VDD levels below 2V)
Notes
1.
2.
Min
10
0
50
1
Max
-
Units
ms
µs
µs/V
ms/V
Notes
1,2
1,2
This parameter is characterized and not 100% tested.
Slope measured at any point on VDD waveform.
Rev. 1.2
Aug. 2007
Page 11 of 13
FM25L512
Mechanical Drawing
8-pin TDFN (5.0 mm x 6.0 mm body, 1.27 mm pad pitch)
6.0 ±0.1
5.0 ±0.1
4.0 ±0.1
3.0 ±0.1
Exposed metal pad.
Do not connect to
anything except Vss.
Pin 1 ID
Pin 1
0.70 ±0.1
3.81 REF
0.0 - 0.05
0.75 ±0.05
0.20 REF.
1.27
0.50 ±0.05
Note: All dimensions in millimeters. This package is footprint compatible with the 8-pin SOIC,
however care must be taken to ensure PCB traces and vias are not placed within the exposed
metal pad area.
TDFN Package Marking Scheme for Body Size 5.0mm x 6.0mm
RGXXXX
LLLL
YYWW
Legend:
R=Ramtron, G=”green” TDFN package
XXXX=base part number
LLLL= lot code
YY=year, WW=work week
Example: “Green” TDFN package, FM25L512, Lot 0012, Year 2006, Work Week 24
RG5L51
0012
0624
Rev. 1.2
Aug. 2007
Page 12 of 13
FM25L512
Revision History
Revision
1.0
Date
8/21/06
1.1
3/15/07
1.2
8/16/07
Rev. 1.2
Aug. 2007
Summary
Changed to Preliminary status. Changed to industrial temperature range.
Changed ISB. Changed tVR spec.
Modified package drawing and removed “preliminary” marking. Modified
Serial Data Bus and HOLD Timing diagrams.
Clarified write protection section (pg. 6). Added comment about exposed
metal pad to Mechanical Drawing page.
Page 13 of 13