iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit FEATURES BENEFITS DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp Package: • Proprietary Enchanced Die Stacked iPEM • 208 Plastic Ball Grid Array (PBGA), 16 x 23mm • 1.00mm ball pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4n-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Eight internal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes (I/T Version) On Die Termination (ODT) Adjustable data – output drive strength 1.8V ±0.1V common core power and I/O supply Programmable CAS latency: 3, 4, 5, 6 or 7 Posted CAS additive latency: 0, 1, 2, 3, 4 or 5 Write latency = Read latency - 1* tCK Organized as 64M x 72 Weight: AS4DDR264M72PBG1 ~ 2.0 grams typical 61% Space Savings 55% I/O reduction vs Individual package approach Reduced part count Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Upgradable to 128M x 72 density in future Pin/Function equivalent to White W3H64M72E-xBSx ConfigurationAddressing Parameter Configuration RefreshCount RowAddress BankAddress ColumnAddress 64Megx72 8Megx16x8Banks 8K A0ͲA12(8k) BA0ͲBA2(8) A0ͲA9(1K) NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only FUNCTIONAL BLOCK DIAGRAM Ax, BA0-2 ODT VRef VCC VSS VSSQ VCCQ VCCQ VCCQ VCCQ VCCQ VSSQ VCCL VSSQ VCCL VSSQ VCCL VSSQ VCCL VSSQ VCCL VSSDL A VSSDL B VSSDL C VSSDL VSSDL D DQ64-71 CS\ WE\ RAS\ CAS\ CKE\ ODT UDMx, LDMx UDSQx,UDSQx\ LDSQx, LDSQx\ CKx,CKx\ A AS4DDR264M72PBG1 Rev. 3.1 01/10 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ODT LDM4 2 2 DQ0-15 B DQ16-31 C UDM4 DQ32-47 D DQ48-63 Micross Components reserves the right to change products or specifications without notice. 1 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 SDRAM-DDRII PINOUT TOP VIEW 1 A 2 3 4 5 6 7 8 9 10 11 Vcc Vss Vcc Vcc Vss Vcc Vcc Vss Vcc Vss A B Vcc Vss NC NC NC NC NC NC NC Vss Vcc B C Vss NC NC NC NC NC NC DQ34 CK3 CK3\ Vss C D DQ35 DQ51 NC NC NC NC DQ50 DQ53 DQ37 CK2\ CK2 D E DQ52 DQ36 DQ33 NC BA2 NC DQ39 LDQS2 LDQS3 DQ48 DQ32 E F LDM3 LDM2 DQ49 DQ43 DQ59 NC DQ55 DQ58 DQ42 G DQ38 DQ54 DQ60 DQ57 UDM2 Vss DQ63 DQ56 DQ40 H UDM3 DQ44 DQ41 DQ46 DQ62 Vcc UDQS2\ DQ47 J Vcc A6 A10 A9 Vcc Vss Vcc A3 A12 RFU Vcc J K Vss A0 A11 Vcc Vss Vref Vss Vcc A1 BA1 Vss K L Vcc A2 A4 A8 Vcc Vss Vcc BA0 A5 A7 Vcc L DQ15 UDQS0\ Vcc DQ30 DQ14 DQ9 DQ12 DQ8 DQ24 DQ31 Vss UDM0 DQ25 DQ28 DQ22 DQ6 N DQ10 DQ26 DQ23 ODT DQ27 DQ11 DQ17 LDM0 LDM1 p M UDQS1\ UDQS1 UDQS0 N P DQ13 DQ29 LDQS1\ LDQS0\ LDQS2\ LDQS3\ F DQ61 DQ45 G UDQS2 UDQS3 UDQS3\ H UDM1 M R DQ0 DQ16 LDQS1 LDQS0 DQ7 LDQS4\ UDQS4 UDQS4\ DQ1 DQ4 DQ20 R T CK0 CK0\ DQ5 DQ21 DQ18 LDQS4 DQ71 CKE WE\ DQ19 DQ3 T U Vss CK1\ CK1 DQ2 RAS\ CAS\ DQ64 DQ70 DQ65 DQ68 Vss U V Vcc Vss CK4\ CK4 CS\ DQ66 DQ69 LDM4 DQ67 Vss Vcc V W Vss Vcc Vss Vcc Vcc Vss Vcc Vcc Vss Vcc Vss W 1 2 3 4 5 6 7 8 9 10 11 Ground CNTRL Array Power UNPOPULATED Address Level REF. NC RFU Data I/O AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 2 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 BGA Locations P6 C9,C10,D10,D11,T1,T2, U2,U3,V3,V4 T8 V5 U5 U6 T9 G5,H1,M11,N7, F1,F2,P10,P11,V8 H9,H10,M2,M3,R7 H7,H11,M1,M5,R8 E8,E9,R3,R4,T6 F10,F11,P1,P2,R6 J2,J3,J4,J8,J9,K2, K3,K9,L2,L3,L4,L9,L10 Symbol ODT CKx, CKx\ Type CNTL Input CNTL Input Description On-Die-Termination: Registered High enables on data bus termination Differential input clocks, one set for each x16bits CKE CS\ RAS\ CAS\ WE\ UDMx LDMx UDQSx UDQSx\ LDQSx LDQSx\ Ax CNTL Input CNTL Input CNTL Input CNTL Input CNTL Input CNTL Input CNTL Input CNTL Input CNTL Input CNTL Input CNTL Input Input Clock enable which activates all on silicon clocking circuitry Chip Selects, one for each 16 bits of the data bus width Command input which along with CAS\, WE\ and CS\ define operations Command input which along with RAS\, WE\ and CS\ define operations Command input which along with RAS\, CAS\ and CS\ define operations One Data Mask cntl. for each upper 8 bits of a x16 word One Data Mask cntl. For each lower 8 bits of a x16 word Data Strobe input for upper byte of each x16 word Differential input of UDQSx, only used when Differential DQS mode is enabled Data Strobe input for lower byte of each x16 word Differential input of LDQSx, only used when Differential DQS mode is enabled Array Address inputs providing ROW addresses for Active commands, and the column address and auto precharge bit (A10) for READ/WRITE commands J10 RFU L8,K10,E5 BA0,BA1,BA2 C8,D1,D2,D7,D8,D9,E1, DQx E2,E3,E7,E10,E11,F3, F4,F5,F7,F8,F9,G1,G2, G3,G4,G7,G8,G9,G10, G11,H2,H3,H4,H5,H8, M4,M7,M8,M9,M10,N1, N2,N3,N4,N5,N8,N9, N10,N11,P3,P4,P5,P7, P8,P9,R1,R2,R5,R9, R10,R11,T3,T4,T5,T7, T10,T11,U4,U7,U8,U9, U10,V6,V7,V9 k6 Vref A2,A4,A5,A7,A8,A10, VCC B1,B11,H6,J1,J5,J7,J11, K4,K8,L1,L5,L7,L11,M6, V1,V11,W2,W4,W5, W7,W8,W10 A3,A6,A9,A11,B2,B10, VSS C1,C11,G6,J6,K1,K5, K7,K11,L6,N6,U1,U11, V2,V10,W1,W3,W6, W9,W11 B3,B4,B5,B6,B7,B8,B9, NC C2,C3,C4,C5,C6,C7,D3, D4,D5,D6,E4, E6, F6 A1 UNPOPULATED AS4DDR264M72PBG1 Rev. 3.1 01/10 Future Input Input Bank Address inputs Input/Output Data bidirectional input/Output pins Supply Supply SSTL_18 Voltage Reference Core Power Supply Supply Core Ground return No connection Unpopulated ball matrix location (location registration aid) Micross Components reserves the right to change products or specifications without notice. 3 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 DESCRIPTION The 4.8Gb DDR2 SDRAM, a high-speed CMOS, dynamic random-access memory containing 4,831,838,208 bits. Each of the five chips in the MCP are internally configured as 8-bank DRAM. The block diagram of the device is shown in Figure 2. Ball assignments and are shown in Figure 3. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAMs, the pipelined, multibank architecture of DDR2 SDRAMs allows for concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. The 4.8Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the x72 DDR2 SDRAM effectively consists of a single 4n-bit-wide, one-clockcycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. A self refresh mode is provided, along with a powersaving power-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18compatible. GENERAL NOTES • The functionality and the timing specifications discussed in this data sheet are for the DLLenabled mode of operation. • Throughout the data sheet, the various figures and text refer to DQs as ¡°DQ.¡± The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, each chip is divided into 2 bytes, the lower byte and upper byte. For the lower byte (DQ0¨CDQ7), DM refers to LDM and DQS refers to LDQS. For the upper byte (DQ8¨CDQ15), DM refers to UDM and DQS refers to UDQS. • Complete functionality is described throughout the document and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. • Any specific requirement takes precedence over a general statement. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. There are strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The MCP DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. INITIALIZATION DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following sequence is required for power up and initialization and is shown in Figure 4 on page 5. The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read, or a burst write of eight with another write. AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 4 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 FIGURE 4 - POWER-UP AND INITIALIZATION Notes appear on page 7 VDD VDDL VDDQ tVTD1 VTT1 VREF T0 tCK Ta0 Tb0 Tc0 Td0 Te0 Tf0 Tg0 Th0 Ti0 Tj0 Tk0 Tl0 Tm0 NOP4 PRE LM5 LM6 LM7 LM8 PRE9 REF10 REF LM11 LM12 LM13 Valid16 A10 = 1 Code Code Code Code A10 = 1 Code Code Code Valid CK# CK tCL tCL LVCMOS 2 SSTL_18 2 CKE LOW LEVEL LOW LEVEL ODT 3 Command 15 DM 3 Address 15 DQS High-Z 15 High-Z RTT High-Z DQ T = 200µs (MIN) Power-up: VDD and stable clock (CK, CK#) T = 400ns (MIN)16 tMRD tRPA tMRD tMRD tMRD tRPA tRFC tRFC tMRD tMRD tMRD See note 17 EMR(2) EMR(3) EMR MR without DLL RESET MR with DLL RESET EMR with OCD default EMR with OCD exit 200 cycles of CK are required before a READ command can be issued. Indicates a break in time scale AS4DDR264M72PBG1 Rev. 3.1 01/10 Normal operation Don’t care Micross Components reserves the right to change products or specifications without notice. 5 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 NOTES: 1. Applying power; if CKE is maintained below 0.2 x VCC, outputs remain disabled. To guarantee RTT (ODT resistance) is off, VREF must be valid and a low level must be applied to the ODT ball (all other inputs may be undefined, I/Os and outputs must be less than VCC during voltage ramp time to avoid DDR2 SDRAM device latch-up). VTT is not applied directly to the device; however, tVTD should be ³0 to avoid device latch-up. At least one of the following two sets of conditions (A or B) must be met to obtain a stable supply state (stable supply defined as VCC, VREF, and VTT are between their minimum and maximum values as stated in DC Operating Conditions table): 6. Issue a LOAD MODE command to the EMR(3). To issue an EMR(3) command, provide HIGH to BA0 and BA1; remaining EMR(3) bits must be “0.” See “Extended Mode Register 3 (EMR 3)” on page 13 for all EMR(3) requirements. 7. Issue a LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE command, provide LOW to BA1 and A0; provide HIGH to BA0; bits E7, E8, and E9 can be set to “0” or “1;” Austin recommends setting them to “0;” remaining EMR bits must be “0. ”See “Extended Mode Register (EMR)” on page 10 for all EMR requirements. 8. Issue a LOAD MODE command to the MR for DLL RESET. 200 cycles of clock input is required to lock the DLL. To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA1 and BA0; CKE must be HIGH the entire time the DLL is resetting; remaining MR bits must be “0.” See “Mode Register (MR)” on page 7 for all MR requirements. 9. Issue PRECHARGE ALL command. 10. Issue two or more REFRESH commands. 11. Issue a LOAD MODE command to the MR with LOW to A8 to initialize device operation (that is, to program operating parameters without resetting the DLL). To access the MR, set BA0 and BA1 LOW; remaining MR bits must be set to desired settings. See “Mode Register (MR)” on page 7 for all MR requirements. 12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and E9 to “1,” and then setting all other desired parameters. To access the EMR, set BA0 LOW and BA1 HIGH (see “Extended Mode Register (EMR)” on page 10 for all EMR requirements). 13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9 to “0,” and then setting all other desired parameters. To access the extended mode registers, EMR, set BA0 LOW and BA1 HIGH for all EMR requirements. 14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after the DLL RESET at Tf0. 15. DM represents UDM, LDM collectively for each die x16 configuration. DQS represents UDQS, USQS, LDQS, LDQS for each die x16 configuration. DQ represents DQ0-DQ15 for each die x16 configuration. 16. Wait a minimum of 400ns then issue a PRECHARGE ALL command. A. (single power source) The VCC voltage ramp from 300mV to VCC(MIN) must take no longer than 200ms. • All VCC are driven from a single power converter output • VTT is limited to 0.95V MAX • VREF tracks VCC/2; VREF must be within ±0.3V with respect to VCC/2 during supply ramp time. • VCC > VREF at all times 2. CKE requires LVCMOS input levels prior to state T0 to ensure DQs are High-Z during device power-up prior to VREF being stable. After state T0, CKE is required to have SSTL_18 input levels. Once CKE transitions to a high level, it must stay HIGH for the duration of the initialization sequence. 3. A10 = PRECHARGE ALL, CODE = desired values for mode registers (bank addresses are required to be decoded). 4. For a minimum of 200μs after stable power and clock (CK, CK#), apply NOP or DESELECT commands, then take CKE HIGH. 5. Issue a LOAD MODE command to the EMR(2). To issue an EMR(2) command, provide LOW to BA0, and provide HIGH to BA1; set register E7 to “0” or “1” to select appropriate self refresh rate; remaining EMR(2) bits must be “0” (see “Extended Mode Register 2 (EMR2)” on page 84 for all EMR(2) requirements). AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 6 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 MODE REGISTER (MR) FIGURE 5 – MODE REGISTER (MR) DEFINITION The mode register is used to define the specific mode of operation of the DDR2 SDRAM. This definition includes the selection of a burst length, burst type, CL, operating mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 5. Contents of the mode register can be altered by re-executing the LOAD MODE (LM) command. If the user chooses to modify only a subset of the MR variables, all variables (M0–M14) must be programmed when the command is issued. 21 12 BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16 15 14 n 12 11 10 0 MR WR 01 PD 9 8 1 Slow exit (low power) M11 M10 M9 The LM command can only be issued (or reissued) when all banks are in the precharged state (idle state) and no bursts are in progress. The controller must wait the specified time tMRD before initiating any subsequent operations such as an ACTIVE command. Violating either of these requirements will result in unspecified operation. BURST LENGTH M15 M16 Burst length is defined by bits M0–M3, as shown in Figure 5. Read and write accesses to the DDR2 SDRAM are burstoriented, with the burst length being programmable to either four or eight. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. 6 5 4 3 2 1 0 Mode Register (Mx) DLL TM CAS# Latency BT Burst Length M2 M1 M0 Burst Length M7 Mode M12 PD Mode 0 Fast exit (normal) The mode register is programmed via the LM command (bits BA2–BA0 = 0, 0,0) and other bits (M13–M0) will retain the stored information until it is programmed again or the device loses power (except for bit M8, which is selfclearing). Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. 7 Address Bus 0 Normal 0 0 0 Reserved 1 0 0 1 Reserved 0 1 0 4 0 1 1 8 Test M8 DLL Reset 0 No 1 0 0 Reserved 1 Yes 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Write Recovery 0 0 0 Reserved 0 0 1 2 M3 0 1 0 3 0 Sequential 0 1 1 4 1 Interleaved 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 Mode Register Definition 0 0 Mode register (MR) 0 1 Extended mode register (EMR) 1 0 Extended mode register (EMR2) 1 1 Extended mode register (EMR3) M6 M5 M4 Burst Type CAS Latency (CL) 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 Notes: 1.A13 Not used on this part, and must be programmed to ‘0’ on this part. 2.BA2 must be programmed to “0” and is reserved for future use. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. BURST TYPE Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3, as shown in Figure 5. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 2. DDR2 SDRAM supports 4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode, full interleave address ordering is supported; however, sequential address ordering is nibble-based. AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 7 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 TABLE 2 - BURST DEFINITION Burst Length Type = Sequential Type = Interleaved DLL RESET is defined by bit M8, as shown in Figure 5. Programming bit M8 to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of “0” after the DLL RESET function has been issued. A1 A0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 WRITE RECOVERY 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Write recovery (WR) time is defined by bits M9-M11, as shown in Figure 5. The WR register is used by the DDR2 SDRAM during WRITE with auto precharge operation. During WRITE with auto precharge operation, the DDR2 SDRAM delays the internal auto precharge operation by WR clocks (programmed in bits M9-M11) from the last data burst. 4 8 DLL RESET Order of Accesses Within a Burst Starting Column Address Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. NOTES: 1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column within the block. 2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column within the block. 3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting column within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. WR values of 2, 3, 4, 5, 6 or 7 clocks may be used for programming bits M9-M11. The user is required to program the value of WR, which is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non integer value to the next integer; WR [cycles] = tWR [ns] / tCK [ns]. Reserved states should not be used as unknown operation or incompatibility with future versions may result. OPERATING MODE The normal operating mode is selected by issuing a command with bit M7 set to “0” and all other bits set to the desired values, as shown in Figure 5. When bit M7 is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1” places the DDR2 SDRAM into a test mode that is only used by the manufacturer and should not be used. No operation or functionality is guaranteed if M7 bit is “1.” POWER-DOWN MODE Active power-down (PD) mode is defined by bit M12, as shown in Figure 5. PD mode allows the user to determine the active power-down mode, which determines performance versus power savings. PD mode bit M12 does not apply to precharge PD mode. When bit M12 = 0, standard active PD mode or “fast-exit” active PD mode is enabled. The tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to be enabled and running during this mode. When bit M12 = 1, a lower-power active PD mode or “slowexit” active PD mode is enabled. The tXARD parameter is used for slow-exit active PD exit timing. The DLL can be enabled, but “frozen” during active PD mode since the exit-to-READ command timing is relaxed. The power difference expected between PD normal and PD low-power mode is defined in the ICC table. AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 8 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 CAS LATENCY (CL) The CAS latency (CL) is defined by bits M4-M6, as shown in Figure 5. CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CL can be set to 3, 4, 5, 6 or 7 clocks, depending on the speed grade option being used. DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This feature allows the READ command to be issued prior to tRCD (MIN) by delaying the internal command to the DDR2 SDRAM by AL clocks. DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Examples of CL = 3 and CL = 4 are shown in Figure 6; both assume AL = 0. If a READ command is registered at clock edge n, and the CL is m clocks, the data will be available nominally coincident with clock edge n+m (this assumes AL = 0). FIGURE 6 - CAS LATENCY (CL) T0 T1 T2 T3 T4 T5 T6 READ NOP NOP NOP NOP NOP NOP CK# CK Command DQS, DQS# DO n DQ DO n+1 DO n+2 DO n+3 CL = 3 (AL = 0) T0 T1 T2 T3 T4 T5 T6 READ NOP NOP NOP NOP NOP NOP CK# CK Command DQS, DQS# DO n DQ DO n+1 DO n+2 DO n+3 CL = 4 (AL = 0) Transitioning data Notes: Don’t care 1. BL = 4. 2. Posted CAS# additive latency (AL) = 0. 3. Shown with nominal tAC, tDQSCK, and tDQSQ. Extended Mode Register (EMR) AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 9 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 EXTENDED MODE REGISTER (EMR) until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, on die termination (ODT) (RTT), posted AL, off-chip driver impedance calibration (OCD), DQS# enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These functions are controlled via the bits shown in Figure 7. The EMR is programmed via the LOAD MODE (LM) command and will retain the stored information The EMR must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could esult in unspecified operation. FIGURE 7 – EXTENDED MODE REGISTER DEFINITION 1 2 BA23 BA1 BA0 An2 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 16 0 A1 A0 8 7 6 5 4 3 2 1 0 15 14 n 12 11 10 9 MRS 02 Out RDQS DQS# OCD Program RTT Posted CAS# RTT ODS DLL Address bus Extended mode register (Ex) E12 Outputs E0 DLL Enable 0 Enabled E6 E2 RTT (Nominal) 0 Enable (normal) 1 Disabled 0 0 RTT disabled 1 Disable (test/debug) 0 1 75: 1 0 150: E1 1 1 50: 0 E11 RDQS Enable 0 No 1 Yes 1 Full(100%) Reduced(40-60%) 4 E5 E4 E3 Posted CAS# Additive Latency (AL) E10 DQS# Enable 0 Enable 0 0 0 0 1 Disable 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 Reserved E9 E8 E7 OCD Operation E15 E14 Output Drive Strength 0 0 0 OCD exit 0 0 1 Reserved 0 1 0 Reserved 1 0 0 Reserved 1 1 1 Enable OCD defaults Mode Register Set 0 0 Mode register (MR) 0 1 Extended mode register (EMR) 1 0 Extended mode register (EMR2) 1 1 Extended mode register (EMR3) Notes: 1.During initialization, all three bits must be set to “1” for OCD default state, then must be set to “0” before initialization is finished, as detailed in the initialization procedure. 2.E13 (A13) must be programmed to “0” and is reserved for future use. 3.E16 must be programmed to “0” and is reserved for future use. 4.Not all AL options are supported in any individual speed grade. AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 10 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 OUTPUT ENABLE/DISABLE DLL ENABLE/DISABLE The DLL may be enabled or disabled by programming bit E0 during the LM command, as shown in Figure 7. The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using an LM command. The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 7. When enabled (E12 = 0), all outputs (DQs, DQS, DQS#, RDQS, RDQS#) function normally. When disabled (E12 = 1), all DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS, RDQS#) are disabled, thus removing output buffer current. The output disable feature is intended to be used during ICC characterization of read current. The DLL is automatically disabled when entering SELF REFRESH operation and is automatically re-enabled and reset upon exit of SELF REFRESH operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a READ command can be issued, to allow time for the internal clock to synchronize with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. ON-DIE TERMINATION (ODT) ODT effective resistance, RTT (EFF), is defined by bits E2 and E6 of the EMR, as shown in Figure 7. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DDR2 SDRAM controller to independently turn on/off ODT for any or all devices. RTT effective resistance values of 50Ω, 75Ω, and 150Ω are selectable and apply to each DQ, DQS/DQS#, RDQS/ RDQS#, UDQS/UDQS#, LDQS/LDQS#, DM, and UDM/ LDM signals. Bits (E6, E2) determine what ODT resistance is enabled by turning on/off “sw1,” “sw2,” or “sw3.” The ODT effective resistance value is elected by enabling switch “sw1,” which enables all R1 values that are 150Ω each, enabling an effective resistance of 75Ω (RTT2(EFF) = R2/2). Similarly, if “sw2” is enabled, all R2 values that are 300Ω each, enable an effective ODT resistance of 150Ω (RTT2(EFF) = R2/2). Switch “sw3” enables R1 values of 100Ω enabling effective resistance of 50Ω Reserved states should not be used, as unknown operation or incompatibility with future versions may result. OUTPUT DRIVE STRENGTH The output drive strength is defined by bit E1, as shown in Figure 7. The normal drive strength for all outputs are specified to be SSTL_18. Programming bit E1 = 0 selects normal (full strength) drive strength for all outputs. Selecting a reduced drive strength option (E1 = 1) will reduce all outputs to approximately 45-60 percent of the SSTL_18 drive strength. This option is intended for the support of lighter load and/or point-to-point environments. DQS# ENABLE/DISABLE The ODT control ball is used to determine when RTT(EFF) is turned on and off, assuming ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input ball are only used during active, active power-down (both fast-exit and slow-exit modes), and precharge powerdown modes of operation. ODT must be turned off prior to entering self refresh. During power-up and initialization of the DDR2 SDRAM, ODT should be disabled until issuing the EMR command to enable the ODT feature, at which point the ODT ball will determine the RTT(EFF) value. Any time the EMR enables the ODT function, ODT may not be driven HIGH until eight clocks after the EMR has been enabled. See “ODT Timing” section for ODT timing diagrams. The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the differential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a single ended mode and the DQS# ball is disabled. When disabled, DQS# should be left floating. This function is also used to enable/disable RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled (E10 = 0), then both DQS# and RDQS# will be enabled. AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 11 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 POSTED CAS ADDITIVE LATENCY (AL) Posted CAS additive latency (AL) is supported to make the command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as shown in Figure 7. Bits E3–E5 allow the user to program the DDR2 SDRAM with an inverse AL of 0, 1, 2, 3, 4, 5 or 6 clocks. Reserved states should not be used as unknown operation or incompatibility with future versions may result. In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued prior to tRCD (MIN) with the requirement that AL = tRCD (MIN). A typical application using this feature would set AL = tRCD (MIN) - 1x tCK. The READ or WRITE command is held for the time of the AL before it is issued internally to the DDR2 SDRAM device. RL is controlled by the sum of AL and CL; RL = AL+CL. Write latency (WL) is equal to RL minus one clock; WL = AL + CL - 1 x tCK. FIGURE 8 - EXTENDED MODE REGISTER 2 (EMR2) DEFINITION 1 2 BA2 BA1 BA0 An1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 16 0 E15 E14 15 14 n MRS 0 12 11 0 0 10 9 8 7 6 0 0 SRT 0 0 5 4 3 2 0 0 0 0 A1 A0 1 0 0 0 Mode Register Set E7 SRT Enable 1X refresh rate (0°C to 85°C) 2X refresh rate (>85°C) 0 0 Mode register (MR) 0 0 1 Extended mode register (EMR) 1 1 0 Extended mode register (EMR2) 1 1 Extended mode register (EMR3) Address bus Extended mode register (Ex) Notes: 1.E16 bit (BA2) must be programmed to “0” and is reserved for future use. 2.Mode bits (En) with corresponding address balls (An) greater than A12 are reserved for future use and must be programmed to “0.” AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 12 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 FIGURE 9 - EXTENDED MODE REGISTER 3 (EMR3) DEFINITION 1 2 BA22 BA1 BA0 An1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 16 15 14 n 12 11 10 0 MRS 0 0 E15 E14 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 A1 A0 1 0 0 0 Address bus Extended mode register (Ex) Mode Register Set 0 0 0 1 Extended mode register (EMR) 1 0 Extended mode register (EMR2) 1 1 Extended mode register (EMR3) Mode register (MR) Notes: Notes: E16 (BA2)address is onlyballs applicable for densities >1Gb, for is reserved formust future use, and must 1.Mode bits (En) with1.corresponding (An) greater than A12 are reserved future use and be programmed to “0.” 2.E16 (BA2) must be programmed to “0” on this device and is reserved for future use. be pro- EXTENDED MODE REGISTER 2 The extended mode register 2 (EMR2) controls functions beyond those controlled by the mode register. Currently all bits in EMR2 are reserved, as shown in Figure 8. The EMR2 is programmed via the LM command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. EMR3 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specifi ed time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. COMMAND TRUTH TABLES The following tables provide a quick reference of DDR2 SDRAM available commands, including CKE power-down modes, and bank-to-bank commands. EMR2 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. EXTENDED MODE REGISTER 3 The extended mode register 3 (EMR3) controls functions beyond those controlled by the mode register. Currently, all bits in EMR3 are reserved, as shown in Figure 9. The EMR3 is programmed via the LM command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 13 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 TABLE 3 - TRUTH TABLE - DDR2 COMMANDS CKE Function RAS# CAS# WE# BA2 thru Previous Cycle Current Cycle CS# LOAD MODE H H L L L L BA REFRESH H H L L L H X X X X SELF-REFRESH Entry H L X X X X X X X X 7 2 BA0 L L L H H X X X L H H H A12 A11 A10 A9-A0 OP CODE Notes 2 SELF-REFRESH exit L H Single Bank Precharge H H L L H L X X L X All banks PRECHARGE H H L L H L X X H X Bank Activate H H L L H L BA ROW ADDRESS Column Address Column Address Column Address Column Address L Column Address Column Address Column Address Column Address 2,3 WRITE H H L L H L BA WRITE with auto precharge H H L H L L BA READ H H L H L H BA READ with auto precharge H H L H L H BA NO OPERATION H X L H H H X X X X Device DESELECT H X H X X X X X X X H X X X L H H H X X X X 4 X X X X 4 POWER-DOWN entry H L POWER-DOWN exit L H H X X X L H H H H L L 2,3 2,3 2,3 Note: 1. All DDR2-SDRAM commands are defined by staes of CS#, RAS#, CAS#, WE#, and CKE a the rising edge of the clock. 2. Bank addresses (BA) BA2-BA0 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed. 3. Burst reads or writes at BL=4 cannot be terminated or interrupted. 4. The power down mode does not perform any REFRESH operations. The duration of power down is therefore limited by the refresh requirements outlined in the AC parametric section. 5. The state of ODT does not effect the states described in this table. The ODT function is not available during self refresh. See “On Die Termination (ODT)” for details. 6. “X” means “H or L” (but a defined logic level) 7. Self refresh exit is asynchronous. AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 14 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC NO OPERATION (NOP) A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE (LM) The mode registers are loaded via inputs BA2–BA0, and A12–A0. BA2–BA0 determine which mode register will be programmed. See “Mode Register (MR)”. The LM command can only be issued when all banks are idle, and a subsequent execute able command cannot be issued until tMRD is met. FIGURE 10 - ACTIVE COMMAND CK# BANK/ROW ACTIVATION ACTIVE COMMAND CK The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA2–BA0 inputs selects the bank, and the address provided on inputs A12–A0 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. CKE CS# RAS# CAS# ACTIVE OPERATION Before any READ or WRITE commands can be issued to a bank within the DDR2 SDRAM, a row in that bank must be opened (activated), even when additive latency is used. This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. WE# After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. The same procedure is used to convert other specification limits from time units to clock cycles. For example, a tRCD (MIN) specification of 20ns with a 266 MHz clock (tCK = 3.75ns) results in 5.3 clocks, rounded up to 6. AS4DDR264M72PBG1 Rev. 3.1 01/10 ADDRESS Row BANK ADDRESS Bank DON’T CARE Micross Components reserves the right to change products or specifications without notice. 15 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 READ COMMAND The READ command is used to initiate a burst read access to an active row. The value on the BA2–BA0 inputs selects the bank, and the address provided on inputs A0–i (where i = A9) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. FIGURE 11 - READ COMMAND READ OPERATION READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. If auto precharge is disabled, the row will be left open after the completion of the burst. CK# CK CKE CS# During READ bursts, the valid data-out element from the starting column address will be available READ latency (RL) clocks later. RL is defined as the sum of AL and CL; RL = AL + CL. The value for AL and CL are programmable via the MR and EMR commands, respectively. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (i.e., at the next crossing of CK and CK#). RAS# CAS# WE# DQS/DQS# is driven by the DDR2 SDRAM along with output data. The initial LOW state on DQS and HIGH state on DQS# is known as the read preamble (tRPRE). The LOW state on DQS and HIGH state on DQS# coincident with the last data-out element is known as the read postamble (tRPST). ADDRESS ENABLE AUTO PRECHARGE A10 DISABLE Upon completion of a burst, assuming no other commands have been initiated, the DQ will go High-Z. BANK ADDRESS Data from any READ burst may be concatenated with data from a subsequent READ command to provide a continuous flow of data. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued x cycles after the first READ command, where x equals BL / 2 cycles. AS4DDR264M72PBG1 Rev. 3.1 01/10 Col Bank DON’T CARE Micross Components reserves the right to change products or specifications without notice. 16 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 WRITE COMMAND The WRITE command is used to initiate a burst write access to an active row. The value on the BA2–BA0 inputs selects the bank, and the address provided on inputs A0–9 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. The time between the WRITE command and the fi rst rising DQS edge is WL ± tDQSS. Subsequent DQS positive rising edges are timed, relative to the associated clock edge, as ± tDQSS. tDQSS is specified with a relatively wide range (25 percent of one clock cycle). All of the WRITE diagrams show the nominal case, and where the two extreme cases (tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will be ignored. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide continuous flow of input data. The fi rst data element from the new burst is applied after the last element of a completed burst. The new WRITE command should be issued x cycles after the first WRITE command, where x equals BL/2. WRITE OPERATION WRITE bursts are initiated with a WRITE command, as shown in Figure 12. DDR2 SDRAM uses WL equal to RL minus one clock cycle [WL = RL - 1CK = AL + (CL - 1CK)]. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. DDR2 SDRAM supports concurrent auto precharge options, as shown in Table 4. DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4 operation. Once the BL = 4 WRITE command is registered, it must be allowed to complete the entire WRITE burst cycle. However, a WRITE (with auto precharge disabled) using BL = 8 operation might be interrupted and truncated ONLY by another WRITE burst as long as the interruption occurs on a 4-bit boundary, due to the 4n prefetch architecture of DDR2 SDRAM. WRITE burst BL = 8 operations may not to be interrupted or truncated with any command except another WRITE command. During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is known as the write postamble. AS4DDR264M72PBG1 Rev. 3.1 01/10 Data for any WRITE burst may be followed by a subsequent READ command. The number of clock cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is greater. Data for any WRITE burst may be followed by a subsequent PRECHARGE command. tWT starts at the end of the data burst, regardless of the data mask condition. Micross Components reserves the right to change products or specifications without notice. 17 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 FIGURE 12 - WRITE COMMAND CK# CK CKE HIGH CS# RAS# CAS# WE# CA ADDRESS EN AP A10 DIS AP BANK ADDRESS BA DON’T CARE Note: CA = column address; BA = bank address; EN AP = enable auto precharge; and DIS AP = disable auto precharge. TABLE 4 - WRITE USING CONCURRENT AUTO PRECHARGE From Command (Bank n ) WRITE with Auto Precharge AS4DDR264M72PBG1 Rev. 3.1 01/10 Minimum Delay (With Concurrent Auto Precharge) (CL-1) + (BL/2) + tWTR READ OR READ w/ AP WRITE OR WRITE w/ AP (BL/2) PRECHARGE or ACTIVE 1 To Command (Bank m ) Units t CK CK t CK t Micross Components reserves the right to change products or specifications without notice. 18 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 PRECHARGE COMMAND The PRECHARGE command, illustrated in Figure 13, is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation a specified time (tRP) after the PRECHARGE command is issued, except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE command issued to the bank. FIGURE 13 – PRECHARGE COMMAND CK# CK CKE HIGH CS# RAS# CAS# WE# PRECHARGE OPERATION Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA2–BA0 select the bank. Otherwise BA2–BA0 are treated as “Don’t Care.” When all banks are to be precharged, inputs BA2–BA0 are treated as “Don’t Care.” ADDRESS ALL BANKS A10 ONE BANK Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of the number of banks already open or closed. If a single-bank PRECHARGE command is issued, tRP timing applies. BA2,- BA0 BA DON’T CARE Note: BA = bank address (if A10 is LOW; otherwise "Don't Care"). issued). The differential clock should remain stable and meet tCKE specifications at least 1 x tCK after entering self refresh mode. All The SELF REFRESH command can be used to retain data in command and address input signals except CKE are “Don’t Care” the DDR2 SDRAM, even if the rest of the system is powered during self refresh. down. When in the self refresh mode, the DDR2 SDRAM retains data without external clocking. All power supply inputs The procedure for exiting self refresh requires a sequence of (including VREF) must be maintained at valid levels upon entry/ commands. First, the differential clock must be stable and meet tCK specifications at least 1 x tCK prior to CKE going back HIGH. exit and during SELF REFRESH operation. Once CKE is HIGH (tCLE(MIN) has been satisfied with four clock The SELF REFRESH command is initiated like a registrations), the DDR2 SDRAM must have NOP or DESELECT REFRESH command except CKE is LOW. The DLL is commands issued for tXSNR because time is required for the automatically disabled upon entering self refresh and is completion of any internal refresh in progress. A simple algorithm automatically enabled upon exiting self refresh (200 clock for meeting both refresh and DLL requirements is to apply NOP cycles must then occur before a READ command can be or DESELECT commands for 200 clock cycles before applying any other command. SELF REFRESH COMMAND Note: Self refresh not available at military temperature. AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 19 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 RESET FUNCTION (CKE LOW Anytime) DDR2 SDRAM applications may go into a reset state anytime during normal operation. If an application enters a reset condition, CKE is used to ensure the DDR2 SDRAM device resumes normal operation after reinitializing. All data will be lost during a reset condition; however, the DDR2 SDRAM device will continue to operate properly if the following conditions outlined in this section are satisfied. If CKE asynchronously drops LOW during any valid operation (including a READ or WRITE burst), the memory controller must satisfy the timing parameter tDELAY before turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM before CKE is raised HIGH, at which time the normal initialization sequence must occur. The DDR2 SDRAM device is now ready for normal operation after the initialization sequence. The reset condition defined here assumes all supply voltages (VDD, VDDQ and VREF) are stable and meet all DC specifications prior to, during, and after the RESET operation. All other input pins of the DDR2 SDRAM device are a “Don’t Care” during RESET with the exception of CKE. AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 20 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 DC OPERATING CONDITIONS Parameter Supply Voltage Symbol VCC MIN TYP MAX Units 1.7 1.8 1.9 V Notes I/O Reference Voltage VREF 0.49 x VCC 0.50 x VCC 0.51 x VCC V 1 I/O Termination Voltag VTT VREF - 0.04 VREF VREF + 0.04 V 2 1. VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ± 1 percent of the DC value. Peak-topeak AC noise on VREF may not exceed ±2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. ABSOLUTE MAXIMUM RATINGS Parameter Min Max Unit VCC Voltage on VCC pin relative to V SS -1.0 2.3 V VIN, VOUT Voltage on any pin relative to V SS -0.5 2.3 TSTG Storage Temperature -55.0 125.0 TCASE Device Operating Temperature -55.0 125.0 Symbol II IOZ IVREF Input Leakage current; Any input 0V<VIN<VCC; VREF = .5XVCC; Other balls not under test = 0V V C o o C ADDR, BAx -10.0 10.0 uA RAS\, CAS\, WE\, CS\, CKE, DM, DQS, DQS\, RDQS -5 5 uA CK, CK\ -5 5 uA DM -5 5 uA OV VOUT VDD, DQ & ODT Disabled -5 5 uA VREF Leakage Current -10 10 uA INPUT / OUTPUT CAPACITANCE TA = 25oC, f = 1 MHz, VCC = 1.8V Parameter Input capacitance (A0-A12, BA0-BA2, CS\, RAS\, CAS\, WE\, CKE, ODT) Symbol CADDR Max 25 Unit pF Input capacitance CK, CK# CIN2 8 pF Input capacitance DM, DQS, DQS# CIN3 10 pF Input capacitance DQ0-71 COUT 12 pF AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 21 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 INPUT DC LOGIC LEVEL All voltages referenced to Vss Parameter Input High (Logic 1) Voltage Symbol VIH (DC) Min VREF + 0.125 Max VCC + 0.3001 Unit V Input Low (Logic 0) Voltage VIL (DC) -0.300 VREF - 0.125 V Note 1: 300mV is allowed provided Vcc does not exceed 1.9V INPUT AC LOGIC LEVEL All voltages referenced to Vss Parameter AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533 Symbol VIH (AC) Min VREF + 0.250 Max VCC+0.3001 Unit V AC Input High (Logic 1) Voltage DDR2-667 VIH (AC) VREF + 0.200 VCC+0.3001 V ACInput Low (Logic 0) Voltage DDR2-400 & DDR2-533 VIL (AC) -0.3 VREF - 0.250 V AC Input Low (Logic 0) Voltage DDR2-667 VIL (AC) -0.3 VREF - 0.200 V Note 1: 300mV is allowed provided Vcc does not exceed 1.9V AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 22 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 DDRII ICC SPECIFICATIONS AND CONDITIONS Parameter Operating Current: One bank active-precharge tCL=tCK(ICC), tRC=tRC(ICC), tRAS=tRAS MIN(ICC); CKE is HIGH, CS\ is HIGH between valid commands; Address bus switching, Data bus switching Operating Current: One bank active-READ-precharge current IOUT=0ma; BL=4, CL=CL(ICC), AL=0; tCK = tCK(ICC), tRCtRC(ICC), tRAS=tRAS MIN(ICC), tRCD=tRCD(ICC); CKE is HIGH, CS\ is HIGH between valid commands; Address bus is switching; Data bus is switching Precharge POWER-DOWN current All banks idle; tCK-tCK(ICC); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Symbol 667 MHZ -3 533 MHZ -38 400 MHZ -5 Units ICC0 660 600 550 mA ICC1 750 650 600 mA ICC2P 35 35 35 mA ICC2Q 300 250 195 mA ICC2N 330 275 220 mA 150 125 115 50 50 50 ICC3N 300 250 200 mA ICC4W 850 700 600 mA ICC4R 850 700 600 mA ICC5 1250 1100 1000 mA ICC6 35 35 35 mA ICC7 1700 1600 1500 mA Precharge quiet STANDBY current All banks idle; tCK=tCK(ICC); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge STANDBY current All banks idle; tCK-=tCK(ICC); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active POWER-DOWN current MRS[12]=0 All banks open; tCK=tCK(ICC); CKE is LOW; Other control and address inputs are stable; Data bus inputs are floating ICC3P mA MRS[12]=1 Active STANDBY current All banks open; tCK=tCK(ICC), tRAS MAX(ICC), tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating Burst WRITE current All banks open, continuous burst writes; BL=4, CL=CL(ICC), tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH betwwn valid commands; Address bus inputs are switching; Data bus Operating Burst READ current All banks open, continuous burst READS, Iout=0mA; BL=4, CL=CL(ICC), AL=0; tCL=tCK(ICC), tRAS=tRAS MAX(ICC), tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH betwwn valid commands; Address and Data bus inputs switching Burst REFRESH current tCK=tCK(ICC); refresh command at every iRFC(ICC) interval; CKE is HIGH, CS\ is HIGH Between valid commands; Address bus inputs are switching; Data bus inputs are switching Self REFRESH current CK and CK\ at 0V; CKE </=0.2V; Other contro, address and data inputs are floating Operating bank Interleave READ current: All bank interleaving READS, IOUT = 0mA; BL=4, CL=CL(ICC), AL=tRCD(ICC)-1xtCK(ICC); tCK=tCK(ICC), tRC=tRC(ICC), tRRD=tRRD(ICC); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 23 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 AC OPERATING SPECIFICATIONS Parameter Clock Clock Cycle Time Clock Jitter DATA Symbol tCKAVG CL=4 tCKAVG CL=3 Clock High Time Clock Low Time Half Clock Period Clock Jitter - Period DATA Strobe CL=5 Min of Clock Jitter - Half Period Clock Jitter - Cycle to Cycle -3 667MHz MIN MAX 3 8 3.75 8 -38 533MHz MIN MAX -5 400MHz MIN MAX Units ns 3.75 8 5 8 ns tCKAVG 5 8 5 8 5 8 ns tCHAVG 0.48 0.52 0.48 0.52 0.48 0.52 tCK tCLAVG tHP tJITPER 0.48 0.52 0.48 0.52 0.48 0.52 tCH,tCL -125 125 -125 125 -125 125 tCK ps ps tJIT DUTY -125 125 -125 125 -150 150 ps tJITCC tCH,tCL 250 tCH,tCL 250 250 ps tERR2PER -175 175 -175 175 -175 175 ps Cumulative Jitter error, 4 Cycles tERR4PER -250 250 -250 250 -250 250 ps Cumulative Jitter error, 6-10 Cycles tERR10PER -350 350 -350 350 -350 350 ps Cumulative Jitter error, 11-50 Cycles DQ hold skew factor DQ output access time from CK/CK\ Data-out High-Z window from CK/CK\ DQS Low-Z window from CL/CK\ tERR50PER tQHS tAC tHZ tLZ1 -450 -450 450 340 450 -450 -500 450 400 500 -450 -600 450 450 600 tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) ps ps ps ps ps tAC(MAX) 2*tAC(MIN) tAC(MAX) 2*tAC(MIN) tAC(MAX) Cumulative Jitter error, 2 Cycles tAC(MAX) tAC(MAX) tAC(MAX) tLZ2 2*tAC(MIN) DQ and DM input setup time relative to DQS tDSJEDEC 100 100 150 ps DQ and DM input hold time relative to DQS DQ and DM input pulse width (for each input) Data Hold skew factor DQ-DQS Hold, DQS to first DQ to go non valid, per access Data valid output window (DVW) DQS input-high pulse width DQS input-low pulse width DQS output access time from CK/CK\ DQS falling edge to CK rising - setup time DQS falling edge from CK rising-hold time DQS-DQ skew, DQS to last DQ valid, per group, per access DQS READ preamble DQS READ postamble WRITE preamble setup time DQS WRITE preamble DQS WRITE postamble Positive DQS latching edge to associated Clock edge WRITE command to first DQS latching transition tDHJEDEC tDIPW tQHS tQH tDVW tDQSH tDQSL tDQSCK tDSS tDSH tDQSQ tRPRE tRPST tWPRES tWPRE tWPST tDQSS 175 0.35 225 0.35 275 0.35 ps tCK ps ps ps tCK tCK ps tCK tCK ps tCK tCK ps tCK tCK tCK tCK DQ Low-Z window from CK/CK\ AS4DDR264M72PBG1 Rev. 3.1 01/10 340 400 450 tHP-tQHS tHP-tQHS tHP-tQHS tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ 0.35 0.35 -400 0.2 0.2 0.35 0.35 -400 0.2 0.2 0.35 0.35 -450 0.2 0.2 0.9 0.4 0 0.35 0.4 -0.25 400 240 1.1 0.6 0.6 0.25 0.9 0.4 0 0.35 0.4 -0.25 400 300 1.1 0.6 0.6 0.25 0.9 0.4 0 0.35 0.4 -0.25 450 350 1.1 0.6 0.6 0.25 WL-tDQSS WL+tDQSS WL-tDQSS WL+tDQSS WL-tDQSS WL+tDQSS ps Micross Components reserves the right to change products or specifications without notice. 24 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 AC OPERATING SPECIFICATIONS (CONTINUED) Parameter Address and Control input puslse width for each input PWRDN ODT S. REFRESH REFRESH COMMAND and ADDRESS Address and Control input setup time Symbol tIPW tISJEDEC -3 667Mbps MIN MAX 0.6 -38 533Mbps MIN MAX 0.6 -5 400Mbps MIN MAX 0.6 200 250 350 ps 275 2 55 10 15 50 40 7.5 15 375 2 55 10 15 50 40 7.5 15 475 2 55 10 15 50 40 7.5 15 ps tCK ns ns ns ns ns ns ns ns ns ns ns tCK ns Address and Control input hold time CAS\ to CAS\ command delay ACTIVE to ACTIVE command (same bank) ACTIVE bank a to ACTIVE bank b Command ACTIVE to READ or WRITE delay 4-Bank activate period ACTIVE to PRECHARGE Internal READ to PRECHARGE command delay WRITE recovery time Auto PRECHARGE WRITE recovery+PRECHARGE time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE, command Cycle time CKE LOW to CK, CK\ uncertainty REFRESH to ACTIVE or REFRESH to REFRESH command Interval Average periodic REFRESH interval [Industrial temp] tIHJEDEC tCCD tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL tWTR tRP tRPA tMRD tDELAY tREFIIT 7.8 Average periodic REFRESH interval [Enhanced temp] tREFIET 5.9 Average periodic REFRESH interval [Military temp] Exit SELF REFRESH to non READ command tREFIXT 3.9 Exit SELF REFRESH to READ command Exit SELF REFRESH timing reference 700001 700001 tWR + tRP tWR + tRP tWR + tRP 7.5 15 7.5 15 10 15 tRP+tCL tRP+tCL tRP+tCL 2 2 2 tIS + tCL + tIH tRFC 127 70000 1 tIS + tCL + tIH 127 70000 1 700001 tIS + tCL + tIH Units tCK 70000 1 ns 7.8 7.8 us 5.9 5.9 us 3.9 3.9 us 127 tXSNR tRFC(min)+1 0 tRFC(min)+1 0 tRFC(min)+1 0 ns tXSRD 200 200 200 tCK tISXR tIS ODT turn-on delay tAOND 2 2 tIS 2 2 2 2 ODT turn-on delay tAOND tAC(min) tAC(max)+ 700 tAC(min) tAC(max)+ 1000 tAC(min) tAC(max)+ 1000 ps ODT turn-off delay tAOPD 2.5 2.5 2.5 2.5 2.5 2.5 tCK ODT turn-off delay tAOF tAC(min) tAC(max)+ 600 tAC(min) tAC(max)+ 600 tAC(min) tAC(max)+ 600 ps tAC(min) + 2000 2 x tCK + tAC(max)+ 1000 tAC(min) + 2000 2 x tCK + tAC(max)+ 1000 ps tAC(min) + 2000 2.5 x tCK + tAC(max)+ 1000 tAC(min) + 2000 2.5 x tCK + tAC(max)+ 1000 ps ODT turn-on (power-down mode) tAONPD tAC(min) + 2000 2 x tCK + tAC(max)+ 1000 ODT turn-off (power-down mode) tAOFPD tAC(min) + 2000 2.5 x tCK + tAC(max)+ 1000 ODT to power-down entry latency ODT power-down exit latency ODT enable from MRS command Exit active POWER-DOWN to READ command, MR[12]=0 Exit active POWER-DOWN to READ command, MR[12]=1 Exit PRECHARGE POWER-DOWN to any non READ CKE Min. HIGH/LOW time tANPD tAXPD tMOD tXARD tSARDS tXP tCLE tIS 3 8 12 2 3 8 12 2 3 8 12 2 7 - AL 6 - AL 6 - AL 2 3 2 3 2 3 ps tCK tCK tCK ns tCK tCK tCK tCK Note 1: Max value reduced to 10,000ns at 125 oC AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 25 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 MECHANICAL DIAGRAM AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 26 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 ORDERING INFORMATION Core Clock Freqency Data Clock Rate Device Grade Availability AS4DDR264M72PBG1-3/IT 333MHz 667Mbs Industrial Consult Factory AS4DDR264M72PBG1-38/IT 266MHz 533Mbs Industrial Consult Factory AS4DDR264M72PBG1-5/IT 200MHZ 400Mbs Industrial Consult Factory AS4DDR264M72PBG1-3/ET 333MHz 667Mbs Enhanced Consult Factory AS4DDR264M72PBG1-38/ET 266MHz 533Mbs Enhanced Consult Factory AS4DDR264M72PBG1-5/ET 200MHZ 400Mbs Enhanced Consult Factory AS4DDR264M72PBG1-3/XT 333MHz 667Mbs Military Consult Factory AS4DDR264M72PBG1-38/XT 266MHz 533Mbs Military Consult Factory AS4DDR264M72PBG1-5/XT 200MHZ 400Mbs Military Consult Factory AS4DDR264M72PBG1R-3/IT 333MHz 667Mbs Industrial - RoHS Consult Factory AS4DDR264M72PBG1R-38/IT 266MHz 533Mbs Industrial - RoHS Consult Factory AS4DDR264M72PBG1R-5/IT 200MHZ 400Mbs Industrial - RoHS Consult Factory AS4DDR264M72PBG1R-3/ET 333MHz 667Mbs Enhanced - RoHS Consult Factory AS4DDR264M72PBG1R-38/ET 266MHz 533Mbs Enhanced - RoHS Consult Factory AS4DDR264M72PBG1R-5/ET 200MHZ 400Mbs Enhanced - RoHS Consult Factory AS4DDR264M72PBG1R-3/XT 333MHz 667Mbs Military - RoHS Consult Factory AS4DDR264M72PBG1R-38/XT 266MHz 533Mbs Military - RoHS Consult Factory AS4DDR264M72PBG1R-5/XT 200MHZ 400Mbs Military - RoHS Consult Factory Part Number IT = Industrial = Industrial class integrated component, fully operable across -40C to +85C ET = Enhanced = Enhanced class integrated component, fully operable across -40C to +105C XT = Military = Mil-Temperature class integrated component, fully operable across -55C to +125C AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or specifications without notice. 27 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 DOCUMENT TITLE 4.8Gb, 64M x 72, DDR2 SDRAM, 16mm x 23mm - 208 PBGA Multi-Chip Package [iPEM] REVISION HISTORY Rev # 0.0 0.5 1.0 1.1 1.5 2.0 2.5 3.0 3.1 AS4DDR264M72PBG1 Rev. 3.1 01/10 History Release Date Initial Release January 2008 Updated Pinout May 2008 Revised part description (pg 1) May 2008 Revised typical weight (pg 1) Reference to compatible part Added configuration addressing table September 2008 to page 1 Updated Drawing December 2008 removed references to VCCQ Updated Drawing January 2009 Updated Drawing April 2009 Updated Drawing* June 2009 *No overall dimensions changed. New product shipped after July 1, 2009 will be with the underfilled package. Changed “Extended” temp reference to “Military” Updated Micross Information January 2010 Status Advance Advance Preliminary Preliminary Preliminary Preliminary Preliminary Preliminary Preliminary Micross Components reserves the right to change products or specifications without notice. 28