TI1 MSP430FR2110IPW16R Mixed-signal microcontroller Datasheet

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MSP430FR2111, MSP430FR2110, MSP430FR2100, MSP430FR2000
SLASE78B – AUGUST 2016 – REVISED JULY 2017
MSP430FR21xx, MSP430FR2000 Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Embedded Microcontroller
– 16-Bit RISC Architecture up to 16 MHz
– Wide Supply Voltage Range (1.8 V to 3.6 V) (1)
• Optimized Low-Power Modes (at 3 V)
– Active Mode: 120 µA/MHz
– Standby
– LPM3.5 With VLO: 1 µA
– Real-Time Clock (RTC) Counter (LPM3.5
With 32768-Hz Crystal): 1 µA
– Shutdown (LPM4.5): 34 nA Without SVS
• High-Performance Analog
– 8-Channel 10-Bit Analog-to-Digital Converter
(ADC)
– Integrated Temperature Sensor
– Internal 1.5-V Reference
– Sample-and-Hold 200 ksps
– Enhanced Comparator (eCOMP)
– Integrated 6-Bit DAC as Reference Voltage
– Programmable Hysteresis
– Configurable High-Power and Low-Power
Modes
• Low-Power Ferroelectric RAM (FRAM)
– Up to 3.75KB of Nonvolatile Memory
– Built-In Error Correction Code (ECC)
– Configurable Write Protection
– Unified Memory of Program, Constants, and
Storage
– 1015 Write Cycle Endurance
– Radiation Resistant and Nonmagnetic
• Intelligent Digital Peripherals
– One 16-Bit Timer With Three Capture/Compare
Registers (Timer_B3)
– One 16-Bit Counter-Only RTC Counter
– 16-Bit Cyclic Redundancy Checker (CRC)
• Enhanced Serial Communications
– Enhanced USCI A (eUSCI_A) Supports UART,
IrDA, and SPI
(1)
Operation voltage is restricted by SVS levels (see VSVSH– and
VSVSH+ in Power Supply Sequencing).
1.2
•
•
•
•
• Clock System (CS)
– On-Chip 32-kHz RC Oscillator (REFO)
– On-Chip 16-MHz Digitally Controlled Oscillator
(DCO) With Frequency-Locked Loop (FLL)
– ±1% Accuracy With On-Chip Reference at
Room Temperature
– On-Chip Very-Low-Frequency 10-kHz Oscillator
(VLO)
– On-Chip High-Frequency Modulation Oscillator
(MODOSC)
– External 32-kHz Crystal Oscillator (LFXT)
– Programmable MCLK Prescalar of 1 to 128
– SMCLK Derived From MCLK With
Programmable Prescalar of 1, 2, 4, or 8
• General Input/Output and Pin Functionality
– 12 I/Os on 16-Pin Package
– 8 Interrupt Pins (4 Pins of P1 and 4 Pins of P2)
Can Wake MCU From LPMs
– All I/Os are Capacitive Touch I/Os
• Development Tools and Software (Also See Tools
and Software)
– Free Professional Development Environments
– Development Kits (MSP-TS430PW20,
MSP‑FET430U20, MSP‑EXP430FR2311, and
MSP‑EXP430FR4133)
• Family Members (Also See Device Comparison)
– MSP430FR2111: 3.75KB of Program FRAM +
1KB of RAM
– MSP430FR2110: 2KB of Program FRAM +
1KB of RAM
– MSP430FR2100: 1KB of Program FRAM +
512 Bytes of RAM
– MSP430FR2000: 0.5KB of Program FRAM +
512 Bytes of RAM
• Package Options
– 16-Pin: TSSOP (PW16)
– 24-Pin: VQFN (RLL)
• For Complete Module Descriptions, See the
MSP430FR4xx and MSP430FR2xx Family User's
Guide
Applications
Appliance Battery Packs
Smoke and Heat Detectors
Door and Window Sensors
Lighting Sensors
•
•
•
Power Monitoring
Personal Care Electronics Portable
Health and Fitness Devices
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FR2111, MSP430FR2110, MSP430FR2100, MSP430FR2000
SLASE78B – AUGUST 2016 – REVISED JULY 2017
1.3
www.ti.com
Description
MSP430FR2000 and MSP430FR21xx devices are part of the MSP430™ microcontroller (MCU) value line
sensing portfolio. This ultra-low-power, low-cost MCU family offers memory sizes from 0.5KB to 4KB of
FRAM unified memory with several package options including a small 3-mm×3-mm VQFN package. The
architecture, FRAM, and integrated peripherals, combined with extensive low-power modes, are optimized
to achieve extended battery life in portable, battery-powered sensing applications. MSP430FR2000 and
MSP430FR21xx devices offer a migration path for 8-bit designs to gain additional features and
functionality from peripheral integration and the data-logging and low-power benefits of FRAM.
Additionally, existing designs using MSP430G2x MCUs can migrate to the MSP430FR2000 and
MSP430F21xx family to increase performance and get the benefits of FRAM.
The MSP430FR2000 and MSP430FR21xx MCUs feature a powerful 16-bit RISC CPU, 16-bit registers,
and a constant generator that contribute to maximum code efficiency. The digitally controlled oscillator
(DCO) also allows the device to wake up from low-power modes to active mode typically in less than
10 μs. The feature set of this MCU meets the needs of applications ranging from appliance battery packs
and battery monitoring to smoke detectors and fitness accessories.
The MSP ultra-low-power (ULP) FRAM microcontroller platform combines uniquely embedded FRAM and
a holistic ultra-low-power system architecture, allowing system designers to increase performance while
lowering energy consumption. FRAM technology combines the low-energy fast writes, flexibility, and
endurance of RAM with the nonvolatile behavior of flash.
MSP430FR2000 and MSP430FR21x MCUs are supported by an extensive hardware and software
ecosystem with reference designs and code examples to get your design started quickly. Development
kits include the MSP-EXP430FR2311 and MSP430FR4133 LaunchPad™ development kit and the
MSP‑TS430PW20 20-pin target development board. TI also provides free MSP430Ware™ software,
which is available as a component of Code Composer Studio™ IDE desktop and cloud versions within TI
Resource Explorer. The MSP430 MCUs are also supported by extensive online collateral, training, and
online support through the E2E™ Community Forum.
Device Information (1)
PART NUMBER
PACKAGE
BODY SIZE (2)
TSSOP (16)
5 mm × 4.4 mm
VQFN (24)
3 mm × 3 mm
MSP430FR2111IPW16
MSP430FR2110IPW16
MSP430FR2100IPW16
MSP430FR2000IPW16
MSP430FR2111IRLL
MSP430FR2110IRLL
MSP430FR2100IRLL
MSP430FR2000IRLL
(1)
(2)
For the most current part, package, and ordering information, see the Package Option Addendum in
Section 9, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
CAUTION
System-level ESD protection must be applied in compliance with the devicelevel ESD specification to prevent electrical overstress or disturbing of data or
code memory. See MSP430™ System-Level ESD Considerations for more
information.
2
Device Overview
Copyright © 2016–2017, Texas Instruments Incorporated
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MSP430FR2111, MSP430FR2110, MSP430FR2100, MSP430FR2000
www.ti.com
1.4
SLASE78B – AUGUST 2016 – REVISED JULY 2017
Functional Block Diagram
Figure 1-1 shows the functional block diagram.
XIN
P1.x, P2.x
XOUT
Cap Touch I/O
LFXT
ADC
FRAM
RAM
eCOMP0
Clock
System
Control
8 channels,
single ended,
10 bit,
200 ksps
(see Note)
3.75KB
2KB
1KB
0.5KB
1KB
512 bytes
With 6-bit
DAC
SYS
CRC16
TB0
eUSCI_A0
16-bit
cyclic
redundancy
check
Timer_B
3 CC
registers
UART,
IrDA, SPI
DVCC
DVSS
Power
Management
Module
RST/NMI
I/O Ports
P1 (1×8 IOs)
P2 (1×4 IOs)
PA (P1, P2)
1×12 IOs
MAB
16-MHz CPU
including
16 Registers
MDB
EEM
TCK
TMS
TDI/TCLK
TDO
SBWTCK
SBWTDIO
JTAG
SBW
Watchdog
RTC
Counter
16-bit
real-time
clock
BAKMEM
32 bytes
backup
memory
LPM3.5 Domain
Copyright © 2017, Texas Instruments Incorporated
NOTE: The ADC is not available on the MSP430FR2000 device.
•
•
•
•
•
Figure 1-1. Functional Block Diagram
The device has one main power pair of DVCC and DVSS that supplies both digital and analog
modules. Recommended bypass and decoupling capacitors are 4.7 µF to 10 µF and 0.1 µF,
respectively, with ±5% accuracy.
Four pins of P1 and four pins of P2 feature the pin-interrupt function and can wake the MCU from all
LPMs, including LPM4, LPM3.5, and LPM4.5.
The Timer_B3 has three capture/compare registers. Only CCR1 and CCR2 are externally connected.
CCR0 registers can be used only for internal period timing and interrupt generation.
In LPM3.5, the RTC counter and backup memory can be functional while the rest of peripherals are off.
All general-purpose I/Os can be configured as Capacitive Touch I/Os.
Device Overview
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Copyright © 2016–2017, Texas Instruments Incorporated
3
MSP430FR2111, MSP430FR2110, MSP430FR2100, MSP430FR2000
SLASE78B – AUGUST 2016 – REVISED JULY 2017
www.ti.com
Table of Contents
1
2
3
Device Overview ......................................... 1
1.1
Features .............................................. 1
1.2
Applications ........................................... 1
1.3
Description ............................................ 2
1.4
Functional Block Diagram ............................ 3
5
5.1
Absolute Maximum Ratings
13
5.2
ESD Ratings
13
7.2
5.3
5.4
13
Active Mode Supply Current Into VCC Excluding
External Current ..................................... 14
59
Peripheral- and Interface-Specific Design
Information .......................................... 62
7.3
Typical Applications ................................. 63
Revision History ......................................... 5
Device Comparison ..................................... 6
Related Products ..................................... 6
Terminal Configuration and Functions .............. 7
4.1
Pin Diagrams ......................................... 7
4.2
Pin Attributes ......................................... 8
4.3
Signal Descriptions .................................. 10
4.4
Pin Multiplexing
4.5
Connection of Unused Pins ......................... 12
4.6
Buffer Type .......................................... 12
.....................................
12
Specifications ........................................... 13
........................
........................................
Recommended Operating Conditions ...............
7
8
Active Mode Supply Current Per MHz .............. 14
Low-Power Mode LPM0 Supply Currents Into VCC
Excluding External Current.......................... 14
Low-Power Mode LPM3, LPM4 Supply Currents
(Into VCC) Excluding External Current .............. 15
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
4
Timing and Switching Characteristics ............... 17
Detailed Description ................................... 35
............................................
.................................................
6.3
Operating Modes ....................................
6.4
Interrupt Vector Addresses..........................
6.5
Memory Organization ...............................
6.6
Bootloader (BSL) ....................................
6.7
JTAG Standard Interface............................
6.8
Spy-Bi-Wire Interface (SBW)........................
6.9
FRAM................................................
6.10 Memory Protection ..................................
6.11 Peripherals ..........................................
6.12 Device Descriptors (TLV) ...........................
6.13 Identification .........................................
Applications, Implementation, and Layout........
7.1
Device Connection and Layout Fundamentals ......
3.1
4
5.13
6
6.1
Overview
6.2
CPU
35
35
35
37
38
38
38
39
39
39
39
57
58
59
Device and Documentation Support ............... 64
8.1
Getting Started and Next Steps ..................... 64
8.2
Device Nomenclature ............................... 64
8.3
Tools and Software
8.4
Documentation Support ............................. 68
Typical Characteristics – LPM3 Supply Currents ... 15
Low-Power Mode LPMx.5 Supply Currents (Into
VCC) Excluding External Current .................... 16
8.5
Related Links ........................................ 69
8.6
Community Resources .............................. 69
8.7
Trademarks.......................................... 69
Typical Characteristics – LPMx.5 Supply Currents . 16
Typical Characteristics - Current Consumption Per
Module .............................................. 16
8.8
Electrostatic Discharge Caution ..................... 69
8.9
Glossary ............................................. 69
Thermal Resistance Characteristics ................ 17
Table of Contents
9
.................................
66
Mechanical, Packaging, and Orderable
Information .............................................. 70
Copyright © 2016–2017, Texas Instruments Incorporated
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Product Folder Links: MSP430FR2111 MSP430FR2110 MSP430FR2100 MSP430FR2000
MSP430FR2111, MSP430FR2110, MSP430FR2100, MSP430FR2000
www.ti.com
SLASE78B – AUGUST 2016 – REVISED JULY 2017
2 Revision History
Changes from August 13, 2016 to July 14, 2017
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Page
Added MSP430FR2100 and MSP430FR2000 devices .......................................................................... 1
Rearranged items in Section 1.1, Features ....................................................................................... 1
Corrected the package family for the RLL package throughout document (changed QFN to VQFN)..................... 1
Upated list of applications in Section 1.2 .......................................................................................... 1
Updated Section 1.3, Description ................................................................................................... 2
Corrected number of bits in port P1 in Figure 1-1, Functional Block Diagram ............................................... 3
Updated the note that starts "This is the remapped functionality controlled by the USCIARMP bit..." in Table 4-2,
Signal Descriptions .................................................................................................................. 11
Updated the note that starts "This is the remapped functionality controlled by the TBRMP bit..." in Table 4-2,
Signal Descriptions .................................................................................................................. 11
Removed former Figure 5-2, Low-Power Mode 3 Supply Current vs Temperature ....................................... 15
Updated notes on Section 5.12, Thermal Resistance Characteristics ...................................................... 17
Changed the entry for eUSCI_A in the LPM3 column from Off to Optional in Table 6-1, Operating Modes ............ 36
Updated the note that starts "This is the remapped functionality controlled by the USCIARMP bit..." in Table 611, eUSCI Pin Configurations ..................................................................................................... 43
Updated the note that starts "This is the remapped functionality controlled by the TBRMP bit..." in Table 6-12,
Timer0_B3 Signal Connections ................................................................................................... 44
Removed SYSBERRIV register (not supported) from Table 6-21, SYS Registers ......................................... 49
Updated descriptions of "Design Kits and Evaluation Modules" in Section 8.3, Tools and Software ................... 66
Revision History
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Copyright © 2016–2017, Texas Instruments Incorporated
5
MSP430FR2111, MSP430FR2110, MSP430FR2100, MSP430FR2000
SLASE78B – AUGUST 2016 – REVISED JULY 2017
www.ti.com
3 Device Comparison
Table 3-1 summarizes the features of the available family members.
Table 3-1. Device Comparison (1)
(1)
(2)
(3)
3.1
(2)
DEVICE
PROGRAM FRAM
(Kbytes)
SRAM
(Bytes)
TB0
eUSCI_A
10-BIT ADC
CHANNELS
eCOMP0
I/O
PACKAGE
TYPE
MSP430FR2111IPW16
3.75
1024
3 × CCR (3)
1
8
1
12
16 PW (TSSOP)
MSP430FR2110IPW16
2
1024
3 × CCR (3)
1
8
1
12
16 PW (TSSOP)
MSP430FR2100IPW16
1
512
3 × CCR (3)
1
8
1
12
16 PW (TSSOP)
MSP430FR2000IPW16
0.5
512
3 × CCR (3)
1
–
1
12
16 PW (TSSOP)
MSP430FR2111IRLL
3.75
1024
3 × CCR (3)
1
8
1
12
24 RLL (VQFN)
MSP430FR2110IRLL
2
1024
3 × CCR (3)
1
8
1
12
24 RLL (VQFN)
MSP430FR2100IRLL
1
512
3 × CCR (3)
1
8
1
12
24 RLL (VQFN)
MSP430FR2000IRLL
0.5
512
3 × CCR (3)
1
–
1
12
24 RLL (VQFN)
For the most current device, package, and ordering information, see the Package Option Addendum in Section 9, or see the TI website
at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging
A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM
outputs.
Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI Microcontrollers
connectivity options.
Low-power and high-performance MCUs, with wired and wireless
Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endless
possibilities. Enabling the connected world with innovations in ultra-low-power
microcontrollers with advanced peripherals for precise sensing and measurement.
MSP430FRxx FRAM Microcontrollers 16-bit microcontrollers for ultra-low-power sensing and system
management in building automation, smart grid, and industrial designs.
Companion Products for MSP430FR2111 Review products that are frequently purchased or used with
this product.
Reference Designs for MSP430FR2111 The TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
6
Device Comparison
Copyright © 2016–2017, Texas Instruments Incorporated
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Product Folder Links: MSP430FR2111 MSP430FR2110 MSP430FR2100 MSP430FR2000
MSP430FR2111, MSP430FR2110, MSP430FR2100, MSP430FR2000
www.ti.com
SLASE78B – AUGUST 2016 – REVISED JULY 2017
4 Terminal Configuration and Functions
4.1
Pin Diagrams
Figure 4-1 shows the pinout of the 16-pin PW package.
P1.1/UCA0CLK/ACLK/C1/A1
1
16
P1.2/UCA0RXD/UCA0SOMI/TB0TRG/C2/A2/Veref-
P1.0/UCA0STE/SMCLK/C0/A0/Veref+
2
15
P1.3/UCA0TXD/UCA0SIMO/C3/A3
TEST/SBWTCK
3
14
P1.4/UCA0STE/TCK/A4
RST/NMI/SBWTDIO
4
13
P1.5/UCA0CLK/TMS/A5
DVCC
5
12
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
DVSS
6
11
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+
P2.7/TB0CLK/XIN
7
10
P2.0/TB0.1/COUT
P2.6/MCLK/XOUT
8
9
P2.1/TB0.2
NOTE: The ADC (signals A0 to A7, Veref+, and Veref-) is not available on the MSP430FR2000 device.
Figure 4-1. 16-Pin PW (TSSOP) (Top View)
P1.2/UCA0RXD/UCA0SOMI/TB0TRG/C2/A2/Veref-
P1.0/UCA0STE/SMCLK/C0/A0/Veref+
NC
NC
NC
P1.1/UCA0CLK/ACLK/C1/A1
Figure 4-2 shows the pinout of the 24-pin RLL package.
24 23 22 21 20 19
NC
2
17
P1.3/UCA0TXD/UCA0SIMO/C3/A3
DVCC
3
16
P1.4/UCA0STE/TCK/A4
DVSS
4
15
P1.5/UCA0CLK/TMS/A5
P2.7/TB0CLK/XIN
5
14
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
NC
6
13
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+
NC
9 10 11 12
P2.1/TB0.2
8
NC
7
NC
18
RST/NMI/SBWTDIO
P2.0/TB0.1/COUT
1
P2.6/MCLK/XOUT
TEST/SBWTCK
NOTE: The ADC (signals A0 to A7, Veref+, and Veref-) is not available on the MSP430FR2000 device.
Figure 4-2. 24-Pin RLL (VQFN) (Top View)
Terminal Configuration and Functions
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MSP430FR2111, MSP430FR2110, MSP430FR2100, MSP430FR2000
SLASE78B – AUGUST 2016 – REVISED JULY 2017
4.2
www.ti.com
Pin Attributes
Table 4-1 lists the attributes of all pins.
Table 4-1. Pin Attributes
PIN NUMBER
PW16
1
RLL
23
SIGNAL
TYPE (3)
BUFFER TYPE (4)
POWER SOURCE
RESET STATE
AFTER BOR (5)
P1.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0CLK
I/O
LVCMOS
DVCC
–
ACLK
O
LVCMOS
DVCC
–
C1
I
Analog
DVCC
–
SIGNAL NAME (1)
A1
2
3
4
20
1
2
(6)
I
Analog
DVCC
–
P1.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0STE
I/O
LVCMOS
DVCC
–
SMCLK
O
LVCMOS
DVCC
–
C0
I
Analog
DVCC
–
A0 (6)
I
Analog
DVCC
–
Veref+ (6)
I
Power
DVCC
–
TEST (RD)
I
LVCMOS
DVCC
OFF
SBWTCK
I
LVCMOS
DVCC
–
RST (RD)
I/O
LVCMOS
DVCC
OFF
–
NMI
SBWTDIO
DVCC
LVCMOS
DVCC
–
DVCC
P
Power
DVCC
N/A
6
4
DVSS
P
Power
DVCC
N/A
7
5
9
10
11
7
11
8
13
I/O
LVCMOS
DVCC
OFF
TB0CLK
I
LVCMOS
DVCC
–
XIN
I
LVCMOS
DVCC
–
P2.6 (RD)
I/O
LVCMOS
DVCC
OFF
MCLK
O
LVCMOS
DVCC
–
XOUT
O
LVCMOS
DVCC
–
P2.1(RD)
I/O
LVCMOS
DVCC
OFF
TB0.2
I/O
LVCMOS
DVCC
–
P2.0 (RD)
I/O
LVCMOS
DVCC
OFF
TB0.1
I/O
LVCMOS
DVCC
–
COUT
O
LVCMOS
DVCC
–
P1.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0TXD
O
LVCMOS
DVCC
–
UCA0SIMO
I/O
LVCMOS
DVCC
–
TB0.2
I/O
LVCMOS
DVCC
–
TDO
O
LVCMOS
DVCC
–
(6)
I
Analog
DVCC
–
VREF+
O
Power
DVCC
–
A7
8
LVCMOS
3
8
(6)
I
I/O
5
P2.7 (RD)
(1)
(2)
(3)
(4)
(5)
(2)
Signals names with (RD) denote the reset default pin name.
To determine the pin mux encodings for each pin, see Section 6.11.15, Input/Output Diagrams.
Signal Types: I = Input, O = Output, I/O = Input or Output.
Buffer Types: LVCMOS, Analog, or Power
Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
N/A = Not applicable
The ADC is not available on the MSP430FR2000 device.
Terminal Configuration and Functions
Copyright © 2016–2017, Texas Instruments Incorporated
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Product Folder Links: MSP430FR2111 MSP430FR2110 MSP430FR2100 MSP430FR2000
MSP430FR2111, MSP430FR2110, MSP430FR2100, MSP430FR2000
www.ti.com
SLASE78B – AUGUST 2016 – REVISED JULY 2017
Table 4-1. Pin Attributes (continued)
PIN NUMBER
PW16
12
SIGNAL
TYPE (3)
BUFFER TYPE (4)
POWER SOURCE
RESET STATE
AFTER BOR (5)
P1.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0RXD
I
LVCMOS
DVCC
–
UCA0SOMI
I/O
LVCMOS
DVCC
–
TB0.1
SIGNAL NAME (1)
RLL
14
I/O
LVCMOS
DVCC
–
TDI
I
LVCMOS
DVCC
–
TCLK
I
LVCMOS
DVCC
–
A6
13
14
15
16
(2)
(6)
I
Analog
DVCC
–
P1.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0CLK
I/O
LVCMOS
DVCC
–
TMS
I
LVCMOS
DVCC
–
A5 (6)
I
Analog
DVCC
P1.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0STE
I/O
LVCMOS
DVCC
–
TCK
I
LVCMOS
DVCC
–
A4 (6)
I
Analog
DVCC
–
I/O
LVCMOS
DVCC
OFF
UCA0TXD
O
LVCMOS
DVCC
–
UCA0SIMO
I/O
LVCMOS
DVCC
–
C3
I
Analog
DVCC
–
A3 (6)
I
Analog
DVCC
–
P1.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0RXD
I
LVCMOS
DVCC
–
UCA0SOMI
I/O
LVCMOS
DVCC
–
TB0TRG
I
LVCMOS
DVCC
–
C2
I
Analog
DVCC
–
A2 (6)
I
Analog
DVCC
–
I
Power
DVCC
–
–
–
–
–
P1.3 (RD)
15
16
17
19
Veref-
(6)
6, 9, 10,
12, 18, 21, NC (7)
22, 24
(7)
NC = Not connected
Terminal Configuration and Functions
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Signal Descriptions
Table 4-2 describes the signals for all device variants and package options.
Table 4-2. Signal Descriptions
PIN NUMBER
PW16
RLL
PIN
TYPE
2
20
I
Analog input A0
A1
1
23
I
Analog input A1
A2
16
19
I
Analog input A2
A3
15
17
I
Analog input A3
A4
14
16
I
Analog input A4
A5
13
15
I
Analog input A5
A6
12
14
I
Analog input A6
A7
11
13
I
Analog input A7
Veref+
2
20
I
ADC positive reference
Veref-
16
19
I
ADC negative reference
C0
2
20
I
Comparator input channel C0
C1
1
23
I
Comparator input channel C1
C2
16
19
I
Comparator input channel C2
C3
15
17
I
Comparator input channel C3
COUT
10
8
O
Comparator output channel COUT
ACLK
1
23
O
ACLK output
MCLK
8
7
O
MCLK output
SMCLK
2
20
O
SMCLK output
XIN
7
5
I
Input terminal for crystal oscillator
XOUT
8
7
O
Output terminal for crystal oscillator
SBWTCK
3
1
I
Spy-Bi-Wire input clock
FUNCTION
SIGNAL NAME
A0
ADC (1)
eCOMP0
Clock
Debug
System
Power
(1)
10
DESCRIPTION
SBWTDIO
4
2
I/O
TCK
14
16
I
Spy-Bi-Wire data input/output
Test clock
TCLK
12
14
I
Test clock input
TDI
12
14
I
Test data input
TDO
11
13
O
Test data output
TMS
13
15
I
Test mode select
TEST
3
1
I
Test mode pin – selected digital I/O on JTAG pins
NMI
4
2
I
Nonmaskable interrupt input
RST
4
2
I/O
DVCC
5
3
P
Power supply
Reset input, active low
DVSS
6
4
P
Power ground
VREF+
11
13
P
Output of positive reference voltage with ground as reference
The ADC is not available on the MSP430FR2000 device.
Terminal Configuration and Functions
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SLASE78B – AUGUST 2016 – REVISED JULY 2017
Table 4-2. Signal Descriptions (continued)
GPIO
SPI and UART
RLL
PIN
TYPE
P1.0
2
20
I/O
General-purpose I/O
P1.1
1
23
I/O
General-purpose I/O
P1.2
16
19
I/O
General-purpose I/O
P1.3
15
17
I/O
General-purpose I/O
P1.4
14
16
I/O
General-purpose I/O
(2)
(2)
SIGNAL NAME
13
15
I/O
General-purpose I/O
P1.6
12
14
I/O
General-purpose I/O (2)
P1.7
11
13
I/O
General-purpose I/O (2)
P2.0
10
8
I/O
General-purpose I/O
P2.1
9
11
I/O
General-purpose I/O
P2.6
8
7
I/O
General-purpose I/O
P2.7
7
5
I/O
General-purpose I/O
UCA0CLK
13
15
I/O
eUSCI_A0 SPI clock input/output
UCA0RXD
12
14
I
UCA0SIMO
11
13
I/O
eUSCI_A0 SPI slave in/master out
UCA0SOMI
12
14
I/O
eUSCI_A0 SPI slave out/master in
UCA0STE
14
16
I/O
eUSCI_A0 SPI slave transmit enable
UCA0TXD
11
13
O
eUSCI_A0 UART transmit data
UCA0CLK (3)
1
23
I/O
eUSCI_A0 SPI clock input/output
UCA0RXD (3)
16
19
I
(3)
15
17
I/O
eUSCI_A0 SPI slave in/master out
UCA0SOMI (3)
16
19
I/O
eUSCI_A0 SPI slave out/master in
UCA0STE (3)
2
20
I/O
eUSCI_A0 SPI slave transmit enable
UCA0TXD
(3)
17
O
eUSCI_A0 UART transmit data
12
14
I/O
Timer TB0 CCR1 capture: CCI1A input, compare: Out1 outputs
TB0.2
11
13
I/O
Timer TB0 CCR2 capture: CCI2A input, compare: Out2 outputs
TB0CLK
7
5
I
Timer clock input TBCLK for TB0
TB0TRG
16
19
I
TB0 external trigger input for TB0OUTH
TB0.1 (4)
10
8
I/O
Timer TB0 CCR1 capture: CCI1A input, compare: Out1 outputs
TB0.2 (4)
9
11
I/O
Timer TB0 CCR2 capture: CCI2A input, compare: Out2 outputs
–
NC
–
VQFN pad
Pad
–
Pad
(4)
eUSCI_A0 UART receive data
15
NC pad
(3)
eUSCI_A0 UART receive data
TB0.1
6, 9,
10,
12,
18,
21,
22, 24
(2)
DESCRIPTION
P1.5
UCA0SIMO
Timer_B
PIN NUMBER
PW16
FUNCTION
Do not connect
VQFN package (RLL) exposed thermal pad. Connect to VSS.
Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to
prevent collisions.
This is the remapped functionality controlled by the USCIARMP bit in the SYSCFG3 register. Only one selected port is valid at the same
time.
This is the remapped functionality controlled by the TBRMP bit in the SYSCFG3 register. Only one selected port is valid at the same
time when TB0 acts as capture input functionality. TB0 PWM outputs regardless of the setting on this remap bit.
Terminal Configuration and Functions
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Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see Section 6.11.15.
4.5
Connection of Unused Pins
Table 4-3 lists the correct termination of unused pins.
Table 4-3. Connection of Unused Pins (1)
(1)
(2)
PIN
POTENTIAL
Px.0 to Px.7
Open
Set to port function, output direction (PxDIR.n = 1)
COMMENT
RST/NMI
DVCC
47-kΩ pullup or internal pullup selected with 10-nF (1.1 nF) pulldown (2)
TEST
Open
This pin always has an internal pulldown enabled.
Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
The pulldown capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like
FET interfaces or GANG programmers.
4.6
Buffer Type
Table 4-4 defines the pin buffer types that are listed in Table 4-1.
Table 4-4. Buffer Type
NOMINAL
VOLTAGE
HYSTERESIS
PU OR PD
NOMINAL
PU OR PD
STRENGTH
(µA)
OUTPUT
DRIVE
STRENGTH
(mA)
LVCMOS
3.0 V
Y (1)
Programmable
See
Section 5.13.4.
See
Section
5.13.4.1.
Analog
3.0 V
No
No
N/A
N/A
See the analog modules in
Section 5 for details.
Power (DVCC)
3.0 V
No
No
N/A
N/A
SVS enables hysteresis on
DVCC.
Power (AVCC)
3.0 V
No
No
N/A
N/A
BUFFER TYPE
(STANDARD)
(1)
12
OTHER
CHARACTERISTICS
Only for input pins
Terminal Configuration and Functions
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5 Specifications
Absolute Maximum Ratings (1)
5.1
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Voltage applied at DVCC pin to VSS
–0.3
4.1
UNIT
V
Voltage applied to any pin (2)
–0.3
VCC + 0.3
(4.1 V Max)
V
Diode current at any device pin
±2
mA
Maximum junction temperature, TJ
85
°C
125
°C
Storage temperature range, Tstg
(1)
(2)
(3)
(3)
–40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±250 V may actually have higher performance.
5.3
Recommended Operating Conditions
MIN
MAX
Supply voltage applied at DVCC pin (1)
VSS
Supply voltage applied at DVSS pin
TA
Operating free-air temperature
–40
85
TJ
Operating junction temperature
–40
85
CDVCC
Recommended capacitor at DVCC
4.7
fSYSTEM
Processor frequency (maximum MCLK frequency)
fACLK
Maximum ACLK frequency
fSMCLK
Maximum SMCLK frequency
(1)
(2)
(3)
(4)
(5)
(6)
(2)
NOM
VCC
1.8
3.6
0
(3) (4)
UNIT
V
V
10
°C
°C
µF
No FRAM wait states
(NWAITSx = 0)
0
8
With FRAM wait states
(NWAITSx = 1) (5)
0
16 (6)
MHz
40
kHz
16 (6)
MHz
Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range.
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
The minimum supply voltage is defined by the SVS levels. See the SVS threshold parameters in Table 5-1.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed
without wait states.
If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to
comply with this operating condition.
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Specifications
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5.4
See
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Active Mode Supply Current Into VCC Excluding External Current
(1)
FREQUENCY (fMCLK = fSMCLK)
PARAMETER
EXECUTION
MEMORY
TEST
CONDITION
1 MHz
0 WAIT STATES
(NWAITSx = 0)
TYP
IAM, FRAM (0%)
IAM, FRAM (100%)
IAM,
(1)
(2)
RAM
(2)
8 MHz
0 WAIT STATES
(NWAITSx = 0)
MAX
TYP
16 MHz
1 WAIT STATE
(NWAITSx = 1)
MAX
TYP
FRAM
0% cache hit ratio
3.0 V, 25°C
460
2670
2940
3.0 V, 85°C
475
2730
2980
FRAM
100% cache hit
ratio
3.0 V, 25°C
191
570
942
3.0 V, 85°C
199
585
960
RAM
3.0 V, 25°C
213
739
1244
UNIT
MAX
µA
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Characterized with program executing typical data
processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency
Program and data entirely reside in FRAM. All execution is from FRAM.
Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.
5.5
Active Mode Supply Current Per MHz
VCC = 3.0 V, TA = 25°C (unless otherwise noted)
PARAMETER
dIAM,FRAM/df
(1)
TEST CONDITIONS
Active mode current consumption per MHz,
execution from FRAM, no wait states (1)
[(IAM 75% cache hit rate at 8 MHz) –
(IAM 75% cache hit rate at 1 MHz)] / 7 MHz
TYP
UNIT
120
µA/MHz
All peripherals are turned on in default settings.
5.6
Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
VCC = 3.0 V, TA = 25°C (unless otherwise noted) (1)
(2)
FREQUENCY (fSMCLK)
PARAMETER
VCC
1 MHz
TYP
ILPM0
(1)
(2)
14
MAX
8 MHz
TYP
MAX
16 MHz
TYP
2.0 V
148
295
398
3.0 V
157
304
402
UNIT
MAX
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK at specified frequency.
Specifications
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5.7
SLASE78B – AUGUST 2016 – REVISED JULY 2017
Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
(see Figure 5-1)
TEMPERATURE
PARAMETER
VCC
–40°C
TYP
ILPM3,XT1
Low-power mode 3, includes SVS (2)
(3) (4)
ILPM3,VLO
Low-power mode 3, VLO, excludes SVS (5)
ILPM3,
RTC
Low-power mode 3, RTC, excludes SVS (6)
ILPM4,
SVS
Low-power mode 4, includes SVS
MAX
25°C
TYP
85°C
MAX
MAX
6.00
3.0 V
0.95
1.07
2.13
2.0 V
0.92
1.03
2.09
3.0 V
0.76
0.87
1.94
2.0 V
0.74
0.85
1.90
3.0 V
0.88
1.00
2.06
2.0 V
0.86
0.98
2.02
3.0 V
0.49
0.58
1.60
2.0 V
0.46
0.56
1.57
3.0 V
0.33
0.42
1.44
2.0 V
0.32
0.41
1.42
ILPM4
Low-power mode 4, excludes SVS
ILPM4, RTC, VLO
Low-power mode 4, RTC is soured from VLO,
excludes SVS
3.0 V
0.48
0.59
1.91
2.0 V
0.48
0.58
1.89
ILPM4, RTC, XT1
Low-power mode 4, RTC is soured from XT1,
excludes SVS
3.0 V
0.89
1.04
2.41
2.0 V
0.88
1.02
2.38
(1)
(2)
(3)
(4)
(5)
(6)
5.8
UNIT
TYP
5.70
µA
µA
µA
µA
µA
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current
Not applicable for devices with HF crystal oscillator only.
Characterized with a Seiko Crystal SC-32S MS1V-T1K crystal with a load capacitance chosen to closely match the required load.
Low-power mode 3, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fMCLK = fSMCLK = 0 MHz
RTC periodically wakes every second with external 32768-Hz as source.
Typical Characteristics – LPM3 Supply Currents
3 V at 25°C and 3 V at 85°C
10
LPM3 Supply Current (µA)
9
8
7
6
5
4
3
2
1
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
0
Temperature (°C)
DVCC = 3 V
RTC Enabled
SVS Disabled
Figure 5-1. Low-Power Mode 3 Supply Current vs Temperature
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Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEMPERATURE
PARAMETER
VCC
–40°C
TYP
ILPM3.5,
XT1
Low-power mode 3.5, includes SVS (1)
(also see Figure 5-2)
ILPM4.5,
SVS
Low-power mode 4.5, includes SVS (4)
Low-power mode 4.5, excludes SVS (5)
(also see Figure 5-3)
ILPM4.5
(1)
(2)
(3)
(4)
(5)
(2) (3)
25°C
MAX
TYP
85°C
MAX
UNIT
TYP
MAX
2.17
3.0 V
0.60
0.66
0.80
2.0 V
0.57
0.64
0.75
3.0 V
0.23
0.25
0.32
2.0 V
0.20
0.23
0.27
3.0 V
0.025
0.034
0.064
2.0 V
0.021
0.029
0.055
µA
0.43
µA
0.130
µA
Not applicable for devices with HF crystal oscillator only.
Characterized with a Seiko Crystal SC-32S crystal with a load capacitance chosen to closely match the required load.
Low-power mode 3.5, includes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5, excludes SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
5.10 Typical Characteristics – LPMx.5 Supply Currents
3 V at 25°C and 3 V at 85°C
0.50
LPM4.5 Supply Current (µA)
LPM3.5 Supply Current (µA)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-40 -30 -20 -10
Temperature (°C)
DVCC = 3 V
XT1, 12.5-pF Crystal
0
10
20
30
40
50
60
70
80
Temperature (°C)
SVS Enabled
Figure 5-2. LPM3.5 Supply Current vs Temperature
DVCC = 3 V
SVS Enabled
Figure 5-3. LPM4.5 Supply Current vs Temperature
5.11 Typical Characteristics - Current Consumption Per Module
MODULE
TEST CONDITIONS
REFERENCE CLOCK
MIN
TYP
MAX
UNIT
Timer_B
SMCLK = 8 Hz, MC = 10
Module input clock
5
µA/MHz
eUSCI_A
UART mode
Module input clock
7
µA/MHz
eUSCI_A
SPI mode
Module input clock
5
µA/MHz
RTC
CRC
16
From start to end of operation
Specifications
32 kHz
85
nA
MCLK
8.5
µA/MHz
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5.12 Thermal Resistance Characteristics
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance, still air
RθJC
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
(1)
(2)
(2)
VALUE
VQFN 24 pin (RLL)
38.7
TSSOP 16 pin (PW16)
106.5
VQFN 24 pin (RLL)
39.5
TSSOP 16 pin (PW16)
41.2
VQFN 24 pin (RLL)
8.6
TSSOP 16 pin (PW16)
51.5
UNIT
ºC/W
ºC/W
ºC/W
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC
standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
5.13 Timing and Switching Characteristics
5.13.1 Power Supply Sequencing
Figure 5-4 shows the power cycle, SVS, and BOR reset conditions.
V
Power Cycle Reset
SVS Reset
VSVS+
BOR Reset
VSVS–
VBOR
tBOR
t
Figure 5-4. Power Cycle, SVS, and BOR Reset Conditions
Table 5-1 lists the characteristics of the SVS and BOR.
Table 5-1. PMM, SVS and BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
VBOR, safe
Safe BOR power-down level
tBOR, safe
Safe BOR reset delay (2)
ISVSH,AM
SVSH current consumption, active mode
VCC = 3.6 V
ISVSH,LPM
SVSH current consumption, low-power modes
VCC = 3.6 V
VSVSH-
SVSH power-down level
1.71
1.81
1.86
V
VSVSH+
SVSH power-up level
1.74
1.88
1.99
V
VSVSH_hys
SVSH hysteresis
tPD,SVSH, AM
SVSH propagation delay, active mode
tPD,SVSH, LPM
SVSH propagation delay, low-power modes
(1)
(2)
0.1
V
10
ms
1.5
240
µA
nA
80
mV
10
µs
100
µs
A safe BOR can only be correctly generated only if DVCC must drop below this voltage before it rises.
When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches VSVSH+.
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5.13.2 Reset Timing
Table 5-2 lists the wake-up time characteristics.
Table 5-2. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
tWAKE-UP FRAM
(Additional) wake-up time to activate the FRAM in
AM if previously disabled through the FRAM
controller or from an LPM if immediate activation is
selected for wakeup (1)
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode
(1)
3V
tWAKE-UP LPM3
Wake-up time from LPM3 to active mode
(1)
3V
Wake-up time from LPM4 to active mode
(2)
tWAKE-UP LPM4
tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode
tWAKE-UP LPM4.5 Wake-up time from LPM4.5 to active mode
tWAKE-UP-RESET
Wake-up time from RST or BOR event to active
mode (2)
tRESET
Pulse duration required at RST/NMI pin to accept
a reset
(1)
(2)
18
3V
(2)
(2)
MIN
SVSHE = 1
SVSHE = 0
TYP
MAX
10
UNIT
µs
200 +
2.5 / fDCO
ns
10
µs
3V
10
µs
3V
350
µs
350
µs
1
ms
1
ms
3V
3V
2
µs
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge.
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
Specifications
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5.13.3 Clock Specifications
Table 5-3 lists the characteristics of the XT1 in low-frequency mode.
Table 5-3. XT1 Crystal Oscillator (Low Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
fXT1, LF
XT1 oscillator crystal, low
frequency
LFXTBYPASS = 0
DCXT1, LF
XT1 oscillator LF duty cycle
Measured at MCLK,
fLFXT = 32768 Hz
fXT1,SW
XT1 oscillator logic-level squarewave input frequency
LFXTBYPASS = 1
DCXT1, SW
LFXT oscillator logic-level squareLFXTBYPASS = 1
wave input duty cycle
OALFXT
Oscillation allowance for
LF crystals (4)
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
CL,eff
Integrated effective load
capacitance (5)
See
tSTART,LFXT Start-up time
fFault,LFXT
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
MIN
(8)
30%
(2) (3)
MAX
70%
40%
0
UNIT
Hz
32768
(6)
XTS = 0 (9)
TYP
32768
fOSC = 32768 Hz
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
(7)
Oscillator fault frequency
VCC
Hz
60%
200
kΩ
1
pF
1000
ms
3500
Hz
To improve EMI on the LFXT oscillator, observe the following guidelines:
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. The input signal is a digital square wave with parametrics
defined in Table 5-9. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For LFXTDRIVE = {0}, CL,eff = 3.7 pF
• For LFXTDRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF
• For LFXTDRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Includes start-up counter of 1024 clock cycles.
Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications may set the
flag. A static condition or stuck at fault condition sets the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
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Table 5-4 lists the frequency characteristics of the DCO FLL.
Table 5-4. DCO FLL, Frequency
Over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
FLL lock frequency, 16 MHz, 25°C
fDCO,
FLL lock frequency, 16 MHz, –40°C to 85°C
Measured at MCLK, internal
trimmed REFO as reference
VCC
MIN
TYP
MAX
3.0 V
–1.0%
1.0%
3.0 V
–2.0%
2.0%
3.0 V
–0.5%
0.5%
3.0 V
40%
UNIT
FLL
FLL lock frequency, 16 MHz, –40°C to 85°C
fDUTY
Duty cycle
Jittercc
Cycle-to-cycle jitter, 16 MHz
Jitterlong
Long term Jitter, 16 MHz
tFLL, lock
FLL lock time
Measured at MCLK, XT1
crystal as reference
Measured at MCLK, XT1
crystal as reference
50%
3.0 V
0.25%
3.0 V
0.022%
3.0 V
245
60%
ms
Table 5-5 lists the frequency characteristics of the DCO.
Table 5-5. DCO Frequency
Over recommended operating free-air temperature (unless otherwise noted) (see Figure 5-5)
PARAMETER
TEST CONDITIONS
VCC
MIN
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
fDCO, 16 MHz
fDCO, 12 MHz
(1)
(1)
fDCO, 8 MHz (1)
fDCO, 4 MHz
(1)
DCO frequency, 16 MHz
DCO frequency, 12 MHz
DCO frequency, 8 MHz
DCO frequency, 4 MHz
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
20
MHz
18.0
30.0
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
6.0
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
9.5
3.0 V
MHz
13.5
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
22.0
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
3.8
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
6.5
3.0 V
MHz
9.5
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
16.0
DCORSEL = 010b,, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
2.0
DCORSEL = 010b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 010b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
UNIT
12.5
3.0 V
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
MAX
7.8
3.2
3.0 V
MHz
4.8
DCORSEL = 010b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
(1)
TYP
8.0
This frequency reflects the achievable frequency range when FLL is either enabled or disabled.
Specifications
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Table 5-5. DCO Frequency (continued)
Over recommended operating free-air temperature (unless otherwise noted) (see Figure 5-5)
PARAMETER
TEST CONDITIONS
VCC
MIN
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
fDCO, 2 MHz
fDCO, 1 MHz
(1)
(1)
UNIT
1.7
3.0 V
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
MHz
2.5
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
4.2
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
0.5
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
DCO frequency, 1 MHz
MAX
1.0
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
DCO frequency, 2 MHz
TYP
0.85
3.0 V
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
MHz
1.2
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
2.1
30
DCOFTRIM = 7
25
DCOFTRIM = 7
Frequency (MHz)
20
DCOFTRIM = 7
15
10
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 7
5
DCOFTRIM = 0
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 0
0
DCO
DCORSEL
DCOFTRIM = 0
511
0
0
DCOFTRIM = 0
511
0
511
0
1
511
0
2
3
511
0
4
511
0
5
Figure 5-5. Typical DCO Frequency
Table 5-6 lists the characteristics of the REFO.
Table 5-6. REFO
Over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
IREFO
TEST CONDITIONS
VCC
REFO oscillator current consumption
TA = 25°C
REFO calibrated frequency
Measured at MCLK
REFO absolute calibrated tolerance
–40°C to 85°C
dfREFO/dT
REFO frequency temperature drift
Measured at MCLK (1)
3.0 V
dfREFO/
dVCC
REFO frequency supply voltage drift
Measured at MCLK at
25°C (2)
1.8 V to 3.6 V
fDC
REFO duty cycle
Measured at MCLK
1.8 V to 3.6 V
tSTART
REFO start-up time
40% to 60% duty cycle
fREFO
(1)
(2)
MIN
3.0 V
MAX
15
3.0 V
1.8 V to 3.6 V
TYP
µA
32768
–3.5%
40%
UNIT
Hz
+3.5%
0.01
%/°C
1
%/V
50%
60%
50
µs
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
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Table 5-7 lists the characteristics of the VLO.
Table 5-7. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fVLO
TEST CONDITIONS
VLO frequency
dfVLO/dT
Measured at MCLK
VLO frequency temperature drift
Measured at MCLK
(1)
dfVLO/dVCC VLO frequency supply voltage drift
Measured at MCLK (2)
f
Measured at MCLK
(1)
(2)
Duty cycle
VCC
MIN
TYP
MAX
UNIT
3.0 V
10
kHz
3.0 V
0.5
%/°C
4
%/V
1.8 V to 3.6 V
3.0 V
50%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
NOTE
The VLO clock frequency is reduced by 15% (typical) when the device switches from active
mode to LPM3 or LPM4, because the reference changes. This lower frequency is not a
violation of the VLO specifications (see Table 5-7).
Table 5-8 lists the characteristics of the MODOSC.
Table 5-8. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
fMODOSC
MODOSC frequency
fMODOSC/dT
MODOSC frequency temperature drift
fMODOSC/dVCC
MODOSC frequency supply voltage drift
fMODOSC,DC
Duty cycle
VCC
MIN
TYP
MAX
UNIT
3.0 V
3.8
4.8
5.8
MHz
3.0 V
0.102
1.8 V to 3.6 V
2.29
3.0 V
40%
%/°C
%/V
50%
60%
TYP
MAX
5.13.4 Digital I/Os
Table 5-9 lists the characteristics of the digital inputs.
Table 5-9. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2V
0.90
1.50
3V
1.35
2.25
2V
0.50
1.10
3V
0.75
1.65
2V
0.3
0.8
3V
0.4
1.2
UNIT
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
3
pF
CI,ana
Input capacitance, port pins with shared analog
VIN = VSS or VCC
functions
5
pF
Ilkg(Px.y)
(1)
(2)
22
High-impedance leakage current
(1) (2)
20
2 V, 3 V
–20
35
50
+20
V
V
V
kΩ
nA
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Specifications
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Table 5-10 lists the characteristics of the digital outputs.
Table 5-10. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.0 V
1.4
TYP
MAX
2.0
VOH
High-level output voltage (also see Figure 5-8 and
Figure 5-9)
I(OHmax) = –3 mA (1)
I(OHmax) = –5 mA (1)
3.0 V
2.4
3.0
VOL
Low-level output voltage (also see Figure 5-6 and
Figure 5-7)
I(OLmax) = 3 mA (1)
2.0 V
0.0
0.60
I(OLmax) = 5 mA (1)
3.0 V
0.0
0.60
fPort_CLK
Clock output frequency
CL = 20 pF (2)
2.0 V
16
3.0 V
16
trise,dig
Port output rise time, digital only port pins
CL = 20 pF
tfall,dig
Port output fall time, digital only port pins
CL = 20 pF
(1)
(2)
UNIT
V
V
MHz
2.0 V
10
3.0 V
7
2.0 V
10
3.0 V
5
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The port can output frequencies at least up to the specified limit and might support higher frequencies.
5.13.4.1 Digital I/O Typical Characteristics
10
Low-Level Output Current (mA)
Low-Level Output Current (mA)
25
85°C
20
25°C
15
10
5
0
85°C
25°C
7.5
5
2.5
0
0
0.5
1
1.5
2
2.5
3
0
0.25
Low-Level Output Voltage (V)
0.75
1
1.25
1.5
1.75
2
Low-Level Output Voltage (V)
Figure 5-6. Typical Low-Level Output Current
vs
Low-Level Output Voltage (DVCC = 3 V)
Figure 5-7. Typical Low-Level Output Current
vs
Low-Level Output Voltage (DVCC = 2 V)
0
0
High-Level Output Current (mA)
High-Level Output Current (mA)
0.5
85°C
-5
25°C
-10
-15
-20
-25
85°C
25 ° C
-2.5
-5
-7.5
-10
0
0.5
1
1.5
2
2.5
High-Level Output Voltage (V)
Figure 5-8. Typical High-Level Output Current
vs
High-Level Output Voltage (DVCC = 3 V)
3
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
High-Level Output Voltage (V)
Figure 5-9. Typical High-Level Output Current
vs
High-Level Output Voltage (DVCC = 2 V)
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5.13.5 VREF+ Built-in Reference
Table 5-11 lists the characteristics of the VREF+.
Table 5-11. VREF+ Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VREF+
Positive built-in reference voltage
EXTREFEN = 1 with 1-mA load current
TCREF+
Temperature coefficient of built-in
reference voltage
EXTREFEN = 1 with 1-mA load current
VCC
2.0 V,
3.0 V
MIN
TYP
MAX
UNIT
1.158
1.2
1.242
V
30
µV/°C
5.13.6 Timer_B
Table 5-12 lists the supported clock frequencies of Timer_B.
Table 5-12. Timer_B Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fTB
24
Timer_B input clock frequency
Specifications
TEST CONDITIONS
Internal: SMCLK or ACLK,
External: TBCLK,
duty cycle = 50% ±10%
VCC
MIN
2.0 V,
3.0 V
TYP
MAX
UNIT
16
MHz
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5.13.7 eUSCI
Table 5-13 lists the clock frequency characteristics of the eUSCI in UART mode.
Table 5-13. eUSCI (UART Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in Mbaud)
Internal: SMCLK or MODCLK,
External: UCLK,
duty cycle = 50% ±10%
VCC
MIN
TYP
MAX
UNIT
2.0 V,
3.0 V
16
MHz
2.0 V,
3.0 V
5
MHz
MAX
UNIT
Table 5-14 lists the switching characteristics of the eUSCI in UART mode.
Table 5-14. eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
UCGLITx = 0
tt
UART receive deglitch time
(1)
12
UCGLITx = 1
40
2.0 V,
3.0 V
UCGLITx = 2
UCGLITx = 3
(1)
ns
68
110
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
Table 5-15 lists the clock frequency characteristics of the eUSCI in SPI master mode.
Table 5-15. eUSCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
feUSCI
eUSCI input clock frequency
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
8
MHz
Internal: SMCLK or MODCLK,
duty cycle = 50% ±10%
Table 5-16 lists the switching characteristics of the eUSCI in SPI master mode.
Table 5-16. eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
UCSTEM = 1,
UCMODEx = 01 or 10
tSTE,LAG
STE lag time, Last clock to STE inactive
UCSTEM = 1,
UCMODEx = 01 or 10
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid,
CL = 20 pF
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
VCC
MIN
MAX
UNIT
3.0 V
1
UCxCLK
cycles
3.0 V
1
UCxCLK
cycles
2.0 V
53
3.0 V
35
2.0 V
0
3.0 V
0
ns
ns
2.0 V
20
3.0 V
20
2.0 V
0
3.0 V
0
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-10 and Figure 5-11.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 510 and Figure 5-11.
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 5-10. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
tVALID,MO
SIMO
Figure 5-11. SPI Master Mode, CKPH = 1
26
Specifications
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Table 5-17 lists the switching characteristics of the eUSCI in SPI slave mode.
Table 5-17. eUSCI (SPI Slave Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time (2)
tHD,SO
SOMI output data hold time
(1)
(2)
(3)
(3)
UCLK edge to SOMI valid,
CL = 20 pF
CL = 20 pF
VCC
MIN
2.0 V
55
3.0 V
45
2.0 V
20
3.0 V
20
MAX
ns
ns
2.0 V
65
3.0 V
40
2.0 V
50
3.0 V
35
2.0 V
10
3.0 V
8
2.0 V
12
3.0 V
12
68
42
3.0 V
5
ns
ns
3.0 V
5
ns
ns
2.0 V
2.0 V
UNIT
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-12 and Figure 5-13.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-12
and Figure 5-13.
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SIMO
tLOW/HIGH
tHD,SIMO
SIMO
tACC
tDIS
tVALID,SOMI
SOMI
Figure 5-12. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tDIS
tVALID,SO
SOMI
Figure 5-13. SPI Slave Mode, CKPH = 1
28
Specifications
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5.13.8 ADC
NOTE
The ADC is not available on the MSP430FR2000 device.
Table 5-18 lists the input conditions of the ADC.
Table 5-18. ADC, Power Supply and Input Range Conditions
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DVCC
ADC supply voltage
V(Ax)
Analog input voltage range
All ADC pins
IADC
Operating supply current into DVCC
terminal, reference current not included,
repeat-single-channel mode
fADCCLK = 5 MHz, ADCON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADCDIV = 0, ADCCONSEQx = 10b
CI
Input capacitance
Only one terminal Ax can be selected at
one time from the pad to the ADC capacitor
array, including wiring and pad
RI
Input MUX ON resistance
DVCC = 2 V, 0 V = VAx = DVCC
VCC
MIN
TYP
MAX
UNIT
2.0
3.6
V
0
DVCC
V
2V
185
3V
207
2.2 V
2.5
µA
3.5
pF
2
kΩ
Table 5-19 lists the timing parameters of the ADC.
Table 5-19. ADC, 10-Bit Timing Parameters
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
fADCCLK
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC linearity
parameters
TEST CONDITIONS
2 V to
3.6 V
0.45
5
5.5
MHz
4.8
5.8
MHz
2.67
µs
100
ns
fADCOSC
Internal ADC oscillator
(MODOSC)
ADCDIV = 0, fADCCLK = fADCOSC
2 V to
3.6 V
3.8
tCONVERT
Conversion time
REFON = 0, Internal oscillator,
10 ADCCLK cycles, 10-bit mode,
fADCOSC = 4.5 MHz to 5.5 MHz
2 V to
3.6 V
2.18
tADCON
Turnon settling time of
the ADC
The error in a conversion started after tADCON is less
than ±0.5 LSB.
Reference and input signal are already settled.
tSample
Sampling time
RS = 1000 Ω, RI = 36000 Ω, CI = 3.5 pF.
Approximately 8 Tau (t) are required for an error of
less than ±0.5 LSB.
2V
1.5
3V
2.0
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Table 5-20 lists the linearity parameters of the ADC.
Table 5-20. ADC, 10-Bit Linearity Parameters
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
Integral linearity error (10-bit mode)
EI
Integral linearity error (8-bit mode)
Differential linearity error (10-bit mode)
ED
Differential linearity error (8-bit mode)
Offset error (10-bit mode)
EO
Offset error (8-bit mode)
Gain error (10-bit mode)
EG
Gain error (8-bit mode)
Total unadjusted error (10-bit mode)
ET
Total unadjusted error (8-bit mode)
VSENSOR
TCSENSOR
tSENSOR
(sample)
(1)
(2)
30
TEST CONDITIONS
Veref+ reference
Veref+ reference
Veref+ reference
Veref+ as reference
Internal 1.5-V reference
Veref+ as reference
Internal 1.5-V reference
Veref+ as reference
Internal 1.5-V reference
Veref+ as reference
Internal 1.5-V reference
VCC
MIN
TYP
MAX
2.4 V to 3.6 V
–2
2
2.0 V to 3.6 V
–2
2
2.4 V to 3.6 V
–1
1
2.0 V to 3.6 V
–1
1
2.4 V to 3.6 V
–6.5
6.5
2.0 V to 3.6 V
–6.5
6.5
2.4 V to 3.6 V
2.0 V to 3.6 V
2.4 V to 3.6 V
2.0 V to 3.6 V
–2.0
2.0
–3.0%
3.0%
–2.0
2.0
–3.0%
3.0%
–2.0
2.0
–3.0%
3.0%
–2.0
2.0
–3.0%
3.0%
UNIT
LSB
LSB
mV
LSB
LSB
LSB
LSB
See
(1)
ADCON = 1, INCH = 0Ch,
TA = 0℃
3.0 V
913
mV
See
(2)
ADCON = 1, INCH = 0Ch
3.0 V
3.35
mV/℃
ADCON = 1, INCH = 0Ch,
Error of conversion result
≤1 LSB, AM and all LPMs
above LPM3
3.0 V
ADCON = 1, INCH = 0Ch,
Error of conversion result
≤1 LSB, LPM3
3.0 V
Sample time required if channel 12 is
selected
30
µs
100
The temperature sensor offset can vary significantly. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
The device descriptor structure contains calibration values for 30℃ ±3℃ and 85°C ±3℃ for each available reference voltage level. The
sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature, ℃ ) + VSENSOR , where TCSENSOR and VSENSOR can be
computed from the calibration values for higher accuracy.
Specifications
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5.13.9 Enhanced Comparator (eCOMP)
Table 5-21 lists the characteristics of the eCOMP.
Table 5-21. eCOMP
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
Supply voltage
VIC
Common-mode input
range
TEST CONDITIONS
VCC
MIN
TYP
DC input hysteresis
UNIT
2.0
3.6
V
0
VCC
V
CPEN = 1, CPHSEL = 00
VHYS
MAX
0
CPEN = 1, CPHSEL = 01
10
2.0 V to 3.6 V
CPEN = 1, CPHSEL = 10
mV
20
CPEN = 1, CPHSEL = 11
30
CPEN = 1, CPMSEL = 0, CPHSEL = 00
±5
–40
Input offset voltage
ICOMP
Quiescent current draw VIC = VCC/2, CPEN = 1, CPMSEL = 0
from VCC, only
VIC = VCC/2, CPEN = 1, CPMSEL = 1
comparator
2.0 V to 3.6 V
IDAC
Quiescent current draw
CPDACREFS = 0, CPEN = 0
from VCC, only DAC
2.0 V to 3.6 V
0.5
µA
CIN
Input channel
capacitance (1)
2.0 V to 3.6 V
1
pF
RIN
Input channel series
resistance
tPD
Propagation delay,
response time
tEN_CP
tEN_CP_DAC
Comparator enable
time
Comparator with
reference DAC enable
time
CPEN = 1, CPMSEL = 1, CPHSEL = 00
On (switch closed)
2.0 V to 3.6 V
Off (switch open)
CPMSEL = 0, CPFLT = 0,
Overdrive = 20 mV (2)
±10
tFDLY
1.3
3.5
10
µA
kΩ
MΩ
µs
2.4
CPEN = 0→1, CPMSEL = 1,
V+ and V- from pads, Overdrive = 20 mV (2)
CPEN = 0→1, CPDACEN=0→1,
CPMSEL = 0, CPDACREFS = 1,
CPDACBUF1 = 0F, Overdrive = 20 mV (2)
9.3
2.0 V to 3.6 V
µs
12
9.3
2.0 V to 3.6 V
µs
113
(2)
0.7
1.1
2.0 V to 3.6 V
CPMSEL = 0, CPFLTDY = 10,
Overdrive = 20 mV, (2) CPFLT = 1
1.9
CPMSEL = 0, CPFLTDY = 11,
Overdrive = 20 mV, (2) CPFLT = 1
3.7
VIN = reference into 6-bit DAC,
DAC uses internal REF, n = 0 to 63
20
mV
1
CPEN = 0→1, CPMSEL = 0,
V+ and V- from pads, Overdrive = 20 mV (2)
CPMSEL = 0, CPFLTDY = 01,
Overdrive = 20 mV, (2)
CPFLT = 1
35
50
CPMSEL = 0, CPFLTDY = 00,
Overdrive = 20 mV, (2)
CPFLT = 1
Propagation delay with
analog filter active
22
2.0 V to 3.6 V
CPMSEL = 1, CPFLT = 0,
Overdrive = 20 mV (2)
CPEN = 0→1, CPDACEN=0→1,
CPMSEL = 1, CPDACREFS = 1,
CPDACBUF1 = 0F, Overdrive = 20 mV
2.0 V to 3.6 V
–40
VOFFSET
µs
VIN ×
n / 64
VCP_DAC
Reference voltage for
built-in 6-bit DAC
INL
Integral nonlinearity
2.0 V to 3.6 V
–0.5
+0.5
LSB
DNL
Differential nonlinearity
2.0 V to 3.6 V
–0.5
+0.5
LSB
(1)
(2)
VIN = reference into 6-bit DAC,
DAC uses VCC as REF, n = 0 to 63
2.0 V to 3.6 V
V
VIN ×
n / 64
For the eCOMP CIN model, see Figure 5-14.
This is measured over the input offset.
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Table 5-21. eCOMP (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IDACOFF
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Zero scale
2.0 V to 3.6 V
0
LSB
Leakage current
2.0 V to 3.6 V
5
nA
MSP430
RS
RI
VI
VC
Cpext
CPAD
CIN
VI = External source voltage
RS = External source resistance
RI = Internal MUX-on input resistance
CIN = Input capacitance
CPAD = PAD capacitance
CPext = Parasitic capacitance, external
VC = Capacitance-charging voltage
Figure 5-14. eCOMP Input Circuit
5.13.10 FRAM
Table 5-22 lists the characteristics of the FRAM.
Table 5-22. FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tRetention
IWRITE
Data retention duration
Current to write into FRAM
IERASE
Erase current
tWRITE
Write time
IREAD
(1)
(2)
(3)
(4)
32
MIN
TYP
MAX
1015
Read and write endurance
TJ = 25°C
100
TJ= 70°C
40
TJ= 85°C
10
UNIT
cycles
years
IREAD (1)
n/a
nA
(2)
tREAD (3)
ns
Read time, NWAITSx = 0
1 / fSYSTEM (4)
ns
Read time, NWAITSx = 1
(4)
ns
2 / fSYSTEM
Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current IREAD is included in the active mode current consumption IAM, FRAM.
n/a = not applicable. FRAM does not require a special erase sequence.
Writing to FRAM is as fast as reading.
The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
Specifications
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5.13.11 Emulation and Debug
Table 5-23 lists the characteristics of the Spy-Bi-Wire interface.
Table 5-23. JTAG, Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-15)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.0 V, 3.0 V
0
8
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.0 V, 3.0 V
0.028
15
µs
tSU,SBWTDIO
SBWTDIO setup time (before falling edge of SBWTCK in TMS and TDI
slot Spy-Bi-Wire )
2.0 V, 3.0 V
4
ns
tHD,SBWTDIO
SBWTDIO hold time (after rising edge of SBWTCK in TMS and TDI
slot Spy-Bi-Wire )
2.0 V, 3.0 V
19
ns
tValid,SBWTDIO
SBWTDIO data valid time (after falling edge of SBWTCK in TDO slot
Spy-Bi-Wire )
2.0 V, 3.0 V
31
ns
(1)
2.0 V, 3.0 V
110
µs
Spy-Bi-Wire return to normal operation time (2)
2.0 V, 3.0 V
100
µs
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)
tSBW, En
tSBW,Ret
(1)
(2)
15
Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
Maximum tSBW,Rst time after pulling or releasing the TEST/SBWTCK pin low, the Spy-Bi-Wire pins revert from their Spy-Bi-Wire function
to their application function. This time applies only if the Spy-Bi-Wire mode was selected.
tSBW,EN
1/fSBW
tSBW,Low
tSBW,High
tSBW,Ret
TEST/SBWTCK
tEN,SBWTDIO
tValid,SBWTDIO
RST/NMI/SBWTDIO
tSU,SBWTDIO
tHD,SBWTDIO
Figure 5-15. JTAG Spy-Bi-Wire Timing
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Table 5-24 lists the characteristics of the 4-wire JTAG interface.
Table 5-24. JTAG, 4-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-16)
PARAMETER
fTCK
TCK input frequency
tTCK,Low
tTCK,high
VCC
(1)
MIN
TYP
MAX
UNIT
10
MHz
2.0 V, 3.0 V
0
TCK low clock pulse duration
2.0 V, 3.0 V
15
ns
TCK high clock pulse duration
2.0 V, 3.0 V
15
ns
tSU,TMS
TMS setup time (before rising edge of TCK)
2.0 V, 3.0 V
11
ns
tHD,TMS
TMS hold time (after rising edge of TCK)
2.0 V, 3.0 V
3
ns
tSU,TDI
TDI setup time (before rising edge of TCK)
2.0 V, 3.0 V
13
ns
tHD,TDI
TDI hold time (after rising edge of TCK)
2.0 V, 3.0 V
5
tz-Valid,TDO
TDO high impedance to valid output time (after falling edge of TCK)
2.0 V, 3.0 V
26
ns
tValid,TDO
TDO to new valid output time (after falling edge of TCK)
2.0 V, 3.0 V
26
ns
tValid-Z,TDO
TDO valid to high-impedance output time (after falling edge of TCK)
2.0 V, 3.0 V
26
ns
tJTAG,Ret
JTAG return to normal operation time
100
µs
Rinternal
Internal pulldown resistance on TEST
50
kΩ
(1)
ns
15
2.0 V, 3.0 V
20
35
Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
1/fTCK
tTCK,Low
tTCK,High
TCK
TMS
tSU,TMS
tHD,TMS
TDI
(or TDO as TDI)
tSU,TDI
tHD,TDI
TDO
tZ-Valid,TDO
tValid,TDO
tValid-Z,TDO
tJTAG,Ret
TEST
Figure 5-16. JTAG 4-Wire Timing
34
Specifications
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6 Detailed Description
6.1
Overview
The Texas Instruments MSP430FR211x family of ultra-low-power microcontrollers consists of several
devices featuring different sets of peripherals. The architecture, combined with five low-power modes, is
optimized to achieve extended battery life (for example, in portable measurement applications). The
devices feature a powerful 16-bit RISC CPU, 16-bit register, and constant generators that contribute to
maximum code efficiency.
The MSP430FR211x devices are microcontroller configurations with one Timer_B, eCOMP with built-in 6bit DAC as an internal reference voltage, a high-performance 10-bit ADC, an eUSCI that supports UART
and SPI, an RTC module with alarm capabilities, and up to 12 I/O pins.
6.2
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register
(SR), and constant generator (CG), respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be
managed with all instructions.
6.3
Operating Modes
The MSP430 has one active mode and several software selectable low-power modes of operation (see
Table 6-1). An interrupt event can wake up the device from low-power mode LPM0, LPM3 or LPM4,
service the request, and restore back to the low-power mode on return from the interrupt program. Lowpower modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption.
NOTE
XT1CLK and VLOCLK can be active during LPM4 if requested by low-frequency peripherals.
Detailed Description
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Table 6-1. Operating Modes
AM
LPM4
LPM3.5
LPM4.5
STANDBY
OFF
ONLY RTC
COUNTER
SHUTDOWN
16 MHz
40 kHz
0
40 kHz
0
120 µA/MHz
40 µA/MHz
1.5 µA
0.42 µA
without SVS
0.66 µA
34 nA
without SVS
Wake-up time
N/A
instant
10 µs
10 µs
150 µs
150 µs
Wake-up events
N/A
All
All
I/O
RTC Counter
I/O
I/O
Regulator
Full
Regulation
Full
Regulation
Partial Power
Down
Partial Power
Down
Partial Power
Down
Power Down
MODE
Maximum system clock
Power consumption at 25°C, 3 V
Power
On
On
Optional
Optional
Optional
Optional
On
On
On
On
On
On
MCLK
Active
Off
Off
Off
Off
Off
SMCLK
Optional
Optional
Off
Off
Off
Off
FLL
Optional
Optional
Off
Off
Off
Off
DCO
Optional
Optional
Off
Off
Off
Off
MODCLK
Optional
Optional
Off
Off
Off
Off
REFO
Optional
Optional
Optional
Off
Off
Off
ACLK
Optional
Optional
Optional
Off
Off
Off
XT1LFCLK
Optional
Optional
Optional
Off
Optional
Off
VLOCLK
Optional
Optional
Optional
Off
Optional
Off
CPU
On
Off
Off
Off
Off
Off
FRAM
On
On
Off
Off
Off
Off
RAM
On
On
On
On
Off
Off
Backup Memory (2)
On
On
On
On
On
Off
Timer_B3
Optional
Optional
Optional
Off
Off
Off
WDT
Optional
Optional
Optional
Off
Off
Off
eUSCI_A
Optional
Optional
Optional
Off
Off
Off
CRC
Optional
Optional
Off
Off
Off
Off
ADC (3)
Optional
Optional
Optional
Off
Off
Off
Peripherals
36
16 MHz
SVS
Core
(1)
(2)
(3)
CPU OFF
LPM3
Brownout
Clock (1)
I/O
LPM0
ACTIVE
MODE
eCOMP
Optional
Optional
Optional
Optional
Off
Off
RTC Counter
Optional
Optional
Optional
Off
Optional
Off
General Digital
Input/Output
On
Optional
State Held
State Held
State Held
State Held
Capacitive Touch I/O
Optional
Optional
Optional
Off
Off
Off
The status shown for LPM4 applies to internal clocks only.
Backup memory contains 32 bytes of register space in the peripheral memory. See Table 6-18 and Table 6-31 for its memory allocation.
The ADC is not available on the MSP430FR2000 device.
Detailed Description
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6.4
SLASE78B – AUGUST 2016 – REVISED JULY 2017
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 6-2
summarizes the interrupts sources, flags, and vectors.
Table 6-2. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
System Reset
Power up, brownout, supply supervisor
External reset RST
Watchdog time-out, key violation
FRAM uncorrectable bit error detection
Software POR, BOR
FLL unlock error
SVSHIFG
PMMRSTIFG
WDTIFG
PMMPORIFG, PMMBORIFG
SYSRSTIV
FLLULPUC
System NMI
Vacant memory access
JTAG mailbox
FRAM access time error
FRAM bit error detection
VMAIFG
JMBINIFG, JMBOUTIFG
CBDIFG, UBDIFG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
FFFEh
63, Highest
(Non)maskable
FFFCh
62
User NMI
External NMI
Oscillator fault
NMIIFG
OFIFG
(Non)maskable
FFFAh
61
Timer0_B3
TB0CCR0 CCIFG0
Maskable
FFF8h
60
Timer0_B3
TB0CCR1 CCIFG1, TB0CCR2
CCIFG2, TB0IFG (TB0IV)
Maskable
FFF6h
59
RTC counter
RTCIFG
Maskable
FFF4h
58
Watchdog timer interval mode
WDTIFG
Maskable
FFF2h
57
eUSCI_A0 receive or transmit
UCTXCPTIFG, UCSTTIFG,
UCRXIFG, UCTXIFG (UART
mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV))
Maskable
FFF0h
56
ADC
ADCIFG0, ADCINIFG,
ADCLOIFG, ADCHIIFG,
ADCTOVIFG, ADCOVIFG
(ADCIV)
Maskable
FFEEh
55
P1
P1IFG.0 to P1IFG.3 (P1IV)
Maskable
FFECh
54
P2
P2IFG.0, P2IFG.1, P2IFG.6 and
P2IFG.7 (P2IV)
Maskable
FFEAh
53
eCOMP0
CPIIFG, CPIFG (CPIV)
Maskable
FFE8h
52
Maskable
FFE6h to
FF88h
Reserved
Signatures
Reserved
BSL Signature 2
0FF86h
BSL Signature 1
0FF84h
JTAG Signature 2
0FF82h
JTAG Signature 1
0FF80h
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6.5
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Memory Organization
Table 6-3 summarizes the memory map of the MSP430FR211x and MSP430FR210x devices.
Table 6-3. Memory Organization
MEMORY TYPE
ACCESS
MSP430FR2111
MSP430FR2110
MSP430FR2100
MSP430FR2000
Read/write
(optional write
protect) (1)
3.75KB
FFFFh to FF80h
FFFFh to F100h
2KB
FFFFh to FF80h
FFFFh to F800h
1KB
FFFFh to FF80h
FFFFh to FC00h
0.5KB
FFFFh to FF80h
FFFFh to FE00h
RAM
Read/write
1KB
23FFh to 2000h
1KB
23FFh to 2000h
512 bytes
21FFh to 2000h
512 bytes
21FFh to 2000h
Bootloader (BSL) memory (ROM)
(TI internal use)
Read only
1KB
13FFh to 1000h
1KB
13FFh to 1000h
1KB
13FFh to 1000h
1KB
13FFh to 1000h
Peripherals
Read/write
4KB
0FFFh to 0000h
4KB
0FFFh to 0000h
4KB
0FFFh to 0000h
4KB
0FFFh to 0000h
Memory (FRAM)
Main: interrupt vectors and signatures
Main: code memory
(1)
6.6
The Program FRAM can be write protected by setting the PFWP bit in the SYSCFG0 register. See the SYS chapter in the
MSP430FR4xx and MSP430FR2xx Family User's Guide for more details.
Bootloader (BSL)
The BSL lets users program the FRAM or RAM using a UART interface. Access to the device memory
through the BSL is protected by an user-defined password. Table 6-4 lists the BSL pin requirements. BSL
entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a
complete description of the features of the BSL and its implementation, see the MSP430FR4xx and
MSP430FR2xx Bootloader (BSL) User's Guide.
Table 6-4. UART BSL Pin Requirements and Functions
6.7
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.7
Data transmit
P1.6
Data receive
VCC
Power Supply
VSS
Ground Supply
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/Os. The TEST/SBWTCK pin is used
to enable the JTAG signals. The RST/NMI/SBWTDIO pin is also is required to interface with MSP430
development tools and device programmers. Table 6-5 lists the JTAG pin requirements. For details on
interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide.
Table 6-5. JTAG Pin Requirements and Function
38
DEVICE SIGNAL
DIRECTION
JTAG FUNCTION
P1.4/UCA0STE/TCK/A4
IN
JTAG clock input
P1.5/UCA0CLK/TMS/A5
IN
JTAG state control
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
IN
JTAG data input, TCLK input
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
Detailed Description
VCC
Power supply
VSS
Ground supply
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6.8
SLASE78B – AUGUST 2016 – REVISED JULY 2017
Spy-Bi-Wire Interface (SBW)
The MSP430 family supports the 2-wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with
MSP430 development tools and device programmers. Table 6-6 lists the Spy-Bi-Wire interface pin
requirements. For further details on interfacing to development tools and device programmers, see the
MSP430 Hardware Tools User's Guide.
Table 6-6. Spy-Bi-Wire Pin Requirements and Functions
6.9
DEVICE SIGNAL
DIRECTION
SBW FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input and output
VCC
Power supply
VSS
Ground supply
FRAM
The FRAM can be programmed using the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. Features of the FRAM include:
• Byte and word access capability
• Programmable wait state generation
• Error correction coding (ECC)
6.10 Memory Protection
The device features memory protection of user access authority and write protection include:
• Securing the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing
JTAG and BSL signatures using the JTAG port, SBW, the BSL, or in-system by the CPU.
• Write protection enabled to prevent unwanted write operation to FRAM contents by setting the control
bits with accordingly password in System Configuration register 0. For more detailed information, see
the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide.
6.11 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be
handled by using all instructions in the memory map. For complete module description, see the
MSP430FR4xx and MSP430FR2xx Family User's Guide.
6.11.1 Power-Management Module (PMM) and On-Chip Reference Voltages
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM
also includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR)
is implemented to provide the proper internal reset signal to the device during power on and power off.
The SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is
available on the primary supply.
The device contains two on-chip reference: 1.5 V for internal reference and 1.2 V for external reference.
The 1.5-V reference is internally connected to ADC channel 13. DVCC is internally connected to ADC
channel 15. When DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily
represent as Equation 1 by using the ADC sampling the 1.5-V reference without any external components
support.
DVCC = (1023 × 1.5 V) / 1.5-V Reference ADC result
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The 1.5-V reference is also internally connected to the comparator built-in DAC as reference voltage.
DVCC is internally connected to another source of the DAC reference, and both are controlled by the
CPDACREFS bit. For more detailed information, see the Comparator chapter of the MSP430FR4xx and
MSP430FR2xx Family User's Guide.
A 1.2-V reference voltage can be buffered and output to P1.7/TDO/A7/VREF+, when EXTREFEN = 1 in
the PMMCTL2 register. ADC channel 7 can also be selected to monitor this voltage. For more detailed
information, see the MSP430FR4xx and MSP430FR2xx Family User's Guide.
NOTE
The ADC is not available on the MSP430FR2000 device.
6.11.2 Clock System (CS) and Clock Distribution
The clock system includes a 32-kHz low-frequency oscillator (XT1), an internal very-low-power lowfrequency oscillator (VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally
controlled oscillator (DCO) that may use frequency-locked loop (FLL) locking with an internal or external
32-kHz reference clock, and on-chip asynchronous high-speed clock (MODOSC). The clock system is
designed to target cost-effective designs with minimal external components. A fail-safe mechanism is
designed for XT1. The clock system module offers the following clock signals.
• Main Clock (MCLK): the system clock used by the CPU and all relevant peripherals accessed by the
bus. All clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8,
16, 32, 64, or 128.
• Sub-Main Clock (SMCLK): the subsystem clock used by the peripheral modules. SMCLK derives from
the MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.
• Auxiliary Clock (ACLK): this clock is derived from the external XT1 clock or internal REFO clock up to
40 kHz.
All peripherals may have one or several clock sources depending on specific functionality. Table 6-7 and
Table 6-8 summarize the clock distribution used in this device.
Table 6-7. Clock Distribution
CLOCK
SOURCE
SELECT BITS
Frequency
Range
MCLK
SMCLK
ACLK
MODCLK
VLOCLK
DC to 16 MHz
DC to 16 MHz
DC to 40 kHz
4 MHz
10 kHz
CPU
N/A
Default
FRAM
N/A
Default
RAM
N/A
Default
CRC
N/A
Default
I/O
N/A
Default
EXTERNAL PIN
TB0
TBSSEL
10b
01b
00b (TB0CLK pin)
eUSCI_A0
UCSSEL
10b or 11b
01b
00b (UCA0CLK pin)
WDTSSEL
00b
01b
ADCSSEL
10b or 11b
01b
RTCSS
01b
01b
WDT
ADC
RTC
(1)
40
(1)
10b
00b
11b
The ADC is not available on the MSP430FR2000 device.
Detailed Description
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SLASE78B – AUGUST 2016 – REVISED JULY 2017
Table 6-8. XTCLK Distribution
XTLFCLK
CLOCK SOURCE
SELECT BITS
AM TO LPM3.5 (DC to 40 kHz)
MCLK
SELMS
10b
SMCLK
SELMS
10b
REFO
SELREF
0b
ACLK
SELA
0b
RTC
RTCSS
10b
OPERATION MODE
6.11.3 General-Purpose Input/Output Port (I/O)
Up to 12 I/O ports are implemented.
• P1 has 8 bits implemented, and P2 has 4 bits implemented.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible to P1 and P2.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt, LPM4, LPM3.5 and LPM4.5 wake-up input capability is available for P1.0 to
P1.3, P2.0, P2.1, P2.6, and P2.7.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
• Capacitive Touch I/O functionality is supported on all pins.
NOTE
Configuration of digital I/Os after BOR reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR
reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared. For
details, see the Configuration After Reset section in the Digital I/O chapter of the
MSP430FR4xx and MSP430FR2xx Family User's Guide.
6.11.4 Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as interval timer and can generate interrupts at
selected time intervals.
Table 6-9. WDT Clocks
WDTSSEL
NORMAL OPERATION
(WATCHDOG AND INTERVAL TIMER MODE)
00
SMCLK
01
ACLK
10
VLOCLK
11
Reserved
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6.11.5 System Module (SYS)
The SYS module handles many of the system functions within the device. These system functions include
power-on reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset
interrupt vector generators, bootloader entry mechanisms, and configuration management (device
descriptors). SYS also includes a data exchange mechanism through SBW called a JTAG mailbox that
can be used in the application. Table 6-10 lists the SYS module interrupt vector registers.
Table 6-10. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
SYSRSTIV, System Reset
SYSSNIV, System NMI
SYSUNIV, User NMI
42
Detailed Description
ADDRESS
015Eh
015Ch
015Ah
INTERRUPT EVENT
VALUE
No interrupt pending
00h
Brownout (BOR)
02h
RSTIFGRST/NMI (BOR)
04h
PMMSWBOR software BOR (BOR)
06h
LPMx.5 wakeup (BOR)
08h
Security violation (BOR)
0Ah
Reserved
0Ch
SVSHIFG SVSH event (BOR)
0Eh
Reserved
10h
Reserved
12h
PMMSWPOR software POR (POR)
14h
WDTIFG watchdog time-out (PUC)
16h
WDTPW password violation (PUC)
18h
FRCTLPW password violation (PUC)
1Ah
Uncorrectable FRAM bit error detection
1Ch
Peripheral area fetch (PUC)
1Eh
PMMPW PMM password violation (PUC)
20h
Reserved
22h
FLL unlock (PUC)
24h
Reserved
26h to 3Eh
No interrupt pending
00h
SVS low-power reset entry
02h
Uncorrectable FRAM bit error detection
04h
Reserved
06h
Reserved
08h
Reserved
0Ah
Reserved
0Ch
Reserved
0Eh
Reserved
10h
VMAIFG Vacant memory access
12h
JMBINIFG JTAG mailbox input
14h
JMBOUTIFG JTAG mailbox output
16h
Correctable FRAM bit error detection
18h
Reserved
1Ah to 1Eh
No interrupt pending
00h
NMIIFG NMI pin or SVSH event
02h
OFIFG oscillator fault
04h
Reserved
06h to 1Eh
PRIORITY
Highest
Lowest
Highest
Lowest
Highest
Lowest
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6.11.6 Cyclic Redundancy Check (CRC)
The 16-bit CRC module produces a signature based on a sequence of data values and can be used for
data checking purposes. The CRC generation polynomial is compliant with CRC-16-CCITT standard of
x16 + x12 + x5 + 1.
6.11.7 Enhanced Universal Serial Communication Interface (eUSCI_A0)
The eUSCI modules are used for serial data communications. The eUSCI_A module supports either
UART or SPI communications. Additionally, eUSCI_A supports automatic baud-rate detection and IrDA.
Table 6-11. eUSCI Pin Configurations
PIN (USCIARMP = 0)
UART
SPI
P1.7
TXD
SIMO
P1.6
RXD
P1.5
eUSCI_A0
P1.4
PIN (USCIARMP = 1)
STE
UART
SPI
(1)
TXD
SIMO
P1.2 (1)
RXD
P1.3
(1)
SOMI
SCLK
SOMI
P1.1 (1)
SCLK
P1.0 (1)
STE
This is the remapped functionality controlled by the USCIARMP bit in the SYSCFG3 register. Only one selected port is valid at the same
time.
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6.11.8 Timers (Timer0_B3)
The Timer0_B3 module is 16-bit timer and counter with three capture/compare registers. The timer can
support multiple captures or compares, PWM outputs, and interval timing (see Table 6-12). Timer0_B3
has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions
and from each of the capture/compare registers. The CCR0 register on Timer0_B3 is not externally
connected and can be used only for hardware period timing and interrupt generation. In Up Mode, it can
be used to set the overflow value of the counter.
Table 6-12. Timer0_B3 Signal Connections
PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
P2.7
TB0CLK
TBCLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
From Capacitive
Touch I/O (internal)
INCLK
From RTC (internal)
CCI0A
ACLK (internal)
CCI0B
DVSS
GND
DVCC
VCC
TB0.1
CCI1A
From eCOMP
(internal)
CCI1B
P1.6 (TBRMP = 0)
P2.0 (TBRMP = 1) (1)
DVSS
GND
DVCC
VCC
TB0.2
CCI2A
From Capacitive
Touch I/O (internal)
CCI2B
DVSS
GND
DVCC
VCC
P1.7 (TBRMP = 0)
P2.1 (TBRMP = 1) (1)
(1)
(2)
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
CCR0
TB0
DEVICE OUTPUT
SIGNAL
TB0.1
CCR1
TB1
To ADC trigger (2)
TB0.2
CCR2
TB2
This is the remapped functionality controlled by the TBRMP bit in the SYSCFG3 register. Only one selected port is valid at the same
time when TB0 acts as capture input functionality. TB0 PWM outputs regardless of the setting on this remap bit.
The ADC is not available on the MSP430FR2000 device.
The interconnection of Timer0_B3 can be used to modulate the eUSCI_A pin of UCA0TXD/UCA0SIMO in
either ASK or part of FSK mode, with which a user can easily acquire a modulated infrared command for
directly driving an external IR diode. The IR functions are fully controlled by SYSCFG1 including IREN
(enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSEL (data select), and IRDATA (data) bits.
For more information, see the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's
Guide.
The Timer_B module can put all Timer_B outputs into a high-impedance state when the selected source is
triggered. The source can be selected from external pin or internal of the device, which is controlled by
TB0TRG in SYS. For more information, see the SYS chapter in the MSP430FR4xx and MSP430FR2xx
Family User's Guide.
44
Detailed Description
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Table 6-13 summarizes the selection of the Timer_B high-impedance trigger.
Table 6-13. TBxOUTH
TB0TRGSEL
TB0OUTH TRIGGER SOURCE
SELECTION
TB0TRGSEL = 0
eCOMP0 output (internal)
TB0TRGSEL= 1
P1.2
(1)
Timer_B PAD OUTPUT HIGH IMPEDANCE
P1.6, P1.7, P2.0, P2.1 (1)
When TB0 is set to PWM output function, both port groups can receive the output, and the output is
controlled by only the PxSEL.y bits.
6.11.9 Backup Memory (BAKMEM)
The BAKMEM supports data retention functionality during LPM3.5 mode. This device provides up to 32
bytes that are retained during LPM3.5.
6.11.10 Real-Time Clock (RTC) Counter
The RTC counter is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, LPM4, and LPM3.5.
This module may periodically wake up the CPU from LPM0, LPM3, LPM4, or LPM3.5 based on timing
from a low-power clock source such as XT1, ACLK, or VLO. In AM, RTC can be driven by SMCLK to
generate high-frequency timing events and interrupts. ACLK and SMCLK both can source to the RTC;
however, only one of them can be selected at any given time. The RTC overflow events trigger:
• Timer0_B3 CCR0A
• ADC conversion trigger when ADCSHSx bits are set as 01b
6.11.11 10-Bit Analog-to-Digital Converter (ADC)
The 10-bit ADC module supports fast 10-bit analog-to-digital conversions with single-ended input. The
module implements a 10-bit SAR core, sample select control, reference generator, and a conversion result
buffer. A window comparator with lower and upper limits allows CPU-independent result monitoring with
three window comparator interrupt flags.
NOTE
The ADC is not available on the MSP430FR2000 device.
Detailed Description
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The ADC supports 10 external inputs and 4 internal inputs (see Table 6-14).
Table 6-14. ADC Channel Connections
(1)
ADCSHSx
ADC CHANNELS
EXTERNAL PIN OUT
0
A0/Veref+
P1.0
1
A1/
P1.1
2
A2/Veref-
P1.2
3
A3
P1.3
4
A4
P1.4
5
A5
P1.5
6
A6
P1.6
7
A7 (1)
P1.7
8
Not used
N/A
9
Not used
N/A
10
Not used
N/A
11
Not used
N/A
12
On-chip temperature sensor
N/A
13
Reference voltage (1.5 V)
N/A
14
DVSS
N/A
15
DVCC
N/A
When A7 is used, the PMM 1.2-V reference voltage can be output to this pin by setting the PMM
control register. The 1.2-V voltage can be directly measured by A7 channel.
The conversion can be started by software or a hardware trigger. Table 6-15 lists the trigger sources that
are available.
Table 6-15. ADC Trigger Signal Connections
ADCSHSx
46
Detailed Description
TRIGGER SOURCE
BINARY
DECIMAL
00
0
ADCSC bit (software trigger)
01
1
RTC event
10
2
TB0.1B
11
3
eCOMP0 COUT
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6.11.12 eCOMP0
The enhanced comparator is an analog voltage comparator with built-in 6-bit DAC as an internal voltage
reference. The integrated 6-bit DAC can be set up to 64 steps for comparator reference voltage. This
module has 4-level programmable hysteresis and a configurable power mode: high-power or low-power
mode.
The eCOMP0 supports external inputs and internal inputs (see Table 6-16) and outputs (see Table 6-17)
Table 6-16. eCOMP0 Input Channel Connections
CPPSEL, CPNSEL
eCOMP0 CHANNELS
EXTERNAL OR INTERNAL
CONNECTION
000
C0
P1.0
001
C1
P1.1
010
C2
P1.2
011
C3
P1.3
100
C4
Not used
101
C5
Not used
110
C6
Built-in 6-bit DAC
BINARY
Table 6-17. eCOMP0 Output Channel Connections
eCOMP0 Out
EXTERNAL PIN OUT, MODULE
1
P2.0
2
TB0.1B ; TB0 (TB0OUTH); ADC
6.11.13 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The EEM on these devices has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers that can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
Detailed Description
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6.11.14 Peripheral File Map
Table 6-18 lists the base address and the memory size of the registers for each peripheral.
Table 6-18. Peripherals Summary
BASE ADDRESS
SIZE
Special Functions (see Table 6-19)
MODULE NAME
0100h
0010h
PMM (see Table 6-20)
0120h
0020h
SYS (see Table 6-21)
0140h
0040h
CS (see Table 6-22)
0180h
0020h
FRAM (see Table 6-23)
01A0h
0010h
CRC (see Table 6-24)
01C0h
0008h
WDT (see Table 6-25)
01CCh
0002h
Port P1, P2 (see Table 6-26)
0200h
0020h
Capacitive Touch I/O (see Table 6-27)
02E0h
0010h
RTC (see Table 6-28)
0300h
0010h
Timer0_B3 (see Table 6-29)
0380h
0030h
eUSCI_A0 (see Table 6-30)
0500h
0020h
Backup Memory (see Table 6-31)
0660h
0020h
ADC (1) (see Table 6-32)
0700h
0040h
eCOMP0 (see Table 6-33)
08E0h
0020h
(1)
The ADC is not available on the MSP430FR2000 device.
Table 6-19. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
SFR interrupt enable
SFR interrupt flag
SFR reset pin control
REGISTER
OFFSET
SFRIE1
00h
SFRIFG1
02h
SFRRPCR
04h
Table 6-20. PMM Registers (Base Address: 0120h)
REGISTER
OFFSET
PMM control 0
REGISTER DESCRIPTION
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
PMM control 2
PMMCTL2
04h
PMM interrupt flags
PMMIFG
0Ah
PM5 control 0
PM5CTL0
10h
48
Detailed Description
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Table 6-21. SYS Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SYSCTL
00h
Bootloader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
System control
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
System configuration 0
SYSCFG0
20h
System configuration 1
SYSCFG1
22h
System configuration 2
SYSCFG2
24h
System configuration 3
SYSCFG3
26h
Table 6-22. CS Registers (Base Address: 0180h)
REGISTER
OFFSET
CS control 0
REGISTER DESCRIPTION
CSCTL0
00h
CS control 1
CSCTL1
02h
CS control 2
CSCTL2
04h
CS control 3
CSCTL3
06h
CS control 4
CSCTL4
08h
CS control 5
CSCTL5
0Ah
CS control 6
CSCTL6
0Ch
CS control 7
CSCTL7
0Eh
CS control 8
CSCTL8
10h
Table 6-23. FRAM Registers (Base Address: 01A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
FRAM control 0
FRCTL0
00h
General control 0
GCCTL0
04h
General control 1
GCCTL1
06h
Table 6-24. CRC Registers (Base Address: 01C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC16DI
00h
CRC data input reverse byte
CRCDIRB
02h
CRC initialization and result
CRCINIRES
04h
CRC result reverse byte
CRCRESR
06h
CRC data input
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Table 6-25. WDT Registers (Base Address: 01CCh)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
OFFSET
WDTCTL
00h
Table 6-26. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
P1IN
00h
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pulling enable
P1REN
06h
Port P1 selection 0
P1SEL0
0Ah
Port P1 selection 1
Port P1 input
Port P1 output
P1SEL1
0Ch
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
P1IE
1Ah
P1IFG
1Ch
P2IN
01h
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 pulling enable
P2REN
07h
Port P2 selection 0
P2SEL0
0Bh
Port P2 selection 1
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
Port P2 output
P2SEL1
0Dh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
P2IE
1Bh
P2IFG
1Dh
Port P2 interrupt enable
Port P2 interrupt flag
Table 6-27. Capacitive Touch I/O Registers (Base Address: 02E0h)
REGISTER DESCRIPTION
Capacitive Touch I/O 0 control
REGISTER
OFFSET
CAPIO0CTL
0Eh
Table 6-28. RTC Registers (Base Address: 0300h)
REGISTER DESCRIPTION
RTC control
RTC interrupt vector
REGISTER
OFFSET
RTCCTL
00h
RTCIV
04h
RTC modulo
RTCMOD
08h
RTC counter
RTCCNT
0Ch
50
Detailed Description
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Table 6-29. Timer0_B3 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0CTL
00h
Capture/compare control 0
TB0CCTL0
02h
Capture/compare control 1
TB0CCTL1
04h
Capture/compare control 2
TB0CCTL2
06h
TB0R
10h
Capture/compare 0
TB0CCR0
12h
Capture/compare 1
TB0CCR1
14h
Capture/compare 2
TB0CCR2
16h
TB0EX0
20h
TB0IV
2Eh
TB0 control
TB0 counter
TB0 expansion 0
TB0 interrupt vector
Table 6-30. eUSCI_A0 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA0CTLW0
00h
eUSCI_A control word 1
UCA0CTLW1
02h
eUSCI_A control rate 0
UCA0BR0
06h
UCA0BR1
07h
eUSCI_A control rate 1
eUSCI_A modulation control
UCA0MCTLW
08h
UCA0STAT
0Ah
eUSCI_A receive buffer
UCA0RXBUF
0Ch
eUSCI_A transmit buffer
UCA0TXBUF
0Eh
eUSCI_A LIN control
UCA0ABCTL
10h
eUSCI_A IrDA transmit control
lUCA0IRTCTL
12h
eUSCI_A IrDA receive control
IUCA0IRRCTL
13h
UCA0IE
1Ah
UCA0IFG
1Ch
UCA0IV
1Eh
eUSCI_A status
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
Detailed Description
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Table 6-31. Backup Memory Registers (Base Address: 0660h)
REGISTER
OFFSET
Backup memory 0
REGISTER DESCRIPTION
BAKMEM0
00h
Backup memory 1
BAKMEM1
02h
Backup memory 2
BAKMEM2
04h
Backup memory 3
BAKMEM3
06h
Backup memory 4
BAKMEM4
08h
Backup memory 5
BAKMEM5
0Ah
Backup memory 6
BAKMEM6
0Ch
Backup memory 7
BAKMEM7
0Eh
Backup memory 8
BAKMEM8
10h
Backup memory 9
BAKMEM9
12h
Backup memory 10
BAKMEM10
14h
Backup memory 11
BAKMEM11
16h
Backup memory 12
BAKMEM12
18h
Backup memory 13
BAKMEM13
1Ah
Backup memory 14
BAKMEM14
1Ch
Backup memory 15
BAKMEM15
1Eh
Table 6-32. ADC Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC control 0
ADCCTL0
00h
ADC control 1
ADCCTL1
02h
ADC control 2
ADCCTL2
04h
ADCLO
06h
ADC window comparator low threshold
ADC window comparator high threshold
ADCHI
08h
ADC memory control 0
ADCMCTL0
0Ah
ADC conversion memory
ADCMEM0
12h
ADC interrupt enable
ADC interrupt flags
ADC interrupt vector word
ADCIE
1Ah
ADCIFG
1Ch
ADCIV
1Eh
Table 6-33. eCOMP0 Registers (Base Address: 08E0h)
REGISTER
OFFSET
Comparator control 0
REGISTER DESCRIPTION
CPCTL0
00h
Comparator control 1
CPCTL1
02h
Comparator interrupt
CPINT
06h
CPIV
08h
CPDACCTL
10h
CPDACDATA
12h
Comparator interrupt vector
Comparator built-in DAC control
Comparator built-in DAC data
52
Detailed Description
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6.11.15 Input/Output Diagrams
6.11.15.1 Port P1 Input/Output With Schmitt Trigger
Figure 6-1 shows the port diagram. Table 6-34 summarizes the selection of the pin functions.
A0..A7
C0,C1,C2,C3
P1REN.x
P1DIR.x
From Module1
00
01
10
11
2 bit
From Module2
DVSS
0
DVCC
1
P1SEL.x= 11
00
01
10
11
P1OUT.x
From Module1
From Module2
DVSS
2 bit
P1SEL.x
EN
To module
D
P1IN.x
P1IE.x
P1 Interrupt
Q
D
Bus
Keeper
S
P1IFG.x
Edge
Select
P1IES.x
From JTAG
To JTAG
P1.0/UCA0STE/SMCLK/C0/A0/Veref+
P1.1/UCA0CLK/ACLK/C1/A1
P1.2/UCA0RXD/UCA0SOMI/TB0TRG/C2/A2/VerefP1.3/UCA0TXD/UCA0SIMO/C3/A3
P1.4/UCA0STE/TCK/A4
P1.5/UCA0CLK/TMS/A5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+
NOTE: Functional representation only.
NOTE: The ADC (signals A0 to A7, Veref+, and Veref-) is not available on the MSP430FR2000 device.
Figure 6-1. Port P1 Input/Output With Schmitt Trigger
Detailed Description
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Table 6-34. Port P1 Pin Functions
PIN NAME (P1.x)
x
P1.0/UCA0STE/SMCLK/
C0/A0/Veref+
P1.1/UCA0CLK/ACLK/
C1/A1
0
1
P1.2/UCA0RXD/
UCA0SOMI/TB0TRG/
C2/A2/Veref-
2
FUNCTION
P1DIR.x
P1SELx
JTAG
P1.0 (I/O)
I: 0; O: 1
00
N/A
UCA0STE
X
01
N/A
SMCLK
1
VSS
0
10
N/A
C0, A0/Veref+ (2)
X
11
N/A
P1.1 (I/O)
I: 0; O: 1
0
N/A
UCA0CLK
X
01
N/A
ACLK
1
VSS
0
10
N/A
C1, A1 (2)
X
11
N/A
P1.2 (I/O)
I: 0; O: 1
00
N/A
X
01
N/A
TB0TRG
0
10
N/A
C2, A2/Veref- (2)
X
11
N/A
I: 0; O: 1
00
N/A
UCA0TXD/UCA0SIMO
X
01
N/A
C3, A3 (2)
X
11
N/A
P1.4 (I/O)
I: 0; O: 1
00
Disabled
UCA0STE
X
01
N/A
A4 (2)
X
11
Disabled
UCA0RXD/UCA0SOMI
P1.3 (I/O)
P1.3/UCA0TXD/
UCA0SIMO/C3/A3
3
P1.4/UCA0STE/TCK/A4
P1.5/UCA0CLK/TMS/A5
4
5
JTAG TCK
X
X
TCK
P1.5 (I/O)
I: 0; O: 1
00
Disabled
UCA0CLK
X
01
N/A
A5 (2)
X
11
Disabled
JTAG TMS
X
X
TMS
P1.6 (I/O)
P1.6/UCA0RXD/
UCA0SOMI/TB0.1/
TDI/TCLK/A6
6
I: 0; O: 1
00
Disabled
UCA0RXD/UCA0SOMI
X
01
N/A
TB0.CCI1A
0
TB0.1
1
10
N/A
A6 (2)
X
11
Disabled
JTAG TDI/TCLK
X
X
TDI/TCLK
I: 0; O: 1
00
Disabled
UCA0TXD/UCA0SIMO
X
01
N/A
TB0.CCI2A
0
TB0.2
1
10
N/A
A7 (2), VREF+
X
11
Disabled
JTAG TDO
X
X
TDO
P1.7 (I/O)
P1.7/UCA0TXD/
UCA0SIMO/TB0.2/
TDO/A7/VREF+
(1)
(2)
54
7
CONTROL BITS AND SIGNALS (1)
X = don't care
The ADC is not available on the MSP430FR2000 device.
Detailed Description
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6.11.15.2 Port P2 Input/Output With Schmitt Trigger
Figure 6-2 shows the port diagram. Table 6-35 summarizes the selection of the pin functions.
P2REN.x
P2DIR.x
From Module1
00
01
10
11
2 bit
From Module2
DVSS
0
DVCC
1
00
01
10
11
P2OUT.x
From Module1
From Module2
DVSS
2 bit
P2SEL.x
EN
To module
D
P2IN.x
P2IE.x
P2 Interrupt
Q
D
Bus
Keeper
S
P2IFG.x
Edge
Select
P2IES.x
P2.0/TB0.1/COUT
P2.1/TB0.2
P2.6/MCLK/XOUT
P2.7/TB0CLK/XIN
NOTE: Functional representation only.
Figure 6-2. Port P2 Input/Output With Schmitt Trigger
Detailed Description
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Table 6-35. Port P2 Pin Functions
PIN NAME (P2.x)
x
FUNCTION
P2.0 (I/O)
P2.0/TB0.1/COUT
0
1
6
(1)
56
7
00
TB0.1
1
01
1
10
P2.1 (I/O)0
I: 0; O: 1
00
TB0.CCI2A
0
TB0.2
1
I: 0; O: 1
MCLK
1
VSS
0
XOUT
P2.7/TB0CLK/XIN
P2SELx
0
P2.6 (I/O)
P2.6/MCLK/XOUT
P2DIR.x
I: 0; O: 1
TB0.CCI1A
COUT
P2.1/TB0.2
CONTROL BITS AND SIGNALS (1)
01
00
01
X
10
P2.7 (I/O)
I: 0; O: 1
00
TB0CLK
0
VSS
1
XIN
X
01
10
X = don't care
Detailed Description
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6.12 Device Descriptors (TLV)
Table 6-36 lists the Device IDs of the MSP430FR211x MCUs. Table 6-37 lists the contents of the device
descriptor tag-length-value (TLV) structure for MSP430FR211x MCUs.
Table 6-36. Device IDs
DEVICE ID
DEVICE
1A04h
1A05h
MSP430FR2111
FA
82
MSP430FR2110
FB
82
MSP430FR2100
20
83
MSP430FR2000
21
83
Table 6-37. Device Descriptors
DESCRIPTION
VALUE
Info length
1A00h
06h
CRC length
1A01h
06h
1A02h
Per unit
1A03h
Per unit
CRC value (1)
Info Block
Device ID
See Table 6-36.
1A06h
Per unit
1A07h
Per unit
Die record tag
1A08h
08h
Die record length
1A09h
0Ah
1A0Ah
Per unit
1A0Bh
Per unit
1A0Ch
Per unit
1A0Dh
Per unit
1A0Eh
Per unit
1A0Fh
Per unit
1A10h
Per unit
1A11h
Per unit
1A12h
Per unit
1A13h
Per unit
ADC calibration tag
1A14h
Per unit
ADC calibration length
1A15h
Per unit
1A16h
Per unit
1A17h
Per unit
1A18h
Per unit
1A19h
Per unit
1A1Ah
Per unit
1A1Bh
Per unit
1A1Ch
Per unit
1A1Dh
Per unit
Die X position
Die Y position
Test result
ADC gain factor
ADC offset
ADC 1.5-V reference temperature 30°C
ADC 1.5-V reference temperature 85°C
(2)
1A05h
Firmware revision
Die Record
(1)
1A04h
Hardware revision
Lot wafer ID
ADC Calibration (2)
MSP430FR211x
ADDRESS
The CRC value includes the checksum from 0x1A04h to 0x1A77h, calculated by applying the CRC-CCITT-16 polynomial of X16+ X12+
X5 + 1
The ADC is not available on the MSP430FR2000 device.
Detailed Description
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Table 6-37. Device Descriptors (continued)
MSP430FR211x
DESCRIPTION
Reference and DCO
Calibration
ADDRESS
VALUE
Calibration tag
1A1Eh
12h
Calibration length
1A1Fh
04h
1A20h
Per unit
1A21h
Per unit
1A22h
Per unit
1A23h
Per unit
1.5-V reference factor
DCO tap settings for 16 MHz, temperature 30°C
(3)
(3)
This value can be directly loaded into the DCO bits in the CSCTL0 register to get accurate 16-MHz frequence at room temperature,
especially when the MCU exits from LPM3 and below. TI suggests using a predivider to decrease the frequency if the temperature drift
might result an overshoot >16 MHz.
6.13 Identification
6.13.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to the errata sheets for the devices in this
data sheet, see Section 8.4.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Hardware Revision" entries in Section 6.12.
6.13.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to the errata sheets for the devices in this data sheet, see
Section 8.4.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Device ID" entries in Section 6.12.
6.13.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in MSP430 Programming With the JTAG Interface.
58
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7 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI's customers are
responsible for determining suitability fo components for their purposes. Customers should
validate and test their implementation to confirm system functionality.
7.1
Device Connection and Layout Fundamentals
This section describes the recommended guidelines when designing with the MSP430. These guidelines
are to make sure that the device has proper connections for powering, programming, debugging, and
optimum analog performance.
7.1.1
Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 10-µF capacitor and a 100-nF low-ESR ceramic decoupling
capacitor to the DVCC pin. Higher-value capacitors may be used but can impact supply rail ramp-up time.
Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few
millimeters).
DVCC
Digital
Power Supply
Decoupling
+
1 µF
100 nF
DVSS
Figure 7-1. Power Supply Decoupling
7.1.2
External Oscillator
Depending on the device variant (see Table 3-1), the device supports only a low-frequency crystal
(32 kHz) on the LFXT pins. External bypass capacitors for the crystal oscillator pins are required.
It is also possible to apply digital clock signals to the LFXIN input pins that meet the specifications of the
respective oscillator if the appropriate LFXTBYPASS mode is selected. In this case, the associated
LFXOUT pins can be used for other purposes. If the LFXOUT pins are left unused, they must be
terminated according to Section 4.5.
Figure 7-2 shows a typical connection diagram. See MSP430 32-kHz Crystal Oscillators for information on
selecting, testing, and designing a crystal oscillator with the MSP430 devices.
XIN
CL1
XOUT
CL2
Figure 7-2. Typical Crystal Connection
Applications, Implementation, and Layout
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JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG
connector and the target device required to support in-system programming and debugging for 4-wire
JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSPFET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.
Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the
target board. If this flexibility is not required, the desired VCC connections may be hardwired to eliminate
the jumper block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s
Guide.
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kW
JTAG
VCC TOOL
VCC TARGET
2
1
4
3
6
TEST
RST/NMI/SBWTDIO
5
8
7
10
9
12
11
14
13
TDO/TDI
TDO/TDI
TDI
TDI
TMS
TCK
TMS
TCK
GND
RST
TEST/SBWTCK
C1
1 nF
(see Note B)
DVSS
Copyright © 2016, Texas Instruments Incorporated
A.
B.
If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-3. Signal Connections for 4-Wire JTAG Communication
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VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kΩ
(see Note B)
JTAG
VCC TOOL
VCC TARGET
2
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
RST/NMI/SBWTDIO
TCK
GND
TEST/SBWTCK
C1
1 nF
(see Note B)
DVSS
Copyright © 2016, Texas Instruments Incorporated
A.
B.
Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.4
Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 10-nF pulldown capacitor. The pulldown capacitor
should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire
JTAG mode with TI tools like FET interfaces or GANG programmers.
See the MSP430FR4xx and MSP430FR2xx Family User's Guide for more information on the referenced
control registers and bits.
7.1.5
Unused Pins
For details on the connection of unused pins, see Section 4.5.
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General Layout Recommendations
•
•
•
•
•
7.1.7
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430
32-kHz Crystal Oscillators for recommended layout guidelines.
Proper bypass capacitors on DVCC, AVCC, and reference pins if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit and ADC signals.
See Circuit Board Layout Techniques for a detailed discussion of PCB layout considerations. This
document is written primarily about op amps, but the guidelines are generally applicable for all mixedsignal applications.
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.
Do's and Don'ts
During power up, power down, and device operation, the voltage difference between AVCC and DVCC
must not exceed the limits specified in Absolute Maximum Ratings. Exceeding the specified limits may
cause malfunction of the device including erroneous writes to RAM and FRAM.
7.2
Peripheral- and Interface-Specific Design Information
7.2.1
ADC Peripheral
NOTE
The ADC is not available on the MSP430FR2000 device.
7.2.1.1
Partial Schematic
Figure 7-5 shows the recommended decoupling circuit with either an internal or an external voltage
reference.
DVSS
Using an external
positive reference
VREF+/VEREF+
+
10 µF
100 nF
Using an external
negative reference
VEREF+
10 µF
100 nF
Figure 7-5. ADC Grounding and Noise Considerations
7.2.1.2
Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in Section 7.1.1 combined with the connections shown in Section 7.2.1.1 prevent this.
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In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital
switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free
design using separate analog and digital ground planes with a single-point connection to achieve high
accuracy.
Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as described in the sections ADC Pin Enable and
1.2-V Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide.
The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-µF capacitor is used to buffer the reference pin and filter any lowfrequency ripple. A bypass capacitor of 100 nF is used to filter out any high-frequency noise.
7.2.1.3
Layout Guidelines
Components that are shown in the partial schematic (see Figure 7-5) should be placed as close as
possible to the respective device pins to avoid long traces, because they add additional parasitic
capacitance, inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
7.3
Typical Applications
Table 7-1 lists several TI Designs that reflect the use of the MSP430FR211x family of devices in different
real-world application scenarios. Consult these designs for additional guidance regarding schematic,
layout, and software implementation. For the most up-to-date list of available TI Designs, see the devicespecific product folders listed in Section 8.5.
Table 7-1. TI Designs
DESIGN NAME
LINK
Thermostat Implementation With MSP430FR4xx
TIDM-FRAM-THERMOSTAT
Water Meter Implementation With MSP430FR4xx
TIDM-FRAM-WATERMETER
Remote Controller of Air Conditioner Using Low-Power Microcontroller
TIDM-REMOTE-CONTROLLER-FOR-AC
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8 Device and Documentation Support
8.1
Getting Started and Next Steps
For more information on the MSP430™ family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started page.
8.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of
three prefixes: MSP, PMS, or XMS (for example, MSP430FR2111). Texas Instruments recommends two
of three possible prefix designators for its support tools: MSP and MSPX. These prefixes represent
evolutionary stages of product development from engineering prototypes (with XMS for devices and MSPX
for tools) through fully qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed Texas Instruments internal qualification
testing.
MSP – Fully-qualified development-support product
XMS devices and MSPX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PW) and temperature range (for example, T). Figure 8-1 provides a legend for
reading the complete device name for any family member.
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MSP 430 FR 2 111 I PW T
Processor Family
MCU Platform
Device Type
Optional: Distribution Format
Series
Feature Set
Packaging
Optional: Temperature Range
Processor Family
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
MCU Platform
430 = TI’s 16-bit MSP430 Low-Power Microcontroller Platform
Device Type
Memory Type
FR = FRAM
Series
4 = Up to 16 MHz with LCD
2 = Up to 16 MHz without LCD
Feature Set
Variations of the device features; see the Device Comparison section for details
Optional: Temperature Range
S = 0°C to 50°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
www.ti.com/packaging
Optional: Distribution Format
T = Small reel
R = Large reel
No marking = Tube or tray
Figure 8-1. Device Nomenclature
Device and Documentation Support
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Tools and Software
All MSP microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties. See them all at Development Kits and Software for
Low-Power MCUs.
Table 8-1 lists the debug features of the MSP430FR211x microcontrollers. See the Code Composer
Studio for MSP430 User's Guide for details on the available features.
Table 8-1. Hardware Debug Features
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
(N)
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
LPMx.5
DEBUGGING
SUPPORT
EEM
VERSION
MSP430Xv2
Yes
Yes
3
Yes
Yes
No
No
No
S
Design Kits and Evaluation Modules
20-pin Target Socket Development Board for MSP430FR23x/21x MCUs The MSP-TS430PW20 is a
stand-alone ZIF socket target board used to program and debug the MSP430 MCU in
system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol. The
development board supports all MSP430FR2000, MSP430FR21x, and MSP430FR23x
FRAM MCUs in a 20-pin or 16-pin TSSOP package (TI package code: PW).
MSP430FR2311 LaunchPad Development Kit The MSP-EXP430FR2311 LaunchPad development kit is
a microcontroller development board for the MSP430FR2000, MSP430FR21x, and
MSP430FR23x MCU families. This kit contains everything needed to evaluate the platform,
including onboard emulation for programming, debugging, and energy measurements. The
onboard buttons and LEDs allow for integration of simple user interaction.
MSP430FR4133 LaunchPad Development Kit The MSP-EXP430FR4133 LaunchPad development kit is
a microcontroller development board for the MSP430FR2xx and MSP430FR4xx MCU family.
This kit contains everything needed to evaluate the MSP430FR2xx and MSP430FR4xx
FRAM platform, including onboard emulation for programming, debugging, and energy
measurements. The onboard buttons and LEDs allow for integration of simple user
interaction, while the 20-pin header for BoosterPack™ plug-in modules allows for the use of
BoosterPack modules for quick user experimentation.
MSP-FET + MSP-TS430PW20 FRAM Microcontroller Development Kit Bundle The MSP-FET430U20
bundle combines two debugging tools that support the 20-pin PW package for the
MSP430FR2000,
MSP430FR21xx
and
MSP430FR23xx
MCUs
(for
example,
MSP430FR2311IPW20). The included tools are MSP-TS430PW20 and MSP-FET.
Software
MSP430Ware™ Software MSP430Ware software is a collection of code examples, data sheets, and
other design resources for all MSP430 devices, delivered in a convenient package. In
addition to providing a complete collection of existing MSP430 design resources,
MSP430Ware software also includes a high-level API called MSP Driver Library. This library
makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of CCS or as a stand-alone package.
MSP430FR21xx Code Examples C Code examples are available for every MSP device that configures
each of the integrated peripherals for various application needs.
MSP Driver Library The abstracted API of MSP Driver Library provides easy-to-use function calls that
free you from directly manipulating the bits and bytes of the MSP430 hardware. Thorough
documentation is delivered through a helpful API Guide, which includes details on each
function call and the recognized parameters. Developers can use Driver Library functions to
write complete projects with minimal overhead.
ULP (Ultra-Low Power) Advisor ULP Advisor™ software is a tool for guiding developers to write more
efficient code to fully use the unique ultra-low-power features of MSP and MSP432
microcontrollers. Aimed at both experienced and new microcontroller developers, ULP
Advisor checks your code against a thorough ULP checklist to help minimize the energy
consumption of your application. At build time, ULP Advisor provides notifications and
remarks to highlight areas of your code that can be further optimized for lower power.
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IEC60730 Software Package The IEC60730 MSP430 software package was developed to help
customers comply with IEC 60730-1:2010 (Automatic Electrical Controls for Household and
Similar Use – Part 1: General Requirements) for up to Class B products, which includes
home appliances, arc detectors, power converters, power tools, e-bikes, and many others.
The IEC60730 MSP430 software package can be embedded in customer applications
running on MSP430s to help simplify the customer's certification efforts of functional safetycompliant consumer devices to IEC 60730-1:2010 Class B.
Fixed Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly
optimized and high-precision mathematical functions for C programmers to seamlessly port a
floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These
routines are typically used in computationally intensive real-time applications where optimal
execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and
Qmath libraries, it is possible to achieve execution speeds considerably faster and energy
consumption considerably lower than equivalent code written using floating-point math.
Floating Point Math Library for MSP430 Continuing to innovate in the low-power and low-cost
microcontroller space, TI provides MSPMATHLIB. Leveraging the intelligent peripherals of
our devices, this floating-point math library of scalar functions that are up to 26 times faster
than the standard MSP430 math functions. Mathlib is easy to integrate into your designs.
This library is free and is integrated in both Code Composer Studio IDE and IAR Embedded
Workbench IDE.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code
Composer Studio (CCS) integrated development environment (IDE) supports all MSP
microcontroller devices. CCS comprises a suite of embedded software utilities used to
develop and debug embedded applications. It includes an optimizing C/C++ compiler, source
code editor, project build environment, debugger, profiler, and many other features.
MSP EnergyTrace™ Technology EnergyTrace technology for MSP430 microcontrollers is an energybased code analysis tool that measures and displays the energy profile of the application
and helps to optimize it for ultra-low-power consumption.
Command-Line Programmer MSP Flasher is an open-source shell-based interface for programming
MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire
(SBW) communication. MSP Flasher can download binary files (.txt or .hex) directly to the
MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often
called a debug probe – which lets users quickly begin application development on MSP lowpower MCUs. Creating MCU software usually requires downloading the resulting binary
program to the MSP device for validation and debugging.
MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device
programmer that can program up to eight identical MSP430 or MSP432 flash or FRAM
devices at the same time. The MSP Gang Programmer connects to a host PC using a
standard RS-232 or USB connection and provides flexible programming options that let the
user fully customize the process.
Device and Documentation Support
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Documentation Support
The following documents describe the MSP430FR211x microcontrollers. Copies of these documents are
available on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (see Section 8.5 for links to product folders). In the upper right corner, click the
"Alert me" button. This registers you to receive a weekly digest of product information that has changed (if
any). For change details, check the revision history of any revised document.
Errata
MSP430FR2111 Device Erratasheet Describes the known exceptions to the functional specifications for
all silicon revisions of this device.
MSP430FR2110 Device Erratasheet Describes the known exceptions to the functional specifications for
all silicon revisions of this device.
MSP430FR2100 Device Erratasheet Describes the known exceptions to the functional specifications for
all silicon revisions of this device.
MSP430FR2000 Device Erratasheet Describes the known exceptions to the functional specifications for
all silicon revisions of this device.
User's Guides
MSP430FR4xx and MSP430FR2xx Family User's Guide
peripherals available in this device family.
Detailed information on the modules and
MSP430 Programming With the Bootloader (BSL) The MSP430 bootloader (BSL, formerly known as
the bootstrap loader) allows users to communicate with embedded memory in the MSP430
microcontroller during the prototyping phase, final production, and in service. Both the
programmable memory (flash memory) and the data memory (RAM) can be modified as
required. Do not confuse the bootloader with the bootstrap loader programs found in some
digital signal processors (DSPs) that automatically load program code (and data) from
external memory to the internal memory of the DSP.
MSP430 Programming With the JTAG Interface This document describes the functions that are
required to erase, program, and verify the memory module of the MSP430 flash-based and
FRAM-based microcontroller families using the JTAG communication port. In addition, it
describes how to program the JTAG access security fuse that is available on all MSP430
devices. This document describes device access using both the standard 4-wire JTAG
interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430
Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultralow-power microcontroller.
Application Reports
MSP430 FRAM Technology – How To and Best Practices FRAM is a nonvolatile memory technology
that behaves similar to SRAM while enabling a whole host of new applications, but also
changing the way firmware should be designed. This application report outlines the how to
and best practices of using FRAM technology in MSP430 from an embedded software
development perspective. It discusses how to implement a memory layout according to
application-specific code, constant, data space requirements, and the use of FRAM to
optimize application energy consumption.
VLO Calibration on the MSP430FR4xx and MSP430FR2xx Family MSP430FR4xx and MSP430FR2xx
(FR4xx/FR2xx) family microcontrollers (MCUs) provide various clock sources, including
some high-speed high-accuracy clocks and some low-power low-system-cost clocks. Users
can select the best balance of performance, power consumption, and system cost. The onchip very low-frequency oscillator (VLO) is a clock source with 10-kHz typical frequency
included in FR4xx/FR2xx family MCUs. The VLO is widely used in a range of applications
because of its ultra-low power consumption.
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SLASE78B – AUGUST 2016 – REVISED JULY 2017
MSP430 32-kHz Crystal Oscillators Selection of the right crystal, correct load circuit, and proper board
layout are important for a stable crystal oscillator. This application report summarizes crystal
oscillator function and explains the parameters to select the correct crystal for MSP430 ultralow-power operation. In addition, hints and examples for correct board layout are given. The
document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding
with silicon technology scaling towards lower voltages and the need for designing costeffective and ultra-low-power components. This application report addresses three different
ESD topics to help board designers and OEMs understand and design robust system-level
designs.
8.5
Related Links
Table 8-2 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430FR2111
Click here
Click here
Click here
Click here
Click here
MSP430FR2110
Click here
Click here
Click here
Click here
Click here
MSP430FR2100
Click here
Click here
Click here
Click here
Click here
MSP430FR2000
Click here
Click here
Click here
Click here
Click here
8.6
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.7
Trademarks
MSP430, LaunchPad, MSP430Ware, Code Composer Studio, E2E, BoosterPack, ULP Advisor,
EnergyTrace are trademarks of Texas Instruments.
8.8
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.9
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430FR2111 MSP430FR2110 MSP430FR2100 MSP430FR2000
Copyright © 2016–2017, Texas Instruments Incorporated
69
MSP430FR2111, MSP430FR2110, MSP430FR2100, MSP430FR2000
SLASE78B – AUGUST 2016 – REVISED JULY 2017
www.ti.com
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
70
Mechanical, Packaging, and Orderable Information
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR2111 MSP430FR2110 MSP430FR2100 MSP430FR2000
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jul-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430FR2000IPW16
PREVIEW
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2000
MSP430FR2000IPW16R
PREVIEW
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2000
MSP430FR2000IRLLR
PREVIEW
VQFN
RLL
24
3000
TBD
Call TI
Call TI
-40 to 85
MSP430FR2000IRLLT
PREVIEW
VQFN
RLL
24
250
TBD
Call TI
Call TI
-40 to 85
MSP430FR2100IPW16
PREVIEW
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2100
MSP430FR2100IPW16R
PREVIEW
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2100
MSP430FR2100IRLLR
PREVIEW
VQFN
RLL
24
3000
TBD
Call TI
Call TI
-40 to 85
MSP430FR2100IRLLT
PREVIEW
VQFN
RLL
24
250
TBD
Call TI
Call TI
-40 to 85
MSP430FR2110IPW16
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2110
MSP430FR2110IPW16R
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2110
MSP430FR2110IRLLR
ACTIVE
VQFN
RLL
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2110
MSP430FR2110IRLLT
ACTIVE
VQFN
RLL
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2110
MSP430FR2111IPW16
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2111
MSP430FR2111IPW16R
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2111
MSP430FR2111IRLLR
ACTIVE
VQFN
RLL
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2111
MSP430FR2111IRLLT
ACTIVE
VQFN
RLL
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2111
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jul-2017
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430FR2110IPW16R
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
MSP430FR2110IRLLR
VQFN
RLL
24
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
MSP430FR2110IRLLT
VQFN
RLL
24
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
MSP430FR2111IPW16R
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
MSP430FR2111IRLLR
VQFN
RLL
24
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
MSP430FR2111IRLLT
VQFN
RLL
24
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430FR2110IPW16R
MSP430FR2110IRLLR
TSSOP
PW
16
2000
367.0
367.0
38.0
VQFN
RLL
24
3000
367.0
367.0
35.0
MSP430FR2110IRLLT
VQFN
RLL
24
250
210.0
185.0
35.0
MSP430FR2111IPW16R
TSSOP
PW
16
2000
367.0
367.0
38.0
MSP430FR2111IRLLR
VQFN
RLL
24
3000
367.0
367.0
35.0
MSP430FR2111IRLLT
VQFN
RLL
24
250
210.0
185.0
35.0
Pack Materials-Page 2
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