HP HCPL-0810-500 High current line driver Datasheet

Agilent HCPL-8100/0810
High Current Line Driver
Data Sheet
Features
• 1 APP driving current
Description
The HCPL-8100 and HCPL0810 are low-cost high current
line drivers. With a 5 V single
supply, they deliver up to 1
APP current. This is ideal for
high current applications such
as a Powerline modem.
The HCPL-8100 and HCPL0810 are internally protected
against over-temperature
conditions through thermal
shutdown. Under-voltage or
over-load condition is sensed
by internal detection circuit
and indicated by Status pin
output. In addition, with the
transmit enable (Tx-en) input,
the line driver output stage
can be disabled to reduce
power dissipation when not
operating.
The HCPL-8100 and HCPL0810 are specified for
operation over extended
temperature range from
-40°C to +85°C. The HCPL8100 is available in DIP-8
package, and the HCPL-0810 is
available in SO-8 package.
•
3.5 MHz gain bandwidth product
•
− 60 dB maximum harmonic
distortion
•
Load detection function
•
Under-voltage detection
•
Over-temperature shutdown
•
5 V single supply
•
Temperature range: −40°C to
+85°C
•
Suitable for FCC Part 15 and
EN50065-1 compliant design
Applications
• Automatic meter reading (AMR)
•
Powerline modem
•
General purpose line driver
•
Signal conditioning
•
Digital-to-analog converter
buffers
Connection Diagram
1
STATUS
2
TX -EN
TX
PLM
Transceiver
Filter
3
4
Status
Tx -out
Tx -en
V CC
Tx -in
GND
R ref
GND
8
7
L
5V
6
5
HCPL-8100/0810
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and /or degradation which may be induced by ESD.
N
Package Pin Out
1
Status
2
Pin Descriptions
Tx-out
8
Tx-en
VCC
7
3
Tx-in
GND
6
4
R ref
GND
5
Pin No. Symbol Function
1
Status Line condition
detection
2
Tx-en
3
4
Tx-in
Rref
5, 6
7
8
GND
VCC
Tx-out
Description
A logic high indicates line conditions
such as
- under-voltage when VCC < 4 V
- load detection when ITx-out < −0.25 A
- over-temperature (thermal
shutdown)
Transmit enable
A logic high enables the Tx-out;
A logic low disables the Tx-out and
changes it to high impedance state
Transmit input
Transmit signal input
Resistor reference
Sets line driver biasing current,
typically 24 kΩ
Power supply ground Power supply and signal ground
5 V power supply
5 V power supply
Transmit output
Transmit signal output, to be enabled
by Tx-en
Block Diagram
Under-Volt
Detection
Status
Tx-en
Tx-in
Rref
1
Status
Output
Load
Detection
Over-Temp
Detection
2
3
Amp
7
6
5
8
VCC
GND
GND
Tx-out
4
Ordering Information
Specify part number followed by option number (if desired).
Example:
HCPL-8100
Standard 8-pin DIP package, 50 units per tube.
HCPL-0810-XXX
No option = SO-8 package, 100 units per tube.
500 = Tape and Reel Packaging Option, 1500 units per reel.
2
Package Outline Drawings
HCPL-8100 Standard 8-pin DIP package
9.50 ± 0.05
(0.374 ± 0.002)
8
7
6
5
DATE CODE
A 8100
YYWW
1
1.19 (0.047) MAX.
2
3
7.87 ± 0.25
(0.310 ± 0.010)
4
1.524 (0.060) MAX.
6.62 ± 0.05
(0.260 ± 0.002)
3.92 (0.155) MAX.
0.381 (0.015) MIN.
3.05 (0.120) MIN.
1.094 ± 0.320
(0.037 ± 0.013)
0.555 (0.022) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
DIMENSIONS IN MILLIMETERS AND (INCHES)
HCPL-0810 Small Outline SO-8 Package
DIMENSIONS IN MILLIMETERS AND (INCHES)
3
5˚ TYP.
0.20 (0.008)
0.35 (0.014)
Solder Reflow Temperature Profile
300
TEMPERATURE (°C)
PREHEATING RATE 3°C + 1°C/- 0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
200
2.5°C ± 0.5°C/SEC.
30
SEC.
160°C
150°C
140°C
SOLDERING
TIME
200°C
30
SEC.
3°C + 1°C/- 0.5°C
100
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
200
250
TIME (SECONDS)
Absolute Maximum Ratings
Parameter
Storage Temperature
Symbol
TS
Min.
−55
Max.
125
Unit
°C
Ambient Operating Temperature
TA
−40
85
°C
Junction Temperature
Supply Voltage
TJ
V CC
−0.5
150
5.5
°C
Volts
Output Voltage
VO
−0.5
V CC
Volts
Tx-in Voltage
V Tx-in
−0.5
V CC
Volts
Tx-en Voltage
V Tx-en
−0.5
V CC
Volts
Solder Reflow Temperature Profile
(See Solder Reflow Temperature Profile Section)
Recommended Operating Conditions
Parameter
Ambient Operating Temperature
Symbol
TA
Min.
Supply Voltage
VCC
4
−40
Typ.
25
Max.
85
Unit
°C
4.75
5
5.25
V
Electrical Specifications
Unless otherwise noted, for sinusoidal waveform input and reference resistor Rref = 24 kΩ, all typical values are
at TA = 25°C and VCC = 5 V; all Minimum/Maximum specifications are at Recommended Operating Conditions.
Parameter
Symbol Min.
Typ.
Max.
Unit
Test Condition
Fig.
VCC Supply Current
ICC
1.2
2
mA
1
20
45
mA
VTx−en = 0 V, VTx−in = 0 VPP,
Tx-out no load
VTx−en = 5 V, VTx−in = 0 VPP,
Tx-out no load
4.0
4.3
V
1
150
°C
2
0.5
APP
VCC Under Voltage
Detection
Junction OverTemperature Threshold
Load Detection
Threshold
Status Logic High
Output
Status Logic Low
Output
Power Supply
Rejection Ratio
DC Bias Voltage
VUVD
3.8
VOH
VCC−1
VCC
V
VTx−en = 5 V, VTx−in = 1.25 VPP,
f = 132 kHz, Gain = − 2, RL = 2.5 Ω
VCC = 3.5 V, IOH = − 4 mA
VOL
0
0.8
V
VCC = 5 V, IOL = 4 mA
50 Hz ripple, Vripple = 200 mVPP,
VTx−en = 5 V, VTx−in = 0 VPP, Tx-out no load
VTx−en = 5 V, Tx-out no load
PSRR
72
dB
VBias
2.27
V
Output Impedance
ZO
12
kΩ
Gain Bandwidth
Product
Transmit Enable
Threshold Voltage
Tx Enable Time
GBW
Vth, Tx
tTx-en
Tx Disable Time
0.5
Ω
3.5
MHz
0.8
2.4
V
0.9
µs
0.2
µs
VTx−en = 5 V, VTx−in = 1 VPP,
RL = 50 Ω
VTx−in = 1 VPP, f = 132 kHz,
Tx-out no load
VTx−en = 5 V, VTx−in = 1.75 VPP,
f = 132 kHz, Tx-out no load
VTx−en = 0 V, VTx−in = 1.75 VPP,
f = 132 kHz, Tx-out no load
VTx−en = 5 V, VTx−out = 3.5 VPP, f = 132 kHz,
Gain = −2, Rref = 24 k Ω, RL= 50 Ω
−65
−60
dB
HD3
−75
−65
dB
IO
1
APP
Thermal Resistance
(HCPL-8100)
θJA
100
°C/W 1 oz. trace, 2-layer PCB, still air, TA = 25°C
Thermal Resistance
(HCPL-0810)
θJA
60
138
70
°C/W 1 oz. trace, 4-layer PCB, still air, TA = 25°C
°C/W 1 oz. trace, 2-layer PCB, still air, TA = 25°C
°C/W 1 oz. trace, 4-layer PCB, still air, TA = 25°C
VTx−en = 5 V, f=132 kHz
Notes:
1. Threshold of falling VCC with hysteresis of 0.2 V (typ.).
2. Threshold of rising junction temperature with hysteresis of 20°C (typ.).
3. See Application Information section for more information on the load detection feature.
4. See Figure 3 for the plot of supply current versus Tx output current.
5
2, 3
12, 13
3
VTx−en = 0 V, VTx−in = 0 VPP,
open loop, f = 132 kHz
VTx−en = 5 V, VTx−in = 0 VPP, f = 132 kHz
HD2
2nd Harmonic
Distortion
3rd Harmonic
Distortion
Output Current
Note
4, 14
11, 15
15
5-10, 16
4
Performance Plots
Unless otherwise noted, all typical plots are at TA = 25°C, VCC = 5 V, sinusoidal waveform input and Rref = 24 kΩ.
3
70
200
VTx-en = 0 V
VTx-en
Tx-en==55VV
1.5
1
R ref
k©
ref= 8 kΩ
R ref
k©
ref= 12 kΩ
k©
R ref
ref= 24 kΩ
0
25
50
30
20
R ref
kΩ
ref = 8 k©
R ref
kΩ
ref = 12 k©
R ref
kΩ
ref = 24 k©
75
0
-50
100
TA - AMBIENT TEMPERATURE - ˚C
Figure 1. Supply current vs. temperature for Tx
disabled.
PHASE
100
210
180
80
150
60
120
40
90
20
0
--20
0.1
PHASE - DEGREES
AOL - VOLTAGE GAIN - dB
120
60
R LL = 50 ©
Ω
1
10
30
100
-66
-68
-70
-72
-74
-76
HD - HARMONIC DISTORTION - dBc
HD - HARMONIC DISTORTION - dBc
- 45
--44
--46
--48
--50
--52
HD2
HD3
--56
--58
--60
--50
f = 450 kHz, Gain = -2,-2,
VTx-out
3.5VVPPPP
= 50 ©
, R, LR=L 50Ω
Tx-out==3.5
-25
0
25
50
75
TA - AMBIENT TEMPERATURE - ˚C
0
25
75
TA - AMBIENT TEMPERATURE - ˚C
Figure 7. Tx-out harmonic distortion vs.
temperature for f = 450 kHz.
100
0.4
0.6
0.8
1
1.2
HD2
HD3
-64
-66
-68
-70
-72
-74
-76
f = 132 kHz, Gain = -2,
VTx-out = 3.5 VPP, RL = 50Ω
-25
0
25
50
75
TA - AMBIENT TEMPERATURE - ˚C
100
Figure 6. Tx-out harmonic distortion vs.
temperature for f = 132 kHz.
-40
HD2
HD3
R ref
kΩ
ref= 24 k©
- 50
- 55
R ref
kΩ
ref= 12 k©
- 60
- 65
- 70
- 75
R ref
kΩ
ref= 8 k©
- 80
Gain = -2, VTx-out = 3.5 VPP, RL = 50Ω
- 85
50
0.2
-62
-80
-50
100
- 90
-25
-
0
-78
Figure 5. Tx-out harmonic distortion vs.
temperature for f = 50 kHz.
- 40
R ref
k©
ref= 8 kΩ
R ref
k©
ref= 12 kΩ
R ref
k©
ref= 24 kΩ
Figure 3. Supply current vs. Tx output current.
f = 50 kHz, Gain = -2,
VTx-out = 3.5 VPP, RL = 50Ω
f - FREQUENCY - Hz
--42
80
ITx-out - Tx OUTPUT CURRENT - APP
-64
--40
100
-60
-80
-50
Figure 4. Gain and phase vs. frequency.
120
100
HD2
HD3
-62
-78
0
1 k 10 k 100 k 1 M 10 M
--54
0
25
50
75
TA - AMBIENT TEMPERATURE - ˚C
-60
HD - HARMONIC DISTORTION - dBc
GAIN
140
40
-25
Figure 2. Supply current vs. temperature for Tx
enabled.
240
140
160
60
HD - HARMONIC DISTORTION - dBc
-25
40
0
50 100 150 200 250 300 350 400 450 500
f - FREQUENCY - kHz
Figure 8. Tx-out harmonic distortion vs.
frequency for different values of Rref at Gain =
-2.
HD2
HD3
-45
HD - HARMONIC DISTORTION - dBc
-50
50
10
0
ICC - SUPPLY CURRENT - mA
ICC - SUPPLY CURRENT - mA
ICC - SUPPLY CURRENT - mA
2
0.5
6
f = 132 kHz
180
60
2.5
R ref
kΩ
ref= 24 k©
-50
-55
R ref
k©
ref= 12 kΩ
-60
-65
-70
-75
-80
R ref
k©
ref= 8 kΩ
-85
Gain = -4,
-4, VVTx-out
==3.5
3.5VPP
V ,PP
R,L R=L50Ω
= 50 ©
Tx-out
-90
0
50 100 150 200 250 300 350 400 450 500
f - FREQUENCY - kHz
Figure 9. Tx-out harmonic distortion vs.
frequency for different values of Rref at Gain =
-4.
HD - HARMONIC DISTORTION - dBc
--60
HD2
--62
HD3
--64
--66
--68
--70
--72
--74
R ref
kΩ
ref= 8 k©
R ref
kΩ
--76
ref = 12 k©
R ref
kΩ
ref= 24 k©
--78
--80
--82
--84
--86
f = 132 kHz, Gain
Gain==-2-2,
VVTx-out
=3.5
3.5VVPPPP
, ,RRL =
--88
Tx-out =
L =5050Ω©
--90
--50
--25
0
25
50
75
100
Tx-out (PIN 8) 0.5 A/DIV
Tx-en (PIN 2)
2 V/DIV
tth
2µs/DIV
Tx-out (PIN 8)
1 V/DIV
tTx-en
2µs/DIV
STATUS
(PIN 1)
2 V/DIV
tth
TA - AMBIENT TEMPERATURE - ˚C
Figure 10. Tx-out harmonic distortion vs.
temperature for different values of Rref.
7
Figure 11. Tx enable time.
Figure 12. Tx-out load detection.
Test Circuit Diagrams
Unless otherwise noted, all test circuits are at TA = 25°C, VCC = 5 V,
sinusoidal waveform input, and signal frequency f = 132 kHz.
20 kΩ
1 µF
1
SCOPE
2
5V
V IN = 1.25 VPP
3
10 kΩ
100 nF
4
Status
Tx -out
Tx -en
V CC
Tx -in
GND
R ref
GND
R ref
8
7
5V
RL
6
2.5 Ω
5
100 µF
100 nF
HCPL-8100/0810
Figure 13. Load detection test circuit.
20 kΩ
V OUT
1 µF
1
2
5V
100 nF
3
10 kΩ
V IN = 1 VPP
f = 10 k ~ 10 MHz
4
Status
Tx -out
Tx -en
V CC
Tx -in
GND
R ref
GND
8
7
5V
RL
6
50 Ω
5
100 µF
100 nF
HCPL-8100/0810
R ref
24 kΩ
Figure 14. Gain bandwidth product test circuit.
20 kΩ
1
2
V IN = 1.75 VPP
100 nF
PULSE GEN.
V PULSE = 5 V,
fPULSE ≤ 1 kHz
3
10 kΩ
4
R ref
24 kΩ
St atus
Tx -out
V CC
Tx -en
Tx -in
GND
R ref
GND
8
V OUT
7
5V
6
5
100 µF
100 nF
HCPL-8100/0810
Figure 15. Tx enable/disable time test circuit.
20 kΩ
1 µF
1
5V
V IN = 1.75 VPP
100 nF
2
3
10 kΩ
R ref
24 kΩ
4
Status
Tx -out
T x-en
V CC
Tx -in
GND
R ref
GND
HCPL - 8100/0810
Figure 16. Tx-out harmonic distortion test circuit.
8
8
7
5V
6
5
100 µF
100 nF
50 Ω
SPECTRUM
ANALYZER
Application Information
The HCPL-8100 and HCPL0810 are designed to work
with various transceivers and
can be used with a variety of
modulation methods including
ASK, FSK and BPSK. Figure 17
shows a typical application in
a powerline modem using
Frequency Shift Keying (FSK)
modulation scheme.
R2
Gain = − R2 / R1
1
STATUS
2
TX-EN
TX
PLM
Transceiver
C1
R1
F ilter
100 nF
3
4
Rref
24 kΩ
Status
Tx-en
Tx -out
VCC
Tx-in
GND
R ref
GND
8
C3
1 µF
R3
2Ω
L
L2
7
C4
X2
D1
5V
6
5
C2
L1
330 µH
C5
100 µF
N
100 nF
HCPL - 8100/0810
Figure 17. Schematic of HCPL-8100 or HCPL-0810 application for FSK modulation scheme.
Line Driver
The line driver is capable of
driving powerline load
impedances with output signals
up to 4 VPP. The internal
biasing of the line driver is
controlled externally via a
resistor Rref connected from
pin 4 to ground. The optimum
biasing point value for
modulation frequencies up to
150 kHz is 24 kΩ. For higher
frequency operation with
certain modulation schemes, it
may be necessary to reduce
the resistor value to enable
compliance with international
regulations.
The output of the line driver
is coupled onto the powerline
using a simple LC coupling
circuit as shown in Figure 18.
Refer to Table 1 for some
typical component values.
Capacitor C2 and inductor L1
attenuate the 50/60 Hz
powerline transmission
frequency. A suitable value for
L1 can range in value from
9
200 µH to 1 mH. To reduce
the series coupling impedance
at the modulation frequency,
L2 is included to compensate
the reactive impedance of C2.
This inductor should be a low
resistive type capable of
meeting the peak current
requirements. To meet many
regulatory requirements,
capacitor C2 needs to be an
X2 type. Since these types of
capacitors typically have a
very wide tolerance range of
20%, it is recommended to use
as low Q factor as possible for
the L2/C2 combination. Using
a high Q coupling circuit will
result in a wide tolerance on
the overall coupling
impedance, causing potential
communication difficulties with
low powerline impedances.
Occasionally with other circuit
configurations, a high Q
coupling arrangement is
recommended, e.g., C2 less
than 100 nF. In this case it is
normally used as a
compromise to filter out of
band harmonics originating
from the line driver. This is
not required with the HCPL8100 or HCPL-0810.
C3
L2
C2
Tx
L
1 µF
X2
L1
N
GND
Figure 18. LC coupling network.
Table 1. Typical component values
for LC coupling network.
Carrier
LC Coupling
Frequency (kHz) L2 (µH) C2 (nF)
110
15
150
120
10
220
132
6.8
220
150
6.8
220
Although the series coupling
impedance is minimized to
reduce insertion loss, it has to
be sufficiently large to limit
the peak current to the
desired level in the worst
expected powerline load
condition. The peak output
current is effectively limited by
the total series coupling
resistance, which is made up
of the series resistance of L2,
the series resistance of the
fuse and any other resistive
element connected in the
coupling network.
To reduce power dissipation
when not operating in transmit
mode the line driver stage is
shut down to a low power
high impedance state by
pulling the Tx-en input (pin 2)
to logic low state.
External Transient Voltage
Protection
To protect the HCPL-8100 and
HCPL-0810 from high voltage
transients caused by power
surges and disconnecting/
connecting the modem, it is
necessary to add an external
6.8 V bi-directional transient
voltage protector (as
component D1 shown in Figure
17).
Additional protection from
powerline voltage surges can
be achieved by adding an
appropriate Metal Oxide
Varistor (MOV) across the
powerline terminals after the
fuse.
Internal Protection and Sensing
The HCPL-8100 and HCPL0810 include several sensing
and protection functions to
ensure robust operation under
wide ranging environmental
conditions.
The first feature is the VCC
Under Voltage Detection (UVD).
In the event of VCC dropping
to a voltage less than 4 V, the
output status pin is switched
to a logic high state.
The next feature is the overtemperature shutdown. This
particular feature protects the
line driver stage from over-
temperature stress. Should the
IC junction temperature reach
a level above 150°C, the line
driver circuit will be shut
down and the output of Status
(pin 1) is pulled to the logic
high state simultaneously.
The final feature is load
detection function. The
powerline impedance is quite
unpredictable and varies not
just at different connection
points but is also time variant.
The HCPL-8100 and HCPL0810 include a current sense
feature, which may be utilized
to feedback information on the
instantaneous powerline load
condition. Should the peak
current reach a level greater
than 0.5 APP, the output of
status pin is pulled to a logic
high state for the entire period
the peak current exceeds -0.25
A as shown in Figure 12.
Using the period of the pulse
together with the known
coupling impedance, the actual
powerline load can be
calculated. Table 2 shows the
logic output of the Status pin.
Table 2. Status pin logic
Status output
Normal
Low
VCC < 4 V
High
Over-Temperature
High
ITx-out < − 0.25 A
High (pulsed)
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Replaces 5989-0573EN
June 11, 2004
5989-1316EN
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