Holtek HT56RB688 Tinypowertm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interface Datasheet

TinyPowerTM A/D Type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
HT56RB688
Revision: 1.00
Date: December 2, 2011
Contents
Table of Contents
Technical Document ...........................................................................7
Features ...............................................................................................7
General Description ............................................................................8
Block Diagram .....................................................................................8
Pin Assignment ...................................................................................9
Pin Description ..................................................................................10
Absolute Maximum Ratings .............................................................12
D.C. Characteristics ..........................................................................13
A.C. Characteristics ..........................................................................16
A/D Converter Characteristics .........................................................18
Power-on Reset Characteristics ......................................................18
DC/DC Converter and LDO Electrical Characteristics ...................19
System Architecture .........................................................................21
Clocking and Pipelining....................................................................21
Program Counter..................................................................................................22
Stack ....................................................................................................................23
Arithmetic and Logic Unit - ALU ...........................................................................23
Program Memory...............................................................................24
Structure...............................................................................................................24
Special Vectors.....................................................................................................24
Look-up Table.......................................................................................................26
Table Program Example.....................................................................................26
Data Memory......................................................................................27
Structure...............................................................................................................28
General Purpose Data Memory ............................................................................28
Special Purpose Data Memory .............................................................................28
Display Memory....................................................................................................28
Special Function Registers ..............................................................30
Indirect Addressing Registers - IAR0, IAR1..........................................................30
Memory Pointers - MP0, MP1 ..............................................................................30
Bank Pointer - BP ................................................................................................31
Accumulator - ACC ..............................................................................................31
Rev. 1.00
2
December 2, 2011
Contents
Program Counter Low Register - PCL..................................................................31
Look-up Table Registers - TBLP, TBHP, TBLH.....................................................32
Status Register - STATUS ...................................................................................32
Interrupt Control Registers....................................................................................33
Timer/Event Counter Registers.............................................................................33
Input/Output Ports and Control Registers .............................................................33
Pulse Width Modulator Registers..........................................................................33
A/D Converter Registers - ADRL, ADRH, ADCR, ACSR......................................33
Serial Interface Module Registers.........................................................................34
Port A Wake-up Register - PAWU ........................................................................34
Pull-High Registers - PAPU, PBPU, PCPU, PDPU, PEPU, PFPU .......................34
Clock Control Register - CLKMOD.......................................................................34
LCD/LED Registers - LCDCTRL, LEDCTRL, LCDIO ...........................................34
Miscellaneous Register - MISC0, MISC1 .............................................................34
Input/Output Ports.............................................................................34
Pull-high Resistors................................................................................................35
Port A Wake-up ....................................................................................................35
Port A Open Drain Function..................................................................................36
I/O Port Control Registers.....................................................................................36
Pin-shared Functions............................................................................................37
I/O Pin Structures .................................................................................................37
Programming Considerations ...............................................................................39
LCD and LED Driver ..........................................................................39
Display Memory....................................................................................................40
LCD/LED Registers ..............................................................................................41
LCD Reset Function .............................................................................................41
Clock Source........................................................................................................42
LCD Driver Output................................................................................................42
LED Driver Output ................................................................................................43
LCD Voltage Source and Biasing..........................................................................44
Programming Considerations ...............................................................................46
Timer/Event Counters .......................................................................50
Configuring the Timer/Event Counter Input Clock Source .....................................51
Timer Registers - TMR0, TMR1L/TMR1H, TMR2, TMR3.....................................51
Timer Control Registers - TMR0C, TMR1C, TMR2C, TMR3C .............................52
Configuring the Timer Mode .................................................................................53
Configuring the Event Counter Mode....................................................................54
Configuring the Pulse Width Measurement Mode.................................................54
Programmable Frequency Divider - PFD .............................................................55
Prescaler ..............................................................................................................56
I/O Interfacing.......................................................................................................56
Timer/Event Counter Pins Internal Filter ...............................................................56
Rev. 1.00
3
December 2, 2011
Contents
Programming Considerations ...............................................................................57
Timer Program Example.......................................................................................58
Pulse Width Modulator .....................................................................59
PWM Overview ....................................................................................................59
8+4 PWM Mode Modulation .................................................................................60
PWM Output Control ............................................................................................60
PWM Register Pairs - PWMnH/PWMnL (n=0~3) .................................................61
PWM Programming Example ...............................................................................61
Analog to Digital Converter..............................................................62
A/D Overview .......................................................................................................62
A/D Converter Data Registers - ADRL, ADRH .....................................................62
A/D Converter Control Registers - ADCR, ADPCR, ACSR ..................................63
A/D Input Pins ......................................................................................................65
Initialising the A/D Converter ................................................................................65
Programming Considerations ...............................................................................67
A/D Programming Example ..................................................................................67
A/D Transfer Function...........................................................................................69
Serial Interface Function - SIM ........................................................70
SPI Interface.........................................................................................................70
SPI Registers .......................................................................................................75
SPI Control Register - SIMnCTL2 ........................................................................78
SPI Communication..............................................................................................79
I2C Interface .........................................................................................................79
I2C Address Register - SIMnAR ...........................................................................81
I2C Bus Communication........................................................................................82
Peripheral Clock Output ...................................................................86
Peripheral Clock Operation...................................................................................86
Buzzer.................................................................................................87
PA0/PA1 Pin Function Control ..............................................................................87
Interrupts............................................................................................89
Interrupt Registers ................................................................................................90
Interrupt Operation ...............................................................................................93
Interrupt Priority.....................................................................................................93
External Interrupt ..................................................................................................94
External Peripheral Interrupt .................................................................................95
Timer/Event Counter Interrupt ..............................................................................95
A/D Interrupt .........................................................................................................96
Smart Card Interrupt.............................................................................................96
Smart Card Insertion/Removal Interrupt ...............................................................96
SIM (SPI/I2C Interface) Interrupts .........................................................................96
Multi-function Interrupt ..........................................................................................97
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4
December 2, 2011
Contents
Real Time Clock Interrupt .....................................................................................97
Time Base Interrupt ..............................................................................................98
Programming Considerations ...............................................................................99
Reset and Initialisation ...................................................................100
Reset Functions .................................................................................................100
Reset Initial Conditions .......................................................................................102
Oscillator..........................................................................................106
System Clock Configurations..............................................................................106
External Crystal/ Ceramic Oscillator - HXT .......................................................106
External RC Oscillator - ERC .............................................................................107
Internal RC Oscillator - HIRC .............................................................................107
Internal 32kHz RC Oscillator - LIRC...................................................................107
External 32.768kHz Oscillator - LXT ..................................................................108
LXT Oscillator Low Power Function ....................................................................109
External Oscillator - EC......................................................................................109
System Operating Modes ...............................................................109
Clock Sources ....................................................................................................109
Operating Modes ................................................................................................112
Power Down Mode and Wake-up ...................................................113
Power Down Mode .............................................................................................113
Entering the Power Down Mode .........................................................................113
Standby Current Considerations .........................................................................113
Wake-up .............................................................................................................113
Low Voltage Detector - LVD ...........................................................114
LVD Operation ....................................................................................................114
Watchdog Timer...............................................................................115
Watchdog Timer Operation .................................................................................115
Clearing the Watchdog Timer..............................................................................116
USB Interface ...................................................................................117
USB Operation ...................................................................................................117
USB Status and Control Registers ......................................................................117
USB Register Summary......................................................................................118
USB Interface Suspend Mode and Wake-up ......................................................126
USB Interrupt Structure .....................................................................................127
Digital to Analog Converter - DAC ................................................128
Operation ...........................................................................................................128
DC/DC Converter and LDO .............................................................129
DC2DC Register.................................................................................................129
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December 2, 2011
Contents
Smart Card Interface .......................................................................130
Interface Pins .....................................................................................................130
Card Detection ...................................................................................................130
Internal Time Counter - ETU, GTC, WTC...........................................................131
Elementary Time Unit - ETU ..............................................................................131
Guard Time Counter - GTC................................................................................132
Waiting Time Counter - WTC ............................................................................132
UART Interface...................................................................................................133
Power Control.....................................................................................................134
Smart Card Interrupt Structure............................................................................135
Programming Considerations .............................................................................136
Smart Card interface Status and Control Registers ............................................136
Configuration Options ....................................................................145
Application Circuits ........................................................................147
Instruction Set .................................................................................148
Introduction.........................................................................................................148
Instruction Timing ...............................................................................................148
Moving and Transferring Data ............................................................................148
Arithmetic Operations .........................................................................................148
Logical and Rotate Operations ...........................................................................148
Branches and Control Transfer...........................................................................149
Bit Operations.....................................................................................................149
Table Read Operations.......................................................................................149
Other Operations................................................................................................149
Instruction Set Summary ....................................................................................150
Instruction Definition ......................................................................152
Package Information .......................................................................162
144-pin LQFP (20mm´20mm) Outline Dimensions.............................................162
Rev. 1.00
6
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Technical Document
·
Application Note
- HA0075E MCU Reset and Oscillator Circuits Application Note
·
Operating voltage:
fSYS=32.768kHz: 2.2V~5.5V
fSYS=4MHz: 2.2V~5.5V
fSYS=12MHz: 3.0V~5.5V
fSYS=20MHz: 4.5V~5.5V
·
Operating current: fSYS=1MHz at 3V, 170mA, typ.
·
OTP Program Memory: 48K´16
·
RAM Data Memory: 3840´8
12 levels subroutine nesting
Up to 48 bidirectional I/O lines
TinyPower technology for low power operation
Three pin-shared external interrupts lines
Three 8-bit programmable Timer/Event Counters with overflow interrupt and 7-stage prescaler
One 16-bit programmable Timer/Event Counters with overflow interrupt
External Crystal (HXT), RC (ERC) and 32.768kHz (LXT) crystal oscillators
Internal high speed RC oscillator - HIRC
Fully integrated RC 32kHz oscillator - LIRC
Externally supplied system clock option - EC
Watchdog Timer function
PFD/Buzzer for audio frequency generation
Dual Serial Interface Modules (SIM): SPI and I2C
Features
·
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·
·
·
·
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·
·
·
·
·
·
·
·
·
·
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·
·
Rev. 1.00
LCD and LED driver function: 80´16 or 88´8
4 operating modes: Normal, Slow, Idle and Sleep
8-channel 12-bit resolution A/D converter
4-channel 12-bit PWM outputs
12-bit D/A converter with 8-level volume control
USB interface
- Fully compliant with USB 1.1 full-speed specification
- Support 6 endpoints including endpoint 0
- Support Interrupt, Control and Bulk transfer
- 160 bytes total FIFO size - 8, 8, 8, 64, 8 and 64 bytes for endpoint0~endpoint 5 respectively
Smartcard interface compatible with and certifiable to the ISO 7816-3 standards
DC/DC converter and LDO function
Low voltage reset function: 2.1V, 3.15V, 4.2V
Low voltage detect function: 2.2V, 3.3V, 4.4V
Bit manipulation instruction
Table read instructions
63 powerful instructions
Up to 0.2ms instruction cycle with 20MHz system clock at VDD=5V
All instructions executed in one or two machine cycles
Power down and wake-up functions to reduce power consumption
Package type: 144-pin LQFP
7
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
General Description
TM
The TinyPower A/D Type 8-bit high performance RISC architecture microcontroller with
LCD/LED driver is specifically designed for applications that interface directly to analog signals and
which require an LCD or LED interface. The device includes analog features such as an integrated
multi-channel Analog to Digital Converter, 12-bit Digital to Analog Converter, LCD/LED driver,
DC/DC Converter and LDO.
With their fully integrated SPI and I2C functions, designers are provided with a means of easy
communication with external peripheral hardware. The benefits of integrated analog features such as
A/D, LCD, etc., and PWM functions, in addition to low power consumption, high performance, I/O
flexibility and low-cost, provides the device with the versatility for a wide range of products in the
home appliance and industrial application areas. Some of these products could include electronic
metering, environmental monitoring, handheld instruments, electronically controlled tools, motor
driving in addition to many others.
The device contains a USB Full-speed interface to allow data communication with an external USB
host controller. It is particularly suitable for applications which require data communication between
PCs and peripheral USB hardware. This device also includes a Smartcard Interface, which is
compatible with and certified to ISO 7816 standards, to provide communication with various types of
Smart Card.
The unique Holtek TinyPower technology also offers the advantages of extremely low current
consumption characteristics, an extremely important consideration in the present trend for low power
battery powered applications. The usual Holtek MCU features such as power down and wake-up
functions, oscillator options, programmable frequency divider, etc., combine to ensure user
applications require a minimum of external components.
Block Diagram
L o w
V o lta g e
D e te c t
W a tc h d o g
T im e r
L o w
V o lta g e
R e s e t
I/O
P o rts
L E D /L E D
D R iv e r
O T P
P ro g ra m
M e m o ry
R e s e t
C ir c u it
8 - b it
R IS C
M C U
C o re
O T P
P r o g r a m m in g
C ir c u itr y
W a tc h d o g
T im e r O s c illa to r
In te rru p t
C o n tr o lle r
E x te rn a l
X T A L /R C
O s c illa to r
In te rn a l R C
O s c illa to r
D a ta
M e m o ry
S ta c k
E x te rn a l
3 2 .7 6 8 k H z
O s c illa to r
A /D
C o n v e rte r
P W M
P F D
S IM s
T im e r s
U S B
S m a rtc a rd
In te rfa c e
D /A
C o n v e rte r
L D O
Rev. 1.00
8
D C /D C
C o n v e rte r
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Pin Assignment
S E G 1 5
S E G 1 4
S E G 1 3
S E G 1 2
S E G 1 1
S E G 1 0
S E G 9
S E G 8
S E G 7
S E G 6
S E G 5
S E G 4
S E G 3
S E G 2
S E G 1
S E G 0
P C 7 /R E S
P C 6 /;P W M 2 /P IN T
P C 5 /P W M 1 /P C L K
P C 4 /P W M 0 /S C S 0
P B 0 /S C K 0 /S C L 0
P B 1 /P S O P /S C L 0
P B 2 /S D O 0
P B 3 /V D D IO
P B 4 /S D O 1
P B 5 /S D I1 /S D A 1
P B 6 /S C K 1 /S C L 1
P B 7 /S C S 1
D M
D P
V 3 3 O
N 0
N 1
N 2
N 3
N C
P A 0 /B
P A 1 /B
P A
P A
Z /IN
Z /IN
2 /A
3 /P
T 0
T 1
U D
F D
/A
/A
/A
/A
N C
N C
1 4 4
1
1 0 9
1 0 8
N C
P A 4 /T
P A 5 /T M R 3 /P
P A 6 /T
P A 7 /T M R 1 /A
M R
W M
M R
N 7
P C 3
P C 2
P C 1
P C 0
2 /A
3 /A
0 /A
/V R
A V
V
V
A V
/O S
/O S
/O S
/O S
C D
C
C
C C
C R
C R D V
C V
S E
V L
C O
C O
C O
C O
C O
C O
C O
C O
C O
C
N C
N 4
N 5
N 6
E F
D D
D D
S S
S S
C 4
C 3
C 2
C 1
E T
C 8
IO
C 4
L K
S T
C C
V O
S S
L F
C D
M 0
M 1
M 2
M 3
M 4
M 5
M 6
M 7
M 8
H T 5 6 R B 6 8 8
1 4 4 L Q F P -A
3 6
7 2
3 7
7 3
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
4 9
5 0
5 1
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S G E
S E G
S E G
S E G
S E G
C O M
C O M
C O M
C O M
C O M
C O M
C O M
N C
5 2
5 3
5 4
5 5
5 6
5 7
5 6
5 9
6 0
6 1
6 2
6 3
6 4
6 5
6 6
6 7
6 8
6 9
7 0
7 1
7 2
7 3
7 4
7 5
7 6
7 7
7 8
7 9
1 5
1 4
1 3
1 2
1 1
1 0
9
Rev. 1.00
9
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Pin Description
The following table depicts the pins common to all devices.
Pin Name
I/O
Configuration
Option
Description
BZ/BZ
PFD
Bidirectional 8-bit input/output port. Each individual bit on this port
can be configured as a wake-up input by the PAWU register control
bit. Software instructions determine if the pin is a CMOS output or
Schmitt Trigger input. A pull-high resistor can be connected to each
pin determined by the PAPU register.
Port A is pin-shared with the A/D input pins. The A/D inputs are
selected via software instructions. Once a Port A line is selected as
an A/D input, the I/O function and pull-high resistor are disabled
automatically.
The BZ/INT0, BZ/INT1, PFD, TMR2, TMR3/PWM3, TMR0 and
TMR1 are pin-shared with PA0, PA1, PA3 and PA4~PA7
respectively.
AUD is the audio output pin from the D/A Converter and pin-shared
with PA2. When the D/A-Converter is enabled, the PA2 I/O function
will be disabled automatically, including any pull-high resistors. If the
D/A Converter output, AUD, and the A/D Converter input, AN2, are
both enabled, then the D/A converter output will be connected to the
AN2 input channel allowing the D/A output to be measured by the
A/D Converter.
VREF is the ADC reference voltage input pin. The ²VREFS² bit in the
ACSR register is used to select either VREF or AVDD as the ADC
reference voltage.
VDDIO
SIM0
SIM1
Bidirectional 8-bit input/output port. Software instructions determine
if the pin is a CMOS output or Schmitt trigger input. A pull-high
resistor can be connected to each pin by the PBPU register.
SDO1, SDI1/SDA1, SCK1/SCL1 and SCS1 are the the SIM1
interface pins, pin-shared with PB4~PB7 respectively and enabled
by a configuration option, as well as the SIM0 interface pins. When
the configuration option enables the SIM function, the I/O function
will be disabled.
The VDDIO pin is an alternate power input pin for certain interface
functions, for example the 3.3V MXIC serial Flash Memory. It is
pin-shared with PB3. A Configuration option is used to determine if
PB3 is selected to be an I/O pin or the alternate power pin VDDIO.
When PB3 is selected as an alternate power pin, VDDIO, the power
supply of all the pins on this port, except PB3, together with PC4 can
be selected individually to come from the VDD pin or from VDDIO by
configuration options.
Input/Output
PA0/BZ/INT0/AN0
PA1/BZ/INT1/AN1
PA2/AUD/AN2
PA3/PFD/AN3
PA4/TMR2/AN4
PA5/TMR3/PWM3/AN5
PA6/TMR0/AN6
PA7/TMR1/AN7/VREF
PB0/SCK0/SCL0
PB1/SDI0/SDA0
PB2/SDO0
PB3/VDDIO *
PB4/SDO1
PB5/SDI1/SDA1
PB6/SCK1/SCL1
PB7/SCS1
Rev. 1.00
I/O
I/O
10
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
I/O
Configuration
Option
I/O
Bidirectional 7-bit input/output port. Software instructions determine
if the pin is a CMOS output or Schmitt trigger input. A pull-high
resistor can be connected to each pin determined by the PCPU
register.
OSC1 and OSC2 are connected to an external RC network or
crystal, determined by configuration options, for the internal system
clock. If the RC system clock option is selected, the OSC2 pin can be
used as an I/O pin. The internal system can come from the internal
ERC or HIRC high speed RC oscillator (HIRC) selected by configuration options.
When the HIRC is selected as the system oscillator, the OSC1 and
or EC
OSC2 pins can be used as normal I/O pins. The abbreviation EC
32.768kHz stands for External Clock mode. In the EC mode, an external clock
source is provided on OSC1 as the system clock.
OSC3 and OSC4 are connected to a 32.768kHz crystal oscillator to
SIM0
form a clock source for fSUB or fSL.
PWM0, PWM1 and PWM2 are pin-shared with PC4, PC5 and PC6
VDDIO
respectively. PC4 is also pin-shared with SCS0, the chip select pin
for the Serial Interface Module 0. The power supply to PC4 can be
selected to come from VDD or VDDIO determined by a configuration
option.
The PCLK is a peripheral clock output pin which is enabled by the
²PCKEN² in the SIM0CTRL register and pin-shared with PC5.
The PINT is the external peripheral interrupt pin and pin-shared with
PC6.
I/O
RES
Schmitt Trigger reset input pin, active low. The RES pin is pin-shared
with PC7 whose function is determined by a configuration option.
When PC7 is configured as an I/O pin, software instructions
determine if this pin is an open drain output or a Schmitt Trigger input
without pull-high resistor.
VLCD
P
¾
LCD power supply
COM15/SEG80
COM14/SEG81
COM13/SEG82
COM12/SEG83
COM11/SEG84
COM10/SEG85
COM9/SEG86
COM8/SEG87
O
¾
COM15~COM8 are LCD driver outputs for LCD panel commons
while SEG80~SEG87 are LCD driver outputs for LCD panel
segments. These pins can be configured as segments or common
LCD driver outputs by related LCD control bits.
COM7~COM0
O
¾
LCD driver outputs for LCD panel commons.
¾
LCD driver outputs for LCD panel segments.
Pin Name
PC0/OSC1
PC1/OSC2
PC2/OSC3
PC3/OSC4
PC4/PWM0/SCS0
PC5/PWM1/PCLK
PC6/PWM2/PINT
PC7/RES
Description
LCD
SEG79~SEG24
SEG23~SEG16/
PF7~PF0
I/O
¾
LCD driver outputs for LCD panel segments.
SEG23~SEG16 can be set as segment outputs or logic I/O pins by
the LCD output control register LCDIO.
SEG15~SEG8/
PE7~PE0
I/O
¾
LCD driver outputs for LCD panel segments.
SEG15~SEG8 can be set as segment outputs or logic I/O pins by the
LCD output control register LCDIO.
SEG7~SEG0/
PD7~PD0
I/O
¾
LCD driver outputs for LCD panel segments.
SEG7~SEG0 can be set as segment outputs or logical I/O pins by
the LCD output control register LCDIO.
Rev. 1.00
11
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
I/O
Configuration
Option
VDD
P
¾
Positive power supply
VSS
P
¾
Negative power supply, ground
AVDD
P
¾
Analog positive power supply
AVSS
P
¾
Analog negative power supply, ground
CVSS
P
¾
DC/DC Converter Negative power supply, ground
DP
I/O
¾
USB D+ line
DM
I/O
¾
USB D- line
P
¾
USB 3.3V regulator output
Pin Name
Description
Power & Ground
USB
V33O
ISO 7816 - Smart Card Interface
VO
P
¾
External diode connection pin for DC/DC converter
SELF
P
¾
External inductor connection pin for DC/DC converter
CRST
O
¾
Smart card reset output
CCLK
O
¾
Smart card clock output
CC4
I/O
¾
Smart card C4 input/output
CC8
I/O
¾
Smart card C8 input/output
CIO
I/O
¾
Smart card data input/output
CDET
I
¾
Smart card detection input
CRDVCC
P
¾
Positive power supply for external smart card
Note: * For proper operation, VDDIO £ VDD
Absolute Maximum Ratings
Supply Voltage ...............................................................................................VSS-0.3V to VSS+6.0V
Storage Temperature .................................................................................................-50°C to 125°C
Input Voltage .................................................................................................VSS-0.3V to VDD+0.3V
Operating Temperature................................................................................................-40°C to 85°C
IOL Total.....................................................................................................................................80mA
IOH Total ..................................................................................................................................-80mA
Total Power Dissipation .........................................................................................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme
conditions may affect device reliability.
Rev. 1.00
12
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
fSYS=4MHz
2.2
¾
5.5
V
fSYS=12MHz
3.0
¾
5.5
V
fSYS=20MHz
4.5
¾
5.5
V
No load,
fSYS=fM=1MHz
¾
170
250
mA
¾
380
570
mA
No load,
fSYS=fM=2MHz
¾
240
360
mA
¾
490
730
mA
No load,
fSYS=fM=4MHz (note 5)
¾
440
660
mA
¾
900
1450
mA
No load,
fSYS=fM=4MHz
¾
380
570
mA
¾
680
1020
mA
No load,
fSYS=fM=6MHz
¾
700
1050
mA
¾
1300
1950
mA
VDD
VDD
Operating Voltage
¾
Conditions
Operating Current
IDD1
IDD2
IDD3
IDD4
IDD5
Operating Current
(HXT, ERC OSC)
Operating Current
(HXT, ERC OSC)
Operating Current
(HXT, ERC, HIRC OSC)
Operating Current
(EC Mode)
Operating Current
(HXT, ERC OSC)
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
IDD6
Operating Current
(HXT, ERC, HIRC OSC)
5V
No load,
fSYS=fM=8MHz
¾
1.8
2.7
mA
IDD7
Operating Current
(HXT, ERC, HIRC OSC)
5V
No load,
fSYS=fM=12MHz
¾
2.6
4.5
mA
Operating Current
(Slow Mode, fM=4MHz)
(Crystal, ERC, HIRC OSC)
¾
150
220
mA
IDD8
¾
340
510
mA
¾
180
270
mA
¾
400
600
mA
¾
270
400
mA
¾
560
840
mA
¾
240
360
mA
¾
540
810
mA
¾
320
480
mA
¾
680
1020
mA
¾
500
750
mA
¾
1000
1500
mA
¾
10
20
mA
¾
20
40
mA
IDD9
IDD10
IDD11
IDD12
IDD13
IDD14
Rev. 1.00
Operating Current
(Slow Mode, fM=4MHz)
(HXT, ERC, HIRC OSC)
Operating Current
(Slow Mode, fM=4MHz)
(HXT, ERC, HIRC OSC)
Operating Current
(Slow Mode, fM=8MHz)
(HXT, ERC, HIRC OSC)
Operating Current
(Slow Mode, fM=8MHz)
(HXT, ERC, HIRC OSC)
Operating Current
(Slow Mode, fM=8MHz)
(HXT, ERC, HIRC OSC)
Operating Current
(fSYS=%LXT or LIRC)
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
No load,
fSYS=fSLOW=500kHz
No load,
fSYS=fSLOW=1MHz
No load,
fSYS=fSLOW=2MHz
No load,
fSYS=fSLOW=1MHz
No load,
fSYS=fSLOW=2MHz
No load,
fSYS=fSLOW=4MHz
&
LCD on, 1/5 bias
(RBIAS=1MW), VLCD=VDD
13
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
¾
15
25
mA
¾
25
40
mA
¾
15
25
mA
¾
25
40
mA
¾
8
16
mA
¾
15
30
mA
¾
40
60
mA
¾
70
110
mA
¾
50
75
mA
¾
80
120
mA
LCD on, 1/3 bias
(RBIAS=60kW), VLCD=VDD
¾
70
110
mA
¾
100
150
mA
System HALT,
LCD off, WDT off,
DC/DC converter Off
¾
0.2
1.0
mA
¾
0.3
2.0
mA
System HALT,
LCD off, WDT on,
DC/DC converter Off
¾
2
4
mA
¾
3
5
mA
System HALT, WDT off,
&
LCD on, 1/5 bias,
DC/DC converter Off,
(RBIAS=1MW), VLCD=VDD
¾
6
10
mA
¾
10
15
mA
System HALT, WDT off,
&
LCD on, 1/4 bias,
DC/DC converter Off,
(RBIAS=800kW), VLCD=VDD
¾
6
10
mA
¾
10
15
mA
System HALT, WDT off,
&
LCD on, 1/3 bias,
DC/DC converter Off,
(RBIAS=600kW), VLCD=VDD
¾
8
12
mA
¾
12
16
mA
System HALT, WDT off,
&
LCD on, 1/5 bias,
DC/DC converter Off,
(RBIAS=100kW), VLCD=VDD
¾
26
39
mA
¾
44
66
mA
System HALT, WDT off,
&
LCD on, 1/4 bias,
DC/DC converter Off,
(RBIAS=80kW), VLCD=VDD
¾
32
48
mA
¾
54
81
mA
System HALT, WDT off,
&
LCD on, 1/3 bias,
DC/DC converter Off,
(RBIAS=60kW), VLCD=VDD
¾
44
66
mA
¾
70
105
mA
VDD
IDD15
IDD16
IDD17
IDD18
IDD19
IDD20
Operating Current
(fSYS=%LXT or LIRC)
3V
Operating Current
(fSYS=%LXT or LIRC)
3V
Operating Current
(fSYS=%LXT or LIRC)
3V
5V
5V
Conditions
&
LCD on, 1/4 bias
(RBIAS=800kW), VLCD=VDD
&
LCD on, 1/3 bias
(RBIAS=600kW), VLCD=VDD
LCD off, WDT off
5V
Operating Current
(fSYS=%LXT or LIRC)
3V
Operating Current
(fSYS=%LXT or LIRC)
3V
Operating Current
(fSYS=%LXT or LIRC)
3V
5V
5V
5V
&
LCD on, 1/5 bias
(RBIAS=100kW), VLCD=VDD
&
LCD on, 1/4 bias
(RBIAS=80kW), VLCD=VDD
&
Standby Current
ISTB1
ISTB2
ISTB3
ISTB4
ISTB5
ISTB6
ISTB7
ISTB8
Rev. 1.00
Standby Current (Sleep)
(fSYS, fSUB, fS, fLCD, fWDT=off)
Standby Current (Sleep)
(fSYS, fLCD off,
fWDT=fSUB=%LXT or LIRC
3V
5V
3V
5V
Standby Current ( Idle)
(fSYS, fWDT=off;
*fS=fSUB=%LXT or LIRC)
3V
Standby Current (Idle)
(fSYS, fWDT=off;
*fS=fSUB=%LXT or LIRC)
3V
Standby Current (Idle)
(fSYS, fWDT=off;
*fS=fSUB=%LXT or LIRC)
3V
Standby Current (Idle)
(fSYS, fWDT=off;
*fS=fSUB=%LXT or LIRC)
3V
Standby Current (Idle)
(fSYS, fWDT=off;
*fS=fSUB=%LXT or LIRC)
5V
Standby Current (Idle)
(fSYS, fWDT=off;
*fS=fSUB=%LXT or LIRC)
3V
5V
5V
5V
5V
5V
5V
14
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Test Conditions
Symbol
Parameter
VDD
ISTB9
fSYS
Standby Current (Idle), (fSYS=on,
fSYS=fM=4MHz, fWDT, fLCD=off,
*fS=fSUB=%LXT or LIRC)
Standby Current (Sleep)
(fSYS, fSUB, fS, fLCS, fWDT=Off)
3V
5V
Min.
Typ.
Max.
Unit
¾
150
250
mA
¾
350
550
mA
Conditions
System HALT, WDT off,
LCD off, SPI or I2C on,
PCLK on, PCLK=fSYS/8
5V
System HALT, LCD Off,
WDT Off, DC/DC converter
Off
¾
0.1
1.2
mA
Input High/Low Voltage
VIL1
Input Low Voltage for I/O Ports,
TMR and INT Pins
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR and INT Pins
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
6
12
¾
mA
10
25
¾
mA
-2
-4
¾
mA
-5
-8
¾
mA
210
420
¾
mA
350
700
¾
mA
-80
-160
¾
mA
-180
-360
¾
mA
2
3
¾
mA
40
¾
¾
mA
60
¾
¾
mA
40
¾
¾
mA
60
¾
¾
mA
400
¾
¾
mA
600
¾
¾
mA
15
¾
¾
mA
15
¾
¾
mA
400
¾
¾
mA
600
¾
¾
mA
15
¾
¾
mA
15
¾
¾
mA
Sink/Source Current
I/O sink current (PA, PB, PC;
SEG, COM level or LED output)
3V
I/O source current (PA, PB, PC;
SEG, COM level or LED output)
3V
LCD Common and Segment
Current
3V
LCD Common and Segment
Current
3V
5V
IOL3
PC7/RES Sink Current
5V
IOL4
Card Clock (CCLK) Sink Current
IOL1
IOH1
IOL2
IOH2
VOL=0.1VDD
5V
VOH=0.9VDD
5V
VOL=0.1VDD
5V
VOH=0.9VDD
VOL=0.1VDD
3V
VOL=0.1VDD
5V
IOH4
Card Clock (CCLK) Source
Current
3V
VOH=0.9VDD
5V
3V
IOL5
VOL=0.1VDD
Card I/O (CIO) Sink Current
5V
3V
IOH5
VOH=0.9VDD
Card I/O (CIO) Source Current
5V
IOL6
IOH6
Rev. 1.00
Card Reset (CRST),
C4/C8 Sink Current
3V
Card Reset (CRST),
C4/C8 Source Current
3V
VOL=0.1VDD
5V
VOH=0.9VDD
5V
15
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
40
60
80
kW
10
30
50
kW
7.5
15.0
22.5
kW
Configuration option: 2.1V
1.98
2.10
2.22
V
Configuration option: 3.15V
2.98
3.15
3.32
V
Configuration option: 4.2V
3.98
4.20
4.42
V
Configuration option: 2.2V
2.08
2.20
2.32
V
Configuration option: 3.3V
3.12
3.30
3.50
V
Configuration option: 4.4V
4.12
4.40
4.70
V
IV33O=-5mA
3.0
3.3
3.6
V
-3% ´
typ.
TBD
+3% ´
typ.
V
VDD
Conditions
Pull-High Resistance
RPH1
RPH2
Pull-high Resistance for General
I/O Ports & Card Detection
(CDET)
3V
Pull-high resistance for Card I/O
(CIO) $
¾
¾
5V
¾
LVR/LVD
VLVR
Low Voltage Reset Voltage
VLVD
Low Voltage Detector Voltage
¾
¾
V33O
USB 3.3V Regulator Output
5V
VBG
Bandgap reference with buffer
voltage
¾
Note:
¾
1. * fS is the internal clock for the Buzzer, RTC, Time base and WDT.
2. % LXT in slow start mode (RTCC.4=1) for D.C. current measurement.
3. LXT = 32768 crystal and LIRC = internal 32K RC oscillator.
4. & LCD waveform is in Type A condition.
5. Timer0/1 off. Timer filter is disabled for all test conditions.
A.C. Characteristics
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
2.2V~5.5V
400
¾
4000
kHz
3.0V~5.5V
400
¾
12000
kHz
4.5V~5.5V
400
¾
20000
kHz
VDD
fSYS1
System Clock
(Crystal, ERC, HIRC OSC)
¾
Conditions
fSYS2
System clock (LXT OSC)
¾
2.2V~5.5V
¾
32768
¾
Hz
fLXT
LXT Frequency
¾
¾
¾
32768
¾
Hz
5V
R=150kW
-2%
4
2%
MHz
-7%
2.2V~ R=150kW, Ta=0°C~70°C
5.5V R=150kW, Ta=-40°C~85°C -11%
4
7%
MHz
4
11%
MHz
f4MERC
Rev. 1.00
4MHz External RC OSC
16
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
3V/5V Ta=25°C
-2%
4
+2%
MHz
3V/5V Ta=25°C
-2%
8
+2%
MHz
-2%
12
+2%
MHz
3V/5V Ta=0~70°C
-5%
4
+5%
MHz
3V/5V Ta=0~70°C
-5%
8
+5%
MHz
Ta=0~70°C
-5%
12
+5%
MHz
2.2V~
Ta=0~70°C
5.5V
-8%
4
+8%
MHz
3.0V~
Ta=0~70°C
5.5V
-8%
8
+8%
MHz
4.5V~
Ta=0~70°C
5.5V
-8%
12
+8%
MHz
2.2V~
Ta= -40°C~85°C
5.5V
-12%
4
+12%
MHz
3.0V~
Ta= -40°C~85°C
5.5V
-12%
8
+12%
MHz
4.5V~
Ta= -40°C~85°C
5.5V
-12%
12
+12%
MHz
2.2V~5.5V
0
¾
4000
kHz
3.0V~5.5V
0
¾
8000
kHz
4.5V~5.5V
0
¾
12000
kHz
28.1
32.0
34.4
kHz
VDD
5V
5V
fHIRC
4/8/12MHz Internal RC OSC
Timer I/P Frequency
(TMR0/TMR1/TMR2/TMR3)
fTIMER
¾
Conditions
Ta=25°C
2.2V~
After Trim
5.5V
fLIRC
32K RC Frequency
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tLVR
Low Voltage Width to Reset
¾
¾
0.1
0.4
0.6
ms
tLVDS
LVD Output Stable Time
¾
LVR disable, LVD enable,
Bandgap voltage ready
¾
¾
100
ms
tSST1
System start-up timer period
( w i t hout f a s t s t ar t - up) f or
HXT/LXT
¾
Power up or wake-up from
HALT
¾
1024
¾
tSYS
tSST2
System start-up timer period
(with fast start-up) for HXT/LXT
¾
wake-up from Idle Mode
(fSL=fLXT)
¾
1
2
tLXT%
tSST3
System start-up timer period
(with fast start-up) for HXT/LXT
¾
wake-up from Idle Mode
(fSL = fLIRC)
¾
1
2
tLIRC*
tINT
Interrupt Pulse Width
¾
1
¾
¾
ms
Note:
¾
*TSYS=1/fSYS
%: tLXT is period of 32768 XTAL
*: tLIRC is period of internal 32K RC
Rev. 1.00
17
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
A/D Converter Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Min.
Typ.
Max.
Unit
2.7
¾
5.5
V
0
¾
VREF
V
Conditions
AVDD
Analog operating voltage
¾
VREF=AVDD
VAD
A/D Input Voltage
¾
144-pin LQFP
VREF
A/D Input Reference Voltage
Range
¾
AVDD=5V
2.0
¾
AVDD+0.1
V
DNL
A/C Differential Non-Linearity
¾
AVDD=5V, VREF=AVDD,
tAD=0.5ms
-2
¾
2
LSB
INL
ADC Integral Non-Linearity
¾
AVDD=5V, VREF=AVDD,
tAD=0.5ms
-4
¾
4
LSB
Additional Power Consumption
if A/D Converter is Used
3V
¾
0.50
0.75
mA
IADC
5V
¾
1.00
1.50
mA
tAD
A/D Converter Clock Period
¾
0.5
¾
10
ms
tADC
A/D Conversion Time (Include
Sample and Hold Time)
¾
¾
16
¾
tAD
tADS
A/D Sampling Time
¾
¾
4
¾
tAD
tON2ST
A/D on to A/D start
¾
2
¾
¾
ms
Note:
¾
¾
12-bit A/D Converter
¾
2.7V~5.5V
ADC conversion time (tADC) = n (bits ADC) + 4 (sampling time).
The conversion for each bit needs one ADC clock (tAD).
Power-on Reset Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Min.
Typ.
Max.
Unit
¾
¾
0.7
mA
Conditions
2.2V~
Ta=25°C
5.5V
IPOR DC
Operating Current
VPOR
VDD Start Voltage to Ensure
Power-on Reset
¾
¾
¾
¾
100
mV
RRVDD
VDD raising rate to Ensure
Power-on Reset
¾
¾
0.035
¾
¾
V/ms
tPOR
Minimum Time for VDD Stays at
VPOR to Ensure Power-on Reset
¾
¾
1
¾
¾
ms
V
D D
tP
O R
R R
V D D
V
P O R
T im e
Rev. 1.00
18
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
DC/DC Converter and LDO Electrical Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
DC/DC
VIN
DC/DC Input Voltage
¾
¾
2.5
¾
5.5
V
VO1DC/DC
DC/DC Output Voltage 1
¾
¾
3.610
3.800
3.990
V
VO2DC/DC
DC/DC Output Voltage 2
¾
¾
4.750
5.500
5.775
V
¾
70
¾
%
¾
Efficiency
IVDD
VDD Supply Current
VIN=5V, VO=5.5V,
IVDD=100mA,
IOUT=55mA, IUSB=15mA
(reception mode),
CPU in Idle Mode
¾
¾
¾
¾
100
mA
5V Regulator Output
VIN
DC/DC Input Voltage
¾
¾
3.6
¾
5.5
V
VCRDVCC
Smart Card Power Supply Voltage
¾
¾
4.6
5.0
5.4
V
ISC
Smart Card Supply Current
¾
¾
¾
¾
55
mA
IOVDET
Current Overload Detection
¾
¾
70
95
150
mA
IQUI
Quiescent Current
¾
¾
100
150
mA
tIDET
Detection Time on Current
Overload
¾
170
¾
1400
ms
tOFF
VCRDVCC Turn Off Time
C £4.7mF,
4.6V~ LOAD
Card voltage=VCRDVCC to
5.4V
0.4V
¾
¾
750
ms
tON
VCRDVCC Turn On Time
C £4.7mF,
4.6V~ LOAD
Card voltage=
5.4V
0V to VCRDVCC (min.)
¾
¾
750
ms
V5PWRGOOD
LDO 5V Power Good Voltage
¾
¾
¾
4.8
¾
V
V5RIPPLE
Ripple on Card Voltage
¾
¾
¾
¾
200
mV
Rev. 1.00
VO=5.5V, VCRDVCC=5V,
CLOAD=4.7mF,
No load current
¾
19
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Test Conditions
Symbol
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
3V Regulator Output
VIN
DC/DC Input Voltage
¾
¾
2.50
¾
5.50
V
VCRDVCC
Smart Card Power Supply Voltage
¾
¾
2.76
3.00
3.24
V
ISC
Smart Card Supply Current
¾
¾
¾
¾
50
mA
IOVDET
Current Overload Detection
¾
¾
70
95
120
mA
tIDET
Detection Time on Current Overload
¾
¾
170
¾
1400
ms
tOFF
VCRDVCC Turn Off Time
C £4.7mF,
4.6V~ LOAD
Card voltage=VCRDVCC to
5.4V
0.4V
¾
¾
750
ms
tON
VCRDVCC Turn On Time
C £4.7mF,
4.6V~ LOAD
Card voltage=
5.4V
0V to VCRDVCC (min.)
¾
¾
750
ms
V3PWRGOOD
LDO 3V Power Good Voltage
¾
¾
¾
2.88
¾
V
V3RIPPLE
Ripple on Card Voltage
¾
¾
¾
¾
200
mV
1.8V Regulator Output
VIN
DC/DC Input Voltage
¾
¾
2.50
¾
5.50
V
VCRDVCC
Smart Card Power Supply Voltage
¾
¾
1.656
1.800
1.944
V
ISC
Smart Card Supply Current
¾
¾
¾
¾
20
mA
IOVDET
Current Overload Detection
¾
¾
70
95
12
mA
tIDET
Detection Time on Current
Overload
¾
¾
170
¾
1400
ms
tOFF
VCRDVCC Turn Off Time
C £4.7mF,
4.6V~ LOAD
Card voltage=VCRDVCC to
5.4V
0.4V
¾
¾
750
ms
tON
VCRDVCC Turn On Time
C £4.7mF,
4.6V~ LOAD
Card voltage=
5.4V
0V to VCRDVCC (min.)
¾
¾
750
ms
V18PWRGOOD
LDO 1.8V Power Good Voltage
¾
1.73
¾
V
Rev. 1.00
¾
¾
20
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to
their internal system architecture. The range of devices take advantage of the usual features found
within RISC microcontrollers providing increased speed of operation and enhanced performance. The
pipelining scheme is implemented in such a way that instruction fetching and instruction execution are
overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or
call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries
out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The
internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal
registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple
addressing methods of these registers along with additional architectural features ensure that a
minimum of external components is required to provide a functional I/O and A/D control system with
maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume
production for controller applications.
Clocking and Pipelining
The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into
four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the
beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one
instruction cycle. Although the fetching and execution of instructions takes place in consecutive
instruction cycles, the pipelining structure of the microcontrollers ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where the contents
of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction
will take one more instruction cycle to execute.
When the external RC oscillator is used, OSC2 is free for use as a nomral I/O pin.
O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m
C o u n te r
P ip e lin in g
P C
P C + 1
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
P C + 2
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
M O V A ,[1 2 H ]
2
C A L L D E L A Y
3
C P L [1 2 H ]
4
:
5
:
6
1
D E L A Y :
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
N O P
Instruction Fetching
Rev. 1.00
21
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
For instructions involving branches, such as jump or call instructions, two machine cycles are required
to complete instruction execution. An extra cycle is required as the program takes one cycle to first
obtain the actual jump or call address and then another cycle to actually execute the branch. The
requirement for this extra cycle should be taken into account by programmers in timing sensitive
applications.
Program Counter
During program execution, the Program Counter is used to keep track of the address of the next
instruction to be executed. It is automatically incremented by one each time an instruction is executed
except for instructions, such as ²JMP² or ²CALL² that demand a jump to a non-consecutive Program
Memory address. It must be noted that only the lower 8 bits, known as the Program Counter Low
Register, are directly addressable.
When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the microcontrollers manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has
been met, the next instruction, which has already been fetched during the present instruction
execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
Program Counter Bits
Mode
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Smart Card Interrupt
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
USB Interrupt
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
External Interrupt 0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
External Interrupt 1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
Smart Card Insertion/Removal
Interrupt
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
A/D Converter Interrupt
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Multi-Function 0 Interrupt
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
Multi-Function 1 Interrupt
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
Program Counter+2 (within current bank)
Skip
Loading PCL
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch
BP.7
BP.6
BP.5
#12
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
PC15~PC8: Current Program Counter bits
#12~#0: Instruction code address bits
BP.7, BP.6, BP.5: Bank pointer bits
1 5 1 4 1 3 1 2
8 7
P ro g ra m
B P
.7
B P
.6
@7~@0: PCL bits
S15~S0: Stack register bits
0
C o u n te r
B P
.5
B a n k P o in te r (B P )
Rev. 1.00
22
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writable register. By transferring data directly into
this register, a short program jump can be executed directly, however, as only this low byte is available
for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such
program jumps are executed it should also be noted that a dummy cycle will be inserted.
The lower byte of the Program Counter is fully accessible under program control. Manipulating the
PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on
the PCL register can be found in the Special Function Register section.
Stack
This is a special part of the memory which is used to save the contents of the Program Counter only.
The stack is neither part of the data nor part of the program space, and is neither readable nor writeable.
The activated level is indexed by the Stack Pointer, SP, and is neither readable nor writeable. At a
subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto
the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or
RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the
Stack Pointer will point to the top of the stack.
P ro g ra m
T o p o f S ta c k
C o u n te r
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
B o tto m
S ta c k L e v e l 3
o f S ta c k
P ro g ra m
M e m o ry
S ta c k L e v e l 1 2
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but
the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the
interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the
structure more easily. However, when the stack is full, a CALL subroutine instruction can still be
executed which will result in a stack overflow. Precautions should be taken to avoid such cases which
might cause unpredictable program branching.
Arithmetic and Logic Unit - ALU
The arithmetic-logic unit or ALU is a critical area of the microcontrollers that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontrollers data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
Rev. 1.00
·
Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
·
Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
·
Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
·
Increment and Decrement INCA, INC, DECA, DEC
·
Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
23
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Program Memory
The Program Memory is the location where the user code or program is stored. For the device the
Program Memory is an OTP type, which means it can be programmed only one time. By using the
appropriate programming tools, this OTP memory device offer users the flexibility to conveniently
debug and develop their applications while also offering a means of field programming.
Structure
The Program Memory has a capacity of 48K´16 bits. The Program Memory is addressed by the
Program Counter and also contains data, table information and interrupt-entries. Table data, which can
be setup in any location within the Program Memory, is addressed by a separate table pointer register.
Special Vectors
Within the Program Memory, certain locations are reserved for special usage such as reset and
interrupts.
Rev. 1.00
·
Location 000H
This vector is reserved for use by the device reset for program initialisation. After a device reset is
initiated, the program will jump to this location and begin execution.
·
Location 004H
This vector is used by the Smart Card interrupt. If a related Smart Card interrupt event occurs, the
program will jump to this location and begin execution if the external interrupt is enabled and the
stack is not full.
·
Location 008H
This vector is used by the USB interrupt. If the related USB interrupt event occurs, the program will
jump to this location and begin execution if the external interrupt is enabled and the stack is not full.
·
Location 00CH
This vector is used by the external interrupt 0. If the related external interrupt pin receives an active
edge, the program will jump to this location and begin execution if the external interrupt is enabled
and the stack is not full.
·
Location 010H
This vector is used by the external interrupt 1. If the related external interrupt pin receives an active
edge, the program will jump to this location and begin execution if the external interrupt is enabled
and the stack is not full.
·
Location 014H
This internal vector is used by the Timer/Event Counter 0. If a Timer/Event Counter 0 overflow
occurs, the program will jump to this location and begin execution if the timer/event counter
interrupt is enabled and the stack is not full.
·
Location 018H
This internal vector is used by the Timer/Event Counter 1. If a Timer/Event Counter 1 overflow
occurs, the program will jump to this location and begin execution if the timer/event counter
interrupt is enabled and the stack is not full.
·
Location 01CH
This vector is used by the Smart Card Insertion/Removal interrupt. If a Smart Card Insertion or
Removal event occurs, the program will jump to this location and begin execution if the external
interrupt is enabled and the stack is not full.
24
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
·
Location 020H
This vector is reserved for the A/D Converter interrupt. If the completion of an A/D conversion
occurs, the program will jump to this location and begin execution if the external interrupt is enabled
and the stack is not full.
·
Location 024H
This internal vector is used by the Multi-function 0 Interrupt. The Multi-function 0 Interrupt vector
is shared by several internal functions such as a Serial Interface Module 0 interrupt, an active edge
appearing on the External Peripheral interrupt pin, a Time Base overflow or a Real Time Clock
overflow. The program will jump to this location and begin execution if the relevant interrupt is
enabled and the stack is not full.
·
Location 028H
This internal vector is used by the Multi-function 1 Interrupt. The Multi-function 1 Interrupt vector
is shared by several internal functions such as a Serial Interface Module 1 interrupt, a Timer/Event
Counter 2 or a Timer/Event Counter 3 overflow. The program will jump to this location and begin
execution if the relevant interrupt is enabled and the stack is not full.
0 0 0 H
In itia lis a tio n
V e c to r
0 0 4 H
S m a rt C a rd
In te rru p t V e c to r
0 0 8 H
U S B
In te rru p t V e c to r
0 0 C H
E x te rn a l In te rru p t 0
V e c to r
0 1 0 H
E x te rn a l In te rru p t 1
V e c to r
0 1 4 H
T im e r /E v e n t C o u n te r 0
In te rru p t V e c to r
0 1 8 H
0 1 C H
0 2 0 H
T im e r /E v e n t C o u n te r 1
In te rru p t V e c to r
S m a r t C a r d In s e r tio n /R e m o v a l
In te rru p t V e c to r
A /D c o n v e r s io n c o m p le tio n
In te rru p t V e c to r
0 2 4 H
M u lti- F u n c tio n 0
In te rru p t V e c to r
0 2 8 H
M u lti- F u n c tio n 1
In te rru p t V e c to r
0 2 C H
7 0 0 H
7 F F H
8 0 0 H
1 F F F H
2 0 0 0 H
B F F F H
1 6 b its
N o t Im p le m e n te d
Program Memory Structure
Rev. 1.00
25
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers can
store fixed data. To use the look-up table, the table pointer must first be setup by placing the lower
order address of the look up data to be retrieved in the table pointer register, TBLP. This register
defines the lower 8-bit address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the current Program Memory
page or last Program Memory page using the ²TABRDC[m]² or ²TABRDL [m]² instructions,
respectively. When these instructions are executed, the lower order table byte from the Program
Memory will be transferred to the user defined Data Memory register [m] as specified in the
instruction. The higher order table data byte from the Program Memory will be transferred to the
TBLH special register. Any unused bits in this transferred higher order byte will be read as ²0².
The following diagram illustrates the addressing/data flow of the look-up table:
L a s t p a g e o r
p re s e n t p a g e
P C 1 5 ~ P C 8
P ro g ra m
H ig h B y te
A d d re s s
P C
T B L P R e g is te r
M e m o ry
D a ta
1 6 b its
U s e r S e le c te d
R e g is te r
R e g is te r T B L H
H ig h B y te
L o w
B y te
Table Location Bits
Instruction
b15
b14
b13
b12
b11
b10
TABRDC [m] PC15 PC14 PC13 PC12 PC11 PC10
TABRDL [m]
1
0
1
1
1
1
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PC9
PC8
@7
@6
@5
@4
@3
@2
@1
@0
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
PC15~PC8: Current program counter bits
TBHP: Table pointer higher-order byte bits.
@7~@0: Table Pointer TBLP bits
Table Program Example
The following example shows how the table pointer and table data is defined and retrieved from the
HT56RB688. This example uses raw table data located in the last page which is stored there using the
ORG statement. The value at this ORG statement is ²BF00H² which refers to the start address of the
last page within the 48K Program Memory of the HT56RB688 microcontroller. The table pointer is
setup here to have an initial value of ²06H². This will ensure that the first data read from the data table
will be at the Program Memory address ²BF06H² or 6 locations after the start of the last page. Note
that the value for the table pointer is referenced to the first address of the present page if the ²TABRDC
[m]² instruction is being used. The high byte of the table data which in this case is equal to zero will be
transferred to the TBLH register automatically when the ²TABRDL [m]² instruction is executed.
Because the TBLH register is a read-only register and cannot be restored, care should be taken to
ensure its protection if both the main routine and Interrupt Service Routine use table read instructions.
If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH
and subsequently cause errors if used again by the main routine. As a rule it is recommended that
simultaneous use of the table read instructions should be avoided. However, in situations where
simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
Rev. 1.00
26
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
main routine table-read instructions. Note that all table related instructions require two instruction
cycles to complete their operation.
Tempreg1 db
tempreg2 db
:
:
?
?
; temporary register #1
; temporary register #2
mov a,06h
; initialise table pointer - note that this address
; is referenced
mov tblp,a
mov a, 0bfh
mov tbhp, a
:
:
; to the last page or present page
; initialise high table pointer
tabrdl
; transfers value in table referenced by table pointer
; to tempregl
; data at prog. memory address ²BF06H² transferred to
; tempreg1 and TBLH
tempreg1
dec tblp
; reduce value of table pointer by one
tabrdl
; transfers value in table referenced by table pointer
; to tempreg2
; data at prog.memory address ²BF05H² transferred to
; tempreg2 and TBLH
; in this example the data ²1AH² is transferred to
; tempreg1 and data ²0FH² to register tempreg2
; the value ²00H² will be transferred to the high byte
; register TBLH
tempreg2
:
:
org BF00h
; sets initial address of last page
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored. Divided into three sections, the first of these is an area of RAM where
special function registers are located. These registers have fixed locations and are necessary for correct
operation of the device. Many of these registers can be read from and written to directly under program
control, however, some remain protected from user manipulation. The second area of Data Memory is
00H
Special Purpose
Data Memory
Bank 1 and Bank 2
LCD Memory
7FH
80H
General Purpose
Data Memory
FFH
Bank 0
Bank 3
Bank 4
Bank 31
Data Memory Structure
Rev. 1.00
27
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
reserved for general purpose use. All locations within this area are read and write accessible under
program control. The third area is reserved for the LCD Memory. This special area of Data Memory is
mapped directly to the LCD display so data written into this memory area will directly affect the
displayed data. The addresses of the LCD Memory area overlap those in the General Purpose Data
Memory area. Switching between the different Data Memory banks is achieved by setting the Bank
Pointer to the correct value.
Bank Number
Data Memory
0
1
2
3~31
Special Purpose
Data Memory
Start Address
Common: 00H
End Address
Common: 7FH
General Purpose and
LCD Data Memory
Start Address
80H
80H
80H
80H
End Address
FFH
CFH
CFH
FFH
Data Memory Content
Structure
The Data Memory is subdivided into several banks, all of which are implemented in 8-bit wide RAM.
The Data Memory located in Bank 0 is subdivided into two sections, the Special Purpose Data
Memory and the General Purpose Data Memory.
The start address of the Data Memory for the device is the address ²00H². Registers which are
common to the microcontroller, such as ACC, PCL, etc., have the same Data Memory address. The
LCD Memory is mapped into Bank 1 and Bank 2. Banks 3 to 31 contain only General Purpose Data
Memory for the device with larger Data Memory capacities. As the Special Purpose Data Memory
registers are mapped into all bank areas, they can subsequently be accessed from any bank location.
General Purpose Data Memory
All microcontroller programs require an area of read/write memory where temporary data can be
stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data
Memory. This area of Data Memory is fully accessible by the user program for both read and write
operations. By using the ²SET [m].i² and ²CLR [m].i² instructions individual bits can be set or reset
under program control giving the user a large range of flexibility for bit manipulation in the Data
Memory. For the device with larger Data Memory capacities, the General Purpose Data Memory, in
addition to being located in Bank 0, is also stored in Banks 3 to Bank 31.
Special Purpose Data Memory
This area of Data Memory is where registers, necessary for the correct operation of the
microcontroller, are stored. Most of the registers are both read and write type but some are protected
and are read only, the details of which are located under the relevant Special Function Register section.
Note that for locations that are unused, any read instruction to these addresses will return the unknow
value. The Special Function registers are mapped into all banks and can therefore be accessed from
any bank location.
Display Memory
The data to be displayed on the LCD or LED display is stored in an area of fully accessible Data Memory.
By writing to this area of RAM, the display output can be directly controlled by the application program.
As this Memory exists in Bank 1 and Bank 2, but have addresses which map into the General Purpose
Data Memory, it is necessary to first ensure that the Bank Pointer is set to the value 01H or 02H before
accessing the Display Memory. The Display Memory can only be accessed indirectly using the Memory
Rev. 1.00
28
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Pointer MP1 and the indirect addressing register IAR1. When the Bank Pointer is set to 01H or 02H to
select Data Memory Bank 1 or Bank 2 to access the Display Memory, if any addresses with a value less
than 80H are read, the Special Purpose Data Memory in Bank 0 will be accessed. Also, if the Bank
Pointer is set to 01H or 02H to select Data Memory Bank 1 or Bank 2, if any addresses higher than the
last address in Bank 1 or Bank 2 are read, then a value of 00H will be returned.
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
2 8 H
2 9 H
2 A H
2 B H
2 C H
2 D H
2 E H
2 F H
3 0 H
3 1 H
3 2 H
3 3 H
3 4 H
3 5 H
3 6 H
3 7 H
3 8 H
3 9 H
3 A H
3 B H
3 C H
3 D H
3 E H
3 F H
4 0 H
4 1 H
4 2 H
4 3 H
4 4 H
4 5 H
4 6 H
4 7 H
4 8 H
4 9 H
4 A H
4 B H
4 C H
4 D H
4 E H
4 F H
5 0 H
5 1 H
5 2 H
5 3 H
5 4 H
5 5 H
5 6 H
5 7 H
5 8 H
5 9 H
5 A H
5 B H
5 C H
5 D H
5 E H
5 F H
6 0 H
6 1 H
6 2 H
6 3 H
6 4 H
6 5 H
6 6 H
6 7 H
6 8 H
6 9 H
6 A H
6 B H
6 C H
6 D H
6 E H
6 F H
7 0 H
7 1 H
7 2 H
7 3 H
7 4 H
7 5 H
7 6 H
7 7 H
7 8 H
7 9 H
7 A H
7 B H
7 C H
7 D H
7 E H
7 F H
IA
M
IA
M
R 0
P 0
R 1
P 1
B P
A C C
P C L
T B L P
T B L H
R T C C
S T A T U S
T B H P
M IS C 0
M IS C 1
C L K M O D
D C 2 D C
IN T C 0
IN T C 1
IN T C 2
M F IC 0
M F IC 1
P A W U
P A P U
P A
P A C
P B P U
P B
P B C
P C P U
P C
P C C
P D P U
P D
P D C
P E P U
P E
P E C
P F P U
P F
P F C
P W M 0 L
P W M 0 H
P W M 1 L
P W M 1 H
P W M 2 L
P W M 2 H
P W M 3 L
P W M 3 H
T M R 0
T M R 0 C
T M R 1 H
T M R 1 L
T M R 1 C
T M R 2
T M R 2 C
T M R 3
T M R 3 C
L E D C T R L
L C D C T R L
L C D IO
R C F L T
S
S
S IM 0
S
S
S IM 1
A D R L
A D R H
A D C R
A C S R
A D P C R
IM 0 C T L
IM 0 C T L
S IM 0 D R
A R /S IM 0
IM 1 C T L
IM 1 C T L
S IM 1 D R
A R /S IM 1
D A L
D A H
D A C T R L
C C R
C S R
C C C R
C E T U 1
C E T U 0
C G T 1
C G T 0
C W T 2
C W T 1
C W T 0
C IE R
C IP R
C T X B
C R X B
0
1
C T L 2
0
1
C T L 2
U S C
U S R
U C C
A W R
S T A L L
S IE S
U M IS C
S E T IO
F IF O 0
F IF O 1
F IF O 2
F IF O 3
F IF O 4
F IF O 5
U IC
N T IM
P IP E
: U n u s e d R e a d a s "X X "
Special Purpose Data Memory
Rev. 1.00
29
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Special Function Registers
To ensure successful operation of the microcontroller, certain internal registers are implemented in the
Data Memory area. These registers ensure correct operation of internal functions such as timers,
interrupts, etc., as well as external functions such as I/O data control and A/D converter operation. The
location of these registers within the Data Memory begins at the address ²00H². Any unused Data
Memory locations between these special function registers and the point where the General Purpose
Memory begins is reserved for future expansion purposes, attempting to read data from these locations
will return a unknow value.
Indirect Addressing Registers - IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM
register space, do not actually physically exist as normal registers. The method of indirect addressing
for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in
contrast to direct memory addressing, where the actual memory address is specified. Actions on the
IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to
the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can
access data from any bank. As the Indirect Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will return a result of ²00H² and writing to the
registers indirectly will result in no operation.
Memory Pointers - MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically
implemented in the Data Memory and can be manipulated in the same way as normal registers
providing a convenient way with which to address and track data. When any operation to the relevant
Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is
the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register,
IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all
banks.
The following example shows how to clear a section of four RAM locations already defined as
locations adres1 to adres4.
data .section ¢data¢
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block
db ?
code .section at 0 ¢code¢
org 00h
start:
mov
mov
mov
mov
a,04h
block,a
a,offset adres1
mp0,a
; setup size of block
clr
inc
sdz
jmp
IAR0
mp0
block
loop
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
; Accumulator loaded with first RAM address
; setup memory pointer with first RAM address
loop:
continue:
The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.
Rev. 1.00
30
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Bank Pointer - BP
The Data Memory is divided into a total of 32 banks. Selecting the required Data Memory area is
achieved using the Bank Pointer. If data in Bank 0 is to be accessed, then the BP register must be
loaded with the value 00H, while if data in Bank 1 is to be accessed, then the BP register must be
loaded with the value 01H, and so on.
The Data Memory is initialised to Bank 0 after a reset, except for the WDT time-out reset in the Power
Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the
Special Function Data Memory is not affected by the bank selection, which means that the Special
Function Registers can be accessed from within any bank. Directly addressing the Data Memory will
always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data
from banks other than Bank 0 must be implemented using Indirect addressing.
Bit
7
6
5
4
3
2
1
0
Name
BP7
BP6
BP5
BP4
BP3
BP2
BP1
BP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~5
|
Bit 4~0
BP7~BP5: Program Memory Bank Selection bits
000: Program Memory Bank 0
001: Program Memory Bank 1
010: Program Memory Bank 2
011: Program Memory Bank 3
100: Program Memory Bank 4
101: Program Memory Bank 5
110~111: not implemented
The Program Memory has the capacity of 48K words implemented as 8K words ´ 6 Banks.
BP4~BP0: Data Memory Bank Selection bits
00000: Bank 0 for General Purpose Data Memory
00001: Bank 1 for LCD Display Memory
00010: Bank 2 for LCD Display Memory
00011~11111: Bank 3 ~ Bank 31 for General Purpose Data Memory
Accumulator - ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results from
the ALU are stored. Without the Accumulator it would be necessary to write the result of each
calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting
in higher programming and timing overheads. Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when transferring data between one user defined
register and another, it is necessary to do this by passing the data through the Accumulator as no direct
transfer between two registers is permitted.
Program Counter Low Register - PCL
To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading a
value directly into this PCL register will cause a jump to the specified Program Memory location,
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.
Rev. 1.00
31
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Look-up Table Registers - TBLP, TBHP, TBLH
These three special function registers are used to control operation of the look-up table which is stored
in the Program Memory. TBLP and TBHP registers are the lower order byte and high order byte table
pointers and indicates the location where the table data is located. Their value must be setup before any
table read commands are executed. Their value can be changed, for example using the ²INC² or
²DEC² instructions, allowing for easy table data pointing and reading. TBLH is the location where the
high order byte of the table data is stored after a table read data instruction has been executed. Note that
the lower order table data byte is transferred to a user defined location.
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation
and system management flags are used to record the status and operation of the microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like
most other registers. Any data written into the status register will not change the TO or PDF flag. In
addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by
executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of the latest operations.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not
be pushed onto the stack automatically. If the contents of the status registers are important and if the
subroutine can corrupt the status register, precautions must be taken to correctly save it.
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
TO
PDF
OV
Z
AC
C
R/W
¾
¾
R
R
R/W
R/W
R/W
R/W
POR
¾
¾
0
0
x
x
x
x
²x² unknown
Bit 7, 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
Unimplemented, read as ²0²
TO: Watchdog Time-Out flag
0: After power up or executing the ²CLR WDT² or ²HALT² instruction
1: A watchdog time-out occurred.
PDF: Power down flag
0: After power up or executing the ²CLR WDT² instruction
1: By executing the ²HALT² instruction
OV: Overflow flag
0: no overflow
1: an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
AC: Auxiliary flag
0: no auxiliary carry
1: an operation results in a carry out of the low nibbles in addition, or no borrow from the
high nibble into the low nibble in subtraction
C: Carry flag
0: no carry-out
1: an operation results in a carry during an addition operation or if a borrow does not take place
during a subtraction operation
C is also affected by a rotate through carry instruction.
32
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Interrupt Control Registers
These 8-bit registers, known as INTC0, INTC1, INTC2, MFIC0, MFIC1 and MISC0, control the
overall operations of the device interrupt functions. By setting various bits within these registers using
standard bit manipulation instructions, the enable/disable function of each interrupt can be
independently controlled. A master interrupt bit within the INTC0 register, the EMI bit, acts like a
global enable/disable control and is used to set all of the interrupt enable bits on or off. This bit is
cleared when an interrupt subroutine is entered to disable further interrupt and is set by executing the
²RETI² instruction. The MISC0 register is used to select the active edges for the two external interrupt
pins INT0 and INT1.
Timer/Event Counter Registers
The device contains several internal 8-bit and 16-bit Timer/Event Counters. The registers TMR0,
TMR2, TMR3 and the register pair TMR1L/TMR1H are the locations where the timer values are
located. These registers can also be preloaded with fixed data to allow different time intervals to be
setup. The associated control registers, TMR0C, TMR1C, TMR2C and TMR3C contain the setup
information for these timers, which determines in what mode the timer is to be used as well as
containing the timer on/off control function.
Input/Output Ports and Control Registers
Within the area of Special Function Registers, the I/O data registers and their associated control
registers play a prominent role. All I/O ports have a designated register correspondingly labeled as PA,
PB, PC, PD, PE and PF. These labeled I/O registers are mapped to specific addresses within the Data
Memory as shown in the Data Memory table, which are used to transfer the appropriate output or input
data on that port. With each I/O port there is an associated control register labeled PAC, PBC, PCC,
PDC, PEC and PFC also mapped to specific addresses within the Data Memory. The control register
specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an
input, the corresponding bit of the control register must be set high while for an output it must be set
low. During program initialization, it is important to first setup the control registers to specify which
pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One
flexible feature of these registers is the ability to directly program single bits using the ²SET [m].i² and
²CLR [m].i² instructions. The ability to change I/O pins from output to input and vice versa by
manipulating specific bits of the I/O control registers during normal program operation is a useful
feature of these devices.
Pulse Width Modulator Registers
The device contains multiple Pulse Width Modulator outputs each with their own related independent
control register pair, known as PWM0L/PWM0H, PWM1L/PWM1H, PWM2L/PWM2H and
PWM3L/PWM3H. The 12-bit contents of each register pair, which defines the duty cycle value for the
modulation cycle of the Pulse Width Modulator, along with an enable bit are contained in these register
pairs.
A/D Converter Registers - ADRL, ADRH, ADCR, ACSR
The device contains a multiple channel 12-bit A/D converter. The correct operation of the A/D
requires the use of two data registers and two control registers. The two data registers, a high byte data
register known as ADRH, and a low byte data register known as ADRL, are the register locations
where the digital value is placed after the completion of an analog to digital conversion cycle.
Functions such as the A/D enable/disable, A/D channel selection and A/D clock frequency are
determined using the two control registers, ADCR and ACSR.
Rev. 1.00
33
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Serial Interface Module Registers
The device contains two Serial Interface Modules named SIM0 and SIM1 and each SIM contains an
SPI and an I2C interface. The SIMxCTL0, SIMxCTL1, SIMxCTL2 and SIMxAR are the control
registers for the Serial Interface function while the SIMxDR is the data register for the Serial Interface
Data where x means 0 and 1.
Port A Wake-up Register - PAWU
All pins on Port A have a wake-up function enable a low going edge on these pins to wake-up the
device when it is in a power down mode. The pins on Port A that are used to have a wake-up function
are selected using this resister.
Pull-High Registers - PAPU, PBPU, PCPU, PDPU, PEPU, PFPU
All I/O pins on Ports PA, PB, PC, PE, PE and PF if setup as inputs, can be connected to an internal
pull-high resistor. The pins which require a pull-high resistor to be connected are selected using these
registers.
Clock Control Register - CLKMOD
The device operates using a dual clock system whose mode is controlled using this register. The
register controls functions such as the clock source, the idle mode enable and the division ratio for the
slow clock.
LCD/LED Registers - LCDCTRL, LEDCTRL, LCDIO
The device contains a fully integrated LCD/LED Driver function which can be setup in various
configurations allowing it to control a wide range of external LCD and LED panels. Most of these
options are controlled using the LCDCTRL and LECTRL registers. As some of the LCD segment
driving pins, which are pin-shared with I/O pins, can also be setup to be used as general I/O pins, the
register named LCDIO is used to select the required function.
Miscellaneous Register - MISC0, MISC1
These registers name MISC0 and MISC1 are used to control the miscellaneous functions such as the
active edge selection of the external interrupt pins, the clock divided ratio selection of the Smart Card
and the Watchdog Timer enable control bits. There are also four bits used to determine if the output
type is open drain or CMOS output for PA0~PA3.
Input/Output Ports
Holtek microcontroller offer considerable flexibility on their I/O ports. With the input or output
designation of every pin fully under user program control, pull-high selections for all ports and
wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a
wide range of application possibilities.
The device provides up to 48 bidirectional input/output lines labeled with port names PA, PB, PC, PD,
PE and PF. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in
the Special Purpose Data Memory table. All of these I/O ports can be used for input and output
operations. For input operation, these ports are non-latching, which means the inputs must be ready at
the T2 rising edge of instruction ²MOV A,[m]², where m denotes the port address. For output
operation, all the data is latched and remains unchanged until the output latch is rewritten.
Rev. 1.00
34
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the use
of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured
as an input have the capability of being connected to an internal pull-high resistor. These pull-high
resistors are selected using registers PAPU, PBPU, PCPU, PDPU, PEPU and PFPU and are
implemented using weak PMOS transistors.
PAWU, PAPU, PA, PAC, PBPU, PB, PBC, PCPU, PC, PCC, PDPU, PD, PDC, PEPU, PE, PEC, PFPU,
PF and PFC Registers
Register
Name
POR
Bit
7
6
5
4
3
2
1
0
PAWU0
PAWU
00H
PAWU7
PAWU6
PAWU5
PAWU4
PAWU3
PAWU2
PAWU1
PA
FFH
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PAC
FFH
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
00H
PAPU7
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PB
FFH
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PBC
FFH
PBC7
PBC6
PBC5
PBC4
PBC3
PBC2
PBC1
PBC0
PBPU
00H
PBPU7
PBPU6
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PBPU0
PC
FFH
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PCC
FFH
PCC7
PCC6
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
PCPU
00H
PCPU7
PCPU6
PCPU5
PCPU4
PCPU3
PCPU2
PCPU1
PCPU0
PD
FFH
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PDC
FFH
PDC7
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDPU
00H
PDPU7
PDPU6
PDPU5
PDPU4
PDPU3
PDPU2
PDPU1
PDPU0
PE
FFH
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PEC
FFH
PEC7
PEC6
PEC5
PEC4
PEC3
PEC2
PEC1
PEC0
PEPU
00H
PEPU7
PEPU6
PEPU5
PEPU4
PEPU3
PEPU2
PEPU1
PEPU0
PF
FFH
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PFC
FFH
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
PFPU
00H
PFPU7
PFPU6
PFPU5
PFPU4
PFPU3
PFPU2
PFPU1
PFPU0
PAWUn: PA wake-up function enable
0: disable
1: enable
PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn: Pull-high function enable
0: disable
1: enable
PAn/PBn/PCn/PDn/PEn/PFn: I/O port data bit
PACn/PBCn/PCCn/PDCn/PECn/PFCn: I/O port type selection bit
0: output
1: input
Port A Wake-up
The HALT instruction forces the microcontroller into a Power Down condition which preserves
power, a feature that is important for battery and otuher low-power applications. Various methods exist
to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins
from high to low. After a HALT instruction forces the microcontroller into entering a Power Down
condition, the processor will remain in a low-power state until the logic condition of the selected
wake-up pin on Port A changes from high to low. This function is especially suitable for applications
that can be woken up via external switches. Each pin on Port A can be selected individually to have this
wake-up feature using the PAWU register.
Rev. 1.00
35
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Port A Open Drain Function
All I/O pins in the device have CMOS structures, however Port A pins PA0~PA3 can also be setup as
open drain structures. This is implemented using the ODE0~ ODE3 bits in the MISC1 register.
MISC1 Register
Bit
7
6
5
4
3
2
1
0
Name
ODE3
ODE2
ODE1
ODE0
WDTEN3
WDTEN2
WDTEN1
WDTEN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
1
0
1
0
Bit 7
Bit 6
ODE3: PA3 Open Drain control
0: disable
1: enable
ODE2: PA2 Open Drain control
0: disable
1: enable
Bit 5
ODE1: PA1 Open Drain control
0: disable
1: enable
Bit 4
ODE0: PA0 Open Drain control
0: disable
1: enable
WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT function enable
Described in Watchdog Timer section.
Bit 3~0
I/O Port Control Registers
Each I/O port has its own control register known as PAC, PBC, etc., to control the input/output
configuration. With this control register, each CMOS output or input with or without pull-high resistor
structures can be reconfigured dynamically under software control. Each pin of the I/O ports is directly
mapped to a bit in its associated port control register. For the I/O pin to function as an input, the
corresponding bit of the control register must be written as a ²1². This will then allow the logic state of
the input pin to be directly read by instructions. When the corresponding bit of the control register is
written as a ²0², the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output,
instructions can still be used to read the output register. However, it should be noted that the program
will in fact only read the status of the output data latch and not the actual logic status of the output pin.
Rev. 1.00
36
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than
one function. Limited numbers of pins can force serious design constraints on designers but by
supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the
chosen function of the multi-function I/O pins is set by configuration options while for others the
function is set by application program control.
·
External Interrupt Inputs
The external interrupt pins INT0 and INT1 are pin-shared with the I/O pins PA0 and PA1. For
applications not requiring an external interrupt input, the pin-shared external interrupt pin can be
used as a normal I/O pin, however to do this, the external interrupt enable bits in the INTC0 register
must be disabled.
·
External Timer Clock Input
The external timer pins TMR0, TMR1, TMR2 and TMR3 are pin-shared with I/O pins. To configure
them to operate as timer inputs, the corresponding control bits in the timer control register must be
correctly set and the pin must also be setup as an input. Note that the original I/O function will
remain even if the pin is setup to be used as an external timer input.
·
PFD Output
The device contains a PFD function whose single output is pin-shared with I/O pin PA3. The output
function of this pin is chosen via a configuration option and remains fixed after the device is
programmed. Note that the corresponding bit of the port control register, PAC.3, must setup the pin
as an output to enable the PFD output. If the PAC port control register has setup the pin as an input,
then the pin will function as a normal logic input with the usual pull-high selection, even if the PFD
configuration option has been selected.
·
PWM Outputs
The device contains several PWM outputs name PWM0~PWM3 shared with pins PC4~PC6 and
PA5. The PWM output functions are chosen via registers. Note that the corresponding bit of the port
control register bit must setup the pin as an output to enable the PWM output. If the port control
register bit has setup the pin as an input, then the pin will function as a normal logic input with the
usual pull-high selection, even if the PWM registers have enabled the PWM function.
·
A/D Inputs
The device contains a multi-channel A/D converter inputs. All of these analog inputs are pin-shared
with I/O pins on Port A. If these pins are to be used as A/D inputs and not as normal I/O pins then the
corresponding bits in the A/D Converter Control Register, ADCR, must be properly set. There are no
configuration options associated with the A/D function. If used as I/O pins, then full pull-high
resistor register remain, however if used as A/D inputs then any pull-high resistor selections
associated with these pins will be automatically disconnected.
I/O Pin Structures
The accompanying diagrams illustrate the internal structures of some I/O pin types. As the exact
logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to
assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does
not permit all types to be shown.
Rev. 1.00
37
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
D D
W e a k
P u ll- U p
Q
C K
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
I/O
p in
A /D
In p u t P o rt
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
Q
S
R e a d D a ta R e g is te r
S y s te m
V
P u ll- H ig h
R e g is te r
S e le c tio n
M
U
X
W a k e -u p
W a k e - u p S e le c t
P A o n ly
Generic Input/Output Structure
V
D a ta B u s
W r ite C o n tr o l R e g is te r
P u ll- H ig h
R e g is te r
S e le c t
C o n tr o l B it
Q
D
D D
W e a k
P u ll- u p
Q
C K
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
D a ta B it
Q
D
C K
S
Q
M
R e a d D a ta R e g is te r
P C R 2
P C R 1
P C R 0
T o A /D
U
X
A n a lo g
In p u t
S e le c to r
C o n v e rte r
A C S 2 ~ A C S 0
A/D Input/Output Structure
Rev. 1.00
38
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Programming Considerations
Within the user program, one of the first things to consider is port initialisation. After a reset, all of the
I/O data and port control registers will be set high. This means that all I/O pins will default to an input
state, the level of which depends on the other connected circuitry and whether pull-high selections
have been chosen. If the port control registers, PAC, PBC, etc., are then programmed to setup some
pins as outputs, these output pins will have an initial high output value unless the associated port data
registers, PA, PB, etc., are first programmed. Selecting which pins are inputs and which are outputs can
be achieved byte-wide by loading the correct values into the appropriate port control register or by
programming individual bits in the port control register using the ²SET [m].i² and ²CLR [m].i²
instructions. Note that when using these bit control instructions, a read-modify-write operation takes
place. The microcontroller must first read in the data on the entire port, modify it to the required new
bit values and then rewrite this data back to the output ports.
T 1
S y s te m
T 2
T 3
T 4
T 1
T 2
T 3
T 4
C lo c k
P o rt D a ta
W r ite to P o r t
R e a d fro m
P o rt
Read/Write Timing
Port A has the additional capability of providing wake-up functions. When the device is in the Power
Down Mode, various methods are available to wake the device up. One of these is a high to low
transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.
LCD and LED Driver
For large volume applications, which incorporate an LCD in their design, the use of a custom display
rather than a more expensive character based display reduces costs significantly. However, the
corresponding COM and SEG signals required, which vary in both amplitude and time, to drive such a
custom display require many special considerations for proper LCD operation to occur. The device
contains a LCD Driver function, with their internal LCD signal generating circuitry and various
options, will automatically generate these time and amplitude varying signals to provide a means of
direct driving and easy interfacing to a range of custom LCDs.
Additionally the device also includes LED driver circuitry which can generated the required signals to
drive the COM and SEGMENT signals for LED panels. The device includes a wide range of options to
enable LCD and LED displays of various types to be driven. The table shows the range of options
available across the device range.
Duty
Driver No.
1/8
88´8
1/16
80´16
Bias
Bias Type
Wave Type
1/3, 1/4, 1/5
R
A, B
LCD Selections
LED Duty
LED Driver No.
Static
88´1
1/4
88´4
1/8
88´8
1/12
80´12
1/16
80´16
LED Selections
Rev. 1.00
39
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
V L C D
V
A
(= V L C D )
V
R
L C D
P o w e r S u p p ly
B
(= V L C D ´ 2 /3 )
V
R
C
(= V L C D ´ 1 /3 )
R
L C D O n /O ff
R
ty p e 1 /3 B ia s
V L C D
V
A
(= V L C D )
V
R
L C D
P o w e r S u p p ly
V
R
R
V
V
R
R
V
R
V
R
L C D O n /O ff
L C D
ty p e 1 /5 B ia s
R
R
D
(= V L C D ´ 1 /4 )
E
(= V L C D ´ 1 /5 )
C
(= V L C D ´ 2 /4 )
D
(= V L C D ´ 2 /5 )
L C D
P o w e r S u p p ly
B
(= V L C D ´ 3 /4 )
C
(= V L C D ´ 3 /5 )
R
A
B
(= V L C D ´ 4 /5 )
V
V L C D
V
(= V L C D )
R
O n /O ff
ty p e 1 /4 B ia s
R Type Bias Voltage Levels
Display Memory
An area of Data Memory is especially reserved for use for the LCD/LED display data. This data area is
known as the Display Memory. Any data written here will be automatically read by the internal display
driver circuits, which will in turn automatically generate the necessary LCD or LED driving signals.
Therefore any data written into this Memory will be immediately reflected into the actual display
connected to the microcontroller.
As the Display Memory addresses overlap those of the General Purpose Data Memory, it s stored in its
own independent Bank 1 and Bank 2 area. The Data Memory Bank to be used is chosen by using the
Bank Pointer, which is a special function register in the Data Memory named BP. To access the Display
Memory therefore requires first that Bank 1 or Bank 2 is selected by writing a value of 01H or 02H to
the BP register. After this, the memory can then be accessed by using indirect addressing through the
use of Memory Pointer MP1. With Bank 1 or Bank 2 selected, then using MP1 to read or write to the
memory area starting with address 80H will result in operations to the Display Memory. Directly
addressing the Display Memory is not applicable and will result in a data access to the Bank 0 General
Purpose Data Memory.
The accompanying Display Memory Map diagrams shows how the internal Display Memory is
mapped to the Segments and Commons of the display for the device.
The accompanying waveform diagrams show the generated waveforms for a range of duty and bias
types. The huge number of permutations of available for the LCD and LED waveform types does not
permit all types to be depicted.
Rev. 1.00
40
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
LCD/LED Registers
Control Registers in the Data Memory, are used to control the various setup features of the LCD/LED
Driver. There is one control register named LCDCTRL for the LCD function and one named
LEDCTRL for the LED function. Various bits in these registers control functions such as duty type,
bias type, bias resistor selection as well as overall LCD enable and disable. The LCDEN bit in the
LCDCTRL and LEDEN bit in the LEDCTRL register, which provide the overall LCD/LED
enable/disable function, will only be effective when the device is in the Normal, Slow or Idle Mode. If
the device is in the Sleep Mode, the display will always be disabled. Bits RSEL0 and RSEL1 in the
LCDCTRL register is used to select the internal bias resistors to supply the LCD panel with the correct
bias voltages. A choice to best match the LCD panel used in the application can be selected also to
minimise bias current. The TYPE bit in the same register is used to select whether Type A or Type B
LCD control signals are used.
The register named LCDIO is used to determine if the output function of display pins SEG0~ SEG23
are used as segment drivers or CMOS outputs. If these pins are used as general I/O pins, then the I/O
function including the input/output control, the related output data and pull-high functions is managed
by the original corresponding I/O Port control and data register together with the pull-high control
register.
LCD Output Control Register - LCDIO
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
LCDPF
LCDPE
LCDPD
R/W
¾
¾
¾
¾
¾
R/W
R/W
R/W
POR
¾
¾
¾
¾
¾
0
0
0
Bit 7~3
Bit 2
Bit 1
Bit 0
Unimplemented, read as ²0²
LCDPF: LCD SEG16~SEG23 or I/O Port F selection bit
0: SEG16~SEG23
1: I/O Port F
LCDPE: LCD SEG8~SEG15 or I/O Port E selection bit
0: SEG8~SEG15
1: I/O Port E
LCDPD: LCD SEG0~SEG7 or I/O Port D selection bit
0: SEG0~SEG7
1: I/O Port D
LCD Reset Function
The LCD has an internal reset function that is an OR function of the inverted LCDEN bit in the
LCDCTRL register and the Sleep function. The LCD reset signal is active high. The LCDEN signal is
the inverse of the LCDEN bit in the LCDCTRL register.
Reset LCD = Sleep Mode or LCDEN.
LEDEN = 0 and LCDEN = 1 must be enabled to activate the LCDCTRL register function.
LCDEN
Sleep Mode
Reset LCD
0
Off
Ö
0
On
Ö
1
Off
x
1
On
Ö
LCD Reset Function
Rev. 1.00
41
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Clock Source
The LCD clock source is the internal clock signal fSUB divided by 8 using an internal divider circuit. The
fSUB internal clock is supplied by either the internal 32kHz RC oscillator (LIRC) or the external
32.768kHz oscillator (LXT), the choice of which is determined by a configuration option. For proper
LCD operation, this arrangement is provided to generate an ideal LCD clock source frequency of 4kHz.
fSUB Clock Source
LCD Clock Frequency
Internal 32kHz oscillator (LIRC)
4kHz
External 32.768kHz oscillator (LXT)
4kHz
LCD Clock Source
LCD Driver Output
When the LCDEN bit in the LCDCTRL register is set to 1, the COM and SEG lines will be setup as
LCD driver pins to drive the LCD display.
The number of COM and SEG outputs supplied by the LCD driver and its biasing and duty selections
are dependent upon how the LCD control bits are programmed. The Bias Type is R type and the bias
resistor can be selected using the RSEL1 and RSEL0 bits in the LCDCTRL register.
The nature of Liquid Crystal Displays require that only AC voltages can be applied to their pixels as the
application of DC voltages to LCD pixels may cause permanent damage. For this reason the relative
contrast of an LCD display is controlled by the actual RMS voltage applied to each pixel, which is equal
to the RMS value of the voltage on the COM pin minus the voltage applied to the SEG pin. This
differential RMS voltage must be greater than the LCD saturation voltage for the pixel to be on and less
than the threshold voltage for the pixel to be off. The requirement to limit the DC voltage to zero and to
control as many pixels as possible with a minimum number of connections requires that both a time and
amplitude signal is generated and applied to the application LCD. These time and amplitude varying
signals are automatically generated by the LCD driver circuits in the microcontroller. What is known as
the duty determines the number of common lines used, which are also known as backplanes or COMs.
The duty which is chosen by a control bit to have a value of 1/8 and 1/16 and which equates to a COM
number of 8 and 16 therefore defines the number of time divisions within each LCD signal frame. Two
types of signal generation are also provided, known as Type A and Type B, the required type is selected
via the TYPE bit in the LCDCTRL register. Type B offers lower frequency signals, however lower
frequencies may introduce flickering and influence display clarity.
LCD Control Register - LCDCTRL
Bit
7
6
5
4
3
2
1
0
Name
TYPE
¾
DTYC
BIAS1
BIAS0
RSEL1
RSEL0
LCDEN
R/W
R/W
¾
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
¾
0
0
0
0
0
0
Bit 7
TYPE: LCD Type selection bit
0: Type A
1: Type B
Bit 6
Bit 5
Unimplemented, read as ²0²
DTYC: LCD Duty selection bit
0: 1/8 duty
1: 1/16 duty
BIAS1~BIAS0: LCD Bias selection bits
00: 1/3 bias
01: 1/4 bias
10: 1/5 bias
11: Reserved
Bit 4~3
Rev. 1.00
42
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Bit 2~1
RSEL1~RSEL0: LCD Bias Resistor selection bits
For 1/3 bias:
0x: 600kW
10: 60kW
11: 3kW
For 1/4 bias:
0x: 800kW
10: 80kW
11: 4kW
For 1/5 bias:
0x: 1000kW
10: 100kW
11: 5kW
LCDEN: LCD function enable control
0: disable
1: enable
In Normal, Slow or Idle mode, the LCD function will be enabled or disabled according to that the
LCDEN bit is 1 or 0. In Sleep mode, the LCD function will always be disabled.
Bit 0
LED Driver Output
The LED driver uses the COM and SEG lines to drive the LED display. The number of COM and SEG
outputs supplied by the LED driver and its biasing and duty selections, are dependent upon how the
LED control bits are programmed.
When the LEDEN bit in the LEDCTRL register is set high and the LCDEN bit in the LCDCTRL
register is cleared to 0, the COM and SEG lines will be setup as CMOS output pins to drive the LED
display. The COM and SEG lines can be set to be either active high or active low using bits in the
LEDCTRL register. This provides 4 different timing modes. These are COM low active, SEG low
active; COM low active, SEG high active; COM high active, SEG low active; COM high active, SEG
high active. The COM and SEG lines will have a reverse polarity when in the non-active state when the
display is off. For the LED driver there are a total of 5 different duty cycle selections which are Static,
1/4, 1/8, 1/12 and 1/16. The frame rate of each duty cycle will be between 55Hz and 75Hz.
LED Control Register - LEDCTRL
Bit
7
6
5
4
3
2
1
Name
¾
DTYE2
DTYE1
DTYE0
SEGP
COMP
LEDEN
¾
R/W
¾
R/W
R/W
R/W
R/W
R/W
¾
POR
¾
0
0
0
0
0
¾
Bit 7
Bit 6~4
Bit 3
Rev. 1.00
0
0
Unimplemented, read as ²0²
DTYE2~DTYE0: LED Duty selection bit
000: static
001: 1/4 duty
010: 1/8 duty
011: 1/8 duty
100: 1/12 duty
101: 1/12 duty
110: 1/16 duty
111: 1/16 duty
SEGP: Segment polarity selection bit
0: low active
1: high active
43
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Bit 2
Bit 1
Bit 0
COMP: Common polarity selection bit
0: low active
1: high active
LEDEN: LED function enable control
0: disable
1: enable
In Normal, Slow or Idle mode, the LED function will be enabled or disabled according to that the
LEDEN bit is 1 or 0. In Sleep mode, the LCD function will always be disabled.
Unimplemented, read as ²0²
LCD Voltage Source and Biasing
The time and amplitude varying signals generated by the LCD Driver function require the generation
of several voltage levels for their operation. The number of voltage levels used by the signal depends
upon the value of the BIAS bits in the LCDCTRL register. The device supports the R type biasing and
the bias resistor can be selected via the RSEL bits in the LCDCTRL register.
For the R type biasing an external LCD voltage source must be supplied on pin VLCD to generate the
internal biasing voltages. The VLCD voltage could be the microcontroller power supply VDD or some
other voltage source less than or equal to the VDD voltage. For the R type 1/3 bias selection, four
voltage levels VSS, VA, VB and VC are utilised. The voltage VA is equal to VLCD and VB is equal to
VLCD´2/3 while VC is equal to VLCD ´ 1/3. For the R type 1/4 bias selection, there are five voltage
levels to be used. The difference of each bias voltage is 1/4 ´ VLCD voltage. For 1/5 bias selection, the
difference of each bias voltage is 1/5 ´VLCD. In addition to selecting the LCD bias level, several
values of bias resistor can be chosen using bits in the LCDCTRL register. Different values of internal
bias resistors can be selected using the RSEL0 and RESEL1 bits in the LCDCTRL register. This bias
resistor along with the voltage on pin VLCD will determine the bias current.
V D D
C O M 0
0
1
2
3
8 7
V S S
V S S
V S S
V D D
S E G in
lo w a c tiv e
V D D
S E G
V D D
C O M 0 in
lo w a c tiv e
V D D
C O M 1
V S S
V S S
LED 1/4 Duty, COM High Active,
SEG Low Active, Display Off
V D D
C O M 0 in
lo w a c tiv e
V S S
S E G in
h ig h a c tiv e
V D D
C O M 0 in
h ig h a c tiv e
V D D
V S S
V S S
V D D
S E G in
lo w a c tiv e
V S S
C O M 0 in
h ig h a c tiv e
V D D
S E G in
h ig h a c tiv e
V D D
V S S
V S S
LED Static Mode Normal Operation
Rev. 1.00
44
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
B a n k 1
b 7
b 6
b 5
b 4
b 3
B a n k 2
b 2
b 1
b 0
b 7
8 0 H
S E G
8 1 H
S E G
0
1
b 6
b 5
b 4
b 3
b 2
b 1
b 0
8 0 H
S E G
0
8 1 H
S E G
1
b 5
b 2
b 1
0
b 6
C O M
8 7
1
S E G
C O M
8 7 H
2
8 6
C O M
S E G
3
8 6 H
C O M
8 1
4
S E G
C O M
8 1 H
C O M 5
8 0
C O M 6
S E G
C O M
8 0 H
7
C E H
S E G
7 8
C F H
S E G
7 9
C O M
C O M
1
2
3
0
C O M
4
C O M
C O M
C O M 5
C O M 6
C O M
7
Memory Map - 88´8
B a n k 1
b 7
b 6
b 5
b 4
b 3
B a n k 2
b 2
b 1
b 0
b 7
0
b 4
b 3
b 0
8 0 H
S E G
8 1 H
S E G
1
C E H
S E G
7 8
C E H
S E G
7 8
C F H
S E G
7 9
C F H
S E G
7 9
C O M
C O M
C O M
1 1
1 0
9
1 2
8
C O M
1 3
C O M
C O M
1 4
1
C O M
C O M
2
1 5
C O M
3
C O M
C O M
4
C O M
C O M
C O M 5
C O M 6
C O M
0
7
Memory Map - 80´16
Rev. 1.00
45
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Programming Considerations
Certain precautions must be taken when programming the LCD/LED. One of these is to ensure that the
Display Memory is properly initialised after the microcontroller is powered on. Like the General
Purpose Data Memory, the contents of the Display Memory are in an unknown condition after
power-on. As the contents of the Display Memory will be mapped into the actual display, it is
important to initialise this memory area into a known condition soon after applying power to obtain a
proper display pattern.
Consideration must also be given to the capacitive load of the actual LCD used in the application. As
the load presented to the microcontroller by LCD pixels can be generally modeled as mainly
capacitive in nature, it is important that this is not excessive, a point that is particularly true in the case
of the COM lines which may be connected to many LCD pixels. The accompanying diagram depicts
the equivalent circuit of the LCD.
One additional consideration that must be taken into account is what happens when the
microcontroller enters a Power Down condition. The LCDEN control bit in the LCDCTRL or LEDEN
bit in the LEDCTRL register permits the display to be powered off to reduce power consumption. If
this bit is zero, the driving signals to the display will cease, producing a blank display pattern but
reducing any power consumption associated with the LCD.
After Power-on, note that as the LCDEN and LEDEN bits will be cleared to zero, the display function
will be disabled.
The accompanying timing diagrams depict the display driver signals generated by the microcontroller
for various values of duty and bias. The huge range of various permutations only permit a few types to
be displayed here.
S E G 0
S E G 1
S E G 2
S E G n
C O M 0
C O M 1
C O M 2
C O M n
LCD Panel Equivalent Circuit
Rev. 1.00
46
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
0
1
2
3
0
1
2
3
V D D
C O M 0
V S S
V D D
C O M 1
V S S
V D D
C O M 2
V S S
V D D
C O M 3
V S S
V D D
S E G 0
V S S
V D D
S E G 1
V S S
LED 1/4 Duty, COM High Active, SEG Low Active, Normal Operation
Rev. 1.00
47
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
During Reset or
in Power down Mode
VA
VB
VC
VSS
All common outputs
VA
VB
VC
VSS
All segment outputs
Normal Operation
Mode
1 Frame
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
VA
VB
VC
VSS
VA
VB
VC
VSS
COM0 segments ON
COM1 segments ON
VA
VB
VC
VSS
COM7 segments ON
VA
VB
VC
VSS
VA
VB
VC
VSS
COM0 & COM1
segments ON
COM0 & COM2
segments ON
COM0 & COM7
segments ON
VA
VB
VC
VSS
All segments ON
VA
VB
VC
VSS
LCD Driver Output - Type A, 1/8 Duty, 1/3 Bias
Rev. 1.00
48
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
During Reset or
in Power down Mode
All common outputs
VA
VB
VC
VSS
All segment outputs
VA
VB
VC
VSS
Normal Operation
Mode
1 Frame
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
VA
VB
VC
VSS
VA
VB
VC
VSS
COM0 segments ON
COM1 segments ON
VA
VB
VC
VSS
COM7 segments ON
VA
VB
VC
VSS
VA
VB
VC
VSS
COM0 & COM1
segments ON
COM0 & COM2
segments ON
COM0 & COM7
segments ON
VA
VB
VC
VSS
All segments ON
VA
VB
VC
VSS
LCD Driver Output - Type B, 1/8 Duty, 1/3 Bias
Rev. 1.00
49
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Timer/Event Counters
The provision of timers form an important part of any microcontroller, giving the designer a means of
carrying out time related functions. The device contains several 8-bit and 16-bit count-up timers. As
each timer has three different operating modes, they can be configured to operate as a general timer, an
external event counter or as a pulse width measurement device. The provision of a prescaler to the
clock circuitry of the 8-bit Timer/Event Counter also gives added range to this timer.
There are two types of registers related to the Timer/Event Counters. The first are the registers that
contain the actual value of the Timer/Event Counter and into which an initial value can be preloaded.
Reading from these registers retrieves the contents of the Timer/Event Counter. The second type of
associated register is the Timer Control Register which defines the timer options and determines how
the Timer/Event Counter is to be used. The Timer/Event Counters can have their clock configured to
come from an internal clock source. In addition, their clock source can also be configured to come
from an external timer pin.
D a ta B u s
T n P S C 2 ~ T n P S C 0
(1 /1 ~ 1 /1 2 8 )
fS
7 - s ta g e P r e s c a le r
Y S
T n M 1
T n M 0
P r e lo a d R e g is te r
T im e r /E v e n t C o u n te r
M o d e C o n tro l
T im e r /E v e n t
C o u n te r
F ilte r
T M R n
R e lo a d
T n E
T M n F L T
( F ilte r O n /O ff c o n tr o l)
O v e r flo w
to In te rru p t
8 - b it T im e r /E v e n t C o u n te r
T n O N
¸ 2
P F D 0
8-bit Timer/Event Counter Structure
D a ta B u s
E x te rn a l 3 2 7 6 8 H z
M
In te rn a l 3 2 K -IN T
U
X
C o n fig u r a tio n
O p tio n
fS
fS
Y S
M
/4
U B
U
X
T n M 1
L o w B y te
B u ffe r
T n M 0
1 6 - B it
P r e lo a d R e g is te r
T im e r /E v e n t C o u n te r
M o d e C o n tro l
T n S
F ilte r
T M R n
T M n F L T
( F ilte r O n /O ff c o n tr o l)
H ig h B y te
T n E
T n O N
L o w
R e lo a d
O v e r flo w
to In te rru p t
B y te
1 6 - b it T im e r /E v e n t C o u n te r
¸ 2
P F D 1
16-bit Timer/Event Counter Structure
M
P F D 0
P F D 1
U
X
P F D
C o n fig u r a tio n
O p tio n
Rev. 1.00
50
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Configuring the Timer/Event Counter Input Clock Source
The internal timer¢s clock can originate from various sources. The system clock source is used when
the Timer/Event Counter is in the timer mode or in the pulse width measurement mode. For the 8-bit
Timer/Event Counter this internal clock source is fSYS which is also divided by a prescaler, the division
ratio of which is conditioned by the Timer Control Register, TMRnC, bits TnPSC0~ TnPSC2. For the
16-bit Timer/Event Counter this internal clock source can be chosen from a combination of internal
clocks using a configuration option and the TnS bit in the TMRnC register.
An external clock source is used when the timer is in the event counting mode, the clock source being
provided on an external timer pin TMR0, TMR1, TMR2 or TMR3 depending upon which timer is
used. Depending upon the condition of the TnE bit, each high to low, or low to high transition on the
external timer pin will increment the counter by one.
Name
Bits
Data Register
Control Register
Timer/Event Counter 0
8
TMR0
TMR0C
Timer/Event Counter 1
16
TMR1H/TMR1L
TMR1C
Timer/Event Counter 2
8
TMR2
TMR2C
Timer/Event Counter 3
8
TMR3
TMR3C
Timer Registers - TMR0, TMR1L/TMR1H, TMR2, TMR3
The timer registers are special function registers located in the Special Purpose Data Memory and is the
place where the actual timer value is stored. For the 8-bit Timer/Event Counters, these registers are known
as TMR0, TMR2 or TMR3. For the 16-bit Timer/Event Counter, a pair of registers are required and are
known as TMR1L/TMR1H. The value in the timer registers increases by one each time an internal clock
pulse is received or an external transition occurs on the external timer pin. The timer will count from the
initial value loaded by the preload register to the full count of FFH for the 8-bit timer or FFFFH for the
16-bit timer at which point the timer overflows and an internal interrupt signal is generated. The timer value
will then be reset with the initial preload register value and continue counting.
To achieve a maximum full range count of FFH for the 8-bit timer or FFFFH for the 16-bit timer, the
preload registers must first be cleared to all zeros. It should be noted that after power-on, the preload
register will be in an unknown condition. Note that if the Timer/Event Counter is switched off and data
is written to its preload registers, this data will be immediately written into the actual timer registers.
However, if the Timer/Event Counter is enabled and counting, any new data written into the preload
data registers during this period will remain in the preload registers and will only be written into the
timer registers the next time an overflow occurs.
For the 16-bit Timer/Event Counter which has both low byte and high byte timer registers, accessing
these registers is carried out in a specific way. It must be noted when using instructions to preload data
into the low byte timer register, the data will only be placed in a low byte buffer and not directly into
the low byte timer register. The actual transfer of the data into the low byte timer register is only carried
out when a write to its associated high byte timer register, namely TMR1H, is executed. On the other
hand, using instructions to preload data into the high byte timer register will result in the data being
directly written to the high byte timer register. At the same time the data in the low byte buffer will be
transferred into its associated low byte timer register. For this reason, the low byte timer register should
be written first when preloading data into the 16-bit timer registers. It must also be noted that to read
the contents of the low byte timer register, a read to the high byte timer register must be executed first
to latch the contents of the low byte timer register into its associated low byte buffer. After this has
been done, the low byte timer register can be read in the normal way. Note that reading the low byte
timer register will result in reading the previously latched contents of the low byte buffer and not the
actual contents of the low byte timer register.
Rev. 1.00
51
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Timer Control Registers - TMR0C, TMR1C, TMR2C, TMR3C
The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in
three different modes, the options of which are determined by the contents of their respective control
register.
It is the Timer Control Register together with its corresponding timer registers that control the full
operation of the Timer/Event Counters. Before the timers can be used, it is essential that the
appropriate Timer Control Register is fully programmed with the right data to ensure its correct
operation, a process that is normally carried out during program initialisation.
To choose which of the three modes the timer is to operate in, either in the timer mode, the event
counting mode or the pulse width measurement mode, bits 7 and 6 of the corresponding Timer Control
Register, which are known as the bit pair TnM1/TnM0, must be set to the required logic levels. The
timer-on bit, which is bit 4 of the Timer Control Register and known as TnON, depending upon which
timer is used, provides the basic on/off control of the respective timer. Setting the bit high allows the
counter to run, clearing the bit stops the counter. For timers that have prescalers, bits 0~2 of the Timer
Control Register determine the division ratio of the input clock prescaler. The prescaler bit settings
have no effect if an external clock source is used. If the timer is in the event count or pulse width
measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the
Timer Control Register which is known as TnE. An additional TnS bit in the 16-bit Timer/Event
Counter control register is used to determine the clock source for the Timer/Event Counter.
Timer/Event Counter Control Register - TMRnC (n=0, 2, 3)
Bit
7
6
5
4
Name
TnM1
R/W
R/W
POR
0
3
2
1
0
TnM0
¾
R/W
¾
TnON
TnE
TnPSC2
TnPSC1
TnPSC0
R/W
R/W
R/W
R/W
R/W
0
¾
0
1
0
0
0
Bit 7~6
TnM1~TnM0: Timer/Event Counter Operating mode selection bit
00: no mode available
01: Event Counter mode
10: Timer mode
11: Pulse width measurement mode
Bit 5
Bit 4
Unimplemented, read as ²0²
TnON: Timer/Event Counter counting enable control
0: disable
1: enable
TnE: Timer/Event Counter active edge selection bits
Bit 3
For Event counter mode:
0: count on rising edge
1: count on falling edge
For Pulse width measurement mode:
0: start counting on falling edge
1: start counting on rising edge
Bit 2~0
Rev. 1.00
TnPSC2~TnPSC0: Timer/Event Counter prescaler rate selection bits
000: 1/1
001: 1/2
010: 1/4
011: 1/8
100: 1/16
101: 1/32
110: 1/64
111: 1/128
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December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Timer/Event Counter Control Register - TMRnC (n=1)
Bit
7
6
5
4
3
2
1
0
Name
TnM1
TnM0
TnS
TnON
TnE
¾
¾
¾
R/W
R/W
R/W
R/W
R/W
R/W
¾
¾
¾
POR
0
0
0
0
1
¾
¾
¾
Bit 7~6
Bit 5
Bit 4
Bit 3
Bit 2~0
TnM1~TnM0: Timer/Event Counter Operating mode selection bit
00: no mode available
01: Event Counter mode
10: Timer mode
11: Pulse width measurement mode
TnS: Timer/Event Counter clock source selection bit
0: fSYS/4
1: fSUB
TnON: Timer/Event Counter counting enable control
0: disable
1: enable
TnE: Timer/Event Counter active edge selection bits
For Event counter mode:
0: count on rising edge
1: count on falling edge
For Pulse width measurement mode:
0: start counting on falling edge
1: start counting on rising edge
Unimplemented, read as ²0²
Configuring the Timer Mode
In this mode, the Timer/Event Counter can be utilised to measure fixed time intervals, providing an
internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the
Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct
value as shown.
Control Register Operating Mode
Select Bits for the Timer Mode
Bit7
Bit6
1
0
In this mode the internal clock, fSYS , is used as the internal clock for 8-bit Timer/Event Counters and
fSUB or fSYS/4 is used as the internal clock for 16-bit Timer/Event Counter. However, the clock source,
fSYS, for the 8-bit timer is further divided by a prescaler, the value of which is determined by the
Prescaler Rate Select bits TnPSC2~TnPSC0, which are bits 2~0 in the Timer Control Register. After
the other bits in the Timer Control Register have been setup, the enable bit TnON or TnON, which is
bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter to run. Each
time an internal clock cycle occurs, the Timer/Event Counter increments by one. When it is full and
overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already
loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that
the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset
to zero.
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N + 1
Timer Mode Timing Chart
Rev. 1.00
53
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Configuring the Event Counter Mode
In this mode, a number of externally changing logic events, occurring on the external timer pin, can be
recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode Select bit pair,
TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown.
Control Register Operating Mode
Select Bits for the Event Counter Mode
Bit7
Bit6
0
1
In this mode, the external timer pin, is used as the Timer/Event Counter clock source, however it is not
divided by the internal prescaler. After the other bits in the Timer Control Register have been setup, the
enable bit TnON, which is bit 4 of the Timer Control Register, can be set high to enable the
Timer/Event Counter to run. If the Active Edge Select bit, TnE, which is bit 3 of the Timer Control
Register, is low, the Timer/Event Counter will increment each time the external timer pin receives a
low to high transition. If the Active Edge Select bit is high, the counter will increment each time the
external timer pin receives a high to low transition. When it is full and overflows, an interrupt signal is
generated and the Timer/Event Counter will reload the value already loaded into the preload register
and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter
Interrupt Enable bit in the corresponding Interrupt Control Register, is reset to zero.
E x te rn a l E v e n t
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Chart
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as an
event counter input pin, two things have to happen. The first is to ensure that the Operating Mode
Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counting Mode,
the second is to ensure that the port control register configures the pin as an input. It should be noted
that in the event counting mode, even if the microcontroller is in the Power Down Mode, the
Timer/Event Counter will continue to record externally changing logic events on the timer input pin.
As a result when the timer overflows it will generate a timer interrupt and corresponding wake-up
source.
Configuring the Pulse Width Measurement Mode
In this mode, the Timer/Event Counter can be utilised to measure the width of external pulses applied
to the external timer pin. To operate in this mode, the Operating Mode Select bit pair, TnM1/TnM0, in
the Timer Control Register must be set to the correct value as shown.
Control Register Operating Mode Select Bits
for the Pulse Width Measurement Mode
Bit7
Bit6
1
1
In this mode the internal clock, fSYS, is used as the internal clock for the 8-bit Timer/Event Counter and
fSUB or fSYS/4 is used as the internal clock for the 16-bit Timer/Event Counter. However, the clock
source, fSYS, for the 8-bit timer is further divided by a prescaler, the value of which is determined by the
Prescaler Rate Select bits TnPSC2~TnPSC0, which are bits 2~0 in the Timer Control Register. After
the other bits in the Timer Control Register have been setup, the enable bit TnON, which is bit 4 of the
Timer Control Register, can be set high to enable the Timer/Event Counter, however it will not actually
start counting until an active edge is received on the external timer pin.
If the Active Edge Select bit TnE, which is bit 3 of the Timer Control Register, is low, once a high to
low transition has been received on the external timer pin, the Timer/Event Counter will start counting
until the external timer pin returns to its original high level. At this point the enable bit will be
automatically reset to zero and the Timer/Event Counter will stop counting. If the Active Edge Select
Rev. 1.00
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December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
bit is high, the Timer/Event Counter will begin counting once a low to high transition has been
received on the external timer pin and stop counting when the external timer pin returns to its original
low level. As before, the enable bit will be automatically reset to zero and the Timer/Event Counter
will stop counting. It is important to note that in the Pulse Width Measurement Mode, the enable bit is
automatically reset to zero when the external control signal on the external timer pin returns to its
original level, whereas in the other two modes the enable bit can only be reset to zero under program
control.
The residual value in the Timer/Event Counter, which can now be read by the program, therefore
represents the length of the pulse received on the external timer pin. As the enable bit has now been
reset, any further transitions on the external timer pin will be ignored. Not until the enable bit is again
set high by the program can the timer begin further pulse width measurements. In this way, single shot
pulse measurements can be easily Made.
E x te rn a l T M R
P in In p u t
T n O N
- w ith T n E = 0
P r e s c a le r O u tp u t o r
In te r n a l C lo c k S o u r c e
In c re m e n t
T im e r C o u n te r
+ 1
T im e r
+ 2
+ 3
+ 4
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Measure Mode Timing Chart
It should be noted that in this mode the Timer/Event Counter is controlled by logical transitions on the
external timer pin and not by the logic level. When the Timer/Event Counter is full and overflows, an
interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the
preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event
Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset to zero.
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as a
pulse width measurement pin, two things have to happen. The first is to ensure that the Operating
Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Pulse Width
Measurement Mode, the second is to ensure that the port control register configures the pin as an input.
Programmable Frequency Divider - PFD
The Programmable Frequency Divider provides a means of producing a variable frequency output
suitable for applications requiring a precise frequency generator.
The PFD output is pin-shared with the I/O pin PA3. The PFD function is selected via configuration
option, however, if not selected, the pin can operate as a normal I/O pin.
The clock source for the PFD circuit can originate from either Timer/Event Counter 0 or Timer/Event
Counter 1 overflow signal selected via configuration option. The output frequency is controlled by
loading the required values into the timer registers and prescaler registers to give the required division
ratio. The timer will begin to count-up from this preload register value until full, at which point an
overflow signal is generated, causing the PFD output to change state. The timer will then be
automatically reloaded with the preload register value and continue counting-up.
For the PFD output to function, it is essential that the corresponding bit of the Port A control register PAC
bit 3 is setup as an output. If setup as an input the PFD output will not function, however, the pin can still be
used as a normal input pin. The PFD output will only be activated if bit PA3 is set to ²1². This output data bit
is used as the on/off control bit for the PFD output. Note that the PFD output will be low if the PA3 output
data bit is cleared to ²0².
Rev. 1.00
55
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Using this method of frequency generation, and if a crystal oscillator is used for the system clock, very
precise values of frequency can be generated.
T im e r O v e r flo w
P F D
C lo c k
P A 3 D a ta
P F D
O u tp u t a t P A 3
PFD Output Control
Prescaler
Bits TnPSC0~TnPSC2 of the control register can be used to define the pre-scaling stages of the
internal clock source of the Timer/Event Counter. The Timer/Event Counter overflow signal can be
used to generate signals for the PFD and Timer Interrupt.
I/O Interfacing
The Timer/Event Counter, when configured to run in the event counter or pulse width measurement
mode, require the use of external pins for correct operation. As these pins are shared pins they must be
configured correctly to ensure they are setup for use as Timer/Event Counter inputs and not as a normal
I/O pins. This is implemented by ensuring that the mode select bits in the Timer/Event Counter control
register, select either the event counter or pulse width measurement mode. Additionally the Port
Control Register must be set high to ensure that the pin is setup as an input. Any pull-high resistor on
these pins will remain valid even if the pin is used as a Timer/Event Counter input.
Timer/Event Counter Pins Internal Filter
The external Timer/Event Counter pins are connected to an internal filter to reduce the possibility of
unwanted event counting events or inaccurate pulse width measurements due to adverse noise or
spikes on the external Timer/Event Counter input signal. As this internal filter circuit will consume a
limited amount of power, several control bits named TMnFLT in the RCFLT register are provided to
switch off the filter function, a choice which may be beneficial in power sensitive applications, but in
which the integrity of the input signal is high.
Rev. 1.00
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December 2, 2011
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
RC Filter Control Register - RCFLT
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
INT1FLT
INT0FLT
TM3FLT
TM2FLT
TM1FLT
TM0FLT
R/W
¾
¾
R/W
R/W
R/W
R/W
R/W
R/W
POR
¾
¾
0
0
1
0
0
0
Bit 7~6
Bit 5
Unimplemented, read as ²0²
INT1FLT: External Interrupt 1 input RC Filter enable control
0: disable
1: enable
Bit 4
INT0FLT: External Interrupt 0 input RC Filter enable control
0: disable
1: enable
Bit 3
TM3FLT: Timer/Event Counter 3 input RC Filter enable control
0: disable
1: enable
TM2FLT: Timer/Event Counter 2 input RC Filter enable control
0: disable
1: enable
TM1FLT: Timer/Event Counter 1 input RC Filter enable control
0: disable
1: enable
TM0FLT: Timer/Event Counter 0 input RC Filter enable control
0: disable
1: enable
Bit 2
Bit 1
Bit 0
Programming Considerations
When configured to run in the timer mode, the internal system clock is used as the timer clock source and
is therefore synchronised with the overall operation of the microcontroller. In this mode when the
appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing
the program flow to the respective internal interrupt vector. For the pulse width measurement mode, the
internal system clock is also used as the timer clock source but the timer will only run when the correct
logic condition appears on the external timer input pin. As this is an external event and not synchronized
with the internal timer clock, the microcontroller will only see this external event when the next timer
clock pulse arrives. As a result, there may be small differences in measured values requiring
programmers to take this into account during programming. The same applies if the timer is configured
to be in the event counting mode, which again is an external event and not synchronised with the internal
system or timer clock.
When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to
avoid errors, however as this may result in a counting error, this should be taken into account by the
programmer. Care must be taken to ensure that the timers are properly initialised before using them for
the first time. The associated timer interrupt enable bits in the interrupt control register must be properly
set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer
mode and clock source control bits in timer control register must also be correctly set to ensure the timer
is properly configured for the required application. It is also important to ensure that an initial value is
first loaded into the timer registers before the timer is switched on; this is because after power-on the
initial values of the timer registers are unknown. After the timer has been initialised the timer can be
turned on and off by controlling the enable bit in the timer control register. Note that setting the timer
enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly
setup. Setting the timer enable bit high together with a mode bit modification, may lead to improper
timer operation if executed as a single timer control register byte write instruction.
Rev. 1.00
57
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt
control register will be set. If the timer interrupt is enabled this will in turn generate an interrupt signal.
However irrespective of whether the interrupts are enabled or not, a Timer/Event counter overflow
will also generate a wake-up signal if the device is in a Power-down condition. This situation may
occur if the Timer/Event Counter is in the Event Counting Mode and if the external signal continues to
change state. In such a case, the Timer/Event Counter will continue to count these external events and
if an overflow occurs the device will be woken up from its Power-down condition. To prevent such a
wake-up from occurring, the timer interrupt request flag should first be set high before issuing the
HALT instruction to enter the Power Down Mode.
Timer Program Example
This program example shows how the Timer/Event Counter registers are setup, along with how the
interrupts are enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of
the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the
same bit. This example program sets the Timer/Event Counter to be in the timer mode, which uses the
internal system clock as the clock source.
org
org
org
org
org
org
04h
reti
08h
reti
0ch
reti
10h
reti
14h
jmp tmr0int
:
2Ch
tmr0int:
:
reti
:
:
begin:
mov
a,09bh
mov
tmr0,a;
mov
a,081h
mov
tmr0c,a
mov
a,002h
intc1,a
set
intc0.0
set
tmr0c.4
previously setup
Rev. 1.00
; Smart Card interrupt vector
; USB interrupt vector
; External interrupt 0 vector
; External interrupt 1 vector
; Timer/Event Counter 0 interrupt vector
; jump here when the Timer/Event Counter 0 overflows
;internal Timer/Event Counter 0 interrupt routine
; Timer/Event Counter 0 main program placed here
;setup Timer 0 registers
; setup Timer 0 preload value
;
;
;
;
setup
timer
setup
timer
Timer 0 control register
mode and prescaler set to /2
interrupt register
0 interrupt
; enable master interrupt
; start Timer/Event Counter 0 - note mode bits must be
58
December 2, 2011
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Pulse Width Modulator
The device contains a series of Pulse Width Modulation, PWM, outputs. Useful for the applications
such as motor speed control, the PWM function provides an output with a fixed frequency but with a
duty cycle that can be varied by setting particular values into the corresponding PWM register.
PWM Mode
Channels
Output Pin
Register Names
PWM0
8+4
PC4
PWM0H/PWM0L
PWM1
8+4
PC5
PWM1H/PWM1L
PWM2
8+4
PC6
PWM2H/PWM2L
PWM3
8+4
PA5
PWM3H/PWM3L
PWM Overview
A register pair, located in the Data Memory is assigned to each Pulse Width Modulator output and are
known as the PWM registers. It is in each register pair that the 12-bit value, which represents the
overall duty cycle of one modulation cycle of the output waveform, should be placed. The PWM
registers also contain the enable/disable control bit for the PWM outputs. To increase the PWM
modulation frequency, each modulation cycle is modulated into sixteen individual modulation
sub-sections, known as the 8+4 mode. Note that it is only necessary to write the required modulation
value into the corresponding PWM register as the subdivision of the waveform into its sub-modulation
cycles is implemented automatically within the microcontroller hardware. The PWM clock source is
the system clock fSYS.
This method of dividing the original modulation cycle into a further 16 sub-cycles enables the
generation of higher PWM frequencies, which allow a wider range of applications to be served. As
long as the periods of the generated PWM pulses are less than the time constants of the load, the PWM
output will be suitable as such long time constant loads will average out the pulses of the PWM output.
The difference between what is known as the PWM cycle frequency and the PWM modulation
frequency should be understood. As the PWM clock is the system clock, fSYS, and as the PWM value is
12-bits wide, the overall PWM cycle frequency is fSYS/4096. However, when in the 8+4 mode of
operation, the PWM modulation frequency will be fSYS/256.
Rev. 1.00
PWM Modulation
Frequency
PWM Cycle
Frequency
PWM Cycle
Duty
fSYS/256
fSYS/4096
(PWM register
value)/4096
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December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
8+4 PWM Mode Modulation
Each full PWM cycle, as it is 12-bits wide, has 4096 clock periods. However, in the 8+4 PWM mode,
each PWM cycle is subdivided into sixteen individual sub-cycles known as modulation cycle 0 ~
modulation cycle 15, denoted as ²i² in the table. Each one of these sixteen sub-cycles contains 256 clock
cycles. In this mode, a modulation frequency increase of sixteen is achieved. The 12-bit PWM register
value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The
first group which consists of bit4~bit11 is denoted here as the DC value. The second group which
consists of bit0~bit3 is known as the AC value. In the 8+4 PWM mode, the duty cycle value of each of
the two modulation sub-cycles is shown in the following table.
Parameter
AC (0~15)
DC (Duty Cycle)
i<AC
DC+1
256
i³AC
DC
256
Modulation cycle i
(i=0~15)
8+4 Mode Modulation Cycle Values
The accompanying diagram illustrates the waveforms associated with the 8+4 mode of PWM operation. It is important to note how the single PWM cycle is subdivided into 16 individual modulation
cycles, numbered 0~15 and how the AC value is related to the PWM value.
fS
Y S
/2
[P W M ] = 1 6 0 0
P W M
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 1 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 1 /2 5 6
1 0 1 /2 5 6
1 0 1 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 1 /2 5 6
1 0 1 /2 5 6
1 0 1 /2 5 6
[P W M ] = 1 6 0 1
P W M
[P W M ] = 1 6 0 2
P W M
[P W M ] = 1 6 1 5
P W M
1 0 1 /2 5 6
P W M
m o d u la tio n p e r io d : 2 5 6 /fS
M o d u la tio n c y c le 0
1 0 1 /2 5 6
1 0 1 /2 5 6
Y S
M o d u la tio n c y c le 1
P W M
M o d u la tio n c y c le 2
c y c le : 4 0 9 6 /fS
M o d u la tio n c y c le 1 5
M o d u la tio n c y c le 0
Y S
8+4 PWM Mode
PWM Output Control
The four PWM0~PWM3 outputs are shared with I/O pins. To operate as a PWM output and not as an
I/O pin, the relevant PWM enable control bit in PWMnL register must be set high where n denotes 0
from 3. A zero must also be written to the corresponding bit in the relevant port control register, to
ensure that the PWM output pin is setup as an output. After these two initial steps have been carried
out, and of course after the required PWM 12-bit value has been written into the PWM register pair
register, writing a ²1² to the corresponding port data register will enable the PWM data to appear on the
pin. Writing a ²0² to the bit will disable the PWM output function and force the output low. In this way,
the Port data register bits, can also be used as an on/off control for the PWM function. Note that if the
enable bit in the PWMnL register is set high to enable the PWM function, but a ²1² has been written to
its corresponding bit in the port control register to configure the pin as an input, then the pin can still
function as a normal input line, with pull-high resistor selections.
Rev. 1.00
60
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
PWM Register Pairs - PWMnH/PWMnL (n=0~3)
PWMnH Register
Bit
7
6
5
4
3
2
1
0
Name
D11
D10
D9
D8
D7
D6
D5
D4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
PWMnL Register
Bit
7
Name
D3
D2
D1
D0
¾
¾
¾
PWMnEN
R/W
R/W
R/W
R/W
R/W
¾
¾
¾
R/W
POR
0
0
0
0
¾
¾
¾
0
²¾²
unimplemented, read as ²0²
D11~D4: PWMn duty DC value
D3~D0: PWMn duty AC value
PWMnEN: PWMn output enable control
0: I/O pin enable
1: PWM output pin enable
PWM Programming Example
The following sample program shows how the PWM output is setup and controlled.
mov
a,64h
mov
pwm0h,a
clr
pwm0l
clr
pcc.4
set
pwm0en
set
pc.4
: :
: :
clr
pc.4
Rev. 1.00
;
;
;
;
;
;
setup PWM0 value to 1600 decimal which is 640H
setup PWM0H register value
setup PWM0L register value
setup pin PC4 as an output
set the PWM0 enable bit
Enable the PWM0 output
; PWM0 output disabled - PC4 will remain low
61
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Analog to Digital Converter
The need to interface to real world analog signals is a common requirement for many electronic
systems. However, to properly process these signals by a microcontroller, they must first be converted
into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the
microcontroller, the need for external components is reduced significantly with the corresponding
follow-on benefits of lower costs and reduced component space requirements.
A D C S 2 ~ A D C S 0
P C R 7 ~ P C R 0
fS
Y S
¸ 2
N
V
D D
P A 7 /A N 7 /V R E F
(N = 0 ~ 5 )
A /D
A D O N B
B it
C lo c k
V R E F S
B it
A /D
P A 0 /A N 0
P A 1 /A N 1
A /D
R e fe r e n c e V o lta g e
A D R L
C o n v e rte r
P A 7 /A N 7
V
A D R H
A /D D a ta
R e g is te r s
S S
1 .2 5 V
V B G E N
E O C B
S T A R T
A C S 4 ,
A C S 2 ~ A C S 0
A D O N B
A/D Converter Structure
A/D Overview
The device contains an 8-channel analog to digital converter which can directly interface to external
analog signals, such as that from sensors or other control signals and convert these signals directly into
either a 12-bit digital value.
Input Channels
Conversion Bits
Input Pins
8
12
PA0~PA7
The accompanying block diagram shows the overall internal structure of the A/D converter, together
with its associated registers.
A/D Converter Data Registers - ADRL, ADRH
The device, which has an internal 12-bit A/D converter, requires two data registers, a high byte
register, known as ADRH, and a low byte register, known as ADRL. After the conversion process
takes place, these registers can be directly read by the microcontroller to obtain the digitised
conversion value. Only the high byte register, ADRH, utilises its full 8-bit contents. The low byte
register utilises only 4 bit of its 8-bit contents as it contains only the lowest bits of the 12-bit converted
value.
In the following table, D0~D11 is the A/D conversion data result bits.
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADRL
D3
D2
D1
D0
¾
¾
¾
¾
ADRH
D11
D10
D9
D8
D7
D6
D5
D4
A/D Data Registers
Rev. 1.00
62
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
A/D Converter Control Registers - ADCR, ADPCR, ACSR
To control the function and operation of the A/D converter, three control registers known as ADCR,
ADPCR and ACSR are provided. These 8-bit registers define functions such as the selection of which
analog channel is connected to the internal A/D converter, which pins are used as analog inputs and
which are used as normal I/Os, the A/D clock source as well as controlling the start function and
monitoring the A/D converter end of conversion status.
The ACS4, ACS2~ACS0 bits in the register and the ACS4 bit in the ACSR register define the channel
number. As the device contains only one actual analog to digital converter circuit, each of the
individual 8 analog inputs must be routed to the converter. It is the function of the ACS2~ACS0 bits in
the ADCR register and the ACS4 bit in the ACSR register to determine which analog channel is
actually connected to the internal A/D converter.
The ADPCR control register contains the PCR7~PCR0 bits which determine which pins on Port A are
used as analog inputs for the A/D converter and which pins are to be used as normal I/O pins. If the
PCRn bit has a value of 1, the related pin on PORT A will be set as an analog input. If the PCRn bit is
set to zero, then the related pin on Port A will be setup as a normal I/O pin.
ACSR Register
Bit
7
6
5
4
3
2
1
0
Name
TEST
ADONB
ACS4
VBGEN
VREFS
ADCS2
ADCS1
ADCS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2~0
Rev. 1.00
TEST: For test only, read as 1
ADONB: A/D Converter enable control
0: A/D converter is turned on
1: A/D converter is turned off
ACS4: Internal Band-gap reference voltage channel input selection
0: A/D converter analog channel is connected to the analog input from AN0 to AN/7
1: A/D converter analog channel is connected to the internal Band-gap voltage VBG
VBGEN: Band-gap reference voltage enable control
0: Band-gap voltage VBG is disabled and connected to the ground
1: Band-gap voltage VBG is enabled
The band-gap reference voltage VBG is used for the A/D converter and LVD/LVR function, which
is controlled by the band-gap reference voltage enable bit VBGEN in the ACSR register. If the
VBG is not used for the A/D converter and the LVD/LVR function is disabled, the microcontroller
hardware will automatically turned off the band-gap reference voltage to conserve power. Care
must be taken as when the VREFS bit is set high for the A/D converter, then a VBG turn on time
tBG must be allowed before any A/D conversions are implemented.
VREFS: A/D converter reference voltage selection bit
0: from the internal voltage AVDD
1: from the external pin VREF
The A/D reference voltage can come from either the internal voltage AVDD or the external
voltage VREF, which is selected by the VREFS bit in the ACSR register. When the VREFS bit
is cleared to 0, the reference voltage of the A/D converter comes from the internal A/D power
supply VADD and the external VREF pin can be used as an I/O pin or other pin-shared function.
When the VREFS bit is set to 1, the reference voltage of the A/D converter comes from the
external VREF pin and the I/O or other pin-shared functions are disabled.
ADCS2~ADCS0: Select A/D converter clock source
000: fSYS/2
001: fSYS/8
010: fSYS/32
011: undefined
100: fSYS
101: fSYS/4
110: fSYS/16
111: undefined
63
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
ADCR Register
Bit
7
6
5
4
3
2
1
0
Name
START
EOCB
¾
¾
¾
ACS2
ACS1
ACS0
R/W
R/W
R
¾
¾
¾
R/W
R/W
R/W
POR
0
1
¾
¾
¾
0
0
0
Bit 7
START: Start the A/D conversion
0®1®0 : start
0®1
: reset the A/D converter and set EOCB to ²1²
Bit 6
EOCB: End of A/D Conversion flag
0: A/D conversion ended
1: A/D conversion waiting or in progress
Bit 5~3
unimplemented, read as ²0²
Bit 2~0
ACS2~ACS0: A/D converter channel selection bits
000: AN0 is selected
001: AN1 is selected
010: AN2 is selected
011: AN3 is selected
100: AN4 is selected
101: AN5 is selected
110: AN6 is selected
111: AN7 is selected
only valid if ACS4=0
ADPCR Register
Bit
7
6
5
4
3
2
1
0
Name
PCR7
PCR6
PCR5
PCR4
PCR3
PCR2
PCR1
PCR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
PCR7~PCR0: A/D converter analog channel configuration
0: I/O pin or other pin-shared function
1: A/D analog channel
When the related bit is set to 1, the corresponding pin is used as an analog input and all other
pin-shared functions are disabled automatically.
The START bit in the register is used to start and reset the A/D converter. When the microcontroller
sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR
register will be set to a ²1² and the analog to digital converter will be reset. It is the START bit that is
used to control the overall on/off operation of the internal analog to digital converter.
The EOCB bit in the ADCR register is used to indicate when the analog to digital conversion process is
complete. This bit will be automatically set to ²0² by the microcontroller after a conversion cycle has
ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control
register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated.
This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt
address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll
the EOCB bit in the ADCR register to check whether it has been cleared as an alternative method of
detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock fSYS, is first divided by
a division ratio, the value of which is determined by the ADCS2, ADCS1 and ADCS0 bits in the
ACSR register.
Rev. 1.00
64
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Controlling the on/off function of the A/D converter circuitry is implemented using the ADONB bit in
the ACSR register. When the ADONB bit is cleared to 0, the A/D converter is enabled.
Although the A/D clock source is determined by the system clock fSYS, and by bits ADCS2~ADCS0,
there are some limitations on the maximum A/D clock source speed that can be selected. As the minimum
value of permissible A/D clock period, tAD, is 0.5ms, care must be taken for system clock frequencies equal
to or greater than 4MHz. For example, if the system clock operates at a frequency of 4MHz, the
ADCS2~ADCS0 bits should not be set to ²100². Doing so will give A/D clock periods that are less than the
minimum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following
table for examples, where values marked with an asterisk * show where, depending upon the device,
special care must be taken, as the values may be less than the specified minimum A/D Clock Period.
A/D Clock Period (tAD)
fSYS
ADCS=000
ADCS=001
ADCS=010
ADCS=011
ADCS=100
ADCS=101
ADCS=110
ADCS=111
(tAD=2/fSYS)
(tAD=8/fSYS)
(tAD=32/fSYS)
(undefined)
(tAD=1/fSYS)
(tAD=4/fSYS)
(tAD=16/fSYS)
(undefined)
1MHz
2ms
8ms
32ms
Undefined
1ms
4ms
16ms
Undefined
2MHz
1ms
4ms
16ms
Undefined
500ns
2ms
8ms
Undefined
4MHz
500ns
2ms
8ms
Undefined
250ns*
1ms
4ms
Undefined
8MHz
250ns*
1ms
4ms
Undefined
125ns*
500ns
2ms
Undefined
12MHz
167ns*
667ns
2.67ms
Undefined
83ns*
333ns*
1.33ms
Undefined
A/D Clock Period Examples
A/D Input Pins
All of the A/D analog input pins are pin-shared with the I/O pins on Port A. Bits PCR7~PCR0 in the
ADPCR register, determine whether the input pins are setup as normal input/output pins or whether
they are setup as analog inputs. In this way, pins can be changed under program control to change their
function from normal I/O operation to analog inputs and vice versa. Pull-high resistors, which are
setup through register programming, apply to the input pins only when they are used as normal I/O
pins, if setup as A/D inputs the pull-high resistors will be automatically disconnected. Note that it is not
necessary to first setup the A/D pin as an input in the port control register to enable the A/D input as
when the PCR7~PCR0 bits enable an A/D input, the status of the port control register will be
overridden. The A/D converter has its own power supply pins AVDD and AVSS and a VREF reference
pin. The analog input values must not be allowed to exceed the value of VREF.
Initialising the A/D Converter
The internal A/D converter must be initialised in a special way. Each time the A/D channel selection
bits are modified by the program, the A/D converter must be re-initialised. If the A/D converter is not
initialised after the channel selection bits are changed, the EOCB flag may have an undefined value,
which may produce a false end of conversion signal. To initialise the A/D converter after the channel
selection bits have changed, then the START bit in the ADCR register must first be set high and then
immediately cleared to zero. This will ensure that the EOCB flag is correctly set to a high condition.
Summary of A/D Conversion Steps
The following summarises the individual steps that should be executed in order to implement an A/D
conversion process.
Rev. 1.00
·
Step 1
Select the required A/D conversion clock by correctly programming bits ADCS2, ADCS1 and
ADCS0 in the register.
·
Step 2
Enable the A/D by clearing the in the ACSR register to zero.
65
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
·
Step 3
Select which channel is to be connected to the internal A/D converter by correctly programming the
ACS4, ACS2~ACS0 bits which are also contained in the register.
·
Step 4
Select which pins on the I/O port are to be used as A/D inputs and configure them as A/D input pins
by correctly programming the PCR7~PCR0 bits in the ADPCR register.
·
Step 5
If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure
the A/D converter interrupt function is active. The master interrupt control bit, EMI, in the INTC0
interrupt control register must be set to ²1² and the A/D converter interrupt enable bit, EADI, in the
INTC2 register must also be set to ²1².
·
Step 6
The analog to digital conversion process can now be initialised by setting the START bit in the
ADCR register from ²0² to ²1² and then to ²0² again. Note that this bit should have been originally
set to ²0².
·
Step 7
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR
register can be polled. The conversion process is complete when this bit goes low. When this occurs
the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an
alternative method if the interrupts are enabled and the stack is not full, the program can wait for an
A/D interrupt to occur.
When checking for the end of the conversion process, if the method of polling the bit in the ADCR
register is used, the interrupt enable step above can be omitted.
Note
The accompanying diagram shows graphically the various stages involved in an analog to digital
conversion process and its associated timing.
The setting up and operation of the A/D converter function is fully under the control of the application
program as there are no configuration options associated with the A/D converter. After an A/D
conversion process has been initiated by the application program, the microcontroller internal hardware
will begin to carry out the conversion, during which time the program can continue with other functions.
The time taken for the A/D conversion is 16tAD where tAD is equal to the A/D clock period.
P C R 7 ~
P C R 0
0 0 0 0 0 0 0 0 B
0 0 0 0 0 1 0 1 B
0 0 0 0 0 1 0 0 B
0 0 0 0 0 0 0 0 B
A D O N B
tO
A D C m o d u le
O N
N 2 S T
o n
A /D
tA
s a m p lin g tim e
A /D
tA
D C S
o ff
s a m p lin g t im e
o n
o ff
D C S
S T A R T
E O C B
A C S 2 ~
A C S 0 *
x x x B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
A /D
N o te :
A /D c
tA D C S
tA D C =
"*" o n
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e p o r t c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
x x x B
E n d o f A /D
c o n v e r s io n
tA D C
c o n v e r s io n tim e
A /D
lo c k m u s t b e fS Y S , fS Y S /2 , fS Y S /4 , fS Y S /8 , fS Y S /1 6 o r fS
= 4 tA D
tA D C S + n * tA D ; n = b it c o u n t o f A D C r e s o lu tio n
ly v a lid if A C S 4 = 0
Y S
tA D C
c o n v e r s io n tim e
/3 2
A/D Conversion Timing
Rev. 1.00
66
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Programming Considerations
The A/D converter can be powered down by setting the ADONB bit in ACSR register to reduce power
consumption. It is an important ability for some applications such as battery powered or handheld
appliance.
Another important programming consideration is that when the A/D channel selection bits change
value, the A/D converter must be re-initialised. This is achieved by pulsing the START bit in the
ADCR register immediately after the channel selection bits have changed state. The exception to this
is where the channel selection bits are all cleared, in which case the A/D converter is not required to be
re-initialised.
A/D Programming Example
The following two programming examples illustrate how to setup and implement an A/D conversion.
In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when
the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to
determine when the conversion is complete.
Example: using an EOCB polling method to detect the end of conversion
clr
mov
mov
mov
mov
mov
Mov
EADI
a,00000001B
ACSR,a
a,0FH
ADPCR,a,
a,00H
ADCR,a
:
:
Start_conversion:
clr START
set START
clr START
Polling_:
sz
EOCB
jmp
mov
mov
mov
mov
polling_EOC
a,ADRL
adrl_buffer,a
a,ADRH
adrh_buffer,a
; disable ADC interrupt
; select fSYS/8 as A/D clock and turn on ADONB bit
; setup ADPCR register to configure Port A pin PA0~PA3
; as A/D inputs
; and select AN0 to be connected to the A/D converter
:
; As the Port A channel bits have changed the
; following START
; signal (0-1-0) must be issued
; instruction cycles
; reset A/D
; start A/D
; poll the ADCR register EOCB bit to detect end
; of A/D conversion
; continue polling
; read low byte conversion result value
; save result to user defined register
; read high byte conversion result value
; save result to user defined register
:
jmp
Rev. 1.00
start_conversion ; start next A/D conversion
67
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Example: using the interrupt method to detect the end of conversion
clr
mov
mov
mov
mov
Mov
mov
EADI
a,00000001B
ACSR,a
a, 0FH
ADPCR,a
a, 00H
ADCR,a
; disable ADC interrupt
; select fSYS/8 as A/D clock and turn on ADONB bit
; setup ADPCR register to configure Port A pin PA0~PA3
; as A/D inputs
; and select AN0 to be connected to the A/D converter
:
; As the Port A channel bits have changed the
; following START signal(0-1-0) must be issued
;
:
Start_conversion:
clr START
set START
; reset A/D
clr START
; start A/D
clr ADF
; clear ADC interrupt request flag
set EADI
; enable ADC interrupt
set EMI
; enable global interrupt
:
:
:
; ADC interrupt service routine
ADC_:
mov acc_stack,a
; save ACC to user defined memory
mov a,STATUS
mov status_stack,a
; save STATUS to user defined memory
:
:
mov a,ADRL
; read low byte conversion result value
mov adrl_buffer,a
; save result to user defined register
mov a,ADRH
; read high byte conversion result value
mov adrh_buffer,a
; save result to user defined register
:
:
EXIT__ISR:
mov a,status_stack
mov STATUS,a
mov a,acc_stack
clr ADF
reti
Rev. 1.00
; restore STATUS from user defined memory
; restore ACC from user defined memory
; clear ADC interrupt flag
68
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
A/D Transfer Function
As the device contains a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH.
Since the full-scale analog input value is equal to the VDD or VREF voltage, this gives a single bit analog
input value of (VDD or VREF /4096). The diagram shows the ideal transfer function between the analog
input value and the digitised output value for the A/D converter.
Note that to reduce the quantisation error, a 0.5 LSB offset is added to the A/D Converter input. Except
for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below
where they would change without the offset, and the last full scale digitized value will change at a point
1.5 LSB below the VDD or VREF level.
1 .5 L S B
F F F H
F F E H
F F D H
A /D C o n v e r s io n
R e s u lt
0 .5 L S B
0 3 H
0 2 H
0 1 H
0
1
2
3
4 0 9 3 4 0 9 4
4 0 9 5 4 0 9 6
(
V
D D
o r V
4 0 9 6
R E F
)
A n a lo g In p u t V o lta g e
Ideal A/D Transfer Function
Rev. 1.00
69
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Serial Interface Function - SIM
The device contains two Serial Interface Modules named SIM0 and SIM1 to implement Serial
Interface Function, which includes both the four line SPI interface and the two line I2C interface types,
to allow an easy method of communication with external peripheral hardware. Having relatively
simple communication protocols, these serial interface types allow the microcontroller to interface to
external SPI or I2C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM
interface pins are pin-shared with other I/O pins therefore the SIM interface function must first be
selected using a configuration option. As both interface types share the same pins and registers, the
choice of whether the SPI or I2C type is used is made using a bit in an internal register.
D a ta B u s
S IM n D R
S D In P in
T x /R x S h ift R e g is te r
C K E G n b it
C K P O L n b it
C lo c k
E d g e /P o la r ity
C o n tro l
S C K n P in
fS Y S
fS U B
T im e r /E v e n t C o u n te r
S D O n P in
E n a b le /D is a b le
B u s y
S ta tu s
C o n fig u r a tio n
O p tio n
W C O L n F la g
T R F n F la g
C lo c k
S o u r c e S e le c t
S C S n P in
C S E N n b it
C o n fig u r a tio n
O p tio n
E n a b le /D is a b le
SPI Block Diagram
SPI Interface
The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash
or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a
synchronous serial data interface that has a relatively simple communication protocol simplifying the
programming requirements when communicating with external hardware devices.
The communication is full duplex and operates as a slave/master type, where the MCU can be either
master or slave. Although the SPI interface specification can control multiple slave devices from a
single master, here, as only a single select pin, SCS, is provided only one slave device can be connected
to the SPI bus.
S P I S la v e
S P I M a s te r
S C K
S C K
S D O
S D I
S D O
S D I
S C S
S C S
SPI Master/Slave Connection
Rev. 1.00
70
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
·
SPI Interface Operation
The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin
names SDIn, SDOn, SCKn and SCSn where n stands for 0 and 1 respectively. Pins SDIn and SDOn
are the Serial Data Input and Serial Data Output lines, SCKn is the Serial Clock line and SCSn is the
Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C
function pins, the SPI interface must first be enabled by selecting the SIMn enable configuration
options and setting the correct bits in the SIMnCTL0/SIMnCTL2 register. After the SIMn
configuration option has been configured it can also be additionally disabled or enabled using the
SIMnEN bit in the SIMnCTL0 register. Communication between devices connected to the SPI
interface is carried out in a slave/master mode with all data transfer initiations being implemented by
the master. The Master also controls the clock signal. As each SIM only contains a single SCS pin,
only one slave device can be utilized for each SIM.
The SPI function in this device offers the following features:
¨ Full
duplex synchronous data transfer
¨ Both
Master and Slave modes
¨ LSB
first or MSB first data transmission modes
¨ Transmission
¨ Rising
complete flag
or falling active clock edge
¨ WCOLn
and CSENn bit enabled or disable select
The status of the SPI interface pins is determined by a number of factors such as whether the device
is in the master or slave mode and upon the condition of certain control bits such as CSENn,
SIMnEN and SCSn. In the table I, Z represents an input floating condition. There are several
configuration options associated with the SPI interface. One of these is to enable the SIMn function
which selects the SIMn pins rather than normal I/O pins. Note that if the configuration option does
not select the SIMn function then the SIMnEN bit in the SIMnCTL0 register will have no effect.
Another two SIMn configuration options determine if the CSENn and WCOLn bits are to be used.
Configuration Option
Function
SIMn Function
SIMn interface or I/O pins
SPI CSENn bit
Enable/Disable
SPI WCOLn bit
Enable/Disable
SPI Interface Configuration Options
Rev. 1.00
71
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
SIM0 Control Register 0 - SIM0CTL0
Bit
7
6
5
4
Name
S0SIM2
S0SIM1
S0SIM0
PCKEN
3
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
0
0
2
1
0
SIM0EN
¾
R/W
R/W
¾
0
0
¾
PCKPSC1 PCKPSC0
Bit 7~5
S0SIM2~S0SIM0: SIM0 mode and clock selection
000: SIM0 in SPI master mode with fSYS/4 clock source
001: SIM0 in SPI master mode with fSYS/16 clock source
010: SIM0 in SPI master mode with fSYS/64 clock source
011: SIM0 in SPI master mode with fSUB clock source
100: SIM0 in SPI master mode with Timer/Event Counter 0 overflow/2 clock (PFD0)
101: SIM0 in SPI slave mode
2
110: SIM0 in I C mode
111: Reserved
Bit 4
PCKEN: Peripheral Clock PCK enable control
0: PCK output is disabled
1: PCK output is enabled
PCKPSC1~PCKPSC0: Peripheral Clock PCK output clock prescaler
00: fSYS
01: fSYS/4
10: fSYS/8
11: Timer/Event Counter 0 overflow /2 (PFD0)
SIM0EN: SIM0 enable control
0: SIM0 is disabled
1: SIM0 is enabled
Bit 3~2
Bit 1
unimplemented, read as ²0²
Bit 0
SIM1 Control Register 0 - SIM1CTL0
Bit
7
6
5
4
3
2
1
Name
S1SIM2
S1SIM1
S1SIM0
¾
¾
¾
SIM1EN
¾
R/W
R/W
R/W
R/W
¾
¾
¾
R/W
¾
POR
1
1
1
¾
¾
¾
0
¾
Bit 7~5
S1SIM2~S1SIM0: SIM1 mode and clock selection
000: SIM1 in SPI master mode with fSYS/4 clock source
001: SIM1 in SPI master mode with fSYS/16 clock source
010: SIM1 in SPI master mode with fSYS/64 clock source
011: SIM1 in SPI master mode with fSUB clock source
100: SIM1 in SPI master mode with Timer/Event Counter 0 overflow/2 clock (PFD0)
101: SIM1 in SPI slave mode
2
110: SIM1 in I C mode
111: Reserved
Bit 4~2
unimplemented, read as ²0²
Bit 1
SIM1EN: SIM1 enable control
0: SIM1 is disabled
1: SIM1 is enabled
Bit 0
unimplemented, read as ²0²
Rev. 1.00
72
0
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
SIMn Control Register 1 - SIMnCTL1 (n=0 or 1) for I2C Mode
Bit
7
6
5
4
3
2
1
0
Name
HCFn
HAASn
HBBn
HTXn
TXAKn
SRWn
¾
RXAKn
R/W
R/W
R/W
R/W
R/W
R/W
R/W
¾
R/W
POR
1
0
0
0
0
0
¾
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
2
HCFn: I C Bus data transfer completion flag
0: Data is being transferred
1: Completion of an 8-bit data transfer
The HCFn flag is the data transfer flag. This flag will be zero when data is being transferred.
Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated.
2
HAASn: I C Bus address match flag
0: No address match
1: Address match
The HAASn flag is the address match flag. This flag is used to determine if the slave device
address is the same as the master transmit address. If the addresses match, then this bit will be
high. If there is no address match, then the flag will be low.
2
HBBn: I C Bus busy flag
2
0: I C Bus is not busy
2
1: I C Bus is busy
2
2
The HBBn flag is the I C busy flag. This flag will be 1 when the I C bus is busy which will occur
when a START signal is detected. The flag will be set to 0 when the bus is free which will occur
when a STOP signal is detected.
2
HTXn: Select I C slave device is transmitter or receiver
0: Slave device is the receiver
1: Slave device is the transmitter
2
TXAKn: I C Bus transmit acknowledge flag
0: Slave sends acknowledge flag
1: Slave does not send acknowledge flag
The TXAKn bit is the transmit acknowledge flag. After the slave device receipt of 8-bit of data,
this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device
must always set TXAKn bit to 0 before further data is received.
2
SRWn: I C Slave Read/Write flag
0: Slave device should be in receive mode
1: Slave device should be in transmit mode
2
The SRWn flag is the I C Slave Read/Write flag. This flag determines whether the master device
2
wishes to transmit or receive data to or from the I C bus. When the transmitted address and
slave address is match, that is when the HAASn flag is set high, the slave device will check the
SRWn flag to determine whether it should be in transmit mode or receive mode. If the SRWn flag
is high, the master is requesting to read data from the bus, so the slave device should be in
transmit mode. When the SRWn flag is zero, the master will write data to the bus, therefore the
slave device should be in receive mode to read this data.
unimplemented, read as ²0²
2
RXAKn: I C Bus Receive acknowledge flag
0: Slave receives acknowledge flag
1: Slave does not receive acknowledge flag
The RXAKn flag is the receiver acknowledge flag. When the RXAKn flag is 0, it means that a
acknowledge signal has been received at the 9th clock, after 8 bits of data have been
transmitted. When the slave device in the transmit mode, the slave device checks the RXAKn flag
to determine if the master receiver wishes to receive the next byte. The slave transmitter will
therefore continue sending out data until the RXAKn flag is 1. When this occurs, the slave
transmitter will release the SDAn line to allow the master to send a STOP signal to release the
2
I C Bus.
73
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
SIMn Control Register 2 - SIMnCTL2 (n=0 or 1) for SPI Mode
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
CKPOLn
CKEGn
MLSn
CSENn
WCOLn
TRFn
R/W
¾
¾
R/W
R/W
R/W
R/W
R/W
R/W
POR
¾
¾
0
0
0
0
0
0
Bit 7~6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
undefined bit, read as 0
CKPOLn: Determines the base condition of the SPI clock line
0: the SCKn line will be high when the SPI clock is inactive
1: the SCKn line will be low when the SPI clock is inactive
The CKPOLn bit determines the base condition of the SPI clock line, if the bit is high, then the
SCKn line will be low when the clock is inactive. When the CKPOLn bit is low, then the SCKn line
will be high when the clock is inactive.
CKEGn: Determines SPI SCKn active clock edge type
CKPOLn=0
0: SCKn is high base level and data capture at SCKn rising edge
1: SCKn is high base level and data capture at SCKn falling edge
CKPOLn=1
0: SCKn is low base level and data capture at SCKn falling edge
1: SCKn is low base level and data capture at SCKn rising edge
The CKEGn and CKPOLn bits are used to setup the way that the clock signal outputs and inputs
data on the SPI bus. These two bits must be configured before data transfer is executed
otherwise an erroneous clock edge may be generated. The CKPOLn bit determines the base
condition of the clock line. If the bit is high, then the SCKn line will be low when the clock is
inactive. When the CKPOLn bit is low, then the SCKn line will be high when the clock is inactive.
The CKEGn bit determines active clock edge type which depends upon the condition of CKPOLn
bit.
MLSn: SPI Data shift order
0: LSB shift first
1: MSB shift first
This is the data shift select bit and is used to select how the data is transferred, either MSB or
LSB first. Setting the bit high will select MSB first and low for LSB first.
CSENn: SPI SCSn pin control
0: Disable
1: Enable
The CSENn bit is used as an enable/disable for the SCSn pin. If this bit is low, then the
SCSn pin will be disabled and placed into a floating condition. If the bit is high the SCSn pin will
be enabled and used as a select pin.
Note that using the CSENn bit can be disabled or enabled via configuration option.
WCOLn: SPI Write Collision flag
0: No collision
1: Collision
The WCOLn flag is used to detect if a data collision has occurred. If this bit is high it means that
data has been attempted to be written to the SIMnDR register during a data transfer operation.
This writing operation will be ignored if data is being transferred. The bit can be cleared by the
application program. Note that using the WCOLn bit can be disabled or enabled via configuration
option.
TRFn: SPI Transmit/Receive Complete flag
0: Data is being transferred
1: SPI data transmission is completed
The TRFn bit is the Transmit/Receive Complete flag and is set to 1 automatically when an SPI
data transmission is completed, but must set to 0 by the application program. It can be used to
generate an interrupt.
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December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
SPI Registers
There are three internal registers which control the overall operation of the SPI interface for each SIM.
These are the SIMnDR data register and two control registers SIMnCTL0 and SIMnCTL2. Note that
the SIMnCTL1 register is only used by the I2C interface.
Master/Salve
SIMnEN=0
Pin
Master - SIMnEN=1
CSENn=1
Slave - SIMnEN=1
CSENn=0
CSENn=0
SCSn Line=0
(CSENn=1)
SCSn Line=1
(CSENn=1)
SCSn
Z
L
Z
Z
I, Z
I, Z
SDOn
Z
O
O
O
O
Z
SDIn
Z
I, Z
I, Z
I, Z
I, Z
Z
SCKn
Z
H: CKPOLn=0
L: CKPOLn=1
H: CKPOLn=0
L: CKPOLn=1
I, Z
I, Z
Z
Note:
²Z² floating, ²H² output high, ²L² output low, ²I² Input, ²O²output level, ²I,Z² input floating (no pull-high)
SPI Interface Pin Status
The SIMnDR register is used to store the data being transmitted and received. The same register is
used by both the SPI and I2C functions. Before the microcontroller writes data to the SPI bus, the actual
data to be transmitted must be placed in the SIMnDR register. After the data is received from the SPI
bus, the microcontroller can read it from the SIMnDR register. Any transmission or reception of data
from the SPI bus must be made via the SIMnDR register.
Bit
7
6
5
4
3
2
1
0
Label
SnD7
SnD6
SnD5
SnD4
SnD3
SnD2
SnD1
SnD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
X
X
X
X
X
X
X
X
There are also two control registers for the SPI interface, SIMnCTL0 and SIMnCTL2. Note that the
SIMnCTL2 register also has the name SIMnAR which is used by the I2C function. The SIMnCTL1
register is not used by the SPI function, only by the I2C function. Register SIMnCTL0 is used to control the enable/disable function and to set the data transmission clock frequency. Although not connected with the SPI function, the SIMnCTL0 register is also used to control the Peripheral Clock
prescaler. Register SIMnCTL2 is used for other control functions such as LSB/MSB selection, write
collision flag etc.
The following gives further explanation of each SIM related register bit.
Rev. 1.00
·
SIMIDLE
The SIMIDLE bit is used to select if the master SPI interface continues running when the device is in
the IDLE mode. Setting the bit high allows the clock source of the master SPI interface or the
Peripheral clock PCLK, which is selected to come from the divided system clock, to keep active
when the device is in the IDLE mode. This will maintain the master SPI interface operation or the
Peripheral clock PCLK output active if the PCKEN bit is set to 1 in IDLE mode. Clearing the bit to
zero disables any master SPI interface operations or PCLK output in the IDLE mode. This SPI/I2C
idle mode control bit SIMIDLE is located at CLKMOD register bit4.
·
SIMnEN
The bit is the overall on/off control for the SPI interface. When the SIMnEN bit is cleared to zero to
disable the SPI interface, the SDIn, SDOn, SCKn and SCSn lines will be in a floating condition and
the SPI operating current will be reduced to a minimum value. When the bit is high the SPI interface
is enabled. The SIMn configuration option must have first enabled the SIMn interface for this bit to
be effective. Note that when the SIMnEN bit changes from low to high the contents of the SPI
control registers will be in an unknown condition and should therefore be first initialised by the
application program.
75
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
S IM E N n = 1 , C S E N n = 0 ( E x te r n a l P u ll- H ig h )
S C S n
S IM n E N , C S E N n = 1
S C K n (C K P O L n = 1 , C K E G n = 0 )
S C K n (C K P O L n = 0 , C K E G n = 0 )
S C K n (C K P O L n = 1 , C K E G n = 1 )
S C K (C K P O L = 0 , C K E G = 1 )
S D O n (C K E G n = 0 )
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
S D O n (C K E G n = 1 )
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
S D In D a ta C a p tu re
W r ite to S IM n D R
SPI Master Mode Timing
S C S n
S C K n (C K P O L n = 1 )
S C K n (C K P O L n = 0 )
S D O n
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
S D In D a ta C a p tu re
W r ite to S IM n D R
( S D O n n o t c h a n g e u n til fir s t S C K n e d g e )
SPI Slave Mode Timing (CKEGn=0)
S C S n
S C K n (C K P O L n = 1 )
S C K n (C K P O L n = 0 )
S D O n
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
S D In D a ta C a p tu re
W r ite to S IM n D R
( S D O n c h a n g e a s s o o n a s w r itin g o c c u r ; S D O n = flo a tin g if S C S n = 1 )
N o te : F o r S P I s la v e m o d e , if S IM n E N = 1 a n d C S E N = 0 , S P I is a lw a y s e n a b le d
a n d ig n o r e th e S C S n le v e l.
SPI Slave Mode Timing (CKEGn=1)
Rev. 1.00
76
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
A
S P I tra n s fe r
W r ite D a ta
in to S IM n D R
C le a r W C O L n
M a s te r
S la v e
m a s te r o r
s la v e
Y
S n S IM [2 :0 ]= 0 0 0 ,
0 0 1 ,0 1 0 ,0 1 1 o r 1 0 0
W C O L n = 1 ?
N
S IM n [2 :0 ]= 1 0 1
N
c o n fig u r e
C S E N n a n d M L S n
T r a n s m is s io n
c o m p le te d ?
(T R F n = 1 ? )
Y
S IM n E N = 1
R e a d D a ta
fro m S IM n D R
A
C le a r T R F n
T ra n s fe r
F in is h e d ?
N
Y
E N D
SPI Transfer Control Flowchart
·
Rev. 1.00
SIMn0~SIMn2
These bits setup the overall operating mode of the SIMn function. As well as selecting if the I2C or
SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock
frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from
the Timer/Event Counter 0. If the SPI Slave Mode is selected then the clock will be supplied by an
external Master device.
SPI Master/Slave Clock Control and I2C Enable
SIMn_0
SIMn_1
SIMn_2
0
0
0
SPI Master, fSYS/4
0
0
1
SPI Master, fSYS/16
0
1
0
SPI Master, fSYS/64
0
1
1
SPI Master, fSUB
1
0
0
SPI Master Timer/Event Counter 0 overflow/2
1
0
1
SPI Slave
1
1
0
I2C mode
1
1
1
Not used
77
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
SPI Control Register - SIMnCTL2
2
The SIMnCTL2 register is also used by the I C interface but has the name SIMnAR.
Rev. 1.00
·
TRFn
The TRFn bit is the Transmit/Receive Complete flag and is set high automatically when an SPI data
transmission is completed, but must be cleared by the application program. It can be used to generate
an interrupt.
·
WCOLn
The WCOLn bit is used to detect if a data collision has occurred. If this bit is high it means that data
has been attempted to be written to the SIMnDR register during a data transfer operation. This
writing operation will be ignored if data is being transferred. The bit can be cleared by the
application program. Note that using the WCOLn bit can be disabled or enabled via configuration
option.
·
CSENn
The CSENn bit is used as an on/off control for the SCSn pin. If this bit is low then the SCSn pin will
be disabled and placed into a floating condition. If the bit is high the SCSnB pin will be enabled and
used as a select pin. Note that using the CSENn bit can be disabled or enabled via configuration
option.
·
MLS
This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB
first. Setting the bit high will select MSB first and low for LSB first.
·
CKEGn and CKPOLn
These two bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus.
These two bits must be configured before data transfer is executed otherwise an erroneous clock
edge may be generated. The CKPOLn bit determines the base condition of the clock line, if the bit is
high then the SCKn line will be low when the clock is inactive. When the CKPOLn bit is low then
the SCKn line will be high when the clock is inactive. The CKEGn bit determines active clock edge
type which depends upon the condition of CKPOLn.
CKPOLn
CKEGn
SCKn Clock Signal
0
0
High Base Level Active Rising Edge
0
1
High Base Level Active Falling Edge
1
0
Low Base Level Active Falling Edge
1
1
Low Base Level Active Rising Edge
78
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
SPI Communication
After the SPI interface is enabled by setting the SIMnEN bit high, then in the Master Mode, when data
is written to the SIMnDR register, transmission/reception will begin simultaneously. When the data
transfer is complete, the TRFn flag will be set automatically, but must be cleared using the application
program. In the Slave Mode, when the clock signal from the master has been received, any data in the
SIMnDR register will be transmitted and any data on the SDIn pin will be shifted into the SIMnDR
register. The master should output a SCSn signal to enable the slave device before a clock signal is
provided and slave data transfers should be enabled/disabled before/after an SCSn signal is received.
The SPI will continue to function even after a HALT instruction has been executed.
I2C Interface
2
The I C interface is used to communicate with external peripheral devices such as sensors, EEPROM
memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous
serial data transfer. The advantage of only two lines for communication, relatively simple
communication protocol and the ability to accommodate multiple devices on the same bus has made it
an extremely popular interface type for many applications.
I2C Interface Operation
2
The I C serial interface is a two line interface, a serial data line, , and serial clock line, SCLn. As many
devices may be connected together on the same bus, their outputs are both open drain types. For this
reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip
select line exists, as each device on the I2C bus is identified by a unique address which will be
transmitted and received on the I2C bus.
When two devices communicate with each other on the bidirectional I2C bus, one is known as the
master device and one as the slave device. Both master and slave can transmit and receive data,
however, it is the master device that has overall control of the bus. For these devices, which only
operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit
mode and the slave receive mode.
There are several configuration options associated with the I2C interface. One of these is to enable the
function which selects the SIMn pins rather than normal I/O pins. Note that if the configuration option
does not select the SIMn function then the SIMnEN bit in the SIMnCTL0 register will have no effect.
A configuration option exists to allow a clock other than the system clock to drive the I2C interface.
Another configuration option determines the debounce time of the I2C interface. This uses the internal
clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the
clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 1 or
2 system clocks.
Configuration Option
SIMn function
2
I C debounce
Function
SIMn interface or I/O pins
No debounce, 1 system clock; 2 system clocks
I2C Interface Configuration Options
Rev. 1.00
79
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
D a ta B u s
I2C
H T X n B it
S C L n P in
S D A n P in
M
X
S la v e A d d r e s s R e g is te r
(S IM n A R )
A d d re s s
C o m p a ra to r
D ir e c tio n C o n tr o l
D a ta in L S B
D a ta O u t M S B
U
D a ta R e g is te r
(S IM n D R )
S h ift R e g is te r
R e a d /w r ite S la v e
A d d re s s M a tc h
H A A S n B it
I2C
In te rru p t
S R W n B it
E n a b le /D is a b le A c k n o w le d g e
T r a n s m it/R e c e iv e
C o n tr o l U n it
8 - b it D a ta C o m p le te
D e te c t S ta rt o r S to p
H C F n B it
H B B n B it
I2C Block Diagram
I2C Registers
2
There are three control registers associated with the I C bus, SIMnCTL0, SIMnCTL1 and SIMnAR
and one data register, SIMnDR. The SIMnDR register, which is shown in the above SPI section, is
used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes
data to the I2C bus, the actual data to be transmitted must be placed in the SIMnDR register. After the
data is received from the I2C bus, the microcontroller can read it from the SIMnDR register. Any
transmission or reception of data from the I2C bus must be made via the SIMnDR register. Note that the
SIMnAR register also has the name SIMnCTL2 which is used by the SPI function. Bits SIMIDLE,
SIMnEN and bits SnSIM2~SnSIM0 in registers SIMnCTL0 and CLKMOD are used by the I2C
interface. The SIMnCTL0 register is shown in the above SPI section.
Rev. 1.00
·
SIMIDLE
When the device is in the IDLE mode, the SIMIDLE bit has no effect if the I2C interface is selected to
be used. Setting the bit high only allows the clock source of the Peripheral clock PCLK, which is
selected to come from the divided system clock, to keep active when the device is in the IDLE mode.
It will maintain the Peripheral clock PCLK output active if the PCKEN bit is set to 1 in IDLE mode.
Clearing the bit to zero disables the PCLK output when the device is in the IDLE mode. This SPI/I2C
IDLE mode control bit SIMIDLE is located at CLKMOD register bit4.
·
SIMnEN
The SIMnEN bit is the overall on/off control for the I2C interface. When the SIMnEN bit is cleared to
zero to disable the I2C interface, the SDAn and SCLn lines will be in a floating condition and the I2C
operating current will be reduced to a minimum value. In this condition the pins can be used as
normal I/O functions. When the bit is high the I2C interface is enabled. The SIMn configuration
option must have first enabled the SIMn interface for this bit to be effective. Note that when the
SIMnEN bit changes from low to high the contents of the I2C control registers will be in an unknown
condition and should therefore be first initialised by the application program.
·
SIMn_0~SIMn_2
These bits setup the overall operating mode of the SIMn function. To select the I2C function, bits
SIMn_2~SIMn_0 should be set to the value 110.
80
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
·
RXAKn
The RXAKn flag is the reception acknowledge flag. When the RXAKn bit has been reset to zero, it
means that a correct acknowledge signal has been received at the 9th clock, after 8 bits of data have
been transmitted. When in the transmit mode, the transmitter checks the RXAKn bit to determine if
the receiver wishes to receive the next byte. The transmitter will therefore continue sending out data
until the RXAKn bit is set high. When this occurs, the transmitter will release the SDAn line to allow
the master to send a STOP signal to release the bus.
·
SRWn
The SRWn bit is the Slave Read/Write bit. This bit determines whether the master device wishes to
transmit or receive data from the I2C bus. When the transmitted address and slave address match,
which is when the HAASn bit is set high, the device will check the SRWn bit to determine whether it
should be in transmit mode or receive mode. If the SRWn bit is high, the master is requesting to read
data from the bus, so the device should be in transmit mode. When the SRWn bit is zero, the master
will write data to the bus, therefore the device should be in receive mode to read this data.
·
TXAKn
The TXAKn flag is the transmission acknowledge flag. After the receipt of 8-bits of data, this bit will
be transmitted to the bus on the 9th clock. To continue receiving more data, this bit has to be reset to
zero before further data is received.
·
HTXn
The HTXn flag is the transmit/receive mode bit. This flag should be set high to set the transmit mode
and low for the receive mode.
·
HBBn
The HBBn flag is the I2C busy flag. This flag will be high when the I2C bus is busy which will occur
when a START signal is detected. The flag will be reset to zero when the bus is free which will occur
when a STOP signal is detected.
·
HAASn
The HAASn flag is the address match flag. This flag is used to determine if the slave device address
is the same as the master transmit address. If the addresses match then this bit will be high, if there is
no match then the flag will be low.
·
HCFn
The HCFn flag is the data transfer flag. This flag will be zero when data is being transferred. Upon
completion of an 8-bit data transfer the flag will go high and an interrupt will be generated.
I2C Address Register - SIMnAR
The SIMnAR register is also used by the SPI interface but has the name SIMnCTL2. The SIMnAR
register is the location where the 7-bit slave address of the microcontroller is stored. Bits 1~7 of the
SIMnAR register define the microcontroller slave address. Bit 0 is not defined. When a master device,
which is connected to the I2C bus, sends out an address, which matches the slave address in the
SIMnAR register, the microcontroller slave device will be selected. Note that the SIMnAR register is
the same register as SIMnCTL2 which is used by the SPI interface.
Rev. 1.00
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
I2C Bus Communication
2
Communication on the I C bus requires four separate steps, a START signal, a slave device address
transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C
bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the
bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the
address of the microcontroller matches that of the transmitted address, the HAASn bit in the
SIMnCTL1 register will be set and an I2C interrupt will be generated. After entering the interrupt
service routine, the microcontroller slave device must first check the condition of the HAASn bit to
determine whether the interrupt source originates from an address match or from the completion of an
8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted,
the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRWn bit.
This bit will be checked by the microcontroller to determine whether to go into transmit or receive
mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus.
The following are steps to achieve this:
Step 1
Write the slave address of the microcontroller to the I2C bus address register SIMnAR.
Step 2
Set the SIMnEN bit in the SIMnCTL0 register to ²1² to enable the I2C bus.
Step 3
Set the ESIMn bit of the interrupt control register to enable the I2C bus interrupt.
S ta rt
W r ite S la v e
A d d re s s to S IM n A R
S E T S n S IM [2 :0 ]= 1 1 0
S E T S IM n E N
D is a b le
I2C B u s
In te rru p t= ?
E n a b le
C L R E S IM n
P o ll S IM F n to d e c id e
w h e n to g o to I2C B u s IS R
S E T E S IM n
W a it fo r In te r r u p t
G o to M a in P r o g r a m
G o to M a in P r o g r a m
I2C Bus Initialisation Flow Chart
Rev. 1.00
82
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
S C L n
S R W
S la v e A d d r e s s
S ta rt
0
1
S D A n
1
1
0
1
0
1
D a ta
S C L n
1
0
0
1
A C K
0
A C K
0
1
0
S to p
0
S D A n
S = S
S A =
S R =
M = S
D = D
A = A
P = S
S
ta rt (1
S la v e
S R W
la v e d
a ta (8
C K (R
to p (1
S A
b it)
A d d r e s s ( 7 b its )
b it ( 1 b it)
e v ic e s e n d a c k n o w le d g e b it ( 1 b it)
b its )
X A K b it fo r tr a n s m itte r , T X A K b it fo r r e c e iv e r 1 b it)
b it)
S R
M
D
A
D
A
S
S A
S R
M
D
A
D
A
P
I2C Communication Timing Diagram
S ta rt
N o
N o
Y e s
H A A S n = 1
?
Y e s
Y e s
H T X n = 1
?
S R W n = 1
?
N o
R e a d fro m
S IM n D R
S E T H T X n
C L R H T X n
C L R T X A K n
R E T I
W r ite to
S IM n D R
D u m m y R e a d
F ro m S IM n D R
R E T I
R E T I
Y e s
R X A K n = 1
?
N o
C L R H T X n
C L R T X A K n
W r ite to
S IM n D R
D u m m y R e a d
fro m S IM n D R
R E T I
R E T I
I2C Bus ISR Flow Chart
Rev. 1.00
83
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
·
Start Signal
The START signal can only be generated by the master device connected to the I2C bus and not by
the microcontroller, which is only a slave device. This START signal will be detected by all devices
connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the
HBBn bit will be set. A START condition occurs when a high to low transition on the SDAn line
takes place when the SCLn line remains high.
·
Slave Address
The transmission of a START signal by the master will be detected by all devices on the I2C bus. To
determine which slave device the master wishes to communicate with, the address of the slave
device will be sent out immediately following the START signal. All slave devices, after receiving
this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by
the master matches the internal address of the microcontroller slave device, then an internal I2C bus
interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the
read/write status and will be saved to the SRWn bit of the SIMnCTL1 register. The device will then
transmit an acknowledge bit, which is a low level, as the 9th bit.
The microcontroller slave device will also set the status flag HAASn when the addresses match. As
an I2C bus interrupt can come from two sources, when the program enters the interrupt subroutine,
the HAASn bit should be examined to see whether the interrupt source has come from a matching
slave address or from the completion of a data byte transfer. When a slave address is matched, the
device must be placed in either the transmit mode and then write data to the SIMnDR register, or in
the receive mode where it must implement a dummy read from the SIMnDR register to release the
SCLn line.
SIMnAR Register
Bit
7
6
5
4
3
2
1
0
Name
SnA6
SnA5
SnA4
SnA3
SnA2
SnA1
SnA0
¾
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
¾
POR
x
x
x
x
x
x
x
¾
²x² means unknown.
Bit 7~1
Bit 0
Rev. 1.00
2
SnA6~SnA0: I C slave address
2
SnA6~SnA0 is the I C slave address bit6~bit0.
The SIMnAR register is also used by the SPI interface but has the name SIMnCTL2. The
SIMnAR register is the location where the 7-bit slave address of the slave device is stored.
Bit7~bit1 of the SIMnAR register define the device slave address. Bit 0 is not defined.
2
When a master device, which is connected to the I C bus, sends out an address, which matches
the slave address in the SIMnAR register, the slave device will be selected. Note that the
SIMnAR register is the same register address as SIMnCTL2 which is used by the SPI interface.
Unimplemented bit.
This bit can be read or written by user software program.
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December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
·
SRW Bit
The SRWn bit in the SIMnCTL1 register defines whether the microcontroller slave device wishes to
read data from the I2C bus or write data to the I2C bus. The microcontroller should examine this bit to
determine if it is to be a transmitter or a receiver. If the SRWn bit is set to ²1² then this indicates that
the master wishes to read data from the I2C bus, therefore the microcontroller slave device must be
setup to send data to the I2C bus as a transmitter. If the SRWn bit is ²0² then this indicates that the
master wishes to send data to the I2C bus, therefore the microcontroller slave device must be setup to
read data from the I2C bus as a receiver.
·
Acknowledge Bit
After the master has transmitted a calling address, any slave device on the I2C bus, whose own
internal address matches the calling address, must generate an acknowledge signal. This
acknowledge signal will inform the master that a slave device has accepted its calling address. If no
acknowledge signal is received by the master then a STOP signal must be transmitted by the master
to end the communication. When the HAASn bit is high, the addresses have matched and the
microcontroller slave device must check the SRWn bit to determine if it is to be a transmitter or a
receiver. If the SRWn bit is high, the microcontroller slave device should be setup to be a transmitter
so the HTXn bit in the SIMnCTL1 register should be set to ²1² if the SRWn bit is low then the
microcontroller slave device should be setup as a receiver and the HTXn bit in the SIMnCTL1
register should be set to ²0².
·
Data Byte
The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged
receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last.
After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level ²0², before it
can receive the next data byte. If the transmitter does not receive an acknowledge bit signal from the
receiver, then it will release the SDAn line and the master will send out a STOP signal to release
control of the I2C bus. The corresponding data will be stored in the SIMnDR register. If setup as a
transmitter, the microcontroller slave device must first write the data to be transmitted into the
SIMnDR register. If setup as a receiver, the microcontroller slave device must read the transmitted
data from the SIMnDR register.
·
Receive Acknowledge Bit
When the receiver wishes to continue to receive the next data byte, it must generate an acknowledge
bit, known as TXAKn, on the 9th clock. The microcontroller slave device, which is setup as a
transmitter will check the RXAKn bit in the SIMnCTL1 register to determine if it is to send another
data byte, if not then it will release the SDAn line and await the receipt of a STOP signal from the
master.
S C L n
S D A n
S ta r t b it
D a ta
s ta b le
D a ta
a llo w
c h a n g e
S to p b it
Data Timing Diagram
Rev. 1.00
85
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Peripheral Clock Output
The Peripheral Clock Output allows the device to supply external hardware with a clock signal
synchronised to the microcontroller clock.
Peripheral Clock Operation
As the peripheral clock output pin, PCLK, is shared with an I/O line, the required pin function is
chosen via PCKEN in the SIM0CTL0 register. The Peripheral Clock function is controlled using the
SIM0CTL0 register. The clock source for the Peripheral Clock Output can originate from either the
Timer/Event Counter 0 overflow signal divided by two or a divided ratio of the internal fSYS clock.
The PCKEN bit in the SIM0CTL0 register is the overall on/off control, setting the bit high enables the
Peripheral Clock, clearing it disables it. The required division ratio of the system clock is selected
using the PCKPSC0 and PCKPSC1 bits in the same register. If the system enters the Sleep Mode, the
Peripheral Clock output will be disabled.
P C K P S C 0
fS
Y S
P C K P S C 1
P C K E N
¸ 1 , 4 , 8
T im e r /E v e n t C o u n te r 0
o v e r flo w s ig n a l ¸ 2
P C L K
o r I/O
S e le c t
P C L K
o r
I/O
S le e p M o d e
Peripheral Clock Block Diagram
Rev. 1.00
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December 2, 2011
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Buzzer
Operating in a similar way to the Programmable Frequency Divider, the Buzzer function provides a
means of producing a variable frequency output, suitable for applications such as Piezo-buzzer driving
or other external circuits that require a precise frequency generator. The BZ and BZ pins form a
complementary pair, and are pin-shared with I/O pins, PA0 and PA1. A configuration option is used to
select from one of three buzzer options. The first option is for both pins PA0 and PA1 to be used as
normal I/Os, the second option is for both pins to be configured as BZ and BZ buzzer pins, the third
option selects only the PA0 pin to be used as a BZ buzzer pin with the PA1 pin retaining its normal I/O
pin function. Note that the BZ pin is the inverse of the BZ pin which together generate a differential
output which can supply more power to connected interfaces such as buzzers.
The buzzer is driven by the internal clock source, which then passes through a divider, the division
ratio of which is selected by configuration options to provide a range of buzzer frequencies from fS/22
9
to fS/2 . The clock source that generates fS, which in turn controls the buzzer frequency, can originate
from three different sources, the external 32.768kHz oscillator (LXT), the internal 32kHz RC
oscillator (LIRC) or the System oscillator divided by 4 (fSYS/4), the choice of which is determined by
the fS clock source configuration option. Note that the buzzer frequency is controlled by configuration
options, which select both the source clock for the internal clock fS and the internal division ratio.
There are no internal registers associated with the buzzer frequency.
If the configuration options have selected both pins PA0 and PA1 to function as a BZ and BZ
complementary pair of buzzer outputs, then for correct buzzer operation it is essential that both pins
must be setup as outputs by setting bits PAC0 and PAC1 of the PAC port control register to zero. The
PA0 data bit in the PA data register must also be set high to enable the buzzer outputs, if set low, both
pins PA0 and PA1 will remain low. In this way the single bit PA0 of the PA register can be used as an
on/off control for both the BZ and BZ buzzer pin outputs. Note that the PA1 data bit in the PA register
has no control over the BZ buzzer pin PA1.
fS
Y S
/4
fL
X T
fL
IR C
fS S o u rc e
C o n fig u r a tio n
O p tio n
fS
C o n fig u r a tio n O p tio n
D iv id e b y 2 2 ~ 2 9
B Z
B Z
Buzzer Function
PA0/PA1 Pin Function Control
PAC Register
PAC0
PAC Register
PAC1
PA Data Register
PA0
PA Data Register
PA1
Output
Function
0
0
1
x
PA0=BZ
PA1=BZ
0
0
0
x
PA0=²0²
PA1=²0²
0
1
1
x
PA0=BZ
PA1=input line
0
1
0
x
PA0=²0²
PA1=input line
1
0
x
D
PA0=input line
PA1=D
1
1
x
x
PA0=input line
PA0=input line
²x² stands for don¢t care
²D² stands for Data ²0² or ²1²
Rev. 1.00
87
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
If configuration options have selected that only the PA0 pin is to function as a BZ buzzer pin, then the
PA1 pin can be used as a normal I/O pin. For the PA0 pin to function as a BZ buzzer pin, PA0 must be
setup as an output by setting bit PAC0 of the PAC port control register to zero. The PA0 data bit in the
PA data register must also be set high to enable the buzzer output, if set low pin PA0 will remain low. In
this way the PA0 bit can be used as an on/off control for the BZ buzzer pin PA0. If the PAC0 bit of the
PAC port control register is set high, then pin PA0 can still be used as an input even though the
configuration option has configured it as a BZ buzzer output.
In te r n a l C lo c k S o u r c e
P A 0 D a ta
B Z O u tp u t a t P A 0
P A 1 D a ta
B Z O u tp u t a t P A 1
Buzzer Output Pin Control
Note:
The above drawing shows the situation where both pins PA0 and PA1 are selected by configuration option to
be BZ and BZ buzzer pin outputs. The Port Control Register of both pins must have already been setup as
output. The data setup on pin PA1 has no effect on the buzzer outputs.
Note that no matter what configuration option is chosen for the buzzer, if the port control register has
setup the pin to function as an input, then this will override the configuration option selection and force
the pin to always behave as an input pin. This arrangement enables the pin to be used as both a buzzer
pin and as an input pin, so regardless of the configuration option chosen; the actual function of the pin
can be changed dynamically by the application program by programming the appropriate port control
register bit.
Rev. 1.00
88
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an internal
function such as a Timer/Event Counter or an A/D converter requires microcontroller attention, their
corresponding interrupt will enforce a temporary suspension of the main program allowing the
microcontroller to direct attention to their respective needs. The device contains several external
interrupt and internal interrupts functions. The external interrupts are controlled by the action of the
external INT0, INT1 and PINT pins, while the internal interrupts are controlled by the Timer/Event
Counter overflows, the Time Base interrupt, the RTC interrupt, the SIM (SPI/I2C) interrupt, the A/D
converter interrupt, the USB interrupt and Smart Card interrupt.
A u to m a tic a lly D is a b le d b y IS R
C a n b e E n a b le d M a n u a lly
A u to m a tic a lly C le a r e d b y IS R
P r io r ity
S m a rt C a rd In te rru p t
R e q u e s t F la g C R D F
C R D E
U S B In te rru p t
R e q u e s t F la g U S B F
U S B E
E x te rn a l In te rru p t
R e q u e s t F la g E IF 0
E E I0
E x te rn a l In te rru p t
R e q u e s t F la g E IF 1
E M I
H ig h
E E I1
T im e r /E v e n t C o u n te r 0
In te r r u p t R e q u e s t F la g T 0 F
E T 0 I
T im e r /E v e n t C o u n te r 1
In te r r u p t R e q u e s t F la g T 1 F
E T 1 I
S m a r t C a r d In s e r tio n /R e m o v a l
In te r r u p t R e q u e s t F la g C R D F
C IR E
A /D C o n v e rte r
In te r r u p t R e q u e s t F la g A D F
E A D I
In te rru p t
P o llin g
M u lti- fu n c tio n 0
In te r r u p t R e q u e s t F la g M F 0 F
E M F 0 I
M u lti- fu n c tio n 1
In te r r u p t R e q u e s t F la g M F 1 F
E M F 1 I
S IM 0 (S P I/I2C )
In te r r u p t R e q u e s t F la g S IM 0 F
E S IM 0
R e a l T im e C lo c k
In te r r u p t R e q u e s t F la g R T F
E R T I
T im e B a s e
In te r r u p t R e q u e s t F la g T B F
E T B I
E x te r n a l P e r ip h e r a l
In te r r u p t R e q u e s t F la g P E F
E P I
S IM 1 (S P I/I2C )
In te r r u p t R e q u e s t F la g S IM 1 F
E S IM 1
T im e r /E v e n t C o u n te r 2
In te r r u p t R e q u e s t F la g T 2 F
E T 2 I
T im e r /E v e n t C o u n te r 3
In te r r u p t R e q u e s t F la g T 3 F
E T 3 I
L o w
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
Interrupt Structure
Rev. 1.00
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Interrupt Registers
Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by the
INTC0, INTC1, INTC2, MFIC0 and MFIC1 registers, which are located in the Data Memory. By
controlling the appropriate enable bits in these registers each individual interrupt can be enabled or
disabled. Also when an interrupt occurs, the corresponding request flag will be set by the
microcontroller. The global enable flag if cleared to zero will disable all interrupts.
INTC0 Register
Bit
7
6
5
4
3
2
1
0
Name
¾
EIF0
USBF
CRDF
EEI0
USBE
CRDE
EMI
R/W
¾
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
¾
0
0
0
0
0
0
0
Bit 7
Bit 6
unimplemented, read as ²0²
EIF0: External interrupt 0 interrupt request flag
0: inactive
1: active
Bit 5
USBF: USB interrupt request flag
0: inactive
1: active
Bit 4
CRDF: Smart Card interrupt request flag
0: inactive
1: active
EEI0: External interrupt 0 enable
0: disable
1: enable
USBE: USB interrupt enable
0: disable
1: enable
CRDE: Smart Card interrupt enable
0: disable
1: enable
EMI: Master interrupt global enable
0: disable
1: enable
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
INTC1 Register
Bit
7
6
5
4
3
2
1
0
Name
CIRF
T1F
T0F
EIF1
CIRE
ET1I
ET0I
EEI1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
CIRF: Smart Card Insertion/Removal interrupt request flag
0: inactive
1: active
T1F: Timer/Event Counter 1 interrupt request flag
0: inactive
1: active
T0F: Timer/Event Counter 0 interrupt request flag
0: inactive
1: active
EIF1: External interrupt 1 request flag
0: inactive
1: active
CIRE: Smart Card Insertion/Removal interrupt enable
0: disable
1: enable
ET1I: Timer/Event Counter 1 interrupt enable
0: disable
1: enable
ET0I: Timer/Event Counter 0 interrupt enable
0: disable
1: enable
EEI1: External interrupt 1 interrupt enable
0: disable
1: enable
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTC2 Register
Bit
7
6
5
4
3
2
1
0
Name
¾
MF1F
MF0F
ADF
¾
EMF1I
EMF0I
EADI
R/W
¾
R/W
R/W
R/W
¾
R/W
R/W
R/W
POR
¾
0
0
0
¾
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
unimplemented, read as ²0²
MF1F: Multi-Function 1 interrupt request flag
0: inactive
1: active
MF0F: Multi-function 0 interrupt request flag
0: inactive
1: active
ADF: A/D Converter interrupt request flag
0: inactive
1: active
unimplemented, read as ²0²
EMF1I: Multi-Function 1 interrupt enable
0: disable
1: enable
EMF0I: Multi-Function 0 interrupt enable
0: disable
1: enable
EADI: A/D Converter interrupt enable
0: disable
1: enable
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
MFIC0 Register
Bit
7
6
5
4
3
2
1
0
Name
PEF
TBF
RTF
SIM0F
EPI
ETBI
ERTI
ESIM0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
PEF: External Peripheral interrupt request flag
0: inactive
1: active
TBF: Time Base interrupt request flag
0: inactive
1: active
RTF: Real Time Clock interrupt request flag
0: inactive
1: active
2
SIM0F: SIM 0 (SPI/I C) interrupt request flag
0: inactive
1: active
EPI: External Peripheral interrupt enable
0: disable
1: enable
ETBI: Time Base interrupt enable
0: disable
1: enable
ERTI: Real Time Clock interrupt enable
0: disable
1: enable
2
ESIM0: SIM 0 (SPI/I C) interrupt enable
0: disable
1: enable
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MFIC1 Register
Bit
7
6
5
4
3
2
1
0
Name
¾
T3F
T2F
SIM1F
¾
ET3I
ET2I
ESIM1
R/W
¾
R/W
R/W
R/W
¾
R/W
R/W
R/W
POR
¾
0
0
0
¾
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
unimplemented, read as ²0²
T3F: Timer/Event Counter 3 interrupt request flag
0: inactive
1: active
T2F: Timer/Event Counter 2 interrupt request flag
0: inactive
1: active
SIM1F: SIM 1 (SPI/I2C) interrupt request flag
0: inactive
1: active
unimplemented, read as ²0²
ET3I: Timer/Event Counter 3 interrupt enable
0: disable
1: enable
ET2I: Timer/Event Counter 2 interrupt enable
0: disable
1: enable
ESIM1: SIM 1 (SPI/I2C) interrupt enable
0: disable
1: enable
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December 2, 2011
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Interrupt Operation
A Timer/Event Counter overflow, Time Base, RTC overflow, SPI/I2C data transfer complete, an end
of A/D conversion, USB event, Smart Card event, Smart Card insertion/removal or the external
interrupt line being triggered will all generate an interrupt request by setting their corresponding
request flag. When this happens and if their appropriate interrupt enable bit is set, the Program
Counter, which stores the address of the next instruction to be executed, will be transferred onto the
stack. The Program Counter will then be loaded with a new address which will be the value of the
corresponding interrupt vector. The microcontroller will then fetch its next instruction from this
interrupt vector. The instruction at this vector will usually be a JMP statement which will jump to
another section of program which is known as the interrupt service routine. Here is located the code to
control the appropriate interrupt. The interrupt service routine must be terminated with a RETI
statement, which retrieves the original Program Counter address from the stack and allows the
microcontroller to continue with normal execution at the point where the interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
accompanying diagram with their order of priority.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be
cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other
interrupt requests occur during this interval, although the interrupt will not be immediately serviced,
the request flag will still be recorded. If an interrupt requires immediate servicing while the program is
already in another interrupt service routine, the EMI bit should be set after entering the routine, to
allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the
stack must be prevented from becoming full.
Interrupt Priority
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of
simultaneous requests, the following table shows the priority that is applied.
Interrupt Source
Priority
Vector
Smart Card Interrupt
1
04H
USB Interrupt
2
08H
External Interrupt 0
3
0CH
External Interrupt 1
4
10H
Timer/Event Counter 0 Overflow
5
14H
Timer/Event Counter 1 Overflow
6
18H
Smart Card Insertion/Removal Interrupt
7
1CH
A/D Converter Interrupt
8
20H
Multi-function 0 Interrupt
9
24H
Multi-function 1 Interrupt
10
28H
The SIM0 interrupt, Real Time clock interrupt, Time Base interrupt and External Peripheral interrupt share the same interrupt vector which is 24H while the SIM1 interrupt, Timer/Event Counter 2
overflow and Timer/Event Counter 3 overflow interrupt share the same interrupt vector which is
28H. Each of these interrupts has their own individual interrupt flag but also share the same
multi-function interrupt flag named MF0F or MF1F respectively. The MF0F or MF1F flag will be
cleared by hardware once the corresponding Multi-function interrupt is serviced. However the individual interrupts that have triggered the Multi-function interrupt need to be cleared by the application program.
Rev. 1.00
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
External Interrupt
For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable
bits, EEI0 and EEI1, must first be set. Additionally the correct interrupt edge type must be selected
using the MISC0 register to enable the external interrupt function and to choose the trigger edge type.
An actual external interrupt will take place when the external interrupt request flag, EIF0 or EIF1, is
set, a situation that will occur when a transition, whose type is chosen by the edge select bit, appears on
the INT0 or INT1 pin. The external interrupt pins are pin-shared with the I/O pins PA0 and PA1 and
can only be configured as external interrupt pins if their corresponding external interrupt enable bit in
the INTC0 or INTC1 register has been set. The pin must also be setup as an input by setting the
corresponding PAC.0 and PAC.1 bits in the port control register. When the interrupt is enabled, the
stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to
the external interrupt vector at location 0CH or 10H, will take place. When the interrupt is serviced, the
external interrupt request flags, EIF0 or EIF1, will be automatically reset and the EMI bit will be
automatically cleared to disable other interrupts. Note that any pull-high resistor selections on this pin
will remain valid even if the pin is used as an external interrupt input.
The MISC0 register is used to select the type of active edge that will trigger the external interrupt. A
choice of either rising, falling or both rising and falling edge types can be chosen to trigger an external
interrupt. Note that the MISC0 register can also be used to disable the external interrupt function.
The external interrupt pins are connected to an internal filter to reduce the possibility of unwanted external
interrupts due to adverse noise or spikes on the external interrupt input signal. As this internal filter circuit
will consume a limited amount of power, the software control bits named INT0FLT and INT1FLT
respectively in the RCFLT register are provided to switch off the filter function, an option which may be
beneficial in power sensitive applications, but in which the integrity of the input signal is high.
M C U
F ilte r O n /O ff
C o n tro l IN T n F L T
IN T 0
F ilte r
E x te rn a l IN T .0
IN T 1
F ilte r
E x te rn a l IN T .1
MISC0 Register
Bit
Name
7
6
4
3
2
1
0
SMF
SMCEN
INT1S1
INT1S0
INT0S1
INT0S0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Bit 5
Bit 4
Rev. 1.00
CRDCKS1 CRDCKS0
5
CRDCKS1~CRDCKS0: Smart Card interface clock source divided ratio selection
00: fCRD = fM/2
01: fCRD = fM/3
10: fCRD = fM/1
11: fCRD = fM/4
SMF: Smart Card clock output CCLK frequency fCCLK selection
0: fCCLK = fCRD/1
1: fCCLK = fCRD/2
SMCEN: Smart Card interface clock control
0: fCRD is disabled
1: fCRD is enabled
This bit is used to control the Smart Card interface clock source. If this bit is cleared to disable
the clock, the relevant registers in the Smart Card interface module can not be accessed but will
keep the original contents. When the Smart Card interface clock is disabled, it has no effect on
the Card insertion or removal detections.
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Bit 3~2
Bit 1~0
INT1S1~INT1S0: External Interrupt 1 active edge selection
00: disabled
01: rising edge trigger
10: falling edge trigger
11: both rising and falling edges trigger
INT0S1~INT0S0: External Interrupt 0 active edge selection
00: disabled
01: rising edge trigger
10: falling edge trigger
11: both rising and falling edges trigger
External Peripheral Interrupt
The External Peripheral Interrupt operates in a similar way to the external interrupt and is contained
within the Multi-function 0 interrupt.
For an external peripheral interrupt to occur, the global interrupt enable bit, EMI, external peripheral
interrupt enable bit, EPI, and Multi-function 0 interrupt enable bit, EMF0I, must first be set. An actual
external peripheral interrupt will take place when the external interrupt request flag, PEF, is set, a
situation that will occur when a negative transition, appears on the PINT pin. The external peripheral
interrupt pin is pin-shared with one of the I/O pins, and is configured as a peripheral interrupt pin via
the corresponding port control register bit. When the interrupt is enabled, the stack is not full and a
negative transition type appears on the external peripheral interrupt pin, a subroutine call to the
Multi-function interrupt vector at location 24H, will take place. When the external peripheral interrupt
is serviced, the EMI bit will be cleared to disable other interrupts, however only the MF0F interrupt
request flag will be reset. As the PEF flag will not be automatically reset, it has to be cleared by the
application program.
Timer/Event Counter Interrupt
For a Timer/Event Counter 0 or Timer/Event Counter 1 interrupt to occur, the global interrupt enable
bit, EMI, and the corresponding timer interrupt enable bit, ET0I or ET1I must first be set. An actual
Timer/Event Counter interrupt will take place when the Timer/Event Counter request flag, T0F or T1F
is set, a situation that will occur when the Timer/Event Counter overflows. When the interrupt is
enabled, the stack is not full and a Timer/Event Counter overflow occurs, a subroutine call to the timer
interrupt vector at location 14H or 18H, will take place. When the interrupt is serviced, the timer
interrupt request flag, T0F or T1F, will be automatically reset and the EMI bit will be automatically
cleared to disable other interrupts.
Timer Event Counter 0 and Timer/Event Counter 1 have their own individual interrupt vectors.
However the interrupt vector for Timer/Event Counter 2 or Timer/Event counter 3 is contained within
the Multi-function 1 Interrupt. For a Timer/Event Counter 2 or a Timer/Event counter 3 interrupt to
occur, the global interrupt enable bit, EMI, Timer/Event Counter 2 or Timer/Event counter 3 interrupt
enable bit, ET2I or ET3I, and Multi-function 1 interrupt enable bit, EMF1I, must first be set. An actual
interrupt will take place when the Timer/Event Counter 2 or Timer/Event counter 3 request flag, T2F
or T3F, is set, a situation that will occur when the Timer/Event Counter 2 or Timer/Event counter 3
overflows. When the interrupt is enabled, the stack is not full and the Timer/Event Counter 2 or
Timer/Event counter 3 overflows, a subroutine call to the Multi-function interrupt vector at location
28H, will take place. When the Timer/Event 2 or Timer/Event counter 3 interrupt is serviced, the EMI
bit will be cleared to disable other interrupts, however only the MF1F interrupt request flag will be
reset. As the T2F or T3F flag will not be automatically reset, it has to be cleared by the application
program.
Rev. 1.00
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
A/D Interrupt
For an A/D Interrupt to be generated, the global interrupt enable bit EMI and the A/D Interrupt enable
bit EADI must first be set. An actual A/D Interrupt will take place when the A/D Interrupt request flag,
ADF, is set, a situation that will occur when the A/D conversion process has finished. When the
interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to
the A/D interrupt vector at location 20H, will take place. When the A/D Interrupt is serviced, the A/D
interrupt request flag ADF will be automatically reset and the EMI bit will be automatically cleared to
disable other interrupts.
Smart Card Interrupt
For a Smart Card Interrupt to be generated, the global interrupt enable bit EMI must first be set as well
as one of the associated Smart Card event Interrupt enable bits. The Smart Card events that will
generate an interrupt include situations such as a Card voltage error, a Card current overload, a waiting
timer overflow, a parity error, a transmit buffer empty or an end of transmission or reception. Once one
of the associated Smart Card event interrupt enable control bits is set, it will automatically set the
CRDE bit to 1 to enable the related Smart Card interrupt. An actual Smart Card Interrupt will take
place when the Smart Card Interrupt request flag, CRDF, is set, a situation that will occur when a Smart
Card event has occurred. When the interrupt is enabled, the stack is not full and a Smart Card event has
occurred, a subroutine call to the Smart Card interrupt vector at location 04H, will take place. When
the Smart Card Interrupt is serviced, the Smart Card interrupt request flag CRDF will be automatically
reset and the EMI bit will be automatically cleared to disable other interrupts.
Smart Card Insertion/Removal Interrupt
For a Smart Card Insertion/Removal Interrupt to be generated, the global interrupt enable bit EMI and
the Smart Card Insertion/Removal interrupt enable bit CIRE must first be set. An actual Smart Card
Insertion/Removal Interrupt will take place when the Smart Card Insertion/Removal Interrupt request
flag, CIRF, is set, a situation that will occur when the Smart Card has been inserted or removed. When
the interrupt is enabled, the stack is not full and the Smart Card has been inserted or removed, a
subroutine call to the Smart Card Insertion/Removal Interrupt vector at location 1CH, will take place.
When the Smart Card Insertion/Removal Interrupt is serviced, the Smart Card Insertion/Removal
interrupt request flag CIRF will be automatically reset and the EMI bit will be automatically cleared to
disable other interrupts.
SIM (SPI/I2C Interface) Interrupts
2
The two SIM (SPI/I C ) interrupts named SIM0 interrupt and SIM1 interrupt are contained within the
Multi-function 0 Interrupt and Multi-function 1 Interrupt respectively.
For an SIM (SPI/I2C interface) interrupt to occur, the global interrupt enable bit named EMI, the
associated SIM interrupt enable control bit named ESIM0 or ESIM1 and the Multi-function interrupt
enable bit named EMF0I or EMF1I must be first set. An actual SIM (SPI/I2C interface) interrupt will
take place when the SIM (SPI/I2C interface) request flag, SIM0F or SIM1F, is set, a situation that will
occur when a byte of data has been transmitted or received by the SPI/I2C interface or when an I2C
address match occurs. When the interrupt is enabled, the stack is not full and a byte of data has been
transmitted or received by the SPI/I2C interface or an I2C address match occurs, a subroutine call to the
SIM (SPI/I2C interface) interrupt vector at location 24H or 28H respectively, will take place. When
SIM the interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts,
however only the MF0F or MF1F interrupt request flag will be reset. As the SIM request flag known as
SIM0F or SIM1F will not be automatically reset, it has to be cleared by the application program.
Rev. 1.00
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Multi-function Interrupt
Two additional interrupts known as the Multi-function 0 interrupt and Multi-function 1 interrupt are
provided. Unlike the other interrupts, the interrupt has no independent source, but rather is formed
from several other existing interrupt sources. The Multi-function 0 interrupt contains the SIM0
interrupt, Time Base interrupt, Real Time Clock interrupt, External Peripheral interrupt while the
Multi-function 1 interrupt contains the SIM1 interrupt, Timer 2 overflow interrupt and Timer 3
overflow interrupt.
For a Multi-function interrupt to occur, the global interrupt enable bit, EMI, and the Multi-function
interrupt enable bit, EMF0I or EMF1I, must first be set. An actual Multi-function interrupt will take
place when the Multi-function interrupt request flag, MF0F or MF1F, is set. This will occur when
either a Time Base overflow, a Real Time Clock overflow, SIM0 or SIM 1 interrupt, an External
Peripheral Interrupt, Timer 2 overflow interrupt or Timer 3 overflow interrupt is generated. When the
interrupt is enabled and the stack is not full, and either one of the interrupts contained within the
Multi-function interrupts occurs, a subroutine call to the Multi-function interrupt vector at location
24H or 28H respectively will take place. When the interrupt is serviced, the Multi-Function request
flag, MF0F or MF1F, will be automatically reset and the EMI bit will be automatically cleared to
disable other interrupts. However, it must be noted that the request flags from the original source of the
Multi-function interrupt, namely the Time-Base interrupt, Real Time Clock interrupt, SIM interrupts,
External Peripheral interrupt, Timer 2 overflow interrupt or Timer 3 overflow interrupt will not be
automatically reset and must be manually reset by the application program.
Real Time Clock Interrupt
The Real Time Clock Interrupt is contained within the Multi-function 0 Interrupt.
For a Real Time Clock interrupt to be generated, the global interrupt enable bit, EMI, Real Time Clock
interrupt enable bit, ERTI, and Multi-function 0 interrupt enable bit, EMF0I, must first be set. An
actual Real Time Clock interrupt will take place when the Real Time Clock request flag, RTF, is set, a
situation that will occur when the Real Time Clock overflows. When the interrupt is enabled, the stack
is not full and the Real Time Clock overflows, a subroutine call to the Multi-function 0 interrupt vector
at location 24H, will take place. When the Real Time Clock interrupt is serviced, the EMI bit will be
cleared to disable other interrupts, however only the MF0F interrupt request flag will be reset. As the
RTF flag will not be automatically reset, it has to be cleared by the application program.
Similar in operation to the Time Base interrupt, the purpose of the RTC interrupt is also to provide an
interrupt signal at fixed time periods. The RTC interrupt clock source originates from the internal clock
source fS. This fS input clock first passes through a divider, the division ratio of which is selected by
programming the appropriate bits in the RTCC register to obtain longer RTC interrupt periods whose
value ranges from 28/fS~215/fS. The clock source that generates fS, which in turn controls the RTC
interrupt period, can originate from three different sources, the 32.768kHz oscillator (LXT), the
internal 32kHz RC oscillator (LIRC) or the System oscillator divided by 4 (fSYS/4), the choice of which
is determine by the fS clock source configuration option.
fS
Y S
/4
L X T
L IR C
fS S o u rc e
C o n fig u r a tio n
O p tio n
fS
D iv id e b y 2 8 ~ 2
S e t b y R T C C
R e g is te r
R T 2
R T 1
1 5
R T C In te rru p t
2 12/fS ~ 2 15/fS
R T 0
RTC Interrupt
Rev. 1.00
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December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Note that the RTC interrupt period is controlled by both configuration options and an internal register
RTCC. A configuration option selects the source clock for the internal clock fS, and the RTCC register
bits RT2, RT1 and RT0 select the division ratio. Note that the actual division ratio can be programmed
from 28 to 215.
RTCC Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
LVDO
QOSC
LVDC
RT2
RT1
RT0
R/W
¾
¾
R
R/W
R/W
R/W
R/W
R/W
POR
¾
¾
0
0
0
1
1
1
Bit 7~6
Bit 5
unimplemented, read as ²0²
LVDO: Low Voltage Detector Output
0: normal voltage
1: low voltage detected
Bit 4
QOSC: RTC Oscillator Quick-start enable control
0: enable
1: disable
LVDC: Low Voltage Detector enable control
0: disable
1: enable
RT2~RT0: RTC Interrupt Period selection
8
000: 2 /fS
9
001: 2 /fS
10
010: 2 /fS
11
011: 2 /fS
12
100: 2 /fS
13
101: 2 /fS
14
110: 2 /fS
15
111: 2 /fS
Bit 3
Bit 2~0
Time Base Interrupt
The Time Base Interrupt is contained within the Multi-function 0 Interrupt.
For a Time Base Interrupt to be generated, the global interrupt enable bit, EMI, Time Base Interrupt
enable bit, ETBI, and Multi-function 0 interrupt enable bit, EMF0I, must first be set. An actual Time
Base Interrupt will take place when the Time Base Interrupt request flag, TBF, is set, a situation that
will occur when the Time Base overflows. When the interrupt is enabled, the stack is not full and the
Time Base overflows, a subroutine call to the Multi-function 0 interrupt vector at location 24H, will
take place. When the Time Base Interrupt is serviced, the EMI bit will be cleared to disable other
interrupts, however only the MF0F interrupt request flag will be reset. As the TBF flag will not be
automatically reset, it has to be cleared by the application program.
The purpose of the Time Base function is to provide an interrupt signal at fixed time periods. The Time
Base interrupt clock source originates from the Time Base interrupt clock source originates from the
internal clock source fS. This fS input clock first passes through a divider, the division ratio of which is
selected by configuration options to provide longer Time Base interrupt periods. The Time Base
interrupt time-out period ranges from 212/fS~215/fS. The clock source that generates fS, which in turn
controls the Time Base interrupt period, can originate from three different sources, the 32.768kHz
oscillator (LXT), the internal 32kHz RC oscillator (LIRC) or the System oscillator divided by 4
(fSYS/4), the choice of which is determine by the fS clock source configuration option.
Rev. 1.00
98
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Essentially operating as a programmable timer, when the Time Base overflows it will set a Time Base
interrupt flag which will in turn generate an Interrupt request via the Multi-function 0 Interrupt vector.
fS
Y S
/4
L X T
L IR C
fS S o u rc e
C o n fig u r a tio n
O p tio n
fS
C o n fig u r a tio n O p tio n
D iv id e b y 2 1 2 ~ 2 1 5
T im e B a s e In te r r u p t
2 12/fS ~ 2 15/fS
Time Base Interrupt
Programming Considerations
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced,
however, once an interrupt request flag is set, it will remain in this condition in the INTC0, INTC1,
INTC2, MFIC0 and MFIC1 registers until the corresponding interrupt is serviced or until the request
flag is cleared by the application program.
Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt
service routine is executed, as only the Multi-function interrupt request flags, will be automatically
cleared, the individual request flag for the function needs to be cleared by the application program.
It is recommended that programs do not use the ²CALL² instruction within the interrupt service
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If
only one stack is left and the interrupt is not well controlled, the original control sequence will be
damaged once a CALL subroutine is executed in the interrupt subroutine.
Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE
Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is
required to prevent a certain interrupt from waking up the micro controller then its respective request
flag should be first set high before entering the SLEEP or IDLE Mode.
As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the
contents of the accumulator, status register or other registers are altered by the interrupt service
program, their contents should be saved to the memory at the beginning of the interrupt service
routine. To return from an interrupt subroutine, either a ²RET² or ²RETI² instruction may be executed.
The ²RETI² instruction in addition to executing a return to the main program also automatically sets
the EMI bit high to allow further interrupts. The ²RET² instruction however only executes a return to
the main program leaving the EMI bit in its present zero state and therefore disabling the execution of
further interrupts.
Rev. 1.00
99
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside parameters. The most important reset condition
is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the
microcontroller, after a short delay, will be in a well defined state and ready to execute the first
program instruction. After this power-on reset, certain important internal registers will be set to
defined states before the program commences. One of these registers is the Program Counter, which
will be reset to zero forcing the microcontroller to begin program execution from the lowest Program
Memory address.
In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset
condition when the microcontroller is running. One example of this is where after power has been
applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a
case, known as a normal operation reset, some of the microcontroller registers remain unchanged
allowing the microcontroller to proceed with normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All
types of reset operations result in different register conditions being setup.
Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES
reset is implemented in situations where the power supply voltage falls below a certain threshold.
Reset Functions
There are five ways in which a microcontroller reset can occur, through events occurring both
internally and externally:
·
Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring that
all pins will be first set to inputs.
Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is
not fast enough or does not stabilise quickly at power-on, the internal reset function may be
incapable of providing proper reset operation. For this reason it is recommended that an external RC
network is connected to the RES pin, whose additional time delay will ensure that the RES pin
remains low for an extended period to allow the power supply to stabilise. During this time delay,
normal operation of the microcontroller will be inhibited. After the RES line reaches a certain
voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the
microcontroller will begin normal operation. The abbreviation SST in the figures stands for System
Start-up Timer.
V D D
0 .9 V
R E S
tR
D D
S T D
S S T T im e - o u t
C h ip R e s e t
Power-On Reset Timing Chart
For most applications a resistor connected between VDD and the RES pin and a capacitor connected
between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to
the RES pin should be kept as short as possible to minimise any stray noise interference.
For applications that operate within an environment where more noise is present the Enhanced Reset
Circuit shown is recommended.
Rev. 1.00
100
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
More information regarding external reset circuits is located in Application Note HA0075E on the
Holtek website.
V
D D
0 .0 1 m F * *
V D D
1 N 4 1 4 8 *
1 0 k W ~
1 0 0 k W
R E S /P C 7
3 0 0 W *
0 .1 ~ 1 m F
V S S
Note:
²*² It is recommended that this component is added for added ESD protection
²**² It is recommended that this component is added in environments where power line noise is significant
External RES Circuit
·
RES Pin Reset
This type of reset occurs when the microcontroller is already running and the RES pin is forcefully
pulled low by external hardware such as an external switch. In this case as in the case of other reset,
the Program Counter will reset to zero and program execution initiated from this point.
R E S
0 .4 V
0 .9 V
D D
D D
tR
S T D
S S T T im e - o u t
C h ip R e s e t
RES Reset Timing Chart
·
Low Voltage Reset - LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the
device, which is selected via a configuration option. If the supply voltage of the device drops to within a
range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the
device internally. The LVR includes the following specifications: For a valid LVR signal, a low voltage,
i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the
A.C. characteristics. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not
perform a reset function. One of a range of specified voltage values for VLVR can be selected using
configuration options. The VLVR value will be selected as a pair in conjunction with a Low Voltage Detect
value.
L V R
tR
S T D
S S T T im e - o u t
C h ip R e s e t
Low Voltage Reset Timing Chart
Rev. 1.00
101
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
·
Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset
except that the Watchdog time-out flag TO will be set to ²1².
W D T T im e - o u t
tR
S T D
S S T T im e - o u t
C h ip R e s e t
WDT Time-out Reset during Normal Operation
Timing Chart
·
Watchdog Time-out Reset during Power Down
The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most
of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be
cleared to ²0² and the TO flag will be set to ²1². Refer to the A.C. Characteristics for tSST details.
W D T T im e - o u t
tS
S T
S S T T im e - o u t
WDT Time-out Reset during Power Down
Timing Chart
Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known as
PDF and TO are located in the status register and are controlled by various microcontroller operations,
such as the Power Down function or Watchdog Timer. The reset flags are shown in the table:
TO
PDF
RESET Conditions
0
0
RES reset during power-on
u
u
RES or LVR reset during normal operation
1
u
WDT time-out reset during normal operation
1
1
WDT time-out reset during Power Down
Note: ²u² stands for unchanged
The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs.
Item
Rev. 1.00
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins counting
Timer/Event Counter
Timer Counter will be turned off
Prescaler
The Timer Counter Prescaler will be cleared
Input/Output Ports
I/O ports will be setup as inputs
Stack Pointer
Stack Pointer will point to the top of the stack
102
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To
ensure reliable continuation of normal program execution after a reset occurs, it is important to know
what condition the microcontroller is in after a particular reset occurs. The following table describes
how each type of reset affects each of the microcontroller internal registers.
Reset
(Power-on)
RES Reset
(Normal
Operation)
WDT Time-out
(Normal
Operation)
WDT Time-out
(HALT)
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu uuuu uuuu uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu uuuu uuuu uuuu uuuu
BP
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu uuuu uuuu uuuu uuuu
PCL
0000 0000 0000 0000
0000 0000
0000 0000 0000 0000 0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu uuuu uuuu uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu uuuu uuuu uuuu uuuu
RTCC
--00 0111 --00 0111
--00 0111
--uu uuuu --00 0111 --00 0111
STATUS
--00 xxxx
--uu uuuu
--1u uuuu
--11 uuuu --uu uuuu --01 uuuu
TBHP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu uuuu uuuu uuuu uuuu
MISC0
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
MISC1
0000 1010 0000 1010
0000 1010
uuuu uuuu 0000 1010 0000 1010
CLKMOD
0000 0x11 0000 0x11
0000 0x11
uuuu uuuu 0000 0x11 0000 0x11
Register
USB Reset
(Normal)
USB Reset
(HALT)
DC2DC
---- --00 ---- --00
---- --00
---- --uu ---- --00 ---- --00
INTC0
-000 0000 -000 0000
-000 0000
-uuu uuuu -000 0000 -000 0000
INTC1
-000 0000 -000 0000
-000 0000
-uuu uuuu -000 0000 -000 0000
INTC2
--00 --00 --00 --00
--00 --00
--uu --uu --00 --00 --00 --00
MFIC0
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
MFIC1
-000 -000 -000 -000
-000 -000
-uuu -uuu -000 -000 -000 -000
PAWU
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
PAPU
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
PA
1111 1111 1111 1111
1111 1111
uuuu uuuu 1111 1111 1111 1111
PAC
1111 1111 1111 1111
1111 1111
uuuu uuuu 1111 1111 1111 1111
PBPU
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
PB
1111 1111 1111 1111
1111 1111
uuuu uuuu 1111 1111 1111 1111
PBC
1111 1111 1111 1111
1111 1111
uuuu uuuu 1111 1111 1111 1111
PCPU
-000 0000 -000 0000
-000 0000
uuuu uuuu -000 0000 -000 0000
PC
1111 1111 1111 1111
1111 1111
uuuu uuuu 1111 1111 1111 1111
PCC
1111 1111 1111 1111
1111 1111
uuuu uuuu 1111 1111 1111 1111
PDPU
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
PD
1111 1111 1111 1111
1111 1111
uuuu uuuu 1111 1111 1111 1111
PDC
1111 1111 1111 1111
1111 1111
uuuu uuuu 1111 1111 1111 1111
PEPU
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
PE
1111 1111 1111 1111
1111 1111
uuuu uuuu 1111 1111 1111 1111
PEC
1111 1111 1111 1111
1111 1111
uuuu uuuu 1111 1111 1111 1111
PFPU
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
PF
1111 1111 1111 1111
1111 1111
uuuu uuuu 1111 1111 1111 1111
PFC
1111 1111 1111 1111
1111 1111
uuuu uuuu 1111 1111 1111 1111
PWM0L
0000 ---0 0000 ---0
0000 ---0
uuuu ---u 0000 ---0 0000 ---0
Rev. 1.00
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December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Register
Reset
(Power-on)
RES Reset
(Normal
Operation)
WDT Time-out
(Normal
Operation)
WDT Time-out
(HALT)
USB Reset
(Normal)
USB Reset
(HALT)
PWM0H
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
PWM1L
0000 ---0 0000 ---0
0000 ---0
uuuu ---u 0000 ---0 0000 ---0
PWM1H
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
PWM2L
0000 ---0 0000 ---0
0000 ---0
uuuu ---u 0000 ---0 0000 ---0
PWM2H
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
PWM3L
0000 ---0 0000 ---0
0000 ---0
uuuu ---u 0000 ---0 0000 ---0
PWM3H
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
00-0 1000 00-0 1000
00-0 1000
uu-u uuuu 00-0 1000 00-0 1000
TMR1H
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
TMR1C
0000 1--- 0000 1---
0000 1---
uuuu u--- 0000 1--- 0000 1---
TMR2
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR2C
00-0 1000 00-0 1000
00-0 1000
uu-u uuuu 00-0 1000 00-0 1000
TMR3
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR3C
00-0 1000 00-0 1000
00-0 1000
uu-u uuuu 00-0 1000 00-0 1000
LEDCTRL
-000 0000 -000 0000
-000 0000
-uuu uuuu -000 0000 -000 0000
LCDCTRL
0-00 0000 0-00 0000
0-00 0000
u-uu uuuu 0-00 0000 0-00 0000
LCDIO
---- -000 ---- -000
---- -000
---- -uuu ---- -000 ---- -000
RCFLT
--00 0000 --00 0000
--00 0000
--uu uuuu --00 0000 --00 0000
ADRL
xxxx ----
xxxx ----
xxxx ----
uuuu ----
xxxx ----
xxxx ----
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
ADRH
xxxx xxxx
ADCR
01 -- -000 01 -- -000
01 -- -000
uuu-
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--uu 01 -- -000 01 -- -000
ACSR
1100 0000 1100 0000
1100 0000
uuuu uuuu 1100 0000 1100 0000
ADPCR
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
SIM0CTL0
1110 000- 1110 000-
1110 000-
uuuu uuuu 1110 000- 1110 000-
SIM0CTL1
1000 0001 1000 0001
1000 0001
uuuu uu-u 1000 0001 1000 0001
SIM0DR
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
SIM0AR/SIM0CTL2
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
xxxx xxxx
xxxx xxxx
SIM1CTL0
1110 000- 1110 000-
1110 000-
uuuu uuuu 1110 000- 1110 000-
SIM1CTL1
1000 0001 1000 0001
1000 0001
uuuu uu-u 1000 0001 1000 0001
SIM1DR
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
SIM1AR/SIM1CTL2
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
DAL
0000 ---- 0000 ----
0000 ----
uuuu ---- 0000 ---- 0000 ----
DAH
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
DACTRL
xxx- ---0
xxx- ---0
xxx- ---0
uuu- ---u
CCR
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
CSR
1000 0000 1000 0000
1000 0000
uuuu uuuu 1000 0000 1000 0000
CCCR
00xx x0x0
00xx x0x0
00xx x0x0
uuxx xuxu
CETU1
0--- -001 0--- -001
0--- -001
u--- -uuu 0--- -001 0--- -001
CETU0
0111 0100 0111 0100
0111 0100
uuuu uuuu 0111 0100 0111 0100
CGT1
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
CGT0
0000 1100 0000 1100
0000 1100
uuuu uuuu 0000 1100 0000 1100
Rev. 1.00
104
xxxx xxxx
xxx- ---0
00xx x0x0
xxxx xxxx
xxx- ---0
00xx x0x0
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Register
RES Reset
(Normal
Operation)
Reset
(Power-on)
WDT Time-out
(Normal
Operation)
WDT Time-out
(HALT)
USB Reset
(Normal)
USB Reset
(HALT)
CWT2
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
CWT1
0010 0101 0010 0101
0010 0101
uuuu uuuu 0010 0101 0010 0101
CWT0
1000 0000 1000 0000
1000 0000
uuuu uuuu 1000 0000 1000 0000
CIER
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
CIPR
0-00 0000 0-00 0000
0-00 0000
u-uu uuuu 0-00 0000 0-00 0000
CTXB
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
CRXB
0000 0000 0000 0000
0000 0000
uuuu uuuu 0000 0000 0000 0000
USC
1-00 0000 1-00 0000
u-uu uuuu
u-uu uuuu u-00 0100 u-00 0100
USR
--00 0000 --00 0000
--uu uuuu
--uu uuuu --00 0000 --00 0000
UCC
-0-0 0000 -0-0 0000
-u-u uuuu
-u-u uuuu -u-0 u000 -u-0 u000
AWR
0000 0000 0000 0000
uuuu uuuu
uuuu uuuu 0000 0000 0000 0000
STALL
--11 1110 --11 1110
--uu uuuu
--uu uuuu --11 1110 --11 1110
SIES
0000 0000 0000 0000
uuuu uuuu
uuuu uuuu 0000 0000 0000 0000
UMISC
0xx- -000
0xx- -000
uxx- -uuu
uxx- -uuu 000- -000 000- -000
SETIO
--11 1110 --11 1110
--uu uuuu
--uu uuuu --11 1110 --11 1110
FIFO0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu 0000 0000 0000 0000
FIFO1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu 0000 0000 0000 0000
FIFO2
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu 0000 0000 0000 0000
FIFO3
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu 0000 0000 0000 0000
FIFO4
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu 0000 0000 0000 0000
FIFO5
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu 0000 0000 0000 0000
UIC
--00 0000 --00 0000
--uu uuuu
--uu uuuu --00 0000 --00 0000
NTIM
--00 0000 --00 0000
--uu uuuu
--uu uuuu --00 0000 --00 0000
PIPE
--00 000- --00 000-
--uu uuu-
--uu uuu- --00 000- --00 000-
Note:
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Rev. 1.00
105
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Oscillator
Various oscillator options offer the user a wide range of functions according to their various
application requirements. Six types of system clocks can be selected while various clock source
options are provided for maximum flexibility. All oscillator options are selected through the
configuration options.
System Clock Configurations
There are many ways of generating the system clock, three high speed oscillators and two low speed
oscillators supplied clock. An external clock source can also be used as the system clock. The three
high speed oscillators are the external crystal/ceramic oscillator (HXT), the external RC network
(ERC) and the internal high speed RC oscillator (HIRC). The two low speed oscillators are the external
32.768kHz crystal oscillator (LXT) and the internal 32kHz RC oscillator (LIRC). Selecting whether
the low frequency or high oscillator is used as the system oscillator is implemented using the HLCLK
bit in the CLKMOD register. The source clock for the high speed oscillator is chosen via configuration
options as well as the low speed oscillator. The frequency of the slow clock is also determined using
the SLOWC0~SLOWC2 bits in the CLKMOD register.
External Crystal/ Ceramic Oscillator - HXT
After selecting the external crystal configuration option, the simple connection of a crystal across
OSC1 and OSC2, is normally all that is required to create the necessary phase shift and feedback for
oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to
ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic
resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for
oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or
resonator manufacturer¢s specification. In most applications, resistor RP1 is not required, however for
those applications where the LVR function is not used, RP1 may be necessary to ensure the oscillator
stops running when VDD falls below its operating range. The internal oscillator circuit contains a filter
circuit to reduce the possibility of erratic operation due to noise on the oscillator pins. An additional
configuration option must be setup to configure the device according to whether the oscillator
frequency is high, defined as equal to or above 1MHz, or low, which is defined as below 1MHz.
More information regarding oscillator applications is located on the Holtek website.
C 1
O S C 1
R
P 1
O S C 2
C 2
Crystal/Ceramic Oscillator
Crystal Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
20MHz
¾
¾
12MHz
¾
¾
8MHz
¾
¾
4MHz
¾
¾
1MHz
455kHz (see Note 2)
Note:
¾
¾
10pF
10pF
1. C1 and C2 values are for guidance only.
2. XTAL mode configuration option: 455kHz.
3. RP1= 5MW~10MW is recommended.
Crystal Recommended Capacitor Values
Rev. 1.00
106
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
External RC Oscillator - ERC
Using the ERC oscillator only requires that a resistor, with a value between 47kW and 1.5MW, is
connected between OSC1 and VDD, and a 470pF capacitor is connected between OSC1 and ground,
providing a low cost oscillator configuration. It is only the external resistor that determines the
oscillation frequency; the external capacitor has no influence over the frequency and is connected for
stability purposes only. Device trimming during the manufacturing process and the inclusion of
internal frequency compensation circuits are used to ensure that the influence of the power supply
voltage, temperature and process variations on the oscillation frequency are minimised. As a
resistance/frequency reference point, it can be noted that with an external 150kW resistor connected
and with a 5V voltage power supply and temperature of 25°C degrees, the oscillator will have a
frequency of 4MHz within a tolerance of 2%. Here only the OSC1 pin is used, which is shared with I/O
pin PC0, leaving pin PC1 free for use as a normal I/O pin.
Note that an internal capacitor together with the external resistor, ROSC, are the components which
determine the frequency of the oscillator. The external capacitor shown on the diagram does not
influence the frequency of oscillation. This external capacitor should be added to improve oscillator
stability if the open-drain OSC2 output is utilised in the application circuit. The internal oscillator circuit
contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscillator pins.
V
R
D D
O S C
O S C 1
4 7 0 p F
I/O
P in
P C 1
External RC Oscillator - ERC
Internal RC Oscillator - HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components. The
internal RC oscillator has three fixed frequencies of either 4MHz, 8MHz or 12MHz. Device trimming
during the manufacturing process and the inclusion of internal frequency compensation circuits are
used to ensure that the influence of the power supply voltage, temperature and process variations on
the oscillation frequency are minimised. As a result, at a power supply of either 3V or 5V and at a
temperature of 25¢J degrees, the fixed oscillation frequency of 4MHz, 8MHz or 12MHz will have a
tolerance within 2%. Note that if this internal system clock option is selected, as it requires no external
pins for its operation, I/O pins PC0 and PC1 are free for use as normal I/O pins.
Internal 32kHz RC Oscillator - LIRC
The Internal 32kHz System Oscillator is one of the low frequency oscillator choices, which is selected
via configuration option. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V,
requiring no external components for its implementation. Device trimming during the manufacturing
process and the inclusion of internal frequency compensation circuits are used to ensure that the
influence of the power supply voltage, temperature and process variations on the oscillation frequency
are minimised. As a result, at a power supply of 5V and at a temperature of 25°C degrees, the
oscillation frequency of 32kHz will have a frequency range from 28.1kHz to 34.4kHz.
In te rn a l
3 2 k H z
O s c illa to r
fL
IR C
Internal RC Oscillator - LIRC
Rev. 1.00
107
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
External 32.768kHz Oscillator - LXT
The External 32.768kHz Crystal System Oscillator is one of the low frequency oscillator choices,
which is selected via configuration option. This clock source has a fixed frequency of 32.768kHz and
requires a 32.768kHz crystal to be connected between pins OSC3 and OSC4. The external resistor and
capacitor components connected to the 32.768kHz crystal are necessary to provide oscillation. For
applications where precise frequencies are essential, these components may be required to provide
frequency compensation due to different crystal manufacturing tolerances. During power-up there is a
time delay associated with the LXT oscillator waiting for it to start-up.
When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop
microcontroller activity and to conserve power. However, in many microcontroller applications it may
be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or
IDLE Mode. To do this, another clock, independent of the system clock, must be provided.
However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to
add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected
in consultation with the crystal or resonator manufacturers¢ specification. The external parallel
feedback resistor, Rp, is required.
Some configuration options determine if the OSC3/OSC4 pins are used for the LXT oscillator or as
I/O pins.
·
If the LXT oscillator is not used for any clock source, the OSC3/OSC4 pins can be used as
normal I/O pins.
·
If the LXT oscillator is used for any clock source, the 32.768kHz crystal should be connected to
the OSC3/OSC4 pins.
LXT Oscillator C3 and C4 Values
Crystal Frequency
C3
C4
32768Hz
8pF
10pF
Note:
1. C3 and C4 values are for guidance only.
2. RP2=5M~10MW is recommended.
32.768kHz Crystal Recommended Capacitor Values
C 3
3 2 7 6 8 H z
R
O S C 3
3 2 .7 6 8 k H z
P 2
O S C 4
C 4
Crystal/Ceramic Oscillator
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
LXT Oscillator Low Power Function
The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode.
The mode selection is executed using the QOSC bit in the RTCC register.
QOSC Bit
LXT Mode
0
Quick Start
1
Low-power
After power on, the QOSC bit will be automatically cleared to zero ensuring that the LXT oscillator is
in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and
stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed into the
Low-power mode by setting the QOSC bit high. The oscillator will continue to run but with reduced
current consumption, as the higher current consumption is only required during the LXT oscillator
start-up. In power sensitive applications, such as battery applications, where power consumption must
be kept to a minimum, it is therefore recommended that the application program sets the QOSC bit
high about 2 seconds after power-on.
It should be noted that, no matter what condition the QOSC bit is set to, the LXT oscillator will always
function normally, the only difference is that it will take more time to start up if in the Low-power
mode.
External Oscillator - EC
The system clock can also be supplied by an externally supplied clock giving users a method of
synchronizing their external hardware to the microcontroller operation. This is selected using a
configuration option and supplying the clock on pin OSC1. Pin OSC2 can be used as a normal I/O pin
if the external oscillator is used. The internal oscillator circuit contains a filter circuit to reduce the
possibility of erratic operation due to noise on the oscillator pin. However, as the filter circuit
consumes a certain amount of power, an oscillator configuration option exists to turn this filter off. Not
using the internal filter should be considered in power sensitive applications and where the externally
supplied clock is of a high integrity and supplied by a low impedance source.
System Operating Modes
The device has the ability to operate in several different modes. This range of operating modes, known
as Normal Mode, Slow Mode, Idle Mode and Sleep Mode, allow the device to run using a wide range
of different slow and fast clock sources. The devices also possess the ability to dynamically switch
between different clocks and operating modes. With this choice of operating functions users are
provided with the flexibility to ensure they obtain optimal performance from the device according to
their application specific requirements.
Clock Sources
In discussing the system clocks for the device, they can be seen as having a dual clock mode. These
dual clocks are what are known as a High Oscillator and the other as a Low Oscillator. The High and
Low Oscillator are the system clock sources and can be selected dynamically using the HLCLK bit in
the CLKMOD register. The High Oscillator has the internal name fM whose source is selected using a
configuration option from a choice of either an external crystal/resonator, external RC oscillator or
external clock source.
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
CLKMOD Register
Bit
7
6
5
4
3
2
1
0
Name
SLOWC2
SLOWC1
SLOWC0
SIMIDLE
LTO
HTO
IDLEN
HLCLK
R/W
R/W
R/W
R/W
R
R
R/W
R
POR
0
0
0
0
0
0
0
Bit 7~5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
SLOWC2~SLOWC0: Low speed clock frequency fSLOW selection
000: fSL
001: fSL
010: fM/64
011: fM/32
100: fM/16
101: fM/8
110: fM/4
111: fM/2
2
SIMIDLE: SIMn (SPI/I C) Continues Running in IDLE mode control
0: disable
1: enable
LTO: Low speed Oscillator ready flag
0: non-time-out
1: time-out
HTO: High speed Oscillator ready flag
0: non-time-out
1: time-out
IDLEN: Idle mode control
0: disable (SLEEP mode)
1: enable (IDLE mode)
HLCLK: System clock frequency fSYS selection
0: fM
1: fSLOW
The Low Oscillator clock source has the internal name fSL, whose source is also selected by configuration option from a choice of either an external 32.768kHz oscillator (LXT) or the internal 32kHz
RC oscillator (LIRC). This internal fSL, fM clock, is further modified by the SLOWC0~ SLOWC2
bits in the CLKMOD register to provide the low frequency clock source fSLOW.
An additional sub internal clock, with the internal name fSUB, is a 32kHz clock source which can be
sourced from either the internal 32K_INT oscillator or an external 32768 Hz crystal, selected by
configuration option. Together with fSYS/4, it is used as a clock source for certain internal functions
such as the LCD driver, Watchdog Timer, Buzzer, RTC Interrupt and Time Base Interrupt. The LCD
clock source is the fSUB clock source divided by 8, giving a frequency of 4kHz. The internal clock fS, is
simply a choice of either fSUB or fSYS/4, using a configuration option.
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
N o rm a l M o d e
= 0
N "
L E
D
"I
&
L T
H A
S e t "H L C L K "
S le e p M o d e
fM O ff,
L X T o r L IR C O n * ,
fS Y S = O ff
H A
L T
w a
ke
-u
&
"ID
O n ,
L E
N "
=
p
S lo w
0
fM O
L X T o r
fS Y S = fM
o r L X T
H A
L T
&
"ID
w a
ke
-u
L E
N "
=
p
1
Id le M o d e
R e s e t "H L C L K "
-u p
k e
w a
fM O n ,
L X T o r L IR C
fS Y S = fM
fM O ff,
L X T o r L IR C O n #,
fS Y S = O ff
-u p
k e
w a
M o d e
L T
H A
n /O ff,
L IR C O n ,
/2 ~ fM /6 4
o r L IR C
" * " D e p e n d s th e W D T e n a b le /d is a b le c o n d itio n .
1
" =
E N
L
"ID
&
" # " E ith e r th e L X T o r L IR C
m u s t b e O N .
Dual Clock Mode Operation
H ig h O s c illa to r
O S C 1
E C
O S C 1
E R C
O S C 1
E x te r n a l C lo c k F ilte r O ff
C o n fig u r a tio n O p tio n
H X T /E R C /H IR C /E C
C o n fig u r a tio n O p tio n
H X T
O S C 2
fM
M U X
F ilte r
fM
fS
L o w O s c illa to r
M U X
fL
IR C
fS
U B
fS
Y S
M U X
/4
C o n fig u r a tio n
O p tio n
fM /2 , ... fM /6 4 , fS
S L O W C 0
L IR C
X T
S L O W C 1
S L O W C 2
O S C 4
fL
L X T
fS
S lo w
C lo c k
C o n tro l
L
fS
M U X
H IR C
O S C 3
H L C L K B it
fS
Y S
fS
U B
fS
/4
Y S
L O W
L
M U X
T im e r 1
T 1 S
R T C in te r r u p t,
T im e B a s e in te r r u p t,
B u z z e r, W D T
fS C lo c k S e le c t
C o n fig u r a tio n O p tio n
fS
U B
¸ 8
fL
= fS
C D
U B
/8
L C D
Dual Clock Mode Structure
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Operating Modes
After the correct clock source configuration selections are made, overall operation of the chosen clock
is achieved using the CLKMOD register. A combination of the HLCLK and IDLEN bits in the
CLKMOD register and use of the HALT instruction determine in which mode the device will be run.
The devices can operate in the following Modes.
·
Normal mode
fM on, fSLOW on, fSYS=fM, CPU on, fS on, fLCD on/off depending upon the LCDEN bit, fWDT on/off
depending upon the WDT configuration option and WDT control register.
·
Slow Mode0
fM off, fSYS=fSLOW, fSLOW=fSL=fLIRC or fLXT, CPU on, fS on, fLCD on/off depending upon the LCDEN bit, fWDT
on/off depending upon the WDT configuration option and WDT control register.
·
Slow Mode1
fM on, fSYS=fSLOW= fM/2~fM/64, CPU on, fS on, fLCD on/off depending upon the LCDEN bit, fWDT on/off
depending upon the WDT configuration option and WDT control register.
·
IDLE mode
fM, fSLOW, fSYS off, CPU off; fSUB on, fS on/off by selecting fSUB or fSYS /4, fLCD on/off depending upon the
LCDEN bit, fWDT on/off depending upon the WDT configuration option and WDT control register.
The IDLE mode is determined by the IDLE Mode Control bit named IDLEN in the CLKMOD
register when the HALT instruction is executed. If this bit is high, when a HALT instruction is
executed the device will enter the IDLE Mode. If the bit is low the device will enter the SLEEP Mode
when a HALT instruction is executed.
·
SLEEP mode
fM, fSLOW, fSYS, fS, fLCD off, CPU off; fSUB, fWDT on/off depending upon the WDT configuration option and
WDT control register.
The SLEEP mode is determined by setting the IDLE Mode Control bit named IDLEN to 0 when the
HALT instruction is executed.
Operation Mode
Description
CPU
fSYS
fSUB
fS
fLCD
Normal Mode
On
fM
On
On
On/Off (4)
Slow 0 Mode
On
fSLOW=fLIRC or fLXT
On
On
On/Off (4)
Slow 1 Mode
On
fSLOW=fM/2~fM/64
On
On
IDLE Mode
Off
SLEEP Mode
Off
Note:
Off
(1)
On
On/Off (2)
Off
On/Off
Off (3)
On/Off (4)
(3)
On/Off (4)
Off
1. In the IDLE Mode, the fSYS clock on/off function is determined by whether the SIMIDLE bit set to 1 or 0
respectively and can only be used for the master SPI operation or PCLK output for which the clock source
comes from the fSYS clock.
2. In the SLEEP mode the fSUB clock on/off function is determined by whether the WDT is enabled or disabled
respectively.
3. The fS clock on/off function in the IDLE or SLEEP mode is determined by whether the selected clock source
of the WDT function is fSUB or the fSYS/4 clock.
4. The fLCD clock turned on/off function is determined by the LCDEN or LEDEN control bit.
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Power Down Mode and Wake-up
Power Down Mode
All of the Holtek microcontroller have the ability to enter a Power Down Mode. When the device
enters this mode, the normal operating current, will be reduced to an extremely low standby current
level. This occurs because when the device enters the Power Down Mode, the system oscillator is
stopped which reduces the power consumption to extremely low levels, however, as the device
maintains its present internal condition, it can be woken up at a later stage and continue running,
without requiring a full reset. This feature is extremely important in application areas where the MCU
must have its power supply constantly maintained to keep the device in a known condition but where
the power supply capacity is limited such as in battery applications.
Entering the Power Down Mode
There is only one way for the device to enter the Power Down Mode and that is to execute the ²HALT²
instruction in the application program. When this instruction is executed, the following will occur:
·
The system oscillator will stop running and the application program will stop at the ²HALT²
instruction.
·
The Data Memory contents and registers will maintain their present condition.
·
The WDT will be cleared and resume counting if the WDT clock source is selected to come from the
WDT oscillator. The WDT will stop if its clock source originates from the system clock.
·
The I/O ports will maintain their present condition.
·
In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Standby Current Considerations
As the main reason for entering the Power Down Mode is to keep the current consumption of the MCU
to as low a value as possible, perhaps only in the order of several micro-amps, there are other
considerations which must also be taken into account by the circuit designer if the power consumption
is to be minimized. Special attention must be made to the I/O pins on the device. All high-impedance
input pins must be connected to either a fixed high or low level as any floating input pins could create
internal oscillations and result in increased current consumption. This also applies to devices which
have different package types, as there may be undonbed pins, which must either be setup as outputs or
if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads,
which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in
which minimum current is drawn or connected only to external circuits that do not draw current, such
as other CMOS inputs. Also note that additional standby current will also be required if the
configuration options have enabled the Watchdog Timer internal oscillator.
Wake-up
After the system enters the Power Down Mode, it can be woken up from one of various sources listed
as follows:
Rev. 1.00
·
An external reset
·
An external falling edge on Port A
·
A system interrupt
·
A WDT overflow
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
If the system is woken up by an external reset, the device will experience a full system reset, however,
if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both
of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be
determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or
executing the clear Watchdog Timer instructions and is set when executing the ²HALT² instruction.
The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in their original status.
Each pin on Port A can be setup via an individual configuration option to permit a negative transition
on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume
execution at the instruction following the ²HALT² instruction.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where the
related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program
will resume execution at the instruction following the ²HALT² instruction. In this situation, the
interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later
when the related interrupt is finally enabled or when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is not full, in which case the regular interrupt
response takes place. If an interrupt request flag is set to ²1² before entering the Power Down Mode,
the wake-up function of the related interrupt will be disabled.
No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period
equal to 1024 system clock periods will be required before normal system operation resumes.
However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution
will be delayed by an additional one or more cycles. If the wake-up results in the execution of the next
instruction following the ²HALT² instruction, this will be executed immediately after the 1024 system
clock period delay has ended.
Low Voltage Detector - LVD
The Low Voltage Detect internal function provides a means for the user to monitor when the power
supply voltage falls below a certain fixed level as specified in the DC characteristics.
LVD Operation
The LVD function must be first enabled via a configuration option after which bits 3 and 5 of the
RTCC register are used to control the overall function of the LVD. Bit 3 is the enable/disable control
bit and is known as LVDC, when set low the overall function of the LVD will be disabled. Bit 5 is the
LVD detector output bit and is known as LVDO. Under normal operation, and when the power supply
voltage is above the specified VLVD value in the DC characteristic section, the LVDO bit will remain
at a zero value. If the power supply voltage should fall below this VLVD value then the LVDO bit will
change to a high value indicating a low voltage condition. Note that the LVDO bit is a read-only bit. By
polling the LVDO bit in the RTCC register, the application program can therefore determine the
presence of a low voltage condition.
After power-on, or after a reset, the LVD will be switched off by clearing the LVDC bit in the RTCC
register to zero. Note that if the LVD is enabled there will be some power consumption associated with
its internal circuitry, however, by clearing the LVDC bit to zero the power can be minimised. It is
important not to confuse the LVD with the LVR function. In the LVR function an automatic reset will
be generated by the microcontroller, whereas in the LVD function only the LVDO bit will be affected
with no influence on other microcontroller functions.
There are a range of voltage values, selected using a configuration option, which can be chosen to
activate the LVD.
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise. It operates by
providing a device reset when the Watchdog Timer counter overflows.
Watchdog Timer Operation
The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by
one of two sources selected by configuration option: fSUB or fSYS/4. Note that if the Watchdog Timer
configuration option has been disabled, then any instruction relating to its operation will result in no
operation.
Most of the Watchdog Timer options, such as enable/disable, Watchdog Timer clock source and clear
instruction type are selected using configuration options. In addition to a configuration option to
enable the Watchdog Timer, there are four bits, WDTEN3~ WDTEN0, in the MISC1 register to offer
an additional enable control of the Watchdog Timer. These bits must be set to a specific value of 1010
to disable the Watchdog Timer. Any other values for these bits will keep the Watchdog Timer enabled.
After power on these bits will have the disabled value of 1010.
One of the WDT clock sources is the internal fSUB, which can be sourced from either the internal
32kHz RC oscillator (LIRC) or the external 32.768kHz oscillator (LXT). The LIRC oscillator has an
approximate period of 31.2ms at a supply voltage of 5V. However, it should be noted that this specified
internal clock period can vary with VDD, temperature and process variations. The LXT oscillator is
supplied by an external 32768Hz crystal. The other Watchdog Timer clock source option is the fSYS/4
clock. Whether the Watchdog Timer clock source is it¢s the LIRC, the LXT oscillator or fSYS/4, it is
divided by 213~216, using configuration option to obtain the required Watchdog Timer time-out period.
The max time out period is when the 216 option is selected. This time-out period may vary with
temperature, VDD and process variations. As the clear instruction only resets the last stage of the
divider chain, for this reason the actual division ratio and corresponding Watchdog Timer time-out can
vary by a factor of two. The exact division ratio depends upon the residual value in the Watchdog
Timer counter before the clear instruction is executed.
C L R W D T 1 F la g
C o n tro l
L o g ic
C L R W D T 2 F la g
1 o r 2 In s tr u c tio n s
L X T
L IR C
fL
fL
X T
IR C
W D T S o u rc e
C o n fig u r a tio n
O p tio n
C L R
fS
U B
8 - b it D iv id e r
fS /2
8
¸
7 - b it P r e s c a le r
2
W D T T im e - o u t
(2 13/fS , 2 14/fS , 2 15/fS o r 2
1 6
/fS )
C o n fig O p tio n
fS /2
1 2
, fS /2
1 3
, fS /2
1 4
o r fS /2
1 5
Watchdog Timer
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
MISC1 Register
Bit
7
6
5
4
3
2
1
0
Name
ODE3
ODE2
ODE1
ODE0
WDTEN3
WDTEN2
WDTEN1
WDTEN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
1
0
1
0
Bit 7~4
ODE3~ODE0: PA3~PA0 Open Drain control
Described in Input/Output Port section
Bit 3~0
WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT function enable
1010: WDT disabled
Other values: WDT enabled Recommended value is ²0101²
If the ²watchdog timer enable² configuration option is selected, then the watchdog timer will
al ways be enabled and the WDTEN3 ~ WDTEN0 control bits will have no effect. The WDT is
only disabled when both the WDT configuration option is disabled and when bits WDTEN3 ~
WDTEN0¡×1010. The WDT is enabled when either the WDT configuration option is enabled or
when bits WDTEN3 ~ WDTEN0¹1010
If the fSYS/4 clock is used as the Watchdog Timer clock source, it should be noted that when the system enters the Power Down Mode, then the instruction clock is stopped and the Watchdog Timer
will lose its protecting purposes. For systems that operate in noisy environments, using the LIRC oscillator is strongly recommended.
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the
status bit TO. However, if the system is in the Power Down Mode, when a Watchdog Timer time-out
occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will
be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is an
external hardware reset, which means a low level on the RES pin, the second is using the watchdog
software instructions and the third is via a ²HALT² instruction.
Clearing the Watchdog Timer
There are two methods of using software instructions to clear the Watchdog Timer, one of which must
be chosen by configuration option. The first option is to use the single ²CLR WDT² instruction while
the second is to use the two commands ²CLR WDT1² and ²CLR WDT2². For the first option, a simple
execution of ²CLR WDT² will clear the WDT while for the second option, both ²CLR WDT1² and
²CLR WDT2² must both be executed to successfully clear the Watchdog Timer. Note that for this
second option, if ²CLR WDT1² is used to clear the Watchdog Timer, successive executions of this
instruction will have no effect, only the execution of a ²CLR WDT2² instruction will clear the Watchdog
Timer. Similarly after the ²CLR WDT2² instruction has been executed, only a successive ²CLR WDT1²
instruction can clear the Watchdog Timer.
Rev. 1.00
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
USB Interface
The devices contains an embedded USB Module, which is a 4-wire serial bus that allows
communication with an external host device. A token based protocol method is used by the host device
for communication control. Other advantages of the USB bus include live plugging and unplugging
and dynamic device configuration. It is particularly suitable for the devices with data links between
PCs or peripheral devices, or the devices with USB interface such as USB mice, USB keyboards or
USB joysticks, etc.
As the complexity of USB data protocol does not permit comprehensive USB operation information to
be provided in this datasheet, the reader should therefore consult other external information for a
detailed USB understanding.
USB Operation
To communicate with an external USB host, the internal USB module has external pins known as DP
and DM along with the 3.3V regulator output V33O. The USB module has 6 endpoints and a 160 byte
FIFO for the endpoints respectively. A Serial Interface Engine (SIE) decodes the incoming USB data
stream and transfers it to the correct endpoint buffer memory (FIFO). A series of status registers
provide the user with the USB data transfer situation as well as any error conditions. The USB contains
its own independent interrupt which can be used to indicate when the USB FIFOs are accessed by the
host device or a change of the USB operating conditions including the USB suspend mode, resume
event or USB reset occurs.
USB Status and Control Registers
There are several registers associated with the USB function. Some of the registers control the overall
function of the USB module as well as the interrupts, while some of the registers contain the status bits
which indicate the USB data transfer situations and error condition. Also there are FIFOs for the USB
endpoints to store the data received from or to be transmitted to the USB host. The USB module has 6
endpoints (EP0~EP5) with a different FIFO size for each one. The FIFO size is 8 bytes for EP0~EP2
and EP4 which support ²Interrupt transfer², while the FIFO size for EP3 and EP5 is 64 bytes which can
support ²Bulk transfer².
Rev. 1.00
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
USB Register Summary
Address
Name
POR State
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
60H
USC
1-00 0000
URD
¾
PLL
V33C
RESUME
URST
RMWK
SUSP
61H
USR
--00 0000
¾
¾
EP5IF
EP4IF
EP3IF
EP2IF
EP1IF
EP0IF
62H
UCC
-0-0 0000
¾
SYSCLK
¾
SUSP2
USBCKEN
EPS2
EPS1
EPS0
63H
AWR
0000 0000
UAD6
UAD5
UAD4
UAD3
UAD2
UAD1
UAD0
WKEN
64H
STALL
--11 1110
¾
¾
STL5
STL4
STL3
STL2
STL1
STL0
65H
SIES
0000 0000
NMI
¾
CRCF
NAK
IN
OUT
ERR
ASET
66H
UMISC
0xx- -000
LEN0
READY
SETCMD
¾
¾
CLEAR
TX
REQUEST
67H
SETIO
--11 1110
¾
¾
SETIO5
SETIO4
SETIO3
SETIO2
SETIO1
SETIO0
68H
FIFO0
XXXX XXXX
Data for endpoint 0
69H
FIFO1
XXXX XXXX
Data for endpoint 1
6AH
FIFO2
XXXX XXXX
Data for endpoint 2
6BH
FIFO3
XXXX XXXX
Data for endpoint 3
6CH
FIFO4
XXXX XXXX
Data for endpoint 4
6DH
FIFO5
XXXX XXXX
Data for endpoint 5
6EH
¾
¾
Unused, read as 0
6FH
¾
¾
Unused, read as 0
70H
UIC
--00 0000
¾
¾
EU5I
EU4I
EU3I
EU2I
EU1I
EU0I
71H
NTIM
--00 0000
¾
¾
NTI5M
NTI4M
NTI3M
NTI2M
NTI1M
NTI0M
72H
PIPE
--00 000-
¾
¾
EP5E
EP4E
EP3E
EP2E
EP1E
¾
USC Register
The USC register contains the status bits for USB suspend, resume and reset indications. It also
contains the bits used to control the Remote Wake-up, V33O output, PLL function and USB reset
behavior. Further explanation on each bit is given below:
Bit
7
6
5
4
3
2
1
0
Name
URD
¾
PLL
V33C
RESUME
URST
RMWK
SUSP
R/W
R/W
¾
R/W
R/W
R
R
R/W
R
POR
1
0
0
0
0
0
0
0
Bit 7
URD: USB reset signal control
0: USB reset signal can not reset the MCU
1: USB reset signal will reset the MCU
Bit 6
Unimplemented, read as ²0².
Bit 5
PLL: PLL enable control
0: turn on the PLL
1: turn off the PLL
V33C: V33O output enable control
0: turn off the V33O output
1: turn on the V33O output
Bit 4
Rev. 1.00
118
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Bit 3
RESUME: USB resume indication flag
0: USB device does not receive the resume signal or has left the suspend mode.
1: USB device receives the resume signal and is going to leave the suspend mode.
When the USB device receives the resume signal, this bit is set to ²1² by SIE. This bit will appear
for about 20ms, waiting for the MCU to detect it. When the RESUME is set by SIE, an interrupt
will be generated to wake up the MCU. In order to detect the suspend state, MCU should set the
USBCKEN bit to ²1² and clear the PLL bit to ²0² to enable the SIE functions. The RESUME bit
will be cleared when the SUSP bit is set to ²0². When the MCU detects the suspend mode SUSP,
the resume signal RESUME which causes MCU to wake up should be remembered and taken
into consideration.
URST: USB reset indication flag
0: No USB reset event occurred.
1: USB reset event has occurred.
The USB bit is set and cleared by USB SIE. When the URST bit is set to ²1², it indicates that a
USB reset event has occurred and a USB interrupt will be initiated.
Bit 2
Bit 1
RMWK: USB remote wake-up command
0: disable USB remote wake-up command
1: initiate USB remote wake-up command
The RMWK is set to ²1² by MCU to force the USB host leaving the suspend mode. Set RMWK bit
to 1 to initiate the remote walk-up command. When the RMWK bit is set to ²1², a 2ms delay for
clearing this bit to ²0² is necessary to ensure that the RMWK command is accepted by the SIE.
SUSP: USB suspend indication flag
0: USB leaves the suspend mode.
1: USB enters the suspend mode.
This bit is read only and set to ²1² by SIE to indicate that the USB bus enters the suspend mode.
The USB interrupt is also generated when the SUSP bit is asserted.
Bit 0
USR Register
The USR (USB endpoint interrupt status register) register is consisted of the endpoint request flags
(EP0IF~EP5IF) used to indicate which endpoint is accessed. When an endpoint is accessed, the related
endpoint request flag will be set to ²1² by SIE and a USB interrupt will be generated if the control bits
related to the USB interrupt are enabled and the stack in the host MCU is not full. When the active
endpoint request flag is serviced, the endpoint request flag has to be cleared to ²0² by application
program.
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
EP5IF
EP4IF
EP3IF
EP2IF
EP1IF
EP0IF
R/W
¾
¾
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Bit 5~0
Rev. 1.00
Unimplemented, read as ²0².
EP5IF~EP0IF: Endpoint Interrupt request flags
0: the corresponding Endpoint is not accessed.
1: the corresponding Endpoint has been accessed.
119
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
UCC Register
The UCC register is the system clock control register implemented to select the clock used by the
MCU. This register consists of USB clock control bit USBCKEN, second suspend mode control bit
SUSP2 and system clock selection bit SYSCLK. This register is also used to select which endpoint
FIFO is accessed by Endpoint FIFO Selection bits EPS2~EPS0. Further explanation on each of the bits
is given below:
Bit
7
6
5
4
3
2
1
0
Name
¾
SYSCLK
¾
SUSP2
USBCKEN
EPS2
EPS1
EPS0
R/W
¾
R/W
¾
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Unimplemented, read as ²0².
SYSCLK: System clock input selection
0: 12MHz clock is used
1: 6MHz clock is used
This bit is used to specify the system clock oscillator frequency used by the MCU. If a 6MHz
crystal oscillator or resonator is used, this bit should be set to ²1². If a 12MHz crystal oscillator or
resonator is used, this bit should be set to ²0².
Bit 5
Bit 4
Unimplemented, read as ²0².
SUSP2: Suspend mode 2 control
0: optimized setting in suspend mode
1: test setting in suspend mode. The band-gap circuit is turned off.
It is strongly recommended that this bit should be set to ²0² when the USB interface is in suspend
mode. Otherwise, the unpredictable results will occur.
USBCKEN: USB clock enable control
0: USB clock is disabled
1: USB clock is enabled
When the USB device receives the suspend signal sent from the USB host, the USB clock
enable control bit USBCKEN should be set to ²0² to reduce the power consumption.
EPS2~EPS0: Endpoint FIFO selection
000: Endpoint 0 FIFO is selected
001: Endpoint 1 FIFO is selected
010: Endpoint 2 FIFO is selected
011: Endpoint 3 FIFO is selected
100: Endpoint 4 FIFO is selected
101: Endpoint 5 FIFO is selected
11x: reserved for further expansion and can not be used.
The EPS2~EPS0 bits are used to select which endpoint is to be accessed. If the selected
endpoint does not exist, the related functions are not available.
Bit 3
Bit 2~0
AWR Register
The AWR register contains the USB device address and the Remote wake-up function control bit. The
initial value of the USB device address is 00H. The address value extracted from the USB command is
to be immediately loaded into this register or not depending upon the device address update control bit
ASET in the SIES register.
Bit
7
6
5
4
3
2
1
0
Name
UAD6
UAD5
UAD4
UAD3
UAD2
UAD1
UAD0
WKEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~1
UAD6~UAD0: USB device address
Bit 0
WKEN: USB device Remote Wake-up function enable control
0: disable USB remote wake-up function
1: enable USB remote wake-up function
Rev. 1.00
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December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
STALL Register
The STALL register shows whether the corresponding endpoint works properly or not. As soon as the
endpoint works improperly, the related bit in the STALL register has to be set to ²1² by application
program. The contents of the STALL register will be cleared by USB reset signal.
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
STL5
STL4
STL3
STL2
STL1
STL0
R/W
¾
¾
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Unimplemented, read as ²0².
STL5~STL0: USB endpoint stall indication
0: the corresponding USB endpoint is not stalled.
1: the corresponding USB endpoint is stalled.
The STL bit is set by users when the related USB endpoint is stalled. These bits are cleared by
USB reset signal. For endpoint 0 the stall bit STL0 can also be cleared by Setup Token event.
Bit 7~6
Bit 5~0
SIES Register
The SIES register is used to indicate the present signal state which the SIE receives and also control
whether the SIE changes the device address automatically or not.
Bit
7
6
5
4
3
2
1
0
Name
NMI
¾
CRCF
NAK
IN
OUT
ERR
ASET
R/W
R/W
R
R/W
R
R
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
NMI: NAK token interrupt global mask control
0: USB NAK token interrupt for all endpoints is masked.
1: USB NAK token interrupt depends upon the individual mask control bits in NTIM register.
If this bit is cleared to ²0², the interrupt will not occur when the device sends a NAK token to the
USB host. Otherwise, when this bit is set to ²1² and the device sends a NAK token to the USB
host, the NAK token interrupt will be generated or not depending upon the NAK token interrupt
mask control bit NTIxM (x=0~5) in NTIM register.
Bit 6
Bit 5
Unimplemented, read as ²0².
CRCF: Error indication flag during transfer
0: No USB transfer error occurs.
1: USB transfer error has occurred.
The Error conditions include CRC, PID and incomplete token errors. The CRCF bit is set by
hardware and is necessary to be cleared by firmware.
NAK: NAK signal indication flag
0: No NAK signal is transmitted.
1: NAK signal has been transmitted.
The NAK bit is used to indicate that the SIE has transmitted a NAK signal to the USB host in
response to the USB host IN or OUT token when the endpoint was accessed.
IN: IN token indication flag for Endpoint 0
0: the received token packet is not IN token.
1: the received token packet is IN token.
The IN bit is used to indicate that for the USB endpoint 0 the current received signal from the
USB host is IN token.
OUT: OUT token indication flag for Endpoint 0
0: the received token packet is not OUT token.
1: the received token packet is OUT token.
The OUT bit is used to indicate that for the USB endpoint 0 the current received signal from the
USB host is OUT token except for the OUT zero length token. The firmware clears this bit after
the OUT data has been read. Also, this bit will be cleared by SIE after the next valid SETUP
token is received.
Bit 4
Bit 3
Bit 2
Rev. 1.00
121
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Bit 1
ERR: Error indication flag during endpoint 0 FIFO is accessed
0: No error occurs during endpoint 0 FIFO is accessed.
1: Error has occurred during endpoint 0 FIFO is accessed.
The ERR bit is used to indicate that there are some errors occurred during endpoint 0 FIFO is
accessed. This bit is set by SIE and should be cleared by firmware.
ASET: Device Address update control
0: device address is updated immediately when the AWR register is written.
1: device address is updated after the device IN token data has been read
(SETUP stage finished).
Bit 0
The ASET bit is used to configure the SIE to automatically update the device address with the
value stored in the AWR register. When this bit is set to ²1² by firmware, the SIE will update the
device address with the value stored in the AWR register after the USB host has successfully
read the data from the device by IN token. Otherwise, when this bit is cleared to ²0², the SIE will
update the device address immediately after an address is written to the AWR register.
UMISC Register
The UMISC register contains the commands to control the desired endpoint FIFO action along with
the status to show the condition of the desired endpoint FIFO. The UMISC register will be cleared by a
USB reset signal.
Bit
7
6
5
4
3
2
1
0
Name
LEN0
READY
SETCMD
¾
¾
CLEAR
TX
REQUEST
R/W
R/W
R
R/W
¾
¾
R/W
R/W
R/W
POR
0
x
x
0
0
0
0
0
²x² means unknown.
Bit 7
Bit 6
Bit 5
Bit 4~3
Bit 2
Rev. 1.00
LEN0: zero-length packet indication flag for Endpoint 0
0: no operation.
1: a zero-length packet is sent from the USB host.
If this bit is set to 1, it indicates that a 0-sized packet is sent from a USB host. This bit should
be cleared by the application program or by the next valid SETUP token.
READY: Endpoint FIFO Ready indication flag
0: the desired endpoint FIFO is not ready.
1: the desired endpoint FIFO is ready.
This bit is used to indicate whether the desired endpoint FIFO is ready to operate or not.
SETCMD: SETUP command indication flag
0: the data in the endpoint 0 FIFO is not SETUP token.
1: the data in the endpoint 0 FIFO is SETUP token.
This bit is used to indicate whether the data in the Endpoint 0 FIFO is SETUP token or not. It is
set by hardware and cleared by firmware.
Unimplemented, read as ²0².
CLEAR: clear requested FIFO
0: no operation.
1: clear the requested endpoint FIFO.
This bit is used by MCU to clear the requested FIFO, even if the FIFO is not ready. If user
wants to clear the current requested Endpoint FIFO, the CLEAR bit should be set to ²1² to
generate a positive pulse with 2ms pulse width and then clear this bit to zero.
122
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Bit 1
TX: Direction of data transfer between the MCU and the endpoint FIFO
0: the data transfer from the endpoint FIFO to the MCU (MCU read data from the endpoint FIFO).
1: the data transfer from the MCU to the endpoint FIFO (MCU write data to the endpoint FIFO).
This bit defines the direction of data transfer between the MCU and the endpoint FIFO. When
the TX bit is set to high, this means that the MCU desires to write data to the endpoint FIFO.
After the MCU write operation has been complete, this bit has to be cleared to zero before
terminating FIFO request to indicate the end of data transfer. For a MCU read operation, this bit
has to be cleared to zero to show that the MCU desires to read data from the endpoint FIFO and
has to be set to high before terminating FIFO request to indicate the end of data transfer after the
completion of MCU read operation.
REQUEST: FIFO request control
0: no operation.
1: Request the desired FIFO.
Bit 0
This bit is used to request the operation of the desired FIFO. After selecting the desired
endpoint, the FIFO can be requested by setting this bit to high. After completion, this bit has to
be cleared to zero.
The MCU can communicate with the endpoint FIFO by setting the corresponding registers, whose
addresses are listed in the following table. After reading the current data, the next data will show after 2ms, used to check the endpoint FIFO status and responds to the MISC register, if a read/write action is still being implemented.
Some timing constrains are listed here. By setting the MISC register, the MCU can perform reading,
writing and clearing actions. There are some examples shown in the following for the endpoint FIFO
reading, writing and clearing.
Actions
MISC Setting Flow and Status
Check whether FIFOn can be read or not
00H®01H®delay 2ms, check 41H (ready) or 01H (not ready)®00H
Check whether FIFOn can be written or not
02H®03H®delay 2ms, check 43H (ready) or 03H (not ready)®02H
Read FIFOn sequence
00H®01H®delay 2ms, check 41H®read* from FIFOn register and
check not ready (01H)®03H®02H
Write FIFOn sequence
02H®03H®delay 2ms, check 43H®write* to FIFO0 register and
check not ready (03H)®01H®00H
Read 0-sized packet sequence from FIFO0
00H®01H®delay 2ms, check 81H®clear LEN0 (01H)®03H®02H.
Write 0-sized packet sequence to FIFOn
02H®03H®delay 2ms®01H®00H.
Note *: There are 2ms existing between 2 reading actions or between 2 writing actions.
R E Q U E S T
R E Q U E S T
T X
T X
R E A D Y
R E A D Y
R e a d F IF O
Rev. 1.00
T im in g
R e a d F IF O
123
T im in g
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
SETIO Register
The SETIO register is used to configure the endpoint FIFO as IN pipe or OUT pipe.
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
SETIO5
SETIO4
SETIO3
SETIO2
SETIO1
DATATG
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
1
1
1
1
1
0
Unimplemented, read as ²0².
SETIO5~SETIO1: Endpoint 5 FIFO ~ Endpoint FIFO1 pipe direction control.
0: the corresponding endpoint FIFO is configured as OUT pipe.
1: the corresponding endpoint FIFO is configured as IN pipe.
Bit 7~6
Bit 5~1
If the related SETIO bit is set to ²1², the corresponding endpoint FIFO is configured as IN pipe
for IN token operation. Otherwise, the corresponding endpoint FIFO is configured as OUT pipe
for OUT token operation. The purpose of this function is to avoid the USB host from abnormally
sending only an IN token or OUT token and disable the related endpoint.
Bit 0
DATATG: DATA0 toggle bit
0: no operation.
1: DATA0 will be sent first.
As the USB specification defined, when the USB host sends a ²Set Configuration² SETUP
token, the Data pipe should send the DATA0 (Data toggle) first. Therefore, when the USB device
receives a ²Set Configuration² SETUP token, user needs to set DATATG bit to ²1² and then
clear it to zero after a 2ms delay to generate a positive pulse with 2ms pulse width to make sure
that the next data will send a DATA0 first.
FIFO0~FIFO5 Registers
The FIFO0~FIFO5 Registers are used for data transactions between the USB device and the USB host.
The MCU reads data from or writes data to the FIFOs via the application program to complete data
interchange. For ²Interrupt transfer² it is supported by FIFO0~FIFO2 and FIFO4, while it is supported
by FIFO3 and FIFO5 for ²Bulk transfer².
Label
Type
POR
UMISC Setting Flow and Status
FIFO0
R/W
xxxx xxxx
Data pipe for endpoint 0, depth = 8 bytes
FIFO1
R/W
xxxx xxxx
Data pipe for endpoint 1, depth = 8 bytes
FIFO2
R/W
xxxx xxxx
Data pipe for endpoint 2, depth = 8 bytes
FIFO3
R/W
xxxx xxxx
Data pipe for endpoint 3, depth = 64 bytes
FIFO4
R/W
xxxx xxxx
Data pipe for endpoint 4, depth = 8 bytes
FIFO5
R/W
xxxx xxxx
Data pipe for endpoint 5, depth = 64 bytes
²x² means unknown.
Rev. 1.00
124
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
UIC Register
The UIC register is used to control the interrupt request for each endpoint. Interrupts can be enabled or
disabled independently if the corresponding endpoint FIFO pipes are enabled.
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
EU5I
EU4I
EU3I
EU2I
EU1I
EU0I
R/W
¾
¾
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Unimplemented, read as ²0².
EU5I~EU0I: USB Endpoint 5 ~ Endpoint 0 interrupt control as being accessed.
0: disable the corresponding endpoint interrupt as it is accessed.
1: enable the corresponding endpoint interrupt as it is accessed.
Bit 7~6
Bit 5~0
If the related Endpoint FIFO pipe is enabled and the corresponding Endpoint interrupt is
enabled, the USB interrupt for endpoint access will occur. Then an interrupt signal pulse will be
generated sent to MCU to get the attentions from the host MCU.
NTIM Register
The NTIM register is used to control the NAK token interrupt for each endpoint. The NAK token
interrupt can be masked independently by controlling the NTIM register if the NAK token interrupt
global mask control NMI in SIES register is set to 1.
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
NTI5M
NTI4M
NTI3M
NTI2M
NTI1M
NTI0M
R/W
¾
¾
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Bit 5~0
Rev. 1.00
Unimplemented, read as ²0².
NTI5M~NTI0M: USB Endpoint 5 ~ Endpoint 0 NAK Token Interrupt Mask control.
0: the corresponding endpoint NAK token interrupt is not masked.
1: the corresponding endpoint NAK token interrupt is masked.
If the NAK Token Interrupt global mask control is set to ²1² and the corresponding Endpoint NAK
token interrupt is not masked, the NAK token interrupt will occur when the USB device sends a
NAK token to the USB host. Then an interrupt signal pulse will be generated sent to the host
MCU to get the attentions from the host MCU.
125
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
PIPE Register
The PIPE register is used to control that the FIFO pipe for each endpoint is enabled or disable. The
endpoint access interrupt can be controlled independently by configuring the UIC register if the
corresponding Endpoint FIFO pipe is enabled.
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
EP5E
EP4E
EP3E
EP2E
EP1E
¾
R/W
¾
¾
R/W
R/W
R/W
R/W
R/W
¾
POR
0
0
0
0
0
0
0
0
Unimplemented, read as ²0².
EP5E~EP1E: USB Endpoint 5 ~ Endpoint 0 FIFO pipe enable control.
0: the corresponding Endpoint FIFO Pipe is disabled.
1: the corresponding Endpoint FIFO Pipe is enabled.
Bit 7~6
Bit 5~1
If the corresponding Endpoint FIFO pipe is disabled, the read/write operations to the related
Endpoint FIFO Pipe are not available. If the corresponding Endpoint FIFO Pipe and the interrupt
are both enabled, the related USB Endpoint interrupt will be generated as the interrupt trigger
events occur. Otherwise, if the Endpoint FIFO Pipe or the Endpoint interrupt is disabled, the
corresponding Endpoint interrupt will not be generated.
Unimplemented, read as ²0².
Bit 0
USB Interface Suspend Mode and Wake-up
USB Suspend Mode
The MCU and USB Module are powered down independently of each other. The method of powering
down the MCU is covered in the previous MCU section of the datasheet. The USB Module must be
powered down before the MCU is powered down.
If there is no signal on the USB bus for over 3ms, the devices will go into a suspend mode. The
Suspend indication bit SUSP, bit 0 of the USC register, will be set to ²1² and a USB interrupt will be
generated to indicate that the device should jump to the suspend state to meet the 500mA USB suspend
current specification. In order to meet the 500mA suspend current, the firmware should disable the
USB clock by clearing the USB clock enable control bit USBCKEN in the UCC register to ²0.² Also
the USB PLL circuitry control bits known as PLL should be set to 1 to disable the USB PLL function.
The suspend current is about 400mA.
USB Host Wake-up
When the resume signal is asserted by the USB host, the USB device will wake up the MCU with a
USB interrupt and the Resume indication bit RESUME in the USC register will be set. In order to
make the device function properly, the program must set the USBCKEN bit in the UCC register to ²1²
and clear the PLL bit in the USC register to ²0². When the resume signal is de-asserted by the USB
host, the USB device actually leaves the suspend mode and the USB host will communicate with the
USB device. The SUSP bit will be cleared as well as the RESUME bit when the USB device really
leaves the suspend mode. So when the MCU is detecting the Suspend bit, the Resume bit should be
stored and taken into consideration. The following diagram shows the relationship between the SUSP
and RESUME bits and interrupt signal.
S U S P
R E S U M E
In te r r u p t S ig n a l
Suspend and Host Wake-up
Rev. 1.00
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
USB Remote Wake-up
As the device has a remote wake-up function, it can wake up the USB Host by sending a wake-up pulse
by setting the RMWK bit in the USC register to ²1² for 2ms and then setting the RMWK bit to ²0².
Once the USB Host receives a wake-up signal from the device, it will send a Resume signal to the
device. The timing is as follows:
S U S P
2 m s ( m in .)
R M W K
2 .5 m s
( m in .)
R e s u m e
In te r r u p t S ig n a l
Suspend and Remote Wake-up
USB Interrupt Structure
Several individual USB conditions can generate a USB interrupt. When these conditions exist, an
interrupt pulse will be generated to get the attention of the microcontroller. These conditions are the
USB suspended, USB resume, USB reset and USB endpoint FIFO access events. When the USB
interrupt caused by any of these conditions occurs, if the corresponding interrupt control in the host
MCU is enabled and the stack is not full, the program will jump to the corresponding interrupt vector
where it can be serviced before returning to the main program.
For the USB Endpoint FIFO access event, there are the corresponding indication flags to indicate
which endpoint FIFO is accessed. As the Endpoint FIFO access flag is set, it will generate a USB
interrupt signal if the associated Endpoint FIFO pipe and interrupt control are both enabled. The
Endpoint FIFO access flags should be cleared by the application program. As the USB suspended,
USB resume or USB reset condition occurs, the corresponding indication flag, known as SUSP,
RESUME and URST bits, will be set and a USB interrupt will directly generated without any
associated interrupt control being enabled. The SUSP, RESUME and URST bits are read only and set
or cleared by the USB SIE. For a USB interrupt occurred to be serviced, in addition to the bits for the
corresponding interrupt enable control in USB module being set, the global interrupt enable control
and the related interrupt enable control bits in the host MCU must also be set. If these bits are not set,
then no interrupt will be serviced.
U S C R e g is te r
S u s p e n d in d ic a tio n fla g
S U S P
R e s u m e in d ic a tio n fla g
R E S U M E
In te r r u p t s ig n a l to M C U
R e s e t in d ic a tio n fla g
U R S T
E n d p o in t F IF O a c c e s s
in d ic a tio n fla g E P n IF
0
E U n I
0
E P n E
1
1
U IC R e g is te r
P IP E R e g is te r
U S R R e g is te r
USB Interrupt Structure
Rev. 1.00
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HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Digital to Analog Converter - DAC
The device includes a 12-bit Digital to Analog Converter function. This function allows digital data
contained in the device to generate audio signals.
Operation
The data to be converted is stored in two registers DAL and DAH. The DAH register stores the highest
8-bits, DA11~DA4, while DAL stores the lowest 4-bits, DA3~DA0. An additional control register,
DACTRL, provides overall DAC on/off control in addition to a 3-bit 8-level volume control. The
DAC output is channeled to pin AUD which is pin-shared with I/O pin PA2. When the DAC is enabled
by setting the DACEN bit high, then the original I/O function will be disabled, along with any
pull-high resistor options. The DAC output reference voltage is the power supply voltage VDD.
DAH Register
Bit
7
6
5
4
3
2
1
0
Name
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
0
Bit 7~0
DA11~DA4: Audio Output DAC high byte data.
0: USB reset signal can no reset the MCU
1: USB reset signal will reset the MCU
DAL Register
Bit
7
6
5
4
3
2
1
Name
DA3
DA2
DA1
DA0
¾
¾
¾
R/W
R/W
R/W
R/W
R/W
¾
¾
¾
POR
0
0
0
0
0
0
0
Bit 7~4
DA3~DA0: Audio Output DAC low byte data.
Bit 3~0
Unimplemented, read as ²0².
0
DACTRL Register
Bit
7
6
5
4
3
2
1
0
Name
VOL2
VOL1
VOL0
¾
¾
¾
¾
DACEN
R/W
R/W
R/W
R/W
¾
¾
¾
¾
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~5
VOL2~VOL0: Audio Output Volume control.
The audio output is at maximum volume if these bits are set to 111B while the audio output is at
minimum volume if these bits are set to 000B.
Bit 4~1
Unimplemented, read as ²0².
Bit 0
DACEN: DAC enable Control
0: DAC is disabled
1: DAC is enabled
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
DC/DC Converter and LDO
The device contains a DC/DC Converter and an LDO to provide the power supply for the Smart Card
interface pins and the external Smart Card.
The DC/DC Converter is a PFM step-up DC/DC converter with high efficiency and low ripple. It
requires only three external components to provide an output voltage of either 3.8V or 5.5V selected
by the DC/DC output voltage selection bit VSEL in the DC2DC register. The DC/DC voltage output is
connected to an external pin as well as being connected to the LDO input. It also contains an enable
control bit, DCEN, in the DC2DC register to reduce power consumption when in the power down
mode. If the Smart Card voltage output is switched to 0V by clearing the selection bits VC [1:0] in the
CCR register, the DC/DC converter will automatically be turned off even if the enable control bit
DCEN is set to ²1².
The LDO is a three-terminal high current low voltage dropout regulator with over current protection. It
supports three output voltages of 1.8V, 3.0V or 5.0V selected by the Smart Card Voltage selection bits
VC1 and VC0 in the CCR register. It can deliver a maximum output current of 20mA, 50mA and
55mA when the LDO output voltage is 1.8V, 3.0V and 5.0V respectively.
VDD
SELF
VO
CRDVCC
DC/DC
Converter
CVSS
DCEN
LDO
VSEL
VSS
VC1
VC0
CRST
Smart Card
Interface pins
CC8
VDD
CDET
DC2DC Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
¾
DCEN
VSEL
R/W
¾
¾
¾
¾
¾
¾
R/W
R/W
POR
¾
¾
¾
¾
¾
¾
0
0
Bit 7~2
Bit 1
Unimplemented, read as ²0².
DCEN: DC/DC enable control
0: DC/DC converter disabled
1: DC/DC converter enabled
This bit is used to control the DC/DC converter function. If this bit is set to ²1², the DC/DC
output voltage is selected by the VSEL selection bit. If this bit is cleared to 0, the DC/DC
converter function is disabled and the output voltage is equal to the value of (VDD- VDIODE).
Bit 0
Rev. 1.00
VSEL: DC/DC output voltage selection
0: DC/DC output voltage is 3.8V
1: DC/DC output voltage is 5.5V
129
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Smart Card Interface
The device contains a Smart Card Interface compatible with the ISO 7816-3 standard. This interface
includes the Card Insertion/Removal detection, UART interface control logic and data buffers, Power
control circuits, internal Timer Counters and control logic circuits to perform the required Smart Card
operations. The Smart Card interface acts as a Smart Card Reader to facilitate communication with the
external Smart Card. The overall functions of the Smart Card interface is control by a series of registers
including control and status registers.
As the complexity of ISO7816-3 standard data protocol does not permit comprehensive specifications
to be provided in this datasheet, the reader should therefore consult other external information for a
detailed understanding of this standard.
Elementary
Time Unit
(ETU)
fCRD
SMCEN
fETU
fWTC
Waiting Time
Counter (WTC)
Control Registers
fGTC
UART TX/RX
buffers
CRDVCC
CRST
fETU
UART control
circuits
Power
Control
Guard Time
Counter (GTC)
Clock
Control
CCLK
CRDVCC
CIO
I/O Control
CC4
Interrupt
Registers
CC8
VDD
Card Detection
Interrupt to MCU
CDET
Interface Pins
To communicate with an external Smart Card, the internal Smart Card interface has a series of external
pins known as CRDVCC, CRST, CCLK, CIO, CC4, CC8 and CDET. The CRDVCC pin is the power
supply pin of the external Smart Card and the Smart Card interface pins described above except the
CDET pin. It can output several voltage levels as selected by the VC1 and VC0 selection bits. The
CRST pin is the reset output signal which is used to reset the external Smart Card. Together with the
internal CRST control bit the MCU can control the CRST pin level by writing specific data to the
CRST bit and obtain the CRST pin status by reading the CRST bit. The CCLK pin is the clock output
signal used to communicate with the external Smart Card together with the serial data pin, CIO. The
operation of CCLK and CIO can be selected as the UART mode automatically driven by the UART
control circuits, or the Manual mode controlled by configuring the internal CCLK and CIO bits
respectively by the application program. The CDET pin is the external Smart Card detection input pin.
When the external Smart Card is inserted or removed, it can be detected and generate an interrupt
signal which is sent to MCU if the corresponding interrupt control bit is enabled. The CC4 and CC8
pins are used as I/O pins and are controlled by the corresponding CC4 and CC8 bits.
Card Detection
If an external Smart Card is inserted, the internal card detector can detect this insertion operation and
generate a Card insertion interrupt. When the Card is present and detected, the power-on sequence for
the external Smart Card should be activated by the application programs to supply power for the
external Smart Card. Similarly if the Card is removed, the internal card detector can also detect the
removal and consequently generate a Card removal interrupt. Like the Card insertion operation, the
Card Removal deactivation procedure defined in the ISO 7816-3 standard should be activated by the
application programs.
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
The card detector can support two kinds of card detect switch mechanisms. One is a normally open
switch mechanism when the card is not present and the other is a normally closed switch mechanism.
After noting which card detect switch mechanism type is used, the card switch selection should be
configured by setting the selection bit CDET in the CCR Register to correctly detect the Card
presence. No matter what type of the card switch is selected by configuring the CDET bit, the Card
Insertion/Removal Flag, CIRF, in the CSR register will be set to ²1² when the card is actually present
on the CDET pin. Note that there is no hardware de-bounce circuits in the card detector. Any change of
the CDET pin level will cause the CIRF bit to change. The required de-bounce time should be handled
by the application program.
There is a pull high resistor integrated in the card detector. A configuration option can determine
whether the pull high resistor is internally connected to the CDET pin.
Internal Time Counter - ETU, GTC, WTC
For proper data transfer, some timing purposed setting procedures must be executed before the Smart
Card Interface can begin to communicate with the external card. There are three internal counters
named Elementary Time Unit (ETU), Guard Time Counter (GTC) and Waiting Time Counter (WTC)
which are used for the timing related functions in the Smart Card interface operation.
Elementary Time Unit - ETU
The Elementary Time Unit (ETU) is an 11-bit up-counting counter and generates the clock, denoted as
fETU to be used as the operating frequency for the UART transmission and reception in the Smart Card
interface. The clock source of the ETU comes from the Smart Card clock named fCRD derived from the
high speed clock fM. The fCRD clock frequency can be equal to the frequency of fM, fM/2, fM/3 or fM/4
selected by the Smart Card clock source selection bits, CRDCKS1 and CRDCKS0. The data transfer
of the UART interface is a character frame based protocol, which is basically consists of a Start bit,
8-bit data and a Parity bit. The time period tETU (1/fETU), generated by the ETU, is the time unit for
UART character bit. There are two registers related to the ETU known as the low byte ETU register
CETU0 and the high byte ETU register CETU1, which store the expected contents of the ETU. Each
time the high byte ETU register CETU1 is written, the ETU will reload the new written value and
restart counting. The elementary time unit tETU is obtained from the following formula.
tETU=
F
1
x
D
f
F: clock rate conversion integer
D: baud rate adjustment integer
F: clock rate of Smart Card
The values of F and D, as they appear in the above formula, will be obtained from the Answer-to-Reset
packet sent from the external Smart Card to the Smart Card interface, the first time the external Smart
Card is inserted. When the Smart Card interface receives this information, the values which should be
written into the CETU0 and CETU1 can be calculated by F/D. As the value of the ETU registers is
obtained by the above formula, the calculation results of the value may not be an integer. If the
calculation result is not an integer and is less than the integer n but greater than the integer (n-1), either
the integer n or (n-1) should be written into the CETU0 and CETU1 registers depending upon whether
the result is closer to n or (n-1). The integer n mentioned here is a decimal. If the calculation result is
close to the value of (n-0.5), the compensation mode should be enabled by setting the compensation
enable control bit COMP in the CETU1 register to 1 for successful data transfer. When the result is
close to the value of (n-0.5) and the compensation mode is enabled, the value written into the CETU0
and CETU1 registers should be n and then the ETU will generate the time unit sequence with n clock
cycles and next (n-1) clock cycles alternately and so on. This results in an average time unit of (n-0.5)
clock cycles and allows the time granularity down to a half clock cycle. Note that the ETU will reload
the ETU registers value and restart counting at the time when the Start bit appears in the UART mode.
Rev. 1.00
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HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Start bit
Parity bit
Data bits
CIO
P
tETU
n
n
n
n
Character
n n n
n
n
n
COMP=0
(CETU=n)
(1 tETU=n clocks)
COMP=1
n n-1 n n-1 n n-1 n n-1 n n-1
Character Frame and Compensation Mode
Guard Time Counter - GTC
The Guard Time Counter (GTC) is a 9-bit up-counting counter and generates the minimum time
duration known as a character frame denoted as tGTC between two successive characters in a UART
transmission. The clock source of the GTC comes from the ETU named fETU. The character
transmission rate of the UART interface is controlled by tGTC generated by the GTC. There are two
registers related to the GTC known as the low byte GTC register, CGT0, and the high byte GTC
register, CGT1, which store the expected value of the GTC. The GTC value will be reloaded at the end
of the current guard time period. Note that the guard time between the last character received from the
Smart Card and the next character transmitted by the Smart Card interface (Smart Card reader) should
be managed by the application program.
Waiting Time Counter - WTC
The Waiting Time Counter (WTC) is a 24-bit down-counting counter and generates a maximum time
duration denoted as tWTC for the data transmission. The clock source of the WTC comes from the ETU
named fETU. The data transfer is categorized into 2 types. One is the Character transfer which means
each data transmission or reception is one character while the other is the Blocks transfer which means
each data transmission or reception is more than one character. The information related to the data
transfer type or the number of the characters to be transferred is contained in the Answer-to-Reset
packet.
There are three data registers for the WTC known as the low byte WTC register CWT0, the middle
byte WTC register CWT1 and the high byte WTC register CWT2, which store the expected WTC
values. The WTC can be used in both UART mode and Manual mode and can reload the value at
specific conditions. The function of the WTC is controlled by the WTEN bit in the CCR register or by
a configuration option. When the UART interface is set to be operated in the UART mode and the
WTC is enabled, the updated CWT value will be loaded into the WTC as the Start bit is detected. If the
UART interface is set to be operated in the Manual mode and the WTC is enabled, the updated CWT
value will be loaded into the WTC. Regardless of whether it is in the UART mode or Manual mode, if
the WTEN bit is cleared to ²0², the updated CWT value will not be loaded into the WTC until the
WTEN bit is again set to 1 and the WTC underflows from the current loaded value.
When the transfer type is configured as a Character transfer, the WTC will generate the maximum
timeout period of the Character Waiting Time (CWT). If the transfer type is configured as a Block
transfer, the WTC will generate the Character Waiting Time (CWT) except for the last character. The
Block Waiting Time (BWT) should be loaded into the WTC data registers before the Start bit of the
last transmitted character occurs. As the Start bit of the last transmitted character occurs, the BWT
value will be load into the WTC. Then the Smart Card may be expected to transmit data to the Smart
Card interface in the BWT duration. If the Smart Card does not transmit any data characters, the WTC
will underflow. When the WTC underflows, the corresponding request flag, WTF, in the CSR register
Rev. 1.00
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
will be set. The Waiting Time Underflow pending flag, WTP, in the CIPR register, will also be set if
the interrupt enable control bit, WTE, in the CIER register is set. Then an interrupt will be generated to
notify the MCU that the Smart Card has not responded to the Smart Card reader. Note that if the WTC
value is set to zero, the WFT bit will be equal to ²1².
Start bit
Program the CWT
Program the BWT
Smart Card
Interface
Char 0
Char 1
Char n
Smart Card
Char 0
BWT
WTC is reloaded on Start bit
Char 1
CWT
Start bit
UART Interface
Data transfer with the external Smart Card is implemented into two operating modes. One is the UART
mode while the other is the Manual mode. The data transfer mode is selected by the UART mode
selection bit, UMOD, in the CCR register. When the UMOD bit is set to ²1², the UART mode is
enabled and data transfer operates in the UART mode. Otherwise, data transfer operates in the Manual
mode if the UMOD bit is set to ²0². The UART interface is a half-duplex interface and communicates
with the external Smart Card via the CCLK and CIO pins. The CIO pin can be selected to be connected
to a pull high resistor by a configuration option. After a reset condition the UART interface is in the
reception mode but the UART mode is disabled. When the UART mode is selected, data transfer is
driven by the UART circuits automatically through the CCLK and CIO pins.
There are two data registers related to data transmission and reception, CTXB and CRXB, which store
the data to be transmitted and received respectively. If a character is written into the CTXB register in
the UART mode, the UART interface will automatically switch to the transmission mode from the
reception mode after a reset. When the UART transmission or reception has finished, the
corresponding request flag named TXCF or RXCF is set to ²1². If the transmit buffer is empty, the
transmit buffer empty flag, TXBEF, will be set to ²1².
The UART interface supports a parity generator and a parity check function. As the parity error occurs
during a data transfer, the corresponding request flag named, PARF, in the CSR register will be set to
²1². Once the PARF bit is set to ²1², the Parity error pending flag PARP in the CIPR register will be set
to ²1² if the relevant interrupt control bit is enabled. Then an interrupt signal will be generated and sent
to the MCU.
There is a Character Repetition function supported by the UART interface when a parity error occurs.
The Character repetition function is enabled by setting the CREP bit to ²1² and then the repetition
function is activated when the parity error occurs during data transfers. The repetition times can be
selected to be 4 or 5 times by a configuration option. When the CREP bit is set to ²1² and the repetition
times is set to 4 times, the UART interface, if in the transmission mode, will transmit the data
repeatedly for 4 times at most when an error signal occurs. If the data transmitted by the UART
interface is received by the Smart Card receiver without a parity error during these 4 transmissions, the
transmission request flag, TXCF, of the UART interface will be set to ²1² and the PARF bit will be
cleared to ²0². If the UART interface is informed that there is still an error signal during the 4
transmissions, the parity error flag PARF of the UART interface will be set to ²1² at the 5th
transmission but the transmission request flag TXCF will not be set. If the UART interface is in the
reception mode, it will inform the Smart Card transmitter that there is a parity error for at most 4 times.
If the data transmitted by the Smart Card transmitter is received by the UART interface without a parity
error during the 4 receptions, the reception request flag, RXCF, of the UART interface will be set to ²1²
and the PARF bit will be cleared to ²0². If the UART interface informs the Smart Card that there is still
an error signal during the 4 receptions, the parity error flag, PARF, of the UART interface will be set to
²1² at the 5th reception as well as the transmission request flag, RXCF.
Rev. 1.00
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December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
If the CREP bit is set to ²0² and the UART interface is in the reception mode, both the PARF and RXCF
bits will be set to ²1² when the data with parity error has been received but the character repetition will
not be activated. If the UART interface is in the transmission mode and the CREP bit is set to ²0², it acts
as a normal transmitter and the TXCF bit is set to ²1² after the data has been transmitted. It has no effect
on PARF bit.
When data is selected to be transferred in the Manual mode by setting the UMOD bit to ²0², the data is
controlled by the control bit, CIO, in the CCCR register. The value of the CIO bit will be reflected
immediately on the CIO pin in the Manual mode. Note that in the Manual mode the character
repetition function is not used as well as the related flags and all the data transfer is handled by the
application program. The clock used to drive the external Smart Card that appears on the CCLK pin
can be derived from the internal clock source known as the fCRD clock or the control bit, CCLK, in
CCCR register and selected by the Smart Card selection bit, CLKSEL, in the CCCR register. When
CLKSEL is set to ²1² to select the clock source for the Smart Card to be fCRD, a configuration option
can determine whether the clock output on the CCLK pin, which comes from the fCRD clock, is to be
divided by 2 or not. If users wish to handle the CCLK clock manually, the CLKSEL bit should first be
set to 0 and then the value of the CCLK bit will be present on the CCLK pin.
When the Smart Card is first inserted, the data direction convention is sent first in the Answer-to-Reset
packet to inform the Smart Card interface whether the MSB of the data is sent first or the LSB is sent
first. If the direction convention used by the Smart Card is the same as the convention used by the
Smart Card interface, the UART interface will generate a reception interrupt if the reception interrupt
is enabled without a parity error flag. Otherwise, the UART interface will generate a reception
interrupt and the parity error flag will be asserted. By checking the parity error flag the Smart Card
interface can know if the data direction convention is correct or not.
Power Control
When the Smart Card is first inserted and detected, the power-on sequence for the external Smart Card
should be activated by the application programs to supply power to the external Smart Card. All the
information necessary for the Smart Card interface to communicate with the external Card is contained
in the Answer-to-Reset packet including the data transfer type (Character or Blocks), the data direction
convention (MSB or LSB first), the clock rate information (ETU, GTC or WTC), etc. The voltage
level supplied to the Smart Card is also defined in the Answer-to-Reset packet. The Smart Card power
supply voltage level is generated by the LDO and selected by the Smart Card Power Supply voltage
selection bits VC1 and VC0 in the CCR register. When the external Smart Card is inserted, the
application program should set the CRDVCC pin to the expected voltage level defined in the
Answer-to-Reset packet. Similarly, the power deactivation procedure defined in the ISO 7816-3
standard should also be properly arranged by the application programs when the external Smart Card
is removed. After the external Smart Card is removed, the Smart Card Interface Circuitry enable
control bit, CVCC, in the CCCR Register will be automatically cleared to zero to prevent the Smart
Card Interface module from being re-modified. The CRDVCC pin voltage level and the related Smart
Card interface register contents will remain unchanged but the relevant Smart Card Interface pins
including CRST, CCLK, CIO, CC4 and CC8 pins will be kept at a low level when the external Card is
removed.
The Power Control circuitry provides the Card voltage and current indicators to avoid malfunctions.
When the Card voltage is within its specified range, the Card Voltage flag VCOK will be set to ²1². If
the Card is not in the specified range, the VCOK flag will be cleared to ²0² to indicate that the Card
voltage is not within the specified range. As the VCOK bit changes from 1 to 0, the corresponding
pending flag named VCP in CIPR register will be set to ²1² if the Card Voltage error interrupt control
VCE in the CIER register is enabled.
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
When the current consumed by the external Smart Card is within the range specified in the ISO 7816-3
standard, the Card Current Overload flag IOVF will remain at a ²0² value. If the Card current is not
within the specified range, the IOVF flag will be set to ²1² to indicate that the Card Current is too high.
As the IOVF bit is set to 1, the relevant pending flag, IOVFP, in the CIPR register will also be set to 1 if
the Card Current Overload interrupt control enable bit, IOVFE, in the CIER register is enabled.
Card Class
ClassA
ClassB
ClassC
Operation Voltage
3.6~5.5
2.5~5.5
2.5~5.5
Operation Frequency
Maximum
20MHz (VCC³4.0V)
20MHz (VCC³4.0V)
20MHz (VCC³4.0V)
12MHz (VCC³3.6V)
12MHz (VCC³3.0V)
12MHz (VCC³3.0V)
Smart Card Class Operating Conditions
Smart Card Interrupt Structure
There are several conditions for the Smart Card that to generate a Smart Card interrupt. When these
conditions exist, an interrupt pulse will be generated to get the attention of the microcontroller. These
conditions are a Smart Card Insertion/Removal, a Smart Card Voltage error, a Smart Card Current
Overload, a Waiting Time Counter Underflow, a Parity error, an end of a Character Transmission or
Reception and an empty Transmit buffer. When a Smart Card interrupt is generated by any of these
conditions, then if the corresponding interrupt enable control bit in the host MCU is enabled and the
stack is not full, the program will jump to the corresponding interrupt vector where it can be serviced
before returning to the main program.
For Smart Card interrupt events, except for Card Insertion/Removal events, there are corresponding
pending flags which can be masked by the corresponding interrupt enable control bits. When the
related interrupt enable control is disabled, the corresponding interrupt pending flag will not be
affected by the request flag and no interrupt will be generated. If the related interrupt enable control is
enabled, the relevant interrupt pending flag will be affected by the request flag and then the interrupt
will be generated. The pending flag register CIPR is read only and once the pending flag is read by the
application program, it will be automatically cleared while the related request flag should be cleared
by the application program manually.
Card Insertion/Removal
Request flag CIRF
Interrupt Signal to MCU
0
Transmit Buffer Empty
request flag TXBEF
TXBEE
End of Transmission
Request flag TXCF
TXCE
End of Reception
Request flag RXCF
RXCE
0
End of Reception
pending flag RXCP
1
Interrupt Signal to MCU
0
PARE
WTC Underflow
Request flag WTF
WTE
Card Current Overload
Request flag IOVF
IOVFE
CSR Register
End of Transmission
pending flag TXCP
1
0
Parity Error
Request flag PARF
Card Voltage Status
Request flag VCOK
Transmit Buffer Empty
pending flag TXBEP
1
Parity Error
pending flag PARP
1
0
WTC Underflow
pending flag WTP
1
0
Card Current Overload
pending flag IOVFP
1
0
VCE
Card Voltage Error
pending flag VCP
1
CIER Register
CIPR Register
Smart Card Interrupt Structure
Rev. 1.00
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
When a Smart Card Insertion/Removal event occurs, the Card Insertion/Removal request flag, CIRF,
will be set and a Smart Card Insertion/Removal interrupt will be directly generated without any
associated interrupt control being enabled.
For a Smart Card interrupt occurred to be serviced, in addition to the bits for the corresponding
interrupt enable control in the Smart Card interface being set, the global interrupt enable control and
the related interrupt enable control bits in the host MCU must also be set. If these bits are not set, then
no interrupt will be serviced.
Programming Considerations
Since the whole Smart Card interface is driven by the clock fCRD which is derived from the high speed
oscillator clock fM, the Smart Card interface will not operate, even interface registers read/write
operations, if the high speed oscillator clock fM is stopped. For example, if the MCU clock source is
switched to the low speed clock fSL which comes from the low speed oscillator LXT or LIRC, then all
operations related to the Smart Card interface are not performed.
If the frequency of the clock fCRD is slower than the frequency of the high speed oscillator clock fM
divided by 2, it will result in synchronization problems between two different clock domains known as
the CPU clock and the Smart Card interface clock.
Smart Card interface Status and Control Registers
There are several registers associated with the Smart Card function. Some of the registers control the
overall function of the Smart Card interface as well as the interrupts, while some of the registers
contain the status bits which indicate the Smart Card data transfer situations, error conditions and
power supply conditions. Also there are two registers for the UART transmission and reception
respectively to store the data received from or to be transmitted to the external Smart Card.
Addres
s
Name
POR State
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
50H
CCR
0000 0000
RSTCRD
CDET
VC1
VC0
UMOD
WTEN
CREP
CONV
51H
CSR
1000 0000
TXBEF
CIRF
IOVF
VCOK
WTF
TXCF
RXCF
PARF
52H
CCCR
0-xx x0x0
CLKSEL
¾
CC8
CC4
CIO
CCLK
CRST
CVCC
53H
CETU1
0000 0001
COMP
¾
¾
¾
¾
ETU10
ETU9
ETU8
54H
CETU0
0111 0100
ETU7
ETU6
ETU5
ETU4
ETU3
ETU2
ETU1
ETU0
55H
CGT1
---- ---0
¾
¾
¾
¾
¾
¾
¾
GT8
56H
CGT0
0000 1100
GT7
GT6
GT5
GT4
GT3
GT2
GT1
GT0
57H
CWT2
0000 0000
WT23
WT22
WT21
WT20
WT19
WT18
WT17
WT16
58H
CWT1
0010 0101
WT15
WT14
WT13
WT12
WT11
WT10
WT9
WT8
59H
CWT0
1000 0000
WT7
WT6
WT5
WT4
WT3
WT2
WT1
WT0
5AH
CIER
0-00 0000
TXBEE
¾
IOVFE
VCE
WTE
TXCE
RXCE
PARE
5BH
CIPR
0-00 0000
TXBEP
¾
IOVFP
VCP
WTP
TXCP
RXCP
PARP
5CH
CTXB
0000 0000
Smart Card Transmission Buffer (TB7~TB0)
5DH
CRXB
0000 0000
Smart Card Reception Buffer (RB7~RB0)
Smart Card Interface Register Summary
Rev. 1.00
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
CCR Register
The CCR register contains the control bits for the Smart Card interface. Further explanation on each bit
is given below:
Bit
7
6
5
4
3
2
1
0
Name
RSTCRD
CDET
VC1
VC0
UMOD
WTEN
CREP
CONV
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5~4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
RSTCRD: Reset control for the Smart Card interface
0: No Smart Card interface reset
1: Reset the Smart Card interface (except RSTC bit)
This bit is used to reset the whole Smart Card interface except the RSTCRD bit. It is set and
cleared by application program.
CDET: Card switch type selection
0: Switch is normally opened if no card is present
1: Switch is normally closed if no card is present
This bit is set and cleared by application program to configure the switch type of the card
detector.
VC1~VC0: Card voltage selection
00: Card voltage is equal to 0V
01: Card voltage is equal to 1.8V
10: Card voltage is equal to 3V
11: Card voltage is equal to 5V
These bits are set and cleared by application program to select the voltage level for the external
Smart Card.
UMOD: UART mode selection
0: data transfer in Manual mode.
1: data transfer in UART mode.
This bit is set and cleared by application program to configure the data transfer type. If it is
cleared to 0, the CIO pin status is the same as the value of the CIO bit in the CCCR register. If it
is set to 1, the CIO pin is driven by the internal UART control circuitry. Before the data transfer
type is switched from Manual mode to UART mode, the CIO bit must be set to 1 to avoid
a UART malfunction.
WTEN: Waiting Time Counter (WTC) counting control
0: WTC tops counting.
1: WTC starts to count.
The WTEN bit is set and cleared by application program. When the WTEN bit is cleared to 0,
a write access to the CWT2 register will load the value held in the CWT2~CWT0 registers into
the WTC. If it is set to 1, the WTC is enabled and automatically reloaded with the value in
CWT2~CWT0 at each start bit occurrence.
CREP: Character Repetition enable control at parity error condition
0: no retry on parity error
1: automatically retry on parity error
The CREP bit is set and cleared by application program. When the CREP bit is cleared to 0,
both the RXCF and PARF flags will be set on parity error in reception mode after the data is
received while the PARF is set but the TXCF is cleared in the transmission mode. If the CREP
bit is set to 1, the character retry will automatically be activated on parity error for 4 or 5 times
depending upon the configuration option. In the transmission mode the character will be
re-transmitted if the transmitted data is refused and then the parity error flag PARF will be set at
5th or 6th transmission but TXCF will not be set. In the reception mode if the received data has a
parity error, the receiver will inform the transmitter for 4 or 5 times and then the PARF and RXCF
flags will both be set at 5th or 6th reception.
CONV: Data direction convention
0: LSB is transferred first.
1: MSB is transferred first.
This bit is set and cleared by the application program to select if the data is LSB transferred
first or MSB transferred first. When the direction convention is the same as the direction specified
by the external Smart Card, only RXCF will be set to 1 without parity error. Otherwise, both RXCF
and PARF will be set to 1 after the data is received.
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
CSR Register
The CSR register contains the status bits for the Smart Card interface. Further explanation on each bit
is given below:
Bit
7
6
5
4
3
2
1
0
Name
TXBEF
CIRF
IOVF
VCOK
WTF
TXCF
RXCF
PARF
R/W
R
R
R
R
R
R/W
R
R/W
POR
1
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
TXBEF: Transmission buffer empty request flag
0: transmission buffer is not empty
1: transmission buffer is empty
This bit is used to indicate if the transmit buffer is empty and is set or cleared by hardware
automatically.
CIRF: Card Insertion/Removal request flag
0: No card is present.
1: a Card is present
This bit is used to indicate if a card is present and is set or cleared by hardware automatically.
IOVF: Card Current Overload request flag
0: No Card Current overload
1: Card Current overload
The bit is set or cleared by hardware automatically and indicates whether the card current is
overloaded.
VCOK: Card Voltage status flag
0: Card Voltage is not in the specified range
1: Card Voltage is in the specified range
The bit is set or cleared by hardware automatically and indicates whether the card voltage is in
the specified range.
WTF: Waiting Time Counter (WTC) underflow request flag
0: the WTC does not underflow.
1: the WTC underflows.
This bit is set and cleared by application program and indicates if the WTC underflows.
TXCF: Character transmission request flag
0: no character transmitted request
1: a character has been transmitted
The TXCF bit is set by hardware and cleared by application program. If the bit is set to 1,
it indicates that the character has been transmitted.
RXCF: Character Repetition request flag
0: no character received request
1: a character has been received
The RXCF bit is set by hardware automatically and cleared after a read access to the CRXB
register by the application program. The RXCF bit will always be set to 1 when a character is
received regardless of the result of the parity check. When the character has been received, the
received data stored in the CRXB register should be moved to the data memory specified by
users. If the contents of the CRXB register are not read before the end of the next character
shifted in, the data stored in the CRXB register will be overwritten.
PARF: Parity error request flag
0: no parity error request
1: parity error has been occurred
This bit is set by hardware automatically and cleared by the application program. When a
character is received, the parity check circuits will check that the parity is correct or not. If the
result of the parity check is not correct, the parity error request flag, PARF, will be set to 1.
Otherwise, the PARF bit will remain at zero.
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
CCCR Register
The CCCR register contains the control bits of the Smart Card interface pins. Further explanation on
each bit is given below:
Bit
7
6
5
4
3
2
1
0
Name
CLKSEL
¾
CC8
CC4
CIO
CCLK
CRST
CVCC
R/W
R/W
¾
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
x
x
x
0
x
0
x: unknown
Bit 7
CLKSEL: Smart Card Clock selection
0: The content of the CCLK bit is present on the external CCLK pin
1: The clock output on the external CCLK pin comes from the fCRD clock
This bit is used to select the clock source on the external CCLK pin. It is set and cleared by
application program. It is recommended that to activate the clock at a known level a certain value
should be programmed into the CCLK bit before the CLKSEL bit is switched from 1 to 0.
Bit 6
Bit 5
Unimplemented, read as ²0²
CC8: CC8 pin control
0: the status of the external CC8 pin is 0
1: the status of the external CC8 pin is 1
The bit is set and cleared by application program to control the external CC8 pin status. The
value written into this bit will be present on the external CC8 pin. Reading this bit will return the
status present on the CC8 pin.
CC4: CC4 pin control
0: the status of the external CC4 pin is 0
1: the status of the external CC4 pin is 1
The bit is set and cleared by application program to control the external CC4 pin status. The
value written into this bit will be present on the external CC4 pin. Reading this bit will return the
status present on the CC4 pin.
CIO: CIO pin control
0: the status of the external CIO pin is 0
1: the external CIO pin remains at an open drain condition
This bit is available only if the UMOD bit in the CCR register is cleared to 0 (Manual mode). It is
set and cleared by application program to control the external CIO pin status in Manual mode.
Reading this bit will return the status present on the CIO pin. A pull high resistor can be
connected to the CIO pin determined by a configuration option.
CCLK: CCLK pin control
0: the status of the external CCLK pin is 0
1: the status of the external CCLK pin is 1
This bit is available only if the UMOD bit in the CCR register is cleared to 0 (Manual mode). The
bit is set and cleared by application program to control the external CCLK pin status in Manual
mode. Reading this bit will return the current value in the register instead of the status present on
the CCLK pin.
CRST: CRST pin control
0: the status of the external CRST pin is 0
1: the status of the external CRST pin is 1
This bit is set and cleared by application program to control the external CRST pin status to be
used to reset the external Smart Card. Reading this bit will return the present status of the CRST
pin.
CVCC: Smart Card Interface Circuitry enable control
0: Smart card interface circuitry is disabled
1: Smart card interface circuitry is enabled.
This bit is set and cleared by application program to control the Smart card interface module is
switched on or off when the external Card is present. If the external Card is not present on the
CDET pin, this bit is not available to control the Smart card interface circuitry and will
automatically be cleared to 0 by hardware.
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
CETU Registers
The CETU registers, CETU1 and CETU0, contain the specific values determined by the formula
described in the ETU section. It also includes a control bit of the Compensation function for the ETU
time granularity. Note that the value of the ETU must be in the range of 00CH to 7FFH. To obtain the
maximum ETU decimal value of 2048, a 000H value should be written into the ETU10~ETU0 bits.
Further explanation on each bit is given below:
Bit
7
6
5
4
3
2
1
0
Name
COMP
¾
¾
¾
¾
ETU10
ETU9
ETU8
R/W
R/W
¾
¾
¾
¾
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
1
Bit 7
COMP: Compensation function enable control
0: Compensation function is disabled.
1: Compensation function is enabled.
This bit is set and cleared by application program used to control the Compensation function.
The Compensation function has been described and more details can be obtained in the ETU
section.
Bit 6~3
Bit 2~0
Unimplemented, read as ²0².
ETU10~ETU8: bit 10~8 of the ETU value
The bits are set and cleared by application program to modify the ETU values. Writing to the
CETU1 register will reload the updated value into the ETU counter.
CETU0 Register
Bit
7
6
5
4
3
2
1
0
Name
ETU7
ETU6
ETU5
ETU4
ETU3
ETU2
ETU1
ETU0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
1
1
0
1
0
0
Bit 7~0
Rev. 1.00
ETU7~ETU0: bit 7~0 of the ETU value
The bits are set and cleared by application program to modify the ETU values.
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
CGT Registers
The CGT registers named CGT1 and CGT0 store the specific GTC values obtained from the
Answer-to-Reset packet described in the GTC section. Note that the GTC values must be in the range
from 00CH to 1FFH. Further explanation on each bit is given below:
·
CGT1 Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
¾
¾
GT8
R/W
¾
¾
¾
¾
¾
¾
¾
R/W
POR
0
0
0
0
0
0
0
0
Unimplemented, read as ²0²
GT8: bit 8 of the GTC value
Bit 7~1
Bit 0
·
CGT0 Register
Bit
7
6
5
4
3
2
1
0
Name
GT7
GT6
GT5
GT4
GT3
GT2
GT1
GT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
1
1
0
0
Bit 7~0
GT7~GT0: bit 7~0 of the GTC value
The bits GT8~GT0 are set and cleared by application program to modify the GTC values. The updated GTC value will be loaded into the GTC counter at the end of the current guard time period.
CWT Registers
The CWT registers, CWT2, CWT1 and CWT0, store the specific WTC value obtained from the
Answer-to-Reset packet described in the WTC section. Note that the GTC value must be in the range
from 00CH to 1FFH.
·
CWT2 Register
Bit
7
6
5
4
3
2
1
0
Name
WT23
WT22
WT21
WT20
WT19
WT18
WT17
WT16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
WT23~WT16: bit 23~16 of the value
·
CWT1 Register
Bit
7
6
5
4
3
2
1
0
Name
WT15
WT14
WT13
WT12
WT11
WT10
WT9
WT8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
1
0
0
1
0
1
Bit 7~0
Rev. 1.00
WT15~WT8: bit 15~8 of the WTC value
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
·
CWT0 Register
Bit
7
6
5
4
3
2
1
0
Name
WT7
WT6
WT5
WT4
WT3
WT2
WT1
WT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
0
0
0
0
0
0
0
Bit 7~0
WT7~WT0: bit 7~0 of the WTC value
The bits WT23~WT0 are set and cleared by application program to modify the GTC values. The reload conditions of the updated WTC value are described in the WTC section. Users can refer to the
WTC section for more details.
CIER Register
The CIER register contains the interrupt enable control bits for all of the interrupt events in the Smart
Card interface. Further explanation on each bit is given below:
Bit
7
6
5
4
3
2
1
0
Name
TXBEE
¾
IOVFE
VCE
WTE
TXCE
RXCE
PARE
R/W
R/W
¾
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
TXBEE: Transmit Buffer Empty interrupt enable control
0: disable
1: enable
This bit is set and cleared by application program used to control the Transmit Buffer Empty
interrupt. If this bit is set to 1, the Transmit Buffer Empty interrupt will be generated when the
Transmit Buffer is empty.
Bit 6
Bit 5
Unimplemented, read as ²0²
IOVFE: Card Current Overload interrupt enable control
0: disable
1: enable
This bit is set and cleared by application program and is used to control the Card Current
Overload interrupt. If this bit is set to 1, the Card Current Overload interrupt will be generated
when the Card Current is overloaded.
VCE: Card Voltage Error interrupt enable control
0: disable
1: enable
This bit is set and cleared by application program and is used to control the Card Voltage Error
interrupt. If this bit is set to 1, the Card Voltage Error interrupt will be generated when the Card
Voltage is not in the specified range.
WTE: Waiting Time Counter Underflow interrupt enable control
0: disable
1: enable
Bit 4
Bit 3
This bit is set and cleared by application program and is used to control the Waiting Time
Counter Underflow interrupt. If this bit is set to 1, the Waiting Time Counter Underflow interrupt
will be generated when the WTC underflows.
Bit 2
Rev. 1.00
TXCE: Character Transmission Completion interrupt enable control
0: disable
1: enable
This bit is set and cleared by application program and is used to control the Character
Transmission Completion interrupt. If this bit is set to 1, the Character Transmission
Completion interrupt will be generated at the end of the character transmission.
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Bit 1
RXCE: Character Reception Completion interrupt enable control
0: disable.
1: enable.
This bit is set and cleared by application program and is used to control the Character
Reception Completion interrupt. If this bit is set to 1, the Character Reception Completion
interrupt will be generated at the end of the character reception.
Bit 0
PARE: Parity Error interrupt enable control
0: disable
1: enable
This bit is set and cleared by application program and is used to control the Parity Error
interrupt. If this bit is set to 1, the Parity Error interrupt will be generated when a parity error
occurs.
CIPR Register
The CIPR register contains the interrupt pending flags for all of the interrupt events in the Smart Card
interface. These pending flags can be masked by the corresponding interrupt enable control bits.
Further explanation on each bit is given below:
Bit
7
6
5
4
3
2
1
0
Name
TXBEP
¾
IOVFP
VCP
WTP
TXCP
RXCP
PARP
R/W
R
¾
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Rev. 1.00
TXBEP: Transmit Buffer Empty interrupt pending flag
0: no interrupt pending.
1: interrupt pending.
This bit is set by hardware and cleared by a read access to this register using the application
program. It is used to indicate if there is a Transmit Buffer Empty interrupt pending or not. If the
corresponding interrupt enable control bit is set to 1 and the Transmit Buffer is empty, this bit will
be set to 1 to indicate that the Transmit Buffer Empty interrupt is pending.
Unimplemented, read as 0.
IOVFP: Card Current Overload interrupt pending flag
0: no interrupt pending.
1: interrupt pending.
This bit is set by hardware and cleared by a read access to this register using the application
program. It is used to indicate if there is a Card Current Overload interrupt pending or not. If the
corresponding interrupt enable control bit is set to 1 and the Card Current is overloaded, this bit
will be set to 1 to indicate that the Card Current Overload interrupt is pending.
VCP: Card Voltage Error interrupt pending flag
0: no interrupt pending.
1: interrupt pending.
This bit is set by hardware and cleared by a read access to this register using the application
program. It is used to indicate if there is a Card Voltage Error interrupt pending or not. If the
corresponding interrupt enable control bit is set to 1 and the Card Voltage is not in the specified
range, this bit will be set to 1 to indicate that the Card Voltage Error interrupt is pending.
WTP: Waiting Time Counter Underflow interrupt pending flag
0: no interrupt pending.
1: interrupt pending.
This bit is set by hardware and cleared by a read access to this register using the application
program. It is used to indicate if there is a Waiting Time Counter Underflow interrupt pending or
not. If the corresponding interrupt enable control bit is set to 1 and the WTC underflows, this bit
will be set to 1 to indicate that the Waiting Time Counter Underflow interrupt is pending.
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Bit 2
TXCP: Character Transmission Completion interrupt pending flag
0: no interrupt pending.
1: interrupt pending.
This bit is set by hardware and cleared by a read access to this register using the application
program. It is used to indicate if there is a Character Transmission Completion interrupt pending
or not. If the corresponding interrupt enable control bit is set to 1 and a character has been
transmitted, this bit will be set to 1 to indicate that the Character Transmission Completion
interrupt is pending.
RXCP: Character Reception Completion interrupt pending flag
0: no interrupt pending.
1: interrupt pending.
This bit is set by hardware and cleared by a read access to this register using the application
program. It is used to indicate if there is a Character Reception Completion interrupt pending or
not. If the corresponding interrupt enable control bit is set to 1 and a character has been received,
this bit will be set to 1 to indicate that the Character Reception Completion interrupt is pending.
PARP: Parity Error interrupt pending flag
0: no interrupt pending.
1: interrupt pending.
This bit is set by hardware and cleared by a read access to this register using the application
program. It is used to indicate if there is a Parity Error interrupt pending or not. If the
corresponding interrupt enable control bit is set to 1 and the parity error occurs, this bit will be set
to 1 to indicate that the Parity Error interrupt is pending.
Bit 1
Bit 0
CTXB Register
The CTXB register is used to store the data to be transmitted.
Bit
7
6
5
4
3
2
1
0
Name
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
TB7~TB0: data bits 7~0 to be transmitted.
CRXB Register
The CRXB register is used to store the received data. As the character has been received completely,
the value in CRXB register should be read to avoid the next character being overwritten.
Bit
7
6
5
4
3
2
1
0
Name
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
RB7~RB0: bits 7~0 of the received data.
144
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device
during the programming process. During the development process, these options are selected using the
HT-IDE software development tools. As these options are programmed into the device using the
hardware programming tools, once they are selected they cannot be changed later as the application
software has no control over the configuration options. All options must be defined for proper system
function, the details of which are shown in the table.
No.
Options
Oscillator Options
1
High speed System oscillator selection - fM
External XTAL oscillator (HXT), External RC oscillator (ERC), Internal RC oscillator (HIRC) or
External Oscillator (EC)
2
External XTAL oscilaltor (HXT) frequency selection: 455kHz or 1MHz~12MHz
3
External oscillator (EC) clock filter control: enable or disable
4
Internal RC oscillator (HIRC) frequency selection: 4MHz, 8MHz or 12MHz
5
Low speed System oscillator selection - fSL
External 32.768kHz XTAL oscillator (LXT) or Internal 32kHz RC oscillator (LIRC)
6
Oscillator selection for fSUB
External 32.768kHz XTAL oscillator (LXT) or Internal 32kHz RC oscillator (LIRC)
7
WDT Clock selection for fS
fSUB or fSYS/4
Watchdog Options
8
Watchdog Timer function: enable or disable
9
CLRWDT instructions: 1 or 2 instructions
10
WDT time-out period: 212/fS, 213/fS, 214/fS or 215/fS
Time Base Option
11
Time base time-out period selection: 212/fS, 213/fS, 214/fS or 215/fS
Buzzer Options
12
I/O or Buzzer output selection: PA0, PA1; BZ, PA1 or BZ, BZ
13
Buzzer output frequency selection: fS/22, fS/23, fS/24, fS/25, fS/26, fS/27, fS/28 or fS/29
PFD Options
14
I/O or PFD output selection: PA3 or PFD
15
PFD source selection: PFD0 (from Timer/event counter 0) or PFD1 (from Timer/event counter 1)
RES Pin Option
16
I/O or RESB pin selection: PC7 or RES
LVD/LVR Options
17
LVD function: enable or disable
18
LVR function: enable or disable
19
LVR/LVD voltage: 2.1V/2.2V or 3.15V/3.3V or 4.2V/4.4V
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
No.
Options
Smart Card Interface Options
20
CDET pin pull high function: enable or disable
21
CIO pin pull high function: enable or disable
22
Waiting Time Counter (WTC) function: enable or disable
23
Character transfer repetition times selection: 4 times or 5 times
SIM Option
24
Serial Interface Module 0 (SIM0) function: enable or disable
25
SPI0 WCOL bit function: enable or disable
26
SPI0 CSEN bit function: enable or disable
27
I2C0 clock debounce time selection: Disable, 1 system clock or 2 system clocks
28
Serial Interface Module 1 (SIM1) function: enable or disable
29
SPI1 WCOL bit function: enable or disable
30
SPI1 CSEN bit function: enable or disable
31
I2C1 clock debounce time selection: disable, 1 system clock or 2 system clocks
I/O Pin Power Supply Options
32
I/O or VDDIO power pin selection: PB3 or VDDIO
33
PB0~PB2 power supply selection (by bit): VDD or VDDIO
34
PB4~PB7 power supply selection (by bit): VDD or VDDIO
35
PC4 power supply selection: VDD or VDDIO
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Application Circuits
V D D
0 .0 1 m F * *
V D D
S E L F
V O
C V S S
0 .1 m F
R e s e t
C ir c u it
1 0 k W ~
1 0 0 k W
1 N 4 1 4 8
0 .1 ~ 1 m F
3 0 0 W *
R E S /P C 7
P A 0 /A N 0 ~ P A 7 /A N 7
P B 0 ~ P B 7
P C 4 ~ P C 6
V L C D
V S S
C O M 0 ~ C O M 1 5
S E G 0 ~ S E G 7 9
O S C
C ir c u it
P C 0 /O S C 1
C R D V C C
P C 1 O S C 2
C R S T
C V S S
C C L K
C IO
C D E T
C C 4 , C C 8
S e e O s c illa to r
S e c tio n
O S C
C ir c u it
P C 2 /O S C 3
V 3 3 O
P C 3 /O S C 4
D P
D N
S e e O s c illa to r
S e c tio n
Rev. 1.00
L C D
P a n e l
147
S m a rt
C a rd
1 .5 k W
U S B
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case of
Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable
programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call,
or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4
system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be
implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although
instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET,
RETI and table read instructions, it is important to realize that any other instructions which involve
manipulation of the Program Counter Low register or PCL will also take one more cycle to implement.
As instructions which change the contents of the PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A².
For the case of skip instructions, it must be noted that if the result of the comparison involves a skip
operation then this will also take one more cycle, if no skip is involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used operations.
Making use of three kinds of MOV instructions, data can be transferred from registers to the
Accumulator and vice-versa as well as being able to move specific immediate data directly into the
Accumulator. One of the most important data transfer applications is to receive data from the input
ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add
and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be
taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less
than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA
provide a simple means of increasing or decreasing by a value of one of the values in the destination
specified.
Logical and Rotate Operations
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within
the Holtek microcontroller instruction set. As with the case of most instructions involving data
manipulation, data must pass through the Accumulator which may involve additional programming
steps. In all logical data operations, the zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC
and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions
exist depending on program requirements. Rotate instructions are useful for serial port programming
applications where data can be rotated from an internal register into the Carry bit from where it can be
examined and the necessary serial bit set high or low. Another application where rotate data operations
are used is to implement multiplication and division calculations.
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction or to
a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call,
the program must return to the instruction immediately when the subroutine has been carried out. This
is done by placing a return instruction RET in the subroutine which will cause the program to jump
back to the address right after the CALL instruction. In the case of a JMP instruction, the program
simply jumps to the desired location. There is no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special and extremely useful set of branch
instructions are the conditional branches. Here a decision is first made regarding the condition of a
certain data memory or individual bits. Depending upon the conditions, the program will continue with
the next instruction or skip over it and jump to the following instruction. These instructions are the key
to decision making and branching within the program perhaps determined by the condition of certain
input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the ²SET [m].i² or ²CLR [m].i²
instructions respectively. The feature removes the need for programmers to first read the 8-bit output
port, manipulate the input data to ensure that other bits are not changed and then output the port with
the correct new data. This read-modify-write process is taken care of automatically when these bit
operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large amounts
of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data
Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be
setup as a table where data can be directly stored. A set of easy to use instructions provides the means
by which this fixed data can be referenced and retrieved from the Program Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as the
²HALT² instruction for Power-down operations and instructions to control the operation of the
Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
Rev. 1.00
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Instruction Set Summary
The following table depicts a summary of the instruction set categorised according to function and can
be consulted as a basic instruction reference using the following listed conventions.
Table conventions:
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
1
1Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Rev. 1.00
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Mnemonic
Description
Cycles
Flag Affected
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by the
execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and ²CLR WDT2² instructions
are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
4. If the register in Smart Card Interface is assessed by any instruction, the instruction cycle is additionally
added by 1.
Rev. 1.00
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result
is stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical
AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto
the stack. The specified address is then loaded and the program continues execution
from this new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2
will have no effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1
will have no effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement).
Bits which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement).
Bits which previously contained a 1 are changed to 0 and vice versa. The complemented
result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater
than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the
low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set,
then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is
performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag
conditions. Only the C flag may be affected by this instruction which indicates that if the
original BCD sum is greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared.
The power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a
dummy instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 1.00
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TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR
operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be
processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into
bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into
bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.00
156
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit
7 replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated
into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit.
Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.00
157
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if
the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result
is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Data Memory. Note that if
the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result
is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0
the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0
the program proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0,
the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a
dummy instruction while the next instruction is fetched, it is a two cycle instruction. If
the result is not 0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.00
158
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0,
the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0
the program proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0,
the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a
dummy instruction while the next instruction is fetched, it is a two cycle instruction. If
the result is not 0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C
flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to
1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C
flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to
1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag
will be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.00
159
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped.
As this requires the insertion of a dummy instruction while the next instruction is
fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the
following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is
not 0 the program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP)
is moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.00
160
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR
operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical
XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.00
161
December 2, 2011
HT56RB688
TinyPower A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
TM
Package Information
Note that the package information provided here is for consultation purposes only. As this information may be
updated at regular intervals users are reminded to consult the Holtek website
(http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package
information.
144-pin LQFP (20mm´20mm) Outline Dimensions
C
D
1 0 8
G
7 3
H
I
7 2
1 0 9
A
F
B
E
1 4 4
3 7
a
K
J
1
Symbol
A
Rev. 1.00
3 6
Dimensions in inch
Min.
Nom.
Max.
0.862
¾
0.870
B
0.783
¾
0.791
C
0.862
¾
0.870
D
0.783
¾
0.791
E
¾
0.020
¾
F
¾
0.008
¾
G
0.053
¾
0.057
H
¾
¾
0.063
I
¾
0.004
¾
J
0.018
¾
0.030
K
0.004
¾
0.008
a
0°
¾
7°
162
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
A
21.90
¾
22.10
B
19.90
¾
20.10
C
21.90
¾
22.10
D
19.90
¾
20.10
E
¾
0.50
¾
F
¾
0.20
¾
G
1.35
¾
1.45
H
¾
¾
1.60
I
¾
0.10
¾
J
0.45
¾
0.75
K
0.10
¾
0.20
a
0°
¾
7°
163
December 2, 2011
HT56RB688
TinyPowerTM A/D type Smart Card OTP MCU
with LCD, DAC, ISO 7816 and USB Interfaces
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
164
December 2, 2011