HANBit
HDD128M72D18RPW
DDR SDRAM Module 1024Mbyte (128Mx72bit), based on 64Mx8, 4Banks,
8K Ref., 184Pin-DIMM with PLL & Register
Part No. HDD128M72D18RPW
GENERAL DESCRIPTION
The HDD128M72D18RPW is a 128M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory
module. The module consists of eighteen CMOS 64M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages
and 2K EEPROM in 8-pin TSSOP package on a 184-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on
the printed circuit board in parallel for each DDR SDRAM. The HDD128M72D18RPW is a DIMM( Dual in line Memory
Module) .Synchronous design allows precise cycle c ontrol with the use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device
to be useful for a variety of high bandwidth, high performance mem ory system applications. All module components may be
powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
• Part Identification
HDD128M72D18RPW – 13A
:
133MHz (CL=2)
HDD128M72D18RPW – 13B
:
133MHz (CL=2.5)
HDD128M72D18RPW – 16B
:
166MHz (CL=2.5)
• 1024MB(64Mx72) Registered DDR DIMM based on 64Mx8 DDR SDRAM
• 2.5V ± 0.2V VDD and VDDQ power supply
• Auto & self refresh capability (8K Cycles / 64ms)
• All input and output are compatible with SSTL_2 interface
• Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
• All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
• MRS cycle with address key programs
- Latency (Access from column address) : 2, 2.5
- Burst length : 2, 4, 8
- Data scramble : Sequential & Interleave
• Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
• All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
• The used device is 16M x 8bit x 4Banks DDR SDRAM
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HDD128M72D18RPW
PIN ASSIGNMENT
PIN
Front
PIN
1
VREF
2
DQ0
3
Back
PIN
Frontl
PIN
Back
PIN
Front
PIN
32
A5
62
VDDQ
33
DQ24
63
/WE
VSS
34
VSS
64
4
DQ1
35
DQ25
5
DQS0
36
DQS3
6
DQ2
37
93
VSS
124
VSS
154
/RAS
94
DQ4
125
A6
155
DQ45
DQ41
95
DQ5
126
DQ28
156
VDDQ
65
/CAS
96
VDDQ
127
DQ29
157
/CS0
66
VSS
97
DM0
128
VDDQ
158
/CS1
A4
67
DQS5
98
129
DM3
159
DM5
7
VDD
8
DQ3
38
VDD
68
DQ42
99
DQ7
130
A3
160
VSS
39
DQ26
69
DQ43
100
VSS
131
DQ30
161
DQ46
9
NC
40
DQ27
70
VDD
101
NC
132
VSS
162
DQ47
10
/RESET
41
A2
71
* /CS2
102
NC
133
DQ31
163
* /CS3
11
VSS
42
VSS
72
DQ48
103
*A13
134
CB4
164
VDDQ
12
DQ8
43
A1
73
DQ49
104
VDDQ
135
CB5
165
DQ52
13
DQ9
44
CB0
74
VSS
105
DQ12
136
VDDQ
166
DQ53
14
DQS1
45
CB1
75
* CK2
106
DQ13
137
CK0
167
NC
15
VDDQ
46
VDD
76
* /CK2
107
DM1
138
/CK0
168
VDD
16
* CK1
47
DQS8
77
VDDQ
108
VDD
139
VSS
169
DM6
17
* /CK1
48
A0
78
DQS6
109
DQ14
140
DM8
170
DQ54
18
VSS
49
CB2
79
DQ50
110
DQ15
141
A10
171
DQ55
19
DQ10
50
VSS
80
DQ51
111
CKE1
142
CB6
172
VDDQ
20
DQ11
51
CB3
81
VSS
112
VDDQ
143
VDDQ
173
NC
21
CKE0
52
BA1
82
VDDID
113
* BA2
144
CB7
174
DQ60
22
VDDQ
83
DQ56
114
DQ20
175
DQ61
23
DQ16
53
DQ32
84
DQ57
115
A12
145
VSS
176
VSS
24
DQ17
54
VDDQ
85
VDD
116
VSS
146
DQ36
177
DM7
25
DQS2
55
DQ33
86
DQS7
117
DQ21
147
DQ37
178
DQ62
26
VSS
56
DQS4
87
DQ58
118
A11
148
VDD
179
DQ63
27
A9
57
DQ34
88
DQ59
119
DM2
149
DM4
180
VDDQ
28
DQ18
58
VSS
89
VSS
120
VDD
150
DQ38
181
SA0
29
A7
59
BA0
90
NC
121
DQ22
151
DQ39
182
SA1
30
VDDQ
60
DQ35
91
SDA
122
A8
152
VSS
183
SA2
31
DQ19
61
DQ40
92
SCL
123
DQ23
153
DQ44
184
VDDSPD
KEY
DQ6
KEY
Back
* : These pins are not used in this module.
PIN
PIN DESCRIPTION
PIN
PIN DESCRIPTION
A0~A12
Address input
VDD
Power supply(2.5V)
BA0~BA1
Bank Select Address
VDDQ
Power supply for DQs(2.5V)
DQ0~DQ63
Data input/output
VREF
Power supply for reference
CB0~CB7
Check Bit
VDDSPD
Serial EEPROM Power supply(3.3)
DQS0~DQS8
Data Strobe input/output
VSS
Ground
DM0~DM8
Data-in Mask
SA0~SA2
Address in EEPROM
CK0~/CK0
Clock input
SDA
Serial data I/O
CKE0~CKE1
Clock enable input
SCL
Serial clock
/CS0~/CS1
Chip Select input
VDDID
VDD identification flag
/RAS
Row Address strobe
NC
No connection
/CAS
Column Address strobe
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HDD128M72D18RPW
Functional Block Diagram
A0-A12
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HDD128M72D18RPW
PIN FUNCTION DESCRIPTION
Pin
Name
CK, /CK
Clock
Input Function
CK and /CK are differential clock inputs. All address and control input signals are sampled
on the positive edge of CK and negative edge of /CK. Output (read) data is referenced to
both edges of CK. Internal clock signals are derived from CK/ /CK.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in
CKE
Clock Enable
any bank). CKE is synchronous for all functions except for disabling outputs, which is
achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during
power-down and self refresh modes, providing low standby power. CKE will recognizean
LVCMOS LOW level prior to VREF being stable on power-up.
CS enables(registered LOW) and disables(registered HIGH) the command decoder.
/CS0, /CS1
Chip Select
All commands are masked when CS is registered HIGH. CS provides for external bank
selection on systems with multiple banks. CS is considered part of the command code.
A0 ~ A12
Address
BA0 ~ BA1
Bank select address
/RAS
Row address strobe
/CAS
Column address strobe
/WE
Write enable
DQS0 ~ 7
Data Strobe
DM0~7
Input Data Mask
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9, CA11
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE command
is being applied.
Latches row addresses on the positive going edge of the CLK with /RAS low. Enables row
access & precharge.
Latches column addresses on the positive going edge of the CLK with /CAS low. Enables
column access.
Enables write operation and row precharge.
Latches data in starting from /CAS, /WE active.
Output with read data, input with write data. Edge-aligned with read data, cen-tered in write
data. Used to capture write data.
DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH
along with that input data during a WRITE access. DM is sampled on both edges of DQS.
DM pins include dummy loading internally, to matches the DQ and DQS load-ing.
DQ0 ~ 63
Data input/output
Data inputs/outputs are multiplexed on the same pins.
VDDQ
Supply
DQ Power Supply : +2.5V ± 0.2V.
VDD
Supply
Power Supply : +2.5V ± 0.2V (device specific).
VSS
Supply
DQ Ground.
VREF
Supply
SSTL_2 reference voltage.
VSPD
Supply
Serial EEPROM Power Supply : 3.3v
VDDID
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HDD128M72D18RPW
Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNTE
Voltage on any pin relative to Vss
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD supply relative to Vss
VDD
-1.0 ~ 3.6
V
Voltage on VDDQ supply relative to Vss
VDDQ
-0.5 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
1.5 * # of component
W
Short circuit current
IOS
50
mA
Notes: Operation at above absolute maximum rating can adversely affect device reliability
DC operating conditions
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) )
PARAMETER
SYMBOL
MIN
MAX
UNIT
NOTE
Supply Voltage
VDD
2.3
2.7
V
I/O Supply Voltage
VDDQ
2.3
2.7
V
I/O Reference Voltage
VREF
0.49*VDDQ
0.51*VDDQ
V
1
I/O Termination Voltage(system)
VTT
VREF – 0.04
VREF + 0.04
V
2
Input High Voltage
VIH (DC)
VREF + 0.15
VREF + 0.3
V
Input Low Voltage
VIL (DC)
-0.3
VREF - 0.15
V
Input Voltage Level, CK and /CK inputs
VIN (DC)
-0.3
VDDQ + 0.3
V
Input Differential Voltage, CK and /CK inputs
VID (DC)
0.3
VDDQ + 0.6
V
Input leakage current
I LI
-2
2
uA
Output leakage current
I OZ
-5
5
uA
I OH
-16.8
mA
I OL
16.8
mA
I OH
-9
mA
Output High current (Normal strength driver)
; VOUT=VTT + 0.84V
Output Low current (Normal strength driver)
; VOUT=VTT - 0.84V
Output High current (Half strength driver)
; VOUT=VTT + 0.45V
3
Notes :
1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth
limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled to VREF, both of which
may result in VREF noise. VREF should be de-coupled with an inductance of ≤
3nH.
2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on /CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The
AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
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HDD128M72D18RPW
Input / Output Capacitance
(VDD = min to max, VDDQ = 2.5V to 2.7V, TA = 25°C, f = 100MHz)
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input capacitance(A0~A12, BA0~BA1, /RAS, /CAS,/WE)
CIN1
9
11
pF
Input capacitance(CKE0,CKE1)
CIN2
9
11
pF
Input capacitance(/CS0)
CIN3
9
11
pF
Input capacitance(CK0~CK2, /CK0~/CK2)
CIN4
11
12
pF
Input capacitance(DM0~DM7)
CIN5
14
16
pF
Data input/output capacitance (DQ0 ~ DQ63, DQS0~DQS7)
COUT1
14
16
pF
Data input/output capacitance (CB0~CB7)
COUT2
14
16
pF
DC Characteristics
(VDD = 2.7V, T =10°C)
-16B
-13A
-13B
(DDR333@CL=2.5)
(DDR266@CL=2.0)
(DDR266@CL=2.5)
IDD0
2230
2010
2010
mA
IDD1
2500
2280
2280
mA
IDD2P
590
540
540
mA
Symbol
Unit
IDD2F
1420
1290
1290
mA
IDD2Q
950
900
900
mA
IDD3P
1040
990
990
mA
IDD3N
1690
1560
1560
mA
IDD4R
2540
2280
2280
mA
IDD4W
2630
2330
2330
mA
IDD5
3130
2910
2910
mA
590
540
540
mA
560
510
510
mA
4520
4080
4080
mA
Normal
IDD6
Low
Power
IDD7A
Notes
Optional
Notes: Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
AC Operating Conditions
STMBOL
MIN
Input High (Logic 1) Voltage, DQ, DQS and DM signals
PARAMETER
VIH (AC)
VREF + 0.35
MAX
UNIT
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL (AC)
Input Differential Voltage, CK and CK inputs
VID (AC)
Input Crossing Point Voltage, CK and CK inputs
VIX (AC)
NOTE
VREF - 0.31
V
0.7
VDDQ+0.6
V
1
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Notes:
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-tion.
the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
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HDD128M72D18RPW
AC characteristics
(THESE AC CHARACTERISTICS WERE TESTED ON THE COMPONENT)
PARAMETER
DDR333@CL=2.5
DDR266A@CL=2.0
DDR266B@CL=2.5
-16B
-13A
-13B
SYMBOL
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
Row cycle time
tRC
60
65
65
ns
Refresh row cycle time
tRFC
72
75
75
ns
Row active time
tRAS
42
/RAS to /CAS delay
tRCD
18
20
20
ns
Row precharge time
tRP
18
20
20
ns
Row active to Row active delay
tRRD
12
15
15
ns
Write recovery time
tWR
15
15
15
tCK
Last data in to Read command
tWTR
1
1
1
tCK
Col. address to Col. address delay
tCCD
1
1
1
tCK
CL=2.0
Clock cycle time
70K
45
120K
45
NOTE
120K
ns
7.5
12
7.5
12
10
12
ns
6
12
7.5
12
7.5
12
ns
tCK
CL=2.5
Clock high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tDQSCK
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
ns
Output data access time from CK/CK
tAC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to ouput data edge
tDQSQ
-
0.45
-
+0.5
-
+0.5
ns
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
DQS-out access time from CK/CK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
0
0
ns
DQS-in hold time
tWPREH
0.25
0.25
0.25
tCK
tDSS
0.2
0.2
0.2
tCK
DQS-in falling edge to CK rising-setup time
DQS-in falling edge to CK rising hold time
tDSH
0.2
0.2
0.2
tCK
DQS-in high level width
tDQSH
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL
0.35
0.35
0.35
tCK
DQS-in cycle time
tDSC
0.9
0.9
tIS
0.75
0.9
0.9
ns
i,5.7~9
Address and Control Input hold time(Fast)
tIH
0.75
0.9
0.9
ns
i,5.7~9
Address and Control Input setup time(Slow)
tIS
0.8
1.0
1.0
ns
i, 6~9
7
0.9
1.1
3
Address and Control Input setup time(Fast)
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tCK
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HDD128M72D18RPW
Address and Control Input hold time(Slow)
tIH
0.8
Data-out high impedence time from CK/CK
tHZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.7
-0.75
+0.75
-0.75
Data-out low impedence time from CK/CK
1.0
1.0
ns
i, 6~9
+0.75
ns
1
+0.75
ns
1
t LZ
-0.7
Input Slew Rate(for input only pins)
t SL(IO)
0.5
0.5
0.5
ns
Input Slew Rate(for I/O pins)
t SL(O)
0.5
0.5
0.5
tCK
Output Slew Rate(x4,x8)
t SL(O)
1.0
4.5
1.0
4.5
1.0
4.5
Output Slew Rate(x16)
t SL(O)
0.7
5
0.7
5
0.7
5
Output Slew Rate Matching Ratio(rise to fall)
t SLMR
0.67
1.5
0.67
1.5
0.67
1.5
Mode register set cycle time
tMRD
12
15
15
ns
DQ & DM setup time to DQS
tDS
0.45
0.5
0.5
ns
j, k
DQ & DM hold time to DQS
tDH
0.45
0.5
0.5
ns
j, k
Control & Address input pulse width
tIPW
2.2
2.2
2.2
ns
8
DQ & DM input pulse width
tDIPW
1.75
1.75
1.75
ns
8
tCK
Power down exit time
tPDEX
6
7.5
7.5
ns
Exit self refresh to non-Read command
tXSNR
75
75
75
ns
Exit self refresh to read command
tXSRD
200
200
200
tCK
Refresh interval time
tREFI
7.8
tHP
7.8
tHP
ns
4
Output DQS valid window
7.8
tHP
tQH
-
ns
11
-
ns
10,11
0.75
ns
11
0.6
tCK
2
tCK
13
Clock half period
tHP
tQHS
DQS write postamble time
tWPST
command
Autoprecharge write recovery +
Precharge time
tCLmin or
-
tCHmin
Data hold skew factor
Active to Read with Auto precharge
-
-tQHS
tCLmin or
tCHmin
0.55
0.4
0.6
tRAP
tDAL
-tQHS
-
-tQHS
tCLmin or
tCHmin
0.75
0.4
18
0.6
0.4
20
20
(tWR/tCK)+
(tWR/tCK)+
(tWR/tCK)+
(tRP/tCK)
(tRP/tCK)
(tRP/tCK)
Notes :
Maximum burst refresh of 8.
tHZQ transitions occurs in the same assess time windows as valid data transitions. These parameters are not referenced to a specific
voltage level, but specify when the device output is no longer driving.
The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low)
applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time,
depending on tDQSS.
The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system
performance (bus turnaround) will degrade accordingly.
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System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR333, DDR266 devices to ensure proper
system performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS
DDR333
PARAMETER
DQ/DM/DQS input slew rate measured between
DDR266
SYMBOL
MIN
MAX
MIN
MAX
Units
Notes
DCSLEW
TBD
TBD
TBD
TBD
V/ns
a, m
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
Table 2 : Input Setup & Hold Time Derating for Slew Rate
INPUT SLEW RATE
TIS
TIH
UNITS
NOTES
0.5 V/ns
0
0
ps
i
0.4 V/ns
+50
0
ps
i
0.3 V/ns
+100
0
ps
i
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
INPUT SLEW RATE
TDS
TDH
UNITS
NOTES
0.5 V/ns
0
0
ps
k
0.4 V/ns
+75
+75
ps
k
0.3 V/ns
+150
+150
ps
k
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
DELTA SLEW RATE
TDS
TDH
UNITS
NOTES
+/- 0.0 V/ns
0
0
ps
j
+/- 0.25 V/ns
+50
+50
ps
j
+/- 0.5 V/ns
+100
+100
ps
j
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
TYPICAL RANGE
MINIMUM
MAXIMUM
(V/NS)
(V/NS)
(V/NS)
Pullup Slew Rate
1.2 ~ 2.5
1.0
4.5
a,c,d,f,g,h
Pulldown slew
1.2 ~ 2.5
1.0
4.5
b,c,d,f,g,h
SLEW RATE CHARACTERISTIC
NOTES
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
TYPICAL RANGE
MINIMUM
MAXIMUM
(V/NS)
(V/NS)
(V/NS)
Pullup Slew Rate
1.2 ~ 2.5
0.7
5.0
a,c,d,f,g,h
Pulldown slew
1.2 ~ 2.5
0.7
5.0
b,c,d,f,g,h
SLEW RATE CHARACTERISTIC
NOTES
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS
DDR333
DDR266
PARAMETER
MIN
MAX
MIN
MAX
Notes
Output Slew Rate Matching Ratio (Pullup to Pulldown)
TBD
TBD
TBD
TBD
e,m
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REV 1.0 (January. 2005)
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HANBit Electronics Co.,Ltd.
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HDD128M72D18RPW
Component Notes
1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to
a specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ).
2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were
previously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS
could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
5. For command/address input slew rate ≥
1.0 V/ns
6. For command/address input slew rate ≥
0.5 V/ns and < 1.0 V/ns
7. For CK & CK slew rate ≥
1.0 V/ns
8. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by
device design or tester correlation.
9. Slew Rate is measured between VOH(ac) and VOL(ac).
10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into
the clock traces.
11. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1)
The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the
worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and
pchannel to n-channel variation of the output drivers.
12. tDQSQ
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given
cycle.
13. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and
tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3)
tDAL = 5 clocks
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REV 1.0 (January. 2005)
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System Notes :
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and
only one output switching.
Example : For typical slew rate, DQ0 is switching
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
d. Evaluation conditions
Typical : 25 °C (T Ambient), VDDQ = 2.5V, typical process
Minimum : 70 °C (T Ambient), VDDQ = 2.3V, slow - slow process
Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire
temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown
drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. Only intended for operation up to 266 Mbps per pin.
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns
as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or
VIH(DC) to VIL(DC), similarly for rising transitions.
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables
3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the
lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table
given, this would result in the need for an increase in tDS and tDH of 100 ps.
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the
lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew
rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal
transitions through the DC region must be monotony.
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REV 1.0 (January. 2005)
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HANBit Electronics Co.,Ltd.
HANBit
HDD128M72D18RPW
SIMPLIFIED TRUTH TABLE
COMMAND
CKE
CKE
n-1
n
/CS
/R
/C
A
A
S
S
/WE
DM
BA
A10/
A11,A12
0,1
AP
A9~A0
NOTE
Register
Extended MRS
H
X
L
L
L
L
X
OP code
1,2
Register
Mode register set
H
X
L
L
L
L
X
OP code
1,2
L
L
L
H
X
X
L
H
H
H
X
X
Auto refresh
Refresh
Entry
Self
refresh
Exit
Bank active & row addr.
Read &
column
address
Write &
column
address
H
H
L
L
H
H
X
X
X
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
H
X
L
H
L
X
V
H
X
L
H
H
L
X
H
X
L
L
H
L
X
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
Auto precharge disable
Auto precharge eable
Auto precharge enable
Burst Stop
Precharge
Bank selection
All banks
Clock suspend or
Entry
H
L
Exit
L
H
Entry
H
L
Exit
L
H
active power down
Precharge power
H
down mode
DM
No operation command
H
H
L
X
X
H
X
X
X
L
H
H
H
3
3
3
Row address
L
Auto precharge disable
3
4
Column
Address
H
L
4
4
Column
Address
H
4,6
X
V
L
X
H
X
7
X
X
X
X
X
X
V
X
X
X
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t RP after the end of burst.
6. Burst stop command is valid at every burst length.
DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0)
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REV 1.0 (January. 2005)
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HANBit Electronics Co.,Ltd.
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HANBit
HDD128M72D18RPW
PACKAGING INFORMATION
Unit : mm
<Front– Side >
133.35 ± 0.20
30.48± 0.20
A
B
< Rear – Side >
133.35 ± 0.20
30.48± 0.20
***
PCB Thickness : 1.27 ± 0.08 mm
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REV 1.0 (January. 2005)
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HANBit Electronics Co.,Ltd.
HANBit
HDD128M72D18RPW
ORDERING INFORMATION
Part Number
Density
Org.
HDD128M72D18RPW-16B
1024MByte
128M x 72
HDD128M72D18RPW-13A
1024MByte
128M x 72
HDD128M72D18RPW-13B
1024MByte
128M x 72
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REV 1.0 (January. 2005)
Package
184PIN
DIMM
184PIN
DIMM
184PIN
DIMM
14
Ref.
Vcc
8K
2.5V
8K
2.5V
8K
2.5V
MODE
MAX.frq
DDR
166MHz/CL2
Registered
DDR333
DDR
133MHz/CL2
Registered
DDR266
DDR
133MHz/CL2.5
Registered
DDR266
HANBit Electronics Co.,Ltd.