Half-Duplex, iCoupler Isolated RS-485 Transceiver ADM2481 FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 ADM2481 DE TxD RxD A B RE GND2 GND1 08920-001 RS-485 transceiver with electrical data isolation Complies with ANSI TIA/EIA-485-A and ISO 8482: 1987(E) 500 kbps data rate Slew rate-limited driver outputs Low power operation: 2.5 mA maximum Suitable for 5 V or 3.3 V operations (VDD1) High common-mode transient immunity: >25 kV/μs True fail-safe receiver inputs Chatter-free power-up/power-down protection 256 nodes on bus Thermal shutdown protection Safety and regulatory approvals (pending) UL recognition: 2500 V rms for 1 minute per UL 1577 (pending) VDE certificates of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 VIORM = 560 V peak Operating temperature range: −40°C to +85°C GALVANIC ISOLATION FEATURES Figure 1. APPLICATIONS Low power RS-485/RS-422 networks Isolated interfaces Building control networks Multipoint data transmission systems GENERAL DESCRIPTION The ADM2481 differential bus transceiver is an integrated, galvanically isolated component designed for bidirectional data communication on balanced, multipoint bus transmission lines. It complies with ANSI EIA/TIA-485-A and ISO 8482: 1987(E). Using iCoupler® technology from Analog Devices, Inc., the ADM2481 combines a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single package. The logic side of the device is powered with either a 5 V or 3 V supply, and the bus side uses a 5 V supply only. The ADM2481 is slew-limited to reduce reflections with improperly terminated transmission lines. The controlled slew rate limits the data rate to 500 kbps. The input impedance of the device is 96 kΩ, allowing up to 256 transceivers on the bus. Its driver has an active-high enable feature. The driver differential outputs and receiver differential inputs are connected internally to form a differential I/O port. When the driver is disabled or when VDD1 or VDD2 = 0 V, this imposes minimal loading on the bus. An active-high receiver disable feature, which causes the receiver output to enter a high impedance state, is provided as well. The receiver inputs have a true fail-safe feature that ensures a logic-high receiver output level when the inputs are open or shorted. This guarantees that the receiver outputs are in a known state before communication begins and at the point when communication ends. Current limiting and thermal shutdown features protect against output short circuits and bus contention situations that might cause excessive power dissipation. The part is fully specified over the industrial temperature range of −40°C to +85°C and is available in a 16-lead, wide body SOIC package. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADM2481 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................8 Applications ....................................................................................... 1 Test Circuits ..................................................................................... 11 Functional Block Diagram .............................................................. 1 Switching Characteristics .............................................................. 12 General Description ......................................................................... 1 Circuit Description......................................................................... 13 Revision History ............................................................................... 2 Electrical Isolation...................................................................... 13 Specifications..................................................................................... 3 Truth Tables................................................................................. 14 Timing Specifications .................................................................. 4 Thermal Shutdown .................................................................... 14 Package Characteristics ............................................................... 4 True Fail-Safe Receiver Inputs .................................................. 14 Regulatory Information (Pending) ............................................ 4 Magnetic Field Immunity.......................................................... 14 Insulation and Safety-Related Specifications ............................ 4 Applications Information .............................................................. 16 VDE 0884 Insulation Characteristics (Pending) ...................... 5 Printed Circuit Board (PCB) Layout ....................................... 16 Absolute Maximum Ratings............................................................ 6 Isolated Power Supply Circuit .................................................. 16 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 17 Pin Configuration and Function Descriptions ............................. 7 Ordering Guide .......................................................................... 17 REVISION HISTORY 7/10—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADM2481 SPECIFICATIONS 3.0 V ≤ VDD1 ≤ 5.5 V, 4.75 V ≤ VDD2 ≤ 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter DRIVER Differential Outputs Differential Output Voltage Δ |VOD| for Complementary Output States Common-Mode Output Voltage Δ |VOC| for Complementary Output States Output Short-Circuit Current, VOUT = High VOUT = Low Logic Inputs Input High Voltage Input Low Voltage CMOS Logic Input Current (TxD, DE, RE) RECEIVER Differential Inputs Differential Input Threshold Voltage Input Hysteresis Input Resistance (A, B) Input Current (A, B) RxD Logic Output Output High Voltage Output Low Voltage Output Short-Circuit Current Three-State Output Leakage Current POWER SUPPLY CURRENT Logic Side Bus Side COMMON-MODE TRANSIENT IMMUNITY 1 1 Symbol Min VOD VOD VOD3 2.0 1.5 1.5 Typ VOC Max Unit Test Conditions/Comments 5 5 5 5 V V V V 0.2 3 0.2 V V V RL = ∞, see Figure 16 RL = 50 Ω (RS-422), see Figure 16 RL = 27 Ω (RS-485), see Figure 16 VTEST = −7 V to +12 V, VDD1 ≥ 4.75, see Figure 17 RL = 27 Ω or 50 Ω, see Figure 16 RL = 27 Ω or 50 Ω, see Figure 16 RL = 27 Ω or 50 Ω, see Figure 16 +250 +250 mA mA −7 V ≤ VOUT ≤ +12 V −7 V ≤ VOUT ≤ +12 V 0.25 VDD1 +10 V V μA TxD, DE, RE TxD, DE, RE TxD, DE, RE = VDD1 or 0 V 0.125 −0.1 mV mV kΩ mA mA −7 V ≤ VCM ≤ +12 V −7 V ≤ VCM ≤ +12 V −7 V ≤ VCM ≤ +12 V VIN = 12 V VIN = −7 V 0.1 0.4 85 ±1 V V V V mA μA IOUT = 20 μA, VA − VB = 0.2 V IOUT = 4 mA, VA − VB = 0.2 V IOUT = −20 μA, VA − VB = −0.2 V IOUT = −4 mA, VA − VB = −0.2 V VOUT = GND or VCC 0.4 V ≤ VOUT ≤ 2.4 V 2.5 mA 1.3 mA 2.0 1.7 mA mA kV/μs 4.5 V ≤ VDD1 ≤ 5.5 V, outputs unloaded, RE = 0 V 3.0 V ≤ VDD1 ≤ 3.6 V, outputs unloaded, RE = 0 V Outputs unloaded, DE = 5 V Outputs unloaded, DE = 0 V TxD = VDD1 or 0 V, VCM = 1 kV, transient magnitude = 800 V ISC −250 −250 VIH VIL II 0.7 VDD1 −10 +0.01 VTH VHYS −200 −125 20 150 96 VOH VDD1 − 0.1 VDD1 − 0.4 VDD1 − 0.2 VOL ISC 7 IDD1 IDD2 VCM −30 25 Common-mode transient immunity is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. 0 | Page 3 of 20 ADM2481 TIMING SPECIFICATIONS 3.0 V ≤ VDD1 ≤ 5.5 V, 4.75 V ≤ VDD2 ≤ 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter DRIVER Maximum Data Rate Propagation Delay Skew Rise/Fall Time Enable Time Disable Time RECEIVER Propagation Delay Differential Skew Enable Time Disable Time Symbol tPLH, tPHL tSKEW tR, tF tPLH, tPHL tSKEW Min Typ 500 250 200 400 25 40 Max Unit Test Conditions/Comments 620 40 600 1050 1050 kbps ns ns ns ns ns RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 18 and Figure 22 RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 18 and Figure 22 RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 18 and Figure 22 RL = 500 Ω, CL = 100 pF, see Figure 19 and Figure 24 RL = 500 Ω, CL = 15 pF, see Figure 19 and Figure 24 1050 250 70 70 ns ns ns ns CL = 15 pF, see Figure 20 and Figure 23 CL = 15 pF, see Figure 20 and Figure 23 RL = 1 kΩ, CL = 15 pF, see Figure 21 and Figure 25 RL = 1 kΩ, CL = 15 pF, see Figure 21 and Figure 25 PACKAGE CHARACTERISTICS Table 3. Parameter Resistance (Input-Output) 1 Capacitance (Input-Output)1 Input Capacitance 2 1 2 Symbol RI-O CI-O CI Min Typ 1012 3 4 Max Unit Ω pF pF Test Conditions f = 1 MHz Device is considered a 2-terminal device: Pin 1 to Pin 8 are shorted together, and Pin 9 to Pin16 are shorted together. Input capacitance is from any input data pin to ground. REGULATORY INFORMATION (PENDING) Table 4. ADM2481 Approvals Organization UL Approval Type Recognized under the Component Recognition Program of Underwriters Laboratories, Inc. VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 Notes In accordance with UL 1577, each ADM2481 is proof tested by applying an insulation test voltage of ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA). In accordance with DIN V VDE V 0884-10, each ADM2481 is proof tested by applying an insulation test voltage of ≥ 1050 V peak for 1 second (partial discharge detection limit = 5 pC). INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 5. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 2500 7.7 Unit V rms mm Minimum External Tracking (Creepage) L(I02) 7.6 mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min >175 IIIa mm V Rev. 0 | Page 4 of 20 Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (Table 1 in DIN VDE 0110,1/89) ADM2481 VDE 0884 INSULATION CHARACTERISTICS (PENDING) This isolator is suitable for basic electrical isolation only within this safety limit data. Maintenance of this safety data shall be ensured by means of protective circuits. Table 6. Description Installation Classification per DIN VDE 0110 for Rated Mains Voltage ≤150 V rms ≤300 V rms ≤400 V rms Climatic Classification Pollution Degree (Table 1 in DIN VDE 0110) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b1 VIORM × 1.875 = VPR, 100% Production Tested tm = 1 sec, Partial Discharge of < 5 pC Input-to-Output Test Voltage, Method a (After Environmental Tests, Subgroup 1) VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge of < 5 pC (After Input and/or Safety Test, Subgroup 2/3) VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge of < 5 pC Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure; see Figure 13) Case Temperature Input Current Output Current Insulation Resistance at TS, VIO = 500 V Rev. 0 | Page 5 of 20 Symbol Characteristic Unit VIORM VPR I to IV I to III I to II 40/85/21 2 560 1050 VPEAK VPEAK 896 VPEAK VPR 672 VPEAK VTR 4000 VPEAK TS IS, INPUT IS, OUTPUT RS 150 265 335 >109 °C mA mA Ω ADM2481 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All voltages are relative to their respective ground. Table 7. Parameter VDD1 VDD2 Digital Input Voltage (DE, RE, TxD) Digital Output Voltage (RxD) Driver Output/Receiver Input Voltage ESD Rating: Contact (Human Body Model) (A, B Pins) Operating Temperature Range Storage Temperature Range Average Output Current per Pin θJA Thermal Impedance Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) Rating −0.5 V to +7 V −0.5 V to +6 V −0.5 V to VDD1 + 0.5 V −0.5 V to VDD1 + 0.5 V −9 V to +14 V ±2 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +85°C −55°C to +150°C −35 mA to +35 mA 65°C/W 260°C 215°C 220°C Rev. 0 | Page 6 of 20 ADM2481 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD1 1 16 VDD2 GND11 2 RxD 3 RE 4 15 GND21 ADM2481 14 NC 13 B TOP VIEW DE 5 (Not to Scale) 12 A TxD 6 11 NC GND11 7 10 GND21 GND11 8 9 GND21 PIN 9, PIN 10, AND PIN 15 MUST BE CONNECTED TO GND2. 08920-002 NC = NO CONNECT 1 PIN 2, PIN 7, AND PIN 8 MUST BE CONNECTED TO GND . 1 Figure 2. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2, 7, 8 3 Mnemonic VDD1 GND1 RxD 4 RE 5 6 9, 10, 15 11, 14 12 DE TxD GND2 NC A 13 B 16 VDD2 Description Power Supply (Logic Side). Ground (Logic Side). Receiver Output Data. When enabled, if (A − B) ≥ −30 mV, then RxD = high; if (A − B) ≤ −200 mV, then RxD = low. This is a tristate output when the receiver is disabled, that is, when RE is driven high. Receiver Enable Input. This is an active-low input. Driving this input low enables the receiver, and driving it high disables the receiver. Driver Enable Input. Driving the input high enables the driver, and driving it low disables the driver. Transmit Data Input. Data to be transmitted by the driver is applied to this input. Ground (Bus Side). No Connect. Noninverting Driver Output/Receiver Input. When the driver is disabled, or when VDD1 or VDD2 is powered down, Pin A is put into a high impedance state to avoid overloading the bus. Inverting Driver Output/Receiver Input. When the driver is disabled, or when VDD1 or VDD2 is powered down, Pin B is put into a high impedance state to avoid overloading the bus. Power Supply (Bus Side). Rev. 0 | Page 7 of 20 ADM2481 TYPICAL PERFORMANCE CHARACTERISTICS 0.32 1.6 IDD1 _RCVR_ENABLE @ 5.5V 0.30 1.2 OUTPUT VOLTAGE (V) SUPPLY CURRENT (mA) 1.4 1.0 0.8 IDD2 _DE_ENABLE @ 5.5V 0.6 0.28 0.26 0.24 0.4 08920-038 0 –40 25 0.20 –40 85 08920-031 0.22 0.2 –25 –10 5 35 50 65 80 Figure 6. Receiver Output Low Voltage vs. Temperature, IOUT = –4 mA Figure 3. Unloaded Supply Current vs. Temperature 120 4.78 100 4.76 OUTPUT VOLTAGE (V) 80 60 40 20 4.74 4.72 4.70 4.68 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT VOLTAGE (V) 4.66 –40 08920-014 0 08920-032 OUTPUT CURRENT (mA) 20 TEMPERATURE (°C) TEMPERATURE (°C) –25 –10 5 20 35 50 65 80 TEMPERATURE (°C) Figure 4. Output Current vs. Driver Output Low Voltage Figure 7. Receiver Output High Voltage vs. Temperature, IOUT = 4 mA 90 DRIVER OUTPUT CURRENT (mA) 80 –30 –50 –70 –90 70 60 50 40 30 20 –110 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 OUTPUT VOLTAGE (V) 5.0 Figure 5. Output Current vs. Driver Output High Voltage 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 DIFFERENTIAL OUTPUT VOLTAGE (V) Figure 8. Driver Output Current vs. Differential Output Voltage Rev. 0 | Page 8 of 20 08920-013 10 08920-015 OUTPUT CURRENT (mA) –10 ADM2481 600 500 1 tPLHA tPHLA tPLHB tPHLB 300 200 2 0 –40 08920-034 100 –15 10 35 60 4 85 CH1 5.00V CH3 1.00V TEMPERATURE (°C) Figure 9. Driver Propagation Delay vs. Temperature CH2 1.00V CH4 5.00V M200ns A CH1 T 1.33600µs 3.10V 08920-022 TIME (ns) 400 Figure 11. Driver/Receiver Propagation Delay, High to Low 800 700 tPHL 1 600 tPLH 400 300 200 2 0 –40 –15 10 35 60 4 85 CH1 5.00V CH3 1.00V TEMPERATURE (°C) Figure 10. Receiver Propagation Delay vs. Temperature CH2 1.00V CH4 5.00V M200ns A CH1 T 360.000ns 3.10V Figure 12. Driver/Receiver Propagation Delay, Low to High Rev. 0 | Page 9 of 20 08920-023 100 08920-035 TIME (ns) 500 0 300 –5 OUTPUT CURRENT (mA) 350 250 BUS SIDE 200 150 LOGIC SIDE 100 0 50 100 150 200 CASE TEMPERATURE (°C) Figure 13. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per VDE 0884 35 30 25 20 15 10 5 0 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 OUTPUT VOLTAGE (V) 08920-037 OUTPUT CURRENT (mA) –15 –20 Figure 14. Output Current vs. Receiver Output Low Voltage Rev. 0 | Page 10 of 20 –30 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 OUTPUT VOLTAGE (V) Figure 15. Output Current vs. Receiver Output High Voltage 5.0 08920-036 0 –10 –25 50 08920-024 SAFETY-LIMITING CURRENT (mA) ADM2481 ADM2481 TEST CIRCUITS VCC A RL 0V OR 3V VOC 08920-003 RL S1 DE S2 CL VOUT B 08920-006 RL VOD DE IN Figure 16. Driver Voltage Measurement Figure 19. Driver Enable/Disable 375Ω A VOUT RE CL Figure 17. Driver Voltage Measurement over Common-Mode Range Figure 20. Receiver Propagation Delay VCC +1.5V S1 A B CL2 S2 RE CL VOUT 08920-005 RL RL –1.5V CL1 RE IN Figure 18. Driver Propagation Delay Figure 21. Receiver Enable/Disable Rev. 0 | Page 11 of 20 08920-008 375Ω B 08920-007 VTEST 60Ω 08920-004 VOD3 ADM2481 SWITCHING CHARACTERISTICS VDD1 0.5VDD1 0.5VDD1 0V tPLH B 0.7VDD1 DE 0.5VDD1 0.5VDD1 tPHL 0.3VDD1 tZL 1/2VOD tLZ VOD A VOL + 0.5V VOL 90% POINT 90% POINT tZH tHZ A, B 10% POINT 10% POINT tR 04736-009 VOL tF VOH VOH – 0.5V A, B 2.3V 0V Figure 22. Driver Propagation Delay, Rise/Fall Timing 08920-011 VOH 2.3V A, B tSKEW = |tPLH – tPHL| Figure 24. Driver Enable/Disable Timing 0.7VDD1 RE 0.5VDD1 0.5VDD1 0.3VDD1 0V 0V tPLH tPHL tLZ 1.5V RxD VOL + 0.5V OUTPUT LOW tZH VOH VOL tHZ OUTPUT HIGH 1.5V tSKEW = |tPLH – tPHL| 1.5V VOH – 0.5V RxD VOL 08920-010 RxD 1.5V 0V Figure 23. Receiver Propagation Delay Figure 25. Receiver Enable/Disable Timing Rev. 0 | Page 12 of 20 VOH 08920-012 A–B tZL ADM2481 CIRCUIT DESCRIPTION ELECTRICAL ISOLATION iCoupler Technology In the ADM2481, electrical isolation is implemented on the logic side of the interface. Therefore, the part has two main sections: a digital isolation section and a transceiver section (see Figure 26). Driver input and data enable signals, applied to the TxD and DE pins, respectively, and referenced to logic ground (GND1), are coupled across an isolation barrier to appear at the transceiver section referenced to isolated ground (GND2). Similarly, the receiver output, referenced to isolated ground in the transceiver section, is coupled across the isolation barrier to appear at the RxD pin referenced to logic ground (GND1). The digital signals are transmitted across the isolation barrier using iCoupler technology. This technique uses chip-scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. Digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. At the secondary winding, the induced waveforms are then decoded into the binary value that was originally transmitted. VDD1 VDD2 ISOLATION BARRIER A ENCODE TxD DECODE D B DE ENCODE DECODE RxD DECODE ENCODE R DIGITAL ISOLATION GND1 TRANSCEIVER GND2 Figure 26. Digital Isolation and Transceiver Sections Rev. 0 | Page 13 of 20 04736-025 RE ADM2481 TRUTH TABLES TRUE FAIL-SAFE RECEIVER INPUTS The following truth tables use the abbreviations shown in Table 9. The receiver inputs have a true fail-safe feature that ensures that the receiver output is high when the inputs are open or shorted. During line-idle conditions, when no driver on the bus is enabled, the voltage across a terminating resistance at the receiver input decays to 0 V. With traditional transceivers, receiver input thresholds specified between −200 mV and +200 mV mean that external bias resistors are required on the A and B pins to ensure that the receiver outputs are in a known state. The true fail-safe receiver input feature eliminates the need for bias resistors by specifying the receiver input threshold between −30 mV and −200 mV. The guaranteed negative threshold means that when the voltage between A and B decays to 0 V, the receiver output is guaranteed to be high. Table 9. Letter H L X Z NC Description High level Low level Don’t care High impedance (off ) Disconnected Table 10. Transmitting Supply Status VDD1 VDD2 On On On On On On On Off Off On Off Off DE H H L X L X Inputs TxD H L X X L X A H L Z Z Z Z Outputs B L H Z Z Z Z MAGNETIC FIELD IMMUNITY Because iCouplers use a coreless technology, no magnetic components are present, and the problem of magnetic saturation of the core material does not exist. Therefore, iCouplers have essentially infinite dc field immunity. The analysis that follows defines the conditions under which this might occur. The 3 V operating condition of the ADM2481 is examined because it represents the most susceptible mode of operation. Table 11. Receiving Supply Status VDD1 On On On On On On Off VDD2 On On On On On Off Off Inputs A − B (V) >−0.03 <−0.2 −0.2 < A − B < −0.03 Inputs open X X X Outputs RE L or NC L or NC L or NC L or NC H L or NC L or NC RxD H L Indeterminate H Z H L THERMAL SHUTDOWN The ADM2481 contains thermal shutdown circuitry that protects the part from excessive power dissipation during fault conditions. Shorting the driver outputs to a low impedance source can result in high driver currents. The thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. This circuitry is designed to disable the driver outputs when a die temperature of 150°C is reached. As the device cools, the drivers are re-enabled at a temperature of 140°C. The limitation on the ac magnetic field immunity of the iCoupler is set by the condition in which the induced error voltage in the receiving coil (the bottom coil in this case) is made sufficiently large, either to falsely set or reset the decoder. The voltage induced across the bottom coil is given by ⎛ − dβ ⎞ 2 V =⎜ ⎟ ∑ πrn ; n = 1, 2, ... , N ⎝ dt ⎠ where, if the pulses at the transformer output are greater than 1.0 V in amplitude: β is the magnetic flux density (gauss). N is the number of turns in receiving coil. rn is the radius of nth turn in receiving coil (cm). The decoder has a sensing threshold of about 0.5 V; therefore, there is a 0.5 V margin in which induced voltages can be tolerated. Rev. 0 | Page 14 of 20 ADM2481 These magnetic flux density values are shown in Figure 28, using more familiar quantities such as maximum allowable current flow, at given distances away from the ADM2481 transformers. Given the geometry of the receiving coil and an imposed requirement that the induced voltage is, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 27. 1000.00 1.000 0.100 0.010 0.001 1k 10k 100k 1M 10M 100M MAGNETIC FIELD FREQUENCY (Hz) DISTANCE = 5mm 10.00 DISTANCE = 100mm 1.00 0.10 0.01 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 28. Maximum Allowable Current for Various Current-to-ADM2481 Spacings Figure 27. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kGauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse and is the worst-case polarity, it reduces the received pulse from >1.0 V to 0.75 V. This is well above the 0.5 V sensing threshold of the decoder. DISTANCE = 1m 100.00 08920-028 MAXIMUM ALLOWABLE CURRENT (kA) 10.000 08920-027 MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kGAUSS) 100.000 At combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce large enough error voltages to trigger the thresholds of succeeding circuitry. To avoid this possibility, take care in the layout of such traces. Rev. 0 | Page 15 of 20 ADM2481 APPLICATIONS INFORMATION In applications involving high common-mode transients, take care to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout must be designed such that any coupling that does occur equally affects all pins on a given component side. PRINTED CIRCUIT BOARD (PCB) LAYOUT The ADM2481 signal isolated RS-485 transceiver requires no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins (see Figure 29). Failure to ensure this can cause voltage differentials between pins that exceed the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VDD2. The capacitor value must be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin must not exceed 20 mm. VDD2 GND2 NC B A NC GND2 GND2 NC = NO CONNECT Figure 29. Recommended Printed Circuit Board Layout ISOLATION BARRIER VCC SD103C IN + TRANSFORMER DRIVER 22µF VCC OUT SD ADP3330 ERR NR 5V + 10µF GND 78253 SD103C VCC VDD1 VDD2 ADM2481 GND1 GND2 Figure 30. Isolated Power Supply Circuit Rev. 0 | Page 16 of 20 08920-029 ADM2481 The ADM2481 requires isolated power capable of 5 V at 100 mA to be supplied between the VDD2 and GND2 pins. If no suitable integrated power supply is available, a discrete circuit, such as the one in Figure 30, can be used. A centertapped transformer provides electrical isolation. The primary winding is excited with a pair of square waveforms that are 180° out of phase with each other. A pair of Schottky diodes and a smoothing capacitor are used to create a rectified signal from the secondary winding. The ADP3330 linear voltage regulator provides a regulated power supply to the bus-side circuitry of the ADM2481. 08920-127 VDD1 GND1 RxD RE DE TxD GND1 GND1 ISOLATED POWER SUPPLY CIRCUIT ADM2481 OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 45° 8° 0° 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 1.27 (0.0500) 0.40 (0.0157) 032707-B 1 Figure 31. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model 1 ADM2481BRWZ ADM2481BRWZ-RL7 1 Data Rate (kbps) 500 500 Temperature Range −40°C to +85°C −40°C to +85°C Z = RoHS Compliant Part. Rev. 0 | Page 17 of 20 Package Description 16-Lead, Wide Body SOIC_W 16-Lead, Wide Body SOIC_W Package Option RW-16 RW-16 ADM2481 NOTES Rev. 0 | Page 18 of 20 ADM2481 NOTES Rev. 0 | Page 19 of 20 ADM2481 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08920-0-7/10(0) Rev. 0 | Page 20 of 20