LINER LTC1066-1 14-bit dc accurate clock-tunable, 8th order elliptic or linear phase lowpass filter Datasheet

LTC1066-1
14-Bit DC Accurate
Clock-Tunable, 8th Order Elliptic
or Linear Phase Lowpass Filter
U
DESCRIPTIO
FEATURES
■
■
■
■
■
■
■
■
■
■
DC Gain Linearity: 14 Bits
Maximum DC Offset: ±1.5mV
DC Offset TempCo: 7µV/°C
Device Fully Tested at fCUTOFF = 80kHz
Maximum Cutoff Frequency: 120kHz (VS = ±8V)
Drives 1kΩ Load with 0.02% THD or Better
Signal-to-Noise Ratio: 90dB
Input Impedance: 500MΩ
Selectable Elliptic or Linear Phase Response
Operates from Single 5V up to ±8V Power Supplies
The filter does not require any external active components
such as input/output buffers. The input/output impedance
is 500MΩ/0.1Ω and the output of the filter can source or
sink 40mA. When pin 8 is connected to V +, the clock-tocutoff frequency ratio is 50:1 and the input signal is
sampled twice per clock cycle to lower the risk of aliasing.
For frequencies up to 0.75fCUTOFF, the passband ripple is
±0.15dB. The gain at fCUTOFF is –1dB and the filter’s
stopband attenuation is 80dB at 2.3fCUTOFF. Linear phase
operation is also available with a clock-to-cutoff frequency
ratio of 100:1 when pin 8 is connected to ground.
UO
APPLICATI
■
■
■
■
■
The LTC1066-1 is an 8th order elliptic lowpass filter which
simultaneously provides clock-tunability and DC accuracy. The unique and proprietary architecture of the filter
allows 14 bits of DC gain linearity and a maximum of
1.5mV DC offset. An external RC is required for DC
accurate operation. With ±7.5V supplies, a 20k resistor
and a 1µF capacitor, the cutoff frequency can be tuned
from 800Hz to 100kHz. A clock-tunable 10Hz to 100kHz
operation can also be achieved (see Typical Application
section).
S
Instrumentation
Data Acquisition Systems
Anti-Aliasing Filters
Smoothing Filters
Audio Signal Processing
The LTC1066-1 is available in an 18-pin SOL package.
UO
TYPICAL APPLICATI
Amplitude Response
Clock-Tunable, DC Accurate, 800Hz to 80kHz Elliptic Lowpass Filter
20k
10
1µF
0
2
VIN
–7.5V
SHORT CONNECTION UNDER
IC AND SHIELDED BY A
GROUND PLANE
BYPASS THE POWER SUPPLIES
WITH 0.1µF DISC CERAMIC
40kHz ≤ fCLK ≤ 4MHz
7.5V
3
4
5
6
7
8
9
OUT A
V+
–IN A
OUT B
+IN A
V–
+IN B
LTC1066-1
V+
CONNECT 1
FILTEROUT
50/100
CLK
GND
FILTERIN
COMP 2
CONNECT 2
COMP 1
V–
18
17
16
15
7.5V
–10
VOUT;
VOS(OUT) =
2.5mVMAX
–20
14
13
12
30k
fC = 80kHz
–30
fC = 800Hz
–40
–50
–60
15pF
11
10
GAIN (dB)
1
–70
–80
–7.5V
1066-1 TA01
–90
100
1k
10k
100k
FREQUENCY (Hz)
1M
1066-1 TA02
1
LTC1066-1
U
U
W W
W
Total Supply Voltage (V +
RATI GS
PACKAGE/ORDER I FOR ATIO
V –)
to
.......................... 16.5V
Power Dissipation............................................. 700mW
Burn-In Voltage ................................................... 16.5V
Voltage at Any Input ..... (V – – 0.3V) ≤ VIN ≤ (V + + 0.3V)
Maximum Clock Frequency
VS = ±8V ....................................................... 6.1MHz
VS = ±7.5V .................................................... 5.4MHz
VS = ±5V ....................................................... 4.1MHz
VS = Single 5V ............................................... 1.8MHz
Operating Temperature Range* .................. 0°C to 70°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
* For an extended operating temperature range contact LTC Marketing
for details.
ELECTRICAL CHARACTERISTICS
W
AXI U
U
ABSOLUTE
TOP VIEW
OUT A 1
18 V +
–IN A 2
17 OUT B
+IN A 3
16 +IN B
V– 4
15 GND
V+ 5
14 FILTERIN
CONNECT 1 6
ORDER PART
NUMBER
LTC1066-1CS
13 COMP 2
FILTEROUT 7
12 CONNECT 2
50/100 8
11 COMP 1
10 V –
CLK 9
S PACKAGE
18-LEAD PLASTIC SOL
TJMAX = 110°C, θJA = 75°C/ W
Consult factory for other package options and for Industrial and Military
grade parts.
(See Test Circuit)
VS = ±7.5V, RL = 1k, TA = 25°C, fCLK signal level is TTL or CMOS (maximum clock rise or fall time ≤ 1µs) unless otherwise specified.
All AC gain measurements are referenced to passband gain.
PARAMETER
CONDITIONS
Passband Gain (0.01fCUTOFF to 0.25fCUTOFF)
fCLK = 400kHz, fTEST = 2kHz
Passband Ripple (0.01fCUTOFF to 0.75fCUTOFF)
for fCLK/fCUTOFF = 50:1
fCUTOFF ≤ 50kHz (See Note on Test Circuit)
Gain at 0.50fCUTOFF for fCLK/fCUTOFF = 50:1
fCLK = 400kHz, f TEST = 4kHz
MIN
●
dB
dB
0.02
0.05
0.09
0.14
dB
dB
●
– 0.16
– 0.22
– 0.05
– 0.10
0.02
0.02
dB
dB
●
– 0.18
– 0.22
– 0.05
– 0.10
0.05
0.05
dB
dB
●
– 0.36
– 0.45
– 0.20
– 0.30
0.05
0.05
dB
dB
●
– 0.65
– 0.85
– 0.30
– 0.40
0.25
0.75
dB
dB
●
– 1.50
– 1.80
– 1.10
– 1.20
– 0.05
– 0.05
dB
dB
●
– 2.10
– 2.30
– 1.60
– 1.60
– 1.20
– 1.20
dB
dB
●
– 2.20
– 2.50
– 1.60
– 1.60
– 0.05
0.25
dB
dB
●
– 56
– 54
– 58
– 57
– 64
– 64
dB
dB
●
– 53
– 51
– 56
– 55
– 62
– 62
dB
dB
●
– 50
– 48
– 52
– 51
– 60
– 60
dB
dB
fCLK = 400kHz, f TEST = 6kHz
fCLK = 400kHz, f TEST = 8kHz
fCLK = 2MHz, f TEST = 40kHz
fCLK = 4MHz, f TEST = 80kHz
fCLK = 400kHz, fTEST = 16kHz
fCLK = 2MHz, fTEST = 80kHz
fCLK = 4MHz, fTEST = 160kHz
2
0.36
– 0.09
– 0.14
fCLK = 4MHz, f TEST = 60kHz
Gain at 2.00fCUTOFF for fCLK/fCUTOFF = 50:1
0.16
UNITS
●
fCLK = 2MHz, f TEST = 30kHz
Gain at 1.00fCUTOFF for fCLK/fCUTOFF = 50:1
MAX
±0.15
fCLK = 2MHz, f TEST = 20kHz
Gain at 0.75fCUTOFF for fCLK/fCUTOFF = 50:1
– 0.18
TYP
LTC1066-1
ELECTRICAL CHARACTERISTICS
(See Test Circuit)
VS = ±7.5V, RL = 1k, TA = 25°C, fCLK signal level is TTL or CMOS (maximum clock rise or fall time ≤ 1µs) unless otherwise specified.
All AC gain measurements are referenced to passband gain.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Gain at fCUTOFF for fCLK = 20kHz, VS = ±7.5V
fCLK/fCUTOFF = 50:1, fTEST = 400Hz
●
– 1.75
– 1.25
– 0.50
dB
Gain at fCUTOFF for VS = ±2.375V, fCLK/fCUTOFF = 50:1
fCLK = 1MHz, fTEST = 20kHz
●
– 1.75
– 0.70
0.10
dB
Gain at 70kHz for VS = ±5V, fCLK/fCUTOFF = 50:1
fCLK = 4MHz, fTEST = 70kHz
●
1.00
1.40
dB
Linear Phase Response
fCLK/fCUTOFF = 100:1,
Phase at 0.25fCUTOFF
fCLK = 400kHz, f TEST = 1kHz
●
– 48.5
– 48.0
– 50.0
– 50.0
– 51.5
– 52.0
Deg
Deg
Pin 8 at GND
Gain at 0.25fCUTOFF
fCLK = 400kHz, f TEST = 1kHz
●
– 0.65
– 0.25
0.25
dB
Phase at 0.50fCUTOFF
fCLK = 400kHz, f TEST = 2kHz
●
– 97.5
– 97.0
– 99.5
– 99.5
– 101.5
– 102.0
Deg
Deg
Gain at 0.50fCUTOFF
fCLK = 400kHz, f TEST = 2kHz
Phase at 0.75fCUTOFF
fCLK = 400kHz, f TEST = 3kHz
Gain at 0.75fCUTOFF
fCLK = 400kHz, f TEST = 3kHz
Phase at fCUTOFF
fCLK = 400kHz, f TEST = 4kHz
Gain at fCUTOFF
Input Bias Current
fCLK = 400kHz, f TEST = 4kHz
●
– 0.75
– 0.50
– 0.10
dB
●
– 148.0
– 147.5
– 150.5
– 150.5
– 152.5
– 153.0
Deg
Deg
●
– 1.40
– 1.00
– 0.60
dB
●
– 208.0
– 207.5
– 210.0
– 210.0
– 212.5
– 213.0
Deg
Deg
●
– 2.10
– 1.80
– 1.60
dB
●
60
70
135
nA
nA
●
●
±10
±10
±40
±45
nA
nA
VS = ±2.375V
Input Offset Current
VS = ±2.375V
VS ≥ ±5V (Note 2)
Input Offset Current TempCo
±2.375V ≤ VS ≤ ±7.5V
40
pA/°C
Output Voltage Offset TempCo
±2.375V ≤ VS ≤ ±7.5V
7
µV/°C
Output Offset Voltage
VS = ±2.375V, fCLK = 400kHz
Common-Mode Rejection
Power Supply Rejection
Input Voltage Range and Output Voltage Swing
●
±0.5
±1.0
±1.5
mV
mV
VS ≥ ±5V
(Note 2)
●
±0.5
±1.0
±1.5
mV
mV
VS = ±7.5V
VCM = – 5V to 5V
●
90
84
96
90
dB
dB
●
80
78
84
82
dB
dB
±1.2
±1.1
±1.4
●
V
V
±3.4
±3.2
±3.6
●
V
V
±5.4
±5.0
±5.8
●
V
V
VS = ±2.5V to ±7.5V
VS = ±2.375V, RL = 1k
VS = ±5V, RL = 1k
VS = ±7.5V, RL = 1k
Output Short-Circuit Current
±2.375V ≤ VS ≤ ±7.5V
Power Supply Current (Note 1)
VS = ±2.375V
±40
mA
●
14
16
16
19
mA
mA
●
22
23
26
29
mA
mA
●
25
26
30
33
mA
mA
±8
V
VS = ±5V
VS = ±7.5V
Power Supply Range
The ● denotes specifications which apply over the full operating
temperature range.
±2.375
Note 1: The maximum current over temperature is at 0°C. At 70°C the
maximum current is less than its maximum value at 25°C.
Note 2: Guaranteed by design and test correlation.
3
LTC1066-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Gain vs Frequency
VS = ±7.5V, fCLK/ fC = 100:1
Gain vs Frequency
VS = ±7.5V, fCLK/ fC = 50:1
10
0
–10
fCLK= 500kHz
–60
–90
–100
–10
–20
–50
–60
–110
10k
100k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
180
GAIN
GAIN (dB)
1
0
0
–1
– 60
–120
PHASE
–180
ELLIPTIC RESPONSE
fC = 20kHz, fCLK = 1MHz
fCLK/fC = 50:1, PIN 8 AT V +
RF = 20k, CF = 1µF
(SEE BLOCK DIAGRAM)
2
4
6
180
VS = ±7.5V
TA = 25°C
120
60
0
GAIN
–1
–2
–4
–300
–5
–360
8 10 12 14 16 18 20 22
FREQUENCY (kHz)
–6
–180
LINEAR PHASE RESPONSE
fC = 20kHz, fCLK/fC = 100:1
PIN 8 AT GND, RF = 20k, CF = 1µF
(SEE BLOCK DIAGRAM)
2
GAIN
2
60
1
0
0
– 60
–1
–120
–2
PHASE
–5
–6
2
4
6
–240
–4
–300
–5
–360
8 10 12 14 16 18 20 22
FREQUENCY (kHz)
–6
10666-1 G06
A
–2
–3
ELLIPTIC RESPONSE
fC = 20kHz, fCLK/fC = 100:1
PIN 8 AT V –, RF = 20k, CF = 1µF
(SEE BLOCK DIAGRAM)
A. fCLK = 1MHz (GND = 2.5V)
B. fCLK = 1.4MHz (GND = 2V)
C. fCLK = 1.8MHz (GND = 2V)
–1
–180
–3
–4
PHASE (DEG)
0
GAIN (dB)
120
VS = ±5V, TA = 70°C
fCLK /fC = 50:1
RF = 20k, CF = 1µF
RC COMPENSATION
=15pF IN SERIES
WITH 30kΩ
3
2
B
C
GAIN (dB)
1
4
5
4
GAIN (dB)
2
Passband Gain vs Frequency
and fCLK
3
180
–300
10666-1 G05
Passband Gain vs Frequency
and fCLK
VS = ±7.5V
TA = 25°C
–240
–360
8 10 12 14 16 18 20 22
FREQUENCY (kHz)
6
4
10666-1 G04
3
–120
PHASE
–3
–240
Passband Gain and Phase
vs Frequency
– 60
PHASE (DEG)
2
60
PHASE (DEG)
120
–2
–6
1066-1 G03
3
GAIN (dB)
1
–5
1M
Passband Gain and Phase
vs Frequency
VS = ±7.5V
TA = 25°C
–4
10k
100k
FREQUENCY (Hz)
1066-1 G02
3
–3
1k
1M
Passband Gain and Phase
vs Frequency
0
VS = ±7.5V
TA = 25°C
fCLK/fC = 100:1
PIN 8 TO V –
–90
–100
1066-1 G01
2
–60
–110
1k
1M
–50
–80
–110
1k
–40
–70
VS = ±7.5V
TA = 25°C
fCLK/fC = 100:1
NO COMPENSATION
PIN 8 TO AGND
–90
–100
fCLK= 5MHz
fCLK= 1MHz
–30
–40
–80
fCLK= 2.5MHz
fCLK= 5MHz
fCLK= 1MHz
–70
VS = ±7.5V
TA = 25°C
fCLK/fC = 50:1
COMPENSATION
= 30k, 15pF
–80
–10
–20
GAIN (dB)
–40
–50
–70
10
0
–30
GAIN (dB)
–30
GAIN (dB)
10
0
fCLK= 5MHz
–20
Gain vs Frequency
VS = ±7.5V, fCLK/ fC = 100:1
VS = SINGLE 5V
TA = 70°C
fCLK /fC = 50:1
RF = 20k, CF = 1µF
RC COMPENSATION
= 15pF IN SERIES
WITH 30kΩ
1
0
–1
A
–2
B
C D
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
–3
–4
–5
1
10
FREQUENCY (kHz)
50
1066-1 G07
1
10
FREQUENCY (kHz)
100
1066-1 G08
LTC1066-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Passband Gain vs Frequency
1
70
GROUP DELAY (µs)
2
0
–1
A B C
–2
D
–4
A
60
B
VS = ±5V
TA = 25°C
fC = 20kHz
50
C
40
A. fCLK = 2MHz
B. fCLK = 3MHz
C. fCLK = 4MHz
D. fCLK = 5MHz
–3
A. fCLK /fC = 50:1 (PIN 8 TO V +)
B. fCLK /fC = 100:1 (PIN 8 TO V –)
C. LINEAR PHASE REPONSE
fCLK /fC = 100:1 (PIN 8 TO GND)
30
2
100 200
10
FREQUENCY (kHz)
4
6
–65
1066-1 G11
–55
–60
)
–50
GND PIN 15 AT 2V
–65
VS = ±7.5V
–80
–70
(
–75
–80
GND PIN 15 AT 2.5V
–50
–55
–60
–65
–70
–75
–80
–85
–85
–85
–90
0.1
–90
0.1
–90
1
INPUT VOLTAGE (VRMS)
5
1
INPUT VOLTAGE (VRMS)
1066-1 G12
THD + Noise vs Frequency
THD + Noise vs Frequency
THD + Noise vs Frequency
–60
–65
C
–75
B
–60
A. RL = ∞, CL = 100pF
B. RL = 1k, CL = 100pF
C. RL = 200Ω, CL = 100pF
–80
–85
A
–90
1
10
FREQUENCY (kHz)
50
–50
–65
(
–70
–55
–70
–75
–80
–60
–65
–70
–75
–80
–85
–85
–90
–90
1
10
20
FREQUENCY (kHz)
1066-1 G15
–55
)
–50
VS = SINGLE 5V
VIN = 0.5VRMS
TA = 25°C
fCLK = 1MHz
fCLK /fC = 50:1
(5 REPRESENTATIVE
UNITS)
–45
(
–55
VS = ±5V
VIN = 1VRMS
TA = 25°C
fCLK = 1MHz
fCLK /fC = 50:1
(5 REPRESENTATIVE
UNITS)
–45
)
–50
50
–40
20 log THD + NOISE (dB)
VIN
VS = ±7.5V
VIN = 1VRMS
TA = 25°C
fCLK = 2.5MHz
fCLK /fC = 50:1
10
FREQUENCY (kHz)
1066-1 G14
–40
20 log THD + NOISE (dB)
VIN
)
(
1
2
1066-1 G13
–40
–45
VS = ±7.5V
VIN = 1VRMS
TA = 25°C
fCLK = 2.5MHz
fCLK /fC = 50:1
(5 REPRESENTATIVE
UNITS)
–45
(
–70
1.0
THD + Noise vs Frequency
fIN = 1kHz
VS = SINGLE 5V
fCLK = 1MHz
fCLK /fC = 50:1
TA = 25°C
)
VS = ±5V
–60
0.6
0.8
0.4
FREQUENCY (fCUTOFF/FREQUENCY)
–40
–45
–55
–75
0
0.2
8 10 12 14 16 18 20 22
FREQUENCY (kHz)
20 log THD + NOISE (dB)
VIN
TA = 25°C
fIN = 1kHz
fCLK = 1MHz
fCLK /fC = 50:1
–50
A. ELLIPTIC RESPONSE
fCLK /fC = 50:1 (PIN 8 to V +)
B. LINEAR PHASE RESPONSE
fCLK /fC = 100:1 (PIN8 TO GND)
0.25
–40
20 log THD + NOISE (dB)
VIN
)
(
B
0.50
THD + Noise vs Input Voltage
THD + Noise vs Input Voltage
20 log THD + NOISE (dB)
VIN
0.75
1066-1 G10
–40
–45
PHASE DIFFERENCE BETWEEN
ANY TWO UNITS (SAMPLE OF
50 REPRESENTATIVE UNITS)
VS ≥ ±5V, TA = 25°C
fCLK ≤ 2.5MHz
A
1.00
20
1
1066-1 G09
20 log THD + NOISE (dB)
VIN
PHASE DIFFERENCE (±DEG)
VS = ±7.5V, TA = 70°C
fCLK /fC = 50:1
RF = 20k, CF = 1µF
RC COMPENSATION
= 15pF IN SERIES
WITH 30kΩ
3
GAIN (dB)
1.25
80
4
–5
Phase Matching vs Frequency
Group Delay vs Frequency
5
1
10
20
FREQUENCY (kHz)
1066-1 G16
1066-1 G17
5
LTC1066-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Power Supply Current vs
Power Supply Voltage
Transient Response
Transient Response
30
21
1V/DIV
0°C
25°C
70°C
24
1V/DIV
POWER SUPPLY CURRENT (mA)
27
18
15
12
9
6
100µs/DIV
LINEAR PHASE (PIN 8 TO GND)
fIN = 1kHz, fCUTOFF = 10kHz
100µs/DIV
ELLIPTIC RESPONSE (PIN 8 TO V +)
fIN = 1kHz, fCUTOFF = 10kHz
3
0
0
2
4 6 8 10 12 14 16 18 20
TOTAL POWER SUPPLY VOLTAGE (V)
1066-1 G20
1066-1 G19
1066-1 G18
Table 1. Elliptic Response, fC = 10kHz, fCLK/fCUTOFF = 50:1,
VS = ±7.5V, RF = 20k, CF = 1µF, No RC Compensation,
TA = 25°C
FREQUENCY
(kHz)
2.000
3.000
4.000
5.000
6.000
7.000
8.000
9.000
10.000
GAIN
(dB)
0.117
0.118
0.116
0.112
0.104
0.074
– 0.014
– 0.278
– 0.986
PHASE
(DEG)
– 50.09
– 75.75
– 101.96
– 129.25
– 157.82
171.68
138.41
101.26
58.98
GROUP DELAY
(µs)
70.52
72.04
74.32
77.59
82.04
88.56
97.80
110.33
124.91
Table 3. Linear Phase Response, fC = 10kHz,
fCLK/fCUTOFF = 100:1, VS = ±7.5V, RF = 20k, CF = 1µF,
No RC Compensation, TA = 25°C
FREQUENCY
(kHz)
2.000
3.000
4.000
5.000
6.000
7.000
8.000
9.000
10.000
6
GAIN
(dB)
– 0.020
– 0.181
– 0.383
– 0.601
– 0.811
– 1.004
– 1.196
– 1.451
– 1.910
PHASE
(DEG)
– 39.96
– 59.76
– 79.60
– 99.34
– 119.40
– 139.91
– 161.56
175.21
149.99
GROUP DELAY
(µs)
55.25
55.03
54.98
55.28
56.34
58.56
62.34
67.29
72.31
Table 2. Elliptic Response, fC = 50kHz, fCLK/fCUTOFF = 50:1,
VS = ±7.5V, RF = 20k, CF = 1µF, No RC Compensation,
TA = 25°C
FREQUENCY
(kHz)
10.000
15.000
20.000
25.000
30.000
35.000
40.000
45.000
50.000
GAIN
(dB)
0.104
0.105
0.107
0.109
0.107
0.089
0.014
– 0.231
– 0.905
PHASE
(DEG)
– 50.91
– 76.95
– 103.51
– 131.13
– 160.03
169.22
135.72
98.44
56.15
GROUP DELAY
(µs)
14.32
14.61
15.05
15.70
16.57
17.85
19.66
22.10
24.93
Table 4. Linear Phase Response, fC = 50kHz,
fCLK/fCUTOFF = 100:1, VS = ±7.5V, RF = 20k, CF = 1µF,
No RC Compensation, TA = 25°C
FREQUENCY
(kHz)
10.000
15.000
20.000
25.000
30.000
35.000
40.000
45.000
50.000
GAIN
(dB)
0.039
– 0.068
– 0.202
– 0.345
– 0.479
– 0.594
– 0.701
– 0.860
– 1.214
PHASE
(DEG)
– 40.72
– 61.01
– 81.42
– 101.88
– 122.74
– 144.09
– 166.68
169.15
142.72
GROUP DELAY
(µs)
11.30
11.31
11.36
11.48
11.73
12.20
12.99
14.06
15.19
LTC1066-1
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PIN FUNCTIONS
Power Supply Pins (5, 18, 4, 10)
The power supply pins should be bypassed with a 0.1µF
capacitor to an adequate analog ground. The bypass
capacitors should be connected as close as possible to the
power supply pins. The V + pins (5, 18) and the V – pins (4,
10) should always be tied to the same positive supply and
negative supply value respectively. Low noise linear supplies are recommended. Switching power supplies are not
recommended as they will lower the filter dynamic range.
When the LTC1066-1 is powered up with dual supplies
and, if V + is applied prior to a floating V –, connect a signal
diode (1N4148) between pin 10 and ground to prevent
power supply reversal and latch-up. A signal diode
(1N4148) is also recommended between pin 5 and ground
if the negative supply is applied prior to the positive supply
and the positive supply is floating. Note, in most laboratory supplies, reversed biased diodes are always connected between the supply output terminals and ground,
and the above precautions are not necessary. However,
when the filter is powered up with conventional 3-terminal
regulators, the diodes are recommended.
Analog Ground Pin (15)
The filter performance depends on the quality of the
analog signal ground. For either dual or single supply
operation, an analog ground plane surrounding the package is recommended. The analog ground plane should be
connected to any digital ground at a single point. For dual
supply operation, pin 15 should be connected to the
analog ground plane. For single supply operation pin 15
should be biased at 1/2 supply and should be bypassed to
the analog ground plane with at least a 1µF capacitor (see
Typical Applications). For single 5V operation and for
fCLK ≥ 1.4MHz, pin 15 should be biased at 2V. This
minimizes passband gain and phase variations.
Clock Input Pin (9)
Any TTL or CMOS clock source with a square-wave output
and 50% duty cycle (±10%) is an adequate clock source
for the device. The power supply for the clock source
should not be the filter’s power supply. The analog ground
for the filter should be connected to clock’s ground at a
single point only. Table 5 shows the clock’s low and high
level threshold values for a dual or single supply operation.
Sine waves are not recommended for clock input frequencies less than 100kHz, since excessively slow clock rise or
fall times generate internal clock jitter (maximum clock
rise or fall time ≤ 1µs). The clock signal should be routed
from the left side of the IC package and perpendicular to it
to avoid coupling to any input or output analog signal path.
A 200Ω resistor between clock source and pin 9 will slow
down the rise and fall times of the clock to further reduce
charge coupling.
Table 5. Clock Source High and Low Threshold Levels
POWER SUPPLY
HIGH LEVEL
LOW LEVEL
≥ 2.18V
≥ 1.45V
≥ 0.73V
≥ 7.80V
≥ 1.45V
≤ 0.5V
≤ 0.5V
≤ – 2.0V
≤ 6.5V
≤ 0.5V
Dual Supply = ±7.5V
Dual Supply = ±5V
Dual Supply = ±2.5V
Single Supply = 12V
Single Supply = 5V
50:1/100:1 Pin (8)
The DC level at pin 8 determines the ratio of the clock to
the filter cutoff frequency. When pin 8 is connected to
V + the clock-to-cutoff frequency ratio (fCLK / fCUTOFF) is
50:1 and the filter response is elliptic. The design of the
internal switched-capacitor filter was optimized for a 50:1
operation.
When pin 8 is connected to ground (or 1/2 supply for
single supply operation), the fCLK / fCUTOFF ratio is equal to
100:1 and the filter response is pseudolinear phase (see
Group Delay vs Frequency in Typical Performance Characteristic section).
When pin 8 is connected to V – (or ground for single supply
operation), the fCLK / fCUTOFF ratio is 100:1 and the filter
response is transitional Butterworth elliptic. The Typical
Performance Characteristics provide all the necessary
information.
If the DC level at pin 8 is mechanically switched, a 10k
resistor should be connected between pin 8 and the DC
source.
Input Pins (2, 3, 14, 16)
Pin 3 (+IN A) and pin 2 (–IN A) are the positive and
negative inputs of an internal high performance op amp A
7
LTC1066-1
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PIN FUNCTIONS
(see Block Diagram). Input bias current flows out of pins
2 and 3. Pin 16 (+IN B) is the positive input of a high
performance op amp B which is internally connected as
a unity-gain follower. Op amp B buffers the switchedcapacitor network output. The input capacitance of both
op amps is 10pF.
15pF capacitor should be connected between pins 11 and
13. Compensation is recommended for the following
cases shown in Table 6.
Pin 14 (FILTERIN) is the input of a switched-capacitor
network. The input impedance of pin 14 is typically 11k.
VS = Single 5V (AGND = 2V)
TA = 25°C
TA = 70°C
fCUTOFF ≥ 28kHz
fCUTOFF ≥ 24kHz
VS = ±5V
TA = 25°C
TA = 70°C
fCUTOFF ≥ 60kHz
fCUTOFF ≥ 50kHz
VS = ±7.5V
TA = 25°C
TA = 70°C
fCUTOFF ≥ 70kHz
fCUTOFF ≥ 60kHz
Output Pins (1, 7, 17)
Pins 1 and 17 are the outputs of the internal high performance op amps A and B. Pin 1 is usually connected to the
internal switched-capacitor filter network input pin 14. Pin
17 is the buffered output of the filter and it can drive loads
as heavy as 200Ω (see THD + Noise curves under Typical
Performance Characteristics). Pin 7 is the internal switchedcapacitor network output and it can typically sink or
source 1mA.
Table 6. Cases Where an RC Compensation (15pF in Series with
30kΩ pins 11, 13) is Recommended, fCLK/fCUTOFF = 50:1
Connect Pins (6, 12)
Pin 6 (CONNECT 1) and pin 12 (CONNECT 2) should be
shorted. In a printed circuit board the connection should
be done under the IC package through a short trace
surrounded by the analog ground plane. Pin 6 should be
0.2 inches away from any other circuit trace.
Compensation Pins (11, 13)
Pins 11 and 13 are the AC compensation pins. If compensation is needed, an external 30k resistor in series with a
W
BLOCK DIAGRAM
RF
CF
LTC1066-1
–
2
–IN A
HIGH SPEED
OP AMP
+
3
+IN A
V+
5,18
V–
4,10
1
14
OUT A
FILTERIN
GND 50/100 CLK
15
8
9
CONNECT 1
6
8TH ORDER
SWITCHEDCAPACITOR
NETWORK
11
COMP1
13
COMP2
–
12
CONNECT 2
7
FILTEROUT
HIGH SPEED
OP AMP
16
+IN B
+
17
OUT B
PATENT PENDING
11066-1 BD
8
LTC1066-1
TEST CIRCUIT
20k
2
1µF
20Ω
0.1µF
V+
0.1µF
ELLIPTIC +
RESPONSE V
50:1
10k
OUT B
+IN A
+IN B
V–
5
V+
6
8
9
fCLK
(DUTY CYCLE
= 50% ±10%)
–IN A
4
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LINEAR PHASE
RESPONSE
100:1
3
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V–
VIN
V+
OUT A
LTC1066-1
GND
FILTERIN
CONNECT 1
FILTEROUT
COMP 2
CONNECT 2
COMP 1
50/100
V–
CLK
20Ω
18
17
VOUT
16
NOTE: RC COMPENSATION BETWEEN PINS 11 AND 13 IS
REQUIRED ONLY FOR CLOCK-TUNABLE OPERATION FOR:
50kHz < fCUTOFFs ≤ 100kHz.
15
14
THE TEST SPECIFICATIONS FOR:
fCLK = 2MHz, fCUTOFF = 40kHz, AND
fCLK = 4MHz, fCUTOFF = 80kHz
INCLUDE THE EFFECTS OF RC COMPENSATION.
15pF
13
12
11
10
V+
0.1µF
30k
V–
0.1µF
COMPENSATION DOES NOT INFLUECE THE SPECIFICATIONS
FOR:
fCLK = 400kHz, fCUTOFF = 8kHz.
FOR CLOCK-TUNABLE fCUTOFFs FROM 2kHz TO 50kHz
COMPENSATION IS NOT REQUIRED AND THE FILTER’S
PASSBAND PERFORMANCE IS REPRESENTED BY THE
TYPICAL SPECIFICATIONS AT:
1066-1 TC01
fCLK = 400kHz, fCUTOFF = 8kHz.
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APPLICATIONS INFORMATION
75
DC PERFORMANCE
1. DC input voltages in the vicinity of the filter’s half of the
total power supply are processed with exactly 0dB (or
1V/V) of gain.
2. The typical DC input voltage ranges are equal to:
VIN = ±5.8V, VS = ±7.5V
VIN = ±3.6V, VS = ±5V
VIN = ±1.4V, VS = ±2.5V
With an input DC voltage range of VIN = ±5V, (VS =
±7.5V), the measured CMRR was 100dB. Figure 1
shows the DC gain linearity of the filter exceeding the
requirements of a 14-bit, 10V full scale system.
3. The filter output DC offset VOS(OUT) is measured with
the input grounded and with dual power supplies. The
VOS(OUT) is typically ±0.1mV and it is optimized for the
filter connection shown in the test circuit figure. The
filter output offset is equal to:
VOS(OUT) = VOS (op amp A) –IBIAS × RF = 0.1mV (Typ)
4. The VOS(OUT) temperature drift is typically 7µV/°C
(TA > 25°C), and – 7µV/°C (TA < 25°C).
5. The VOS(OUT) temperature drift can be improved by
using an input resistor RIN equal to the feedback resis-
25
VIN – VOUT (µV)
The DC performance of the LTC1066-1 is dictated by the
DC characteristics of the input precision op amp.
50
VS = ±7.5V
TA = 25°C
fCLK = 1MHz
fC = 20kHz
0
–25
–50
–75
–100
–125
–6 –5 –4 –3 –2 –1 0 1 2 3
INPUT VOLTAGE (VDC)
5
4
6
1066-1 F01
Figure 1. DC Gain Linearity
tor RF, however, the absolute value of VOS(OUT) will
increase. For instance, if a 20k resistor is added in series
with pin 3 (see Test Circuit), the output VOS drift will be
improved by 2µV/°C to 3µV/°C, however, the VOS(OUT)
may increase by 1mV(MAX).
6. The filter DC output offset voltage VOS(OUT) is independent from the filter clock frequency (fCLK ≤ 250kHz).
Figures 2 and 3 show the VOS(OUT) variation for three
different power supplies and for clock frequencies up to
5MHz. Both figures were traced with the LTC1066-1
soldered into the PC board. Power supply decoupling is
very important, especially with ±7.5V supplies. If necessary connect a small resistor (20Ω) between pins 5
9
LTC1066-1
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APPLICATIONS INFORMATION
FILTER OUTPUT OFFSET VOLTAGE CHANGE (mV)
and 18, and between pins 10 and 4, to isolate the
precision op amp supply pin from the switched-capacitor network supply (see the Test Circuit).
0.2
0.1
VS = ±2.5V
0
VS = ±5V
–0.1
–0.2
–0.3
VS = ±7.5V
–0.4
–0.5
–0.6
–0.7
LINEAR PHASE
TA = 25°C
fCLK /fC = 100:1
–0.8
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
CLOCK FREQUENCY (MHz)
1066-1 F02
0.2
0
VS = ±2.5V
VS = ±5V
The filter’s low passband ripple, typically 0.05dB, is measured with respect to the AC passband gain.
The LTC1066-1 DC stabilizing loop slightly warps the
filter’s passband performance if the – 3dB frequency of the
feedback passive elements (1/2πRFCF) is more than the
cutoff frequency of the internal switched-capacitor filter
divided by 250. The LTC1066-1 clock tunability directly
relates to the above constraint. Figure 4 illustrates the
passband behavior of the LTC1066-1 and it demonstrates
the clock tunability of the device. A typical LTC1066-1
device was used to trace all four curves of Figure 4. Curve
D, for instance, has nearly zero ripple and 0.04dB passband gain. Curve D’s 20kHz cutoff is much higher than the
8Hz cutoff frequency of the RFCF feedback network, so its
passband is free from any additional error due to RFCF
feedback elements. Curve B illustrates the passband error
when the 1MHz clock of curve D is lowered to 100kHz. A
0.1dB error is added to the filter’s original AC gain of
0.04dB.
–0.2
1.00
–0.4
VS = ±7.5V
–0.6
TA = 25°C
fCLK/fC = 50:1
RF = 20k,
CF = 1µF
0.75
0.50
–0.8
–1.0
GAIN (dB)
FILTER OUTPUT OFFSET VOLTAGE CHANGE (mV)
Figure 2. Output Offset Change vs Clock
(Relative to Offset for fCLK = 250kHz)
absolutely perfect 0dB DC gain and phases into an “imperfect” AC passband gain, typically ±0.1dB.
TA = 25°C
fCLK /fC = 50:1
–1.2
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
CLOCK FREQUENCY (MHz)
0.25
0
A
–0.25
B
C
D
–0.50
1066-1 F03
–0.75
Figure 3. Output Offset Change vs Clock
(Relative to Offset for fCLK = 250kHz)
AC PERFORMANCE
–1.00
10
100
1k
FREQUENCY (Hz)
10k 20k
1
2πRFCF
1
CURVE C: fCUTOFF = 5kHz = 625 ×
2πRFCF
CURVE D: fCUTOFF = 20kHz = 2500 ×
AC (Passband) Gain
CURVE B: fCUTOFF = 2kHz = 250 ×
1
2πRFCF
The passband gain of the LTC1066-1 is equal to the
passband gain of the internal switched-capacitor lowpass
filter, and it is measured at f = 0.25fCUTOFF. Unlike conventional monolithic filters, the LTC1066-1 starts with an
CURVE A: fCUTOFF = 1kHz = 125 ×
1
2πRFCF
10
Figure 4. Passband Behavior
1066-1 F04
LTC1066-1
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APPLICATIONS INFORMATION
Transient Response and Settling Time
The LTC1066-1 exhibits two different transient behaviors.
First, during power-up the DC correcting loop will settle
after the voltage offset of the internal switched-capacitor
network is stored across the feedback capacitor CF (see
Block Diagram). It takes approximately five time constants
(5RFCF) for settling to 1%. Second, following DC loop
settling, the filter reaches steady state. The filter transient
response is then defined by the frequency characteristics
of the internal switched-capacitor lowpass filter. Figure 5
shows details.
DC loop settling is also observed if, at steady state, the DC
offset of the internal switched-capacitor network suddenly
changes. A sudden change may occur if the clock frequency is instantaneously stepped to a value above 1MHz.
ts
OUTPUT
INPUT
90%
50%
td
10%
and on the value of the power supplies. With proper layout
techniques the values of the clock feedthrough are shown
on Table 7.
Table 7. Clock Feedthrough
POWER SUPPLY
50:1
100:1
Single 5V
±5V
±7.5V
70µVRMS
100µVRMS
160µVRMS
90µVRMS
200µVRMS
650µVRMS
Wideband Noise
The wideband noise of the filter is the total RMS value of
the device’s noise spectral density and is used to determine the operating signal-to-noise ratio. Most of its frequency contents lie within the filter passband and cannot
be reduced with post filtering. For instance, the LTC10661 wideband noise at ±5V supply is 100µVRMS, 95µVRMS of
which have frequency contents from DC up to the filter’s
cutoff frequency. The total wideband noise (µVRMS) is
nearly independent of the value of the clock. The clock
feedthrough specifications are not part of the wideband
noise. Table 8 lists the typical wideband noise for each
supply.
Table 8. Wideband Noise
tr
100:1 LINEAR PHASE
0.43 ±5%
fCUTOFF
RISE TIME (tr)
50:1 ELLIPTIC
0.43
±5%
fCUTOFF
SETTLING TIME (ts)
3.4 ±5%
fCUTOFF
2.05
±5%
fCUTOFF
DELAY TIME (td)
0.709 ±5%
fCUTOFF
0.556 ±5%
fCUTOFF
1066-1 F05
Figure 5. Transient Response
Clock Feedthrough
Clock feedthrough is defined as the RMS value of the clock
frequency and its harmonics that are present at the filter’s
output pin (9). The clock feedthrough is tested with the
input pin (2) grounded and depends on PC board layout
POWER SUPPLY
50:1
100:1 (Pin 8 to GND)
Single 5V
±5V
±7.5V
90µVRMS
100µVRMS
106µVRMS
80µVRMS
85µVRMS
90µVRMS
Speed Limitations
To avoid op amp slew rate limiting at maximum clock
frequencies, the signal amplitude should be kept below a
specified level as shown in Table 9.
Table 9. Maximum VIN
INPUT FREQUENCY
MAXIMUM VIN
≥250kHz
≥700kHz
0.50VRMS
0.25VRMS
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APPLICATIONS INFORMATION
Aliasing
0
ALIASED OUTPUT (dB)
In a sampled-data system the sampling theorem says that
if an input signal has any frequency components greater
than one half the sampling frequency, aliasing errors will
appear at the output. In practice, aliasing is not always a
serious problem. High order switched-capacitor lowpass
filters are inherently band limited and significant aliasing
occurs only for input signals centered around the clock
frequency and its multiples.
–60
–80
fCLK – fC fCLK + fC
fCLK
Figure 6 shows the LTC1066-1 aliasing response when
operated with a clock-to-cutoff frequency ratio of 50:1.
With a 50:1 ratio LTC1066-1 samples its input twice
during one clock period and the sampling frequency is
equal to two times the clock frequency.
Figure 7 shows the LTC1066-1 aliased response when
operated with a clock-to-cutoff frequency ratio of 100:1
(linear phase response with pin 8 to ground).
12
2fCLK
2fCLK + 2.3fC
2fCLK – fC 2fCLK + fC
INPUT FREQUENCY
1066-1 F06
Figure 6. Aliasing vs Frequency
fCLK / fC = 50:1 (Pin 8 to V +)
Clock is a 50% Duty Cycle Square Wave
0
ALIASED OUTPUT (dB)
The figure also shows the maximum aliased output generated for inputs in the range of 2fCLK ±fC. For instance, if the
LTC1066-1 is programmed to produce a cutoff frequency
of 20kHz with 1MHz clock, a 10mV, 1.02MHz input signal
will cause a 10µV aliased signal at 20kHz. This signal will
be buried in the noise. Maximum aliasing will occur only
for input signals in the narrow range of 2MHz ±20kHz or
multiples of 2MHz.
2fCLK – 2.3fC
–26
–85
fCLK – 4fC
fCLK
fCLK + 4fC
fCLK – fC fCLK + fC
2fCLK – 4fC
2fCLK
2fCLK + 4fC
2fCLK – fC 2fCLK + fC
INPUT FREQUENCY
Figure 7. Aliasing vs Frequency
fCLK /fC = 100:1 (Pin 8 to Ground)
Clock is a 50% Duty Cycle Square Wave
1066-1 F07
LTC1066-1
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TYPICAL APPLICATIONS
Dual Supply Operation
DC Accurate, 10Hz to 100kHz, Clock-Tunable, 8th Order Elliptic Lowpass Filter
fCLK / fC = 50:1
100k
33µF
0.1µF
1
2
100k
VIN
3
20Ω
–7.5V
7.5V
0.1µF
0.1µF
200Ω
+IN A
+IN B
V–
V+
8
9
fCLK
OUT B
5
7
7.5V
–IN A
4
1N4148* 6
V+
OUT A
LTC1066-1
GND
FILTERIN
CONNECT 1
FILTEROUT
COMP 2
CONNECT 2
COMP 1
50/100
V–
CLK
20Ω
18
7.5V
17
0.1µF
VOUT
16
15
14
13
30k
12
15pF
11
10
1N4148*
0.1µF
–7.5V
MAXIMUM OUTPUT VOLTAGE OFFSET = ±5.5mV, DC LINEARITY = ±0.0063%, TA = 25°C.
THE PINS 6 TO 12 CONNECTION SHOULD BE UNDER THE IC AND SHIELDED BY AN
ANALOG SYSTEM GROUND PLANE.
RC COMPENSATION BETWEEN PINS 11 AND 13 REQUIRED ONLY FOR fCUTOFF ≥ 60kHz.
THE 33µF CAPACITOR IS A NONPOLARIZED, ALUMINUM ELECTROLYTIC, ±20%, 16V
(NICHICON UUPIC 330MCRIGS OR NIC NACEN 33M16V 6.3 × 5.5 OR EQUIVALENT).
* PROTECTION DIODES, 1N4148 ARE OPTIONAL. SEE PIN DESCRIPTIONS.
1066-1 TA03
Single 5V Supply Operation
DC Accurate, 10Hz to 36kHz, Clock-Tunable, 8th Order Elliptic Lowpass Filter
fCLK / fC = 50:1
100k
33µF
0.1µF
1
2
100k
3
VIN
5V
fCLK
OUT B
+IN A
+IN B
V–
V+
8
200Ω
–IN A
5
7
5V
V+
4
6
0.1µF
OUT A
9
LTC1066-1
CONNECT 1
FILTEROUT
50/100
CLK
GND
FILTERIN
COMP 2
CONNECT 2
COMP 1
V–
18
5V
17
0.1µF
VOUT
16
10k
15
14
13
12
1µF
30k
10k
15pF
11
10
INPUT LINEAR RANGE = 1.4V to 3.6V. DC LINEARITY = ±0.0063%.
THE PINS 6 TO 12 CONNECTION SHOULD BE UNDER THE IC AND SHIELDED BY AN
ANALOG SYSTEM GROUND PLANE.
RC COMPENSATION BETWEEN PINS 11 AND 13 REQUIRED ONLY FOR fCUTOFF ≥ 24kHz.
THE 33µF CAPACITOR IS A NONPOLARIZED, ALUMINUM ELECTROLYTIC, ±20%, 16V
(NICHICON UUPIC 330MCRIGS OR NIC NACEN 33M16V 6.3 × 5.5)
1066-1 TA04
13
LTC1066-1
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TYPICAL APPLICATIONS
DC Accurate Lowpass Filter with Input Anti-Aliasing
(fCLK ≤ 250kHz)
2ND ORDER BUTTERWORTH ANTIALIASING FILTER PROVIDES –68dB
ATTENUATION TO INPUTS AT 2fCLK
RF
C2
VIN
20Ω
CF
R2
R1
1
2
C1
3
20Ω
f
f
1
fCUTOFF = CLK ,
= CUTOFF
50 2πRFCF
250
7.5V
–7.5V
0.1µF
7.5V
f –3dB = 2•fCUTOFF (f –3dB IS THE –3dB FREQUENCY OF THE
0.1µF
2ND ORDER ANTI-ALIASING FILTER)
1
= 0.707•f –3dB, R2 = 17.946•R1, C2 = 10•C1
2π(R1 + R2)C1
FOR CUTOFF FREQUENCIES 2kHz TO 5kHz, SET RF = 20k,
CF = 1µF AND R1 + R2 ≤ 2k
fCLK
FOR CUTOFF FREQUENCIES <2kHz, SET R1 + R2 = RF
FOR EXAMPLE:
IF THE CUTOFF FREQUENCY OF LTC1066-1 IS 500Hz, THEN
f –3dB = 1000Hz
1
= 2Hz, SET RF = 80.6k, CF = 1µF AND C1 = 0.0027µF
2πRFCF
R1 + R2 = 80.6k, R1 = 4.22k AND R2 = 76.8k ROUNDED TO NEAREST 1% VALUE.
C2 = 0.027µF ROUNDED TO NEAREST STANDARD VALUE.
NOTE: RF SHOULD BE ≤100k TO MINIMIZE DC OFFSET TO ±5.5mV
OUT A
–IN A
OUT B
+IN A
+IN B
4
V–
5
V+
6
7
8
9
V
+
LTC1066-1
GND
FILTERIN
CONNECT 1
COMP 2
FILTEROUT
CONNECT 2
COMP 1
50/100
V–
CLK
18
17
VOUT
16
0.1µF
15
14
13
12
11
10
–7.5V
0.1µF
1066-1 TA05
DC Accurate Lowpass Filter with Input Anti-Aliasing
(fCLK > 250kHz)
2ND ORDER RC ANTI-ALIASING
FILTER PROVIDES –36dB ATTENUATION
TO INPUTS AT 2fCLK
402Ω
1k
f –3dB IS THE –3dB FREQUENCY
OF THE 2ND ORDER RC FILTER
f –3dB = 5•fCUTOFF
C=
100
f –3dB
µF (f –3dB IN Hz)
20Ω
2
C
3
20Ω
–7.5V
0.1µF
7.5V
0.1µF
–IN A
OUT B
+IN A
V–
5
+
6
8
fCLK
OUT A
V+
4
7
f
fCUTOFF = CLK
50
7.5V
1µF
1
VIN
C
20k
9
V
+IN B
LTC1066-1
CONNECT 1
FILTEROUT
50/100
CLK
GND
FILTERIN
COMP 2
CONNECT 2
COMP 1
V–
18
17
VOUT
16
0.1µF
15
14
13
12
11
10
–7.5V
0.1µF
1066-1 TA06
14
LTC1066-1
U
TYPICAL APPLICATIONS
DC Accurate Clock-Tunable Lowpass Filter with Tunable Input Anti-Aliasing Filter
(Circuit provides at least – 20dB attenuation to input frequencies at 2fCLK.
The clock-tunable range is 5 octaves.)
5V
1µF
0.1µF
+
1
12.1k
20
LTC1045
2
+
19
0.1µF
–
2k
FIRST ORDER RC
LOWPASS ANTI-ALIASING FILTER
0.1µF
3
+
18
–
–5V
5V
CLOCK-TUNABLE,
8TH ORDER LOWPASS FILTER
0.1µF
0.1µF
1k
4
4
+
17
0.1µF
–
500Ω
1
VIN
13
R1
1k
LTC202
2
3
C2
14
C3
20Ω
C1
RF
16
15
CF
9
0.1µF
5
10
+
16
9
1
11
3
7
–
2
C4
8
6
RIN*
C5
5
500Ω
5V
11
12
5
6
12
10
4
CIN*
0.1µF
13
0.1µF
7
8
200Ω
9
LTC1066-1
18
V+
OUT A
17
–IN A
OUT B
16
+IN A
+IN B
15
–
V
GND
14
+
FIN
V
13
CON 1
COMP 2
12
F OUT
CON 2
11
50/100
COMP 1
10
–
CLK
V
CLOCK INPUT
(TTL OR CMOS)
VOUT
0.1µF
–5V
0.1µF
20Ω
0.1µF
LTC1045
6
+
15
8
–
PULSE
AVERAGE
CP
50pF
7
COMPONENT CALCULATIONS FOR A CLOCK-TUNABLE RANGE OF FIVE OCTAVES:
DEFINITIONS:1.THE CUTOFF FREQUENCY OF LTC1066-1 IS ABBREVIATED AS f C
2.f C(LOW) IS THE LOWEST CUTOFF FREQUENCY OF INTEREST
3.A RANGE OF FIVE OCTAVES IS FROM f
C(LOW) TO 32fC(LOW)
COMPONENT CALCULATIONS:
fC(LOW)
1
=
; RIN* = RF (IF RF CAN BE CHOSEN TO BE 20k, RIN AND CIN ARE OMITTED.
2πRFCF f 125
/125 ALLOWS FOR 0.2dB GAIN PEAK IN THE PASSBAND)
C1 =
+
14
RP
–
fC(LOW)
C(LOW)
µF (fC(LOW) IN Hz) ; R1 = 1k
C2 = C1, C3 = 2•C1, C4 = 4•C1, C5 = 8•C1
RA
CA
0.047µF
CP = 50pF; RP =
PULSE
OUTPUT
105
k
50•fC(LOW)
CA = 0.047µF; RA =
EXAMPLE:
CLOCK FREQUENCY DETECTOR
1
5 × 105
k
50•fC(LOW)
LET’S CHOOSE A FIVE OCTAVE RANGE FROM 1kHz TO 32kHz. fC(LOW) = 1kHz (1000Hz).
LET CF = 1µF, THEN RF CALCULATES TO BE 20k. RIN AND CIN OMITTED;
R1 = 1k, C1 = 0.001µF, C2 = 0.001µF, C3 = 0.0022µF, C4 = 0.0039µF,
C5 = 0.0082µF. CP = 50pF, RP = 2k, CA = 0.047µF, RA = 10k
1066-1 TA08
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1066-1
U
TYPICAL APPLICATIONS
100kHz Elliptic Lowpass Filter with Input Anti-Aliasing and Output Clock Feedthrough Filters
(Not DC Accurate)
2ND ORDER BUTTERWORTH INPUT
ANTI-ALIASING FILTER PROVIDES
–68dB ATTENUATION TO INPUTS AT 2fCLK.
f –3dB = 200kHz
2.49k
C1
51pF
1
VIN
10k
2
C2
510pF
3
–8V
0.1µF
8V
0.1µF
fCUTOFF =
OUT B
+IN A
+IN B
5
V+
FILTERIN
FILTEROUT
COMP 2
CONNECT 2
COMP 1
50/100
9
GND
LTC1066-1
CONNECT 1
8
fCLK
C2
C1 =
10
100
C2 =
µF (f –3dB IN Hz)
f –3dB
–IN A
V–
7
fCLK
50
V+
4
6
f –3dB = 2•fCUTOFF
OUT A
V–
CLK
18
17
16
1000pF
0.1µF
15
14
Gain vs Frequency
13
12
10
30k
20pF
0
11
–10
10
–8V
–20
0.1µF
–30
GAIN (dB)
2.49k
OUTPUT CLOCK
FEEDTHROUGH
FILTER
8V
100Ω
VOUT
1066-1 TA07a
–40
–50
–60
–70
–80
–90
–100
10k
100k
1M
FREQUENCY (Hz)
10M
1066-1 TA07b
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S Package
18-Lead Plastic SOL
0.005
(0.127)
RAD MIN
0.291 – 0.299
(7.391 – 7.595)
(NOTE 2)
0.010 – 0.029 × 45°
(0.254 – 0.737)
0.447 – 0.463
(11.354 – 11.760)
(NOTE 2)
18
0.093 – 0.104
(2.362 – 2.642)
17
16
15
14
13
12
11
10
0.037 – 0.045
(0.940 – 1.143)
0° – 8° TYP
0.394 – 0.419
(10.007 – 10.643)
SEE NOTE
0.009 – 0.013
(0.229 – 0.330)
NOTE 1
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
TYP
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
2. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).
16
0.004 – 0.012
(0.102 – 0.305)
0.014 – 0.019
(0.356 – 0.482)
TYP
Linear Technology Corporation
1
2
3
4
5
6
7
8
9
LT/GP 0594 10K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977
 LINEAR TECHNOLOGY CORPORATION 1994