MC74AC4040
12−Stage Binary Ripple
Counter
The MC74AC4040 consists of 12 master-slave flip-flops. The
output of each flip-flop feeds the next and the frequency at each output
is half that of the preceding one. The state of the counter advances on
the negative-going edge of the Clock input. Reset is asynchronous and
active-high.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with the Clock of the
MC74AC4040 for some designs.
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PDIP−16
N SUFFIX
CASE 648
16
1
Features
•
•
•
•
•
140 MHz Typ. Clock
Outputs Source/Sink 24 mA
Operating Voltage Range: 2.0 to 6.0 V
High Noise Immunity
Pb−Free Packages are Available
VCC
Q11
Q10
Q8
Q9
16
15
14
13
12
16
1
RESET CLK
11
10
Q1
SOIC−16
D SUFFIX
CASE 751B
SOEIAJ−16
M SUFFIX
CASE 966
16
1
9
ORDERING INFORMATION
Device
MC74AC4040N
1
2
3
4
5
6
7
8
Q12
Q6
Q5
Q7
Q4
Q3
Q2
GND
Figure 1. Pinout: 16−Lead Packages Conductors
(Top View)
FUNCTION TABLE
Clock
X
Reset
Output State
L
No Change
L
Advance to next state
H
All Outputs are low
Package
Shipping†
PDIP−16
25 Units/Rail
MC74AC4040NG
PDIP−16
(Pb−Free)
25 Units/Rail
MC74AC4040D
SOIC−16
48 Units/Rail
MC74AC4040DG
SOIC−16
(Pb−Free)
48 Units/Rail
MC74AC4040DR2
SOIC−16
2500 Tape & Reel
MC74AC4040DR2G
SOIC−16 2500 Tape & Reel
(Pb−Free)
MC74AC4040M
SOEIAJ−16
50 Units/Rail
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 7
1
Publication Order Number:
MC74AC4040/D
MC74AC4040
9
7
6
5
CLOCK
10
3
2
4
13
12
14
15
1
RESET
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
11
PIN 16 = VCC
PIN 8 = GND
Figure 2. Logic Diagram
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
−0.5 to +7.0
V
VIN
DC Input Voltage (Referenced to GND)
−0.5 to VCC +0.5
V
VOUT
DC Output Voltage (Referenced to GND)
−0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
±20
mA
IOUT
DC Output Current, per Pin
±50
mA
ICC
DC VCC or GND Current per Output Pin
±50
mA
PD
Power Dissipation in Still Air
Plastic{
SOIC Package{
750
500
mW
Tstg
Storage Temperature
TL
Lead Temperature, 1 mm from Case for 10 seconds
(Plastic DIP or SOIC Package)
−65 to +150
°C
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
†Derating: Plastic DIP: − 10mW/°C from 65°C to 125°C SOIC Package: −7.0 mW/°C from 65°C to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
DC Supply Voltage (Referenced to GND)
VIN/VOUT
Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr/tf
Input Rise/Fall Time
(Figure 1)
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
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2
Min
Max
Unit
2.0
6.0
V
0
VCC
−
−40
+85
°C
0
0
0
150
40
25
ns/V
MC74AC4040
DC CHARACTERISTICS (unless otherwise specified)
Symbol
Parameter
Value
Unit
ICC
Maximum Quiescent Supply Voltage
80
mA
Vin = VCC or GND
VCC = 5.5 V, TA = Worst Case
ICC
Maximum Quiescent Supply Current
8.0
mA
Vin = VCC or GND
VCC = 5.5 V, TA = 25°C
DC CHARACTERISTICS
74AC
74AC
VCC
TA = +25°C
TA = −40°C to +85°C
Symbol
Parameter
(V)
Typ
VIH
Minimum High Level Input Voltage
3.0
4.5
5.5
−
−
−
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1 V
or VCC − 0.1 V
3.0
4.5
5.5
−
−
−
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1 V
or VCC − 0.1 V
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
V
3.0
4.5
5.5
−
−
−
2.56
3.86
4.86
2.46
3.76
4.76
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
5.5
−
−
−
0.36
0.36
0.36
0.44
0.44
0.44
5.5
−
±0.1
5.5
−
5.5
−
VIL
VOH
VOL
IIN
IOLD
IOHD
Maximum Low Level Input Voltage
Minimum High Level Output Voltage
Maximum Low Level Output Voltage
Maximum Input Leakage Current
Minimum Dynamic Output Current{
Guaranteed Limits
Conditions
IOUT = −50 mA
V
*VIN = VIL or VIH
−12 mA
IOH
−24 mA
−24 mA
IOUT = 50 mA
V
V
*VIN = VIL or VIH
12 mA
IOL
24 mA
24 mA
±1.0
mA
VI = VCC, GND
−
75
mA
VOLD = 1.65 V Max
−
−75
mA
VOHD = 3.85 V Min
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
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3
Unit
MC74AC4040
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC
74AC
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
VCC*
(V)
Min
Typ
Max
Min
Max
Unit
Fig. No.
fmax
Maximum Clock
Frequency
3.3
5.0
110
130
120
140
−
−
100
120
−
−
MHz
−
nCP to Q1
Propagation Delay
nCP to Q1
3.3
5.0
2.0
2.0
−
−
11
8.0
2.0
2.0
14
10
ns
−
Qn to Qn +1
Propagation Delay
Qn to Qn +1
3.3
5.0
0
0
−
−
5.5
3.5
0
0
6.5
4.5
ns
−
MR to Q
tHL
Propagation Delay
MR to Q
3.3
5.0
3.0
3.0
−
−
12
10
3.0
3.0
15
12
ns
−
trec
nCP to MR
Recovery Time
3.3
5.0
0
0
−2.5
−1.5
−
−
0
0
−
−
ns
−
tw nCP
Minimum Pulse Width
Clock Pin
3.3
5.0
4.0
3.0
3.5
2.5
−
−
4.5
3.5
−
−
ns
−
tw MR
Minimum Pulse Width
Master Reset
3.3
3.0
4.0
3.0
3.5
2.5
−
−
4.5
3.5
−
−
ns
−
Symbol
Parameter
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol
Parameter
Value
Typ
Unit
Test Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0 V
CPD
Power Dissipation Capacitance
50
pF
VCC = 5.0 V
MARKING DIAGRAMS
PDIP−16
SOIC−16
SOEIAJ−16
MC74AC4040N
AWLYYWWG
AC4040G
AWLYWW
74AC4040
ALYW
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
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4
MC74AC4040
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
DIM
A
B
C
D
F
G
H
J
K
L
M
S
S
−T−
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
T A
M
M
STYLE 1:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
STYLE 2:
PIN 1. COMMON DRAIN
2. COMMON DRAIN
3. COMMON DRAIN
4. COMMON DRAIN
5. COMMON DRAIN
6. COMMON DRAIN
7. COMMON DRAIN
8. COMMON DRAIN
9. GATE
10. SOURCE
11. GATE
12. SOURCE
13. GATE
14. SOURCE
15. GATE
16. SOURCE
SOIC
CASE 751B−05
ISSUE J
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
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5
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC74AC4040
PACKAGE DIMENSIONS
SOEIAJ−16
CASE 966−01
ISSUE A
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
9
Q1
M_
E HE
1
8
L
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.78
INCHES
MIN
MAX
−−−
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−−
0.031
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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6
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MC74AC4040/D