Product Folder Sample & Buy Technical Documents Support & Community Tools & Software ADC121S101, ADC121S101-Q1 SNAS304H – JANUARY 2006 – REVISED APRIL 2016 ADC121S101x Single-Channel, 0.5 to 1-Msps, 12-Bit Analog-to-Digital Converter 1 Features 3 Description • • • • • The ADC121S101 is a low-power, single-channel CMOS 12-bit analog-to-digital converter with a highspeed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC121S101 is fully specified over a sample rate range of 500 ksps to 1 Msps. The converter is based upon a successive-approximation register architecture with an internal track-and-hold circuit. 1 • • • • Specified Over a Range of Sample Rates 6-Pin WSON and SOT-23 Packages Variable Power Management Single Power Supply With 2.7 V to 5.25 V Range SPI™, QSPI™, MICROWIRE, and DSP Compatible AEC-Q100 Grade 1 Qualified DNL: +0.5 / −0.3 LSB (Typical) INL: ±0.40 LSB (Typical) Power Consumption: – 3-V Supply: 2 mW (Typical) – 5-V Supply: 10 mW (Typical) 2 Applications • • • • Portable Systems Remote Data Acquisition Instrumentation and Control Systems Automotive The output serial data is straight binary, and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE, and many common DSP serial interfaces. The ADC121S101 operates with a single supply with a range from 2.7 V to 5.25 V. Normal power consumption using a 3 V or 5 V supply is 2 mW and 10 mW, respectively. The power-down feature reduces the power consumption to as low as 2.6 µW using a 5-V supply. The ADC121S101 is packaged in 6-pin WSON and SOT-23 packages. Operation over the temperature range of −40°C to 125°C is specified. Device Information(1) PART NUMBER ADC121S101 PACKAGE BODY SIZE (NOM) WSON (6) 2.50 mm × 2.20 mm SOT-23 (6) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. INL, fSCLK = 10 MHz 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC121S101, ADC121S101-Q1 SNAS304H – JANUARY 2006 – REVISED APRIL 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 4 4 4 4 5 5 7 9 Absolute Maximum Ratings ...................................... ESD Ratings: ADC121S101 ..................................... ESD Ratings: ADC121S101-Q1 ............................... Recommended Operating Conditions....................... Thermal Information ................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. Detailed Description ............................................ 12 8.1 Overview ................................................................. 12 8.2 Functional Block Diagram ....................................... 13 8.3 Feature Description................................................. 13 8.4 Device Functional Modes........................................ 15 9 Application and Implementation ........................ 17 9.1 Application Information............................................ 17 9.2 Typical Application .................................................. 17 10 Power Supply Recommendations ..................... 19 10.1 Power Management .............................................. 19 10.2 Power Supply Noise Considerations..................... 19 11 Layout................................................................... 20 11.1 Layout Guidelines ................................................ 20 11.2 Layout Example ................................................... 20 12 Device and Documentation Support ................. 21 12.1 12.2 12.3 12.4 12.5 Device Support...................................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 22 22 22 22 13 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (January 2014) to Revision H • Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Changes from Revision F (May 2013) to Revision G • Page Changed sentence in the Using the ADC121S101 section.................................................................................................. 13 Changes from Revision E (May 2013) to Revision F • 2 Page Changed layout of National Data Sheet to TI format ............................................................................................................. 1 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 ADC121S101, ADC121S101-Q1 www.ti.com SNAS304H – JANUARY 2006 – REVISED APRIL 2016 5 Device Comparison Table (1) SPECIFIED SAMPLE RATE RANGE RESOLUTION (1) 50 TO 200 KSPS 200 TO 500 KSPS 500 KSPS TO 1 MSPS 12 Bits ADC121S021 ADC121S051 ADC121S101 10 Bits ADC101S021 ADC101S051 ADC101S101 8 Bits ADC081S021 ADC081S051 ADC081S101 All devices are fully pin and function compatible. 6 Pin Configuration and Functions NGF Package 6-Pin WSON Top View V A GND V IN DBV Package 6-Pin SOT-23 Top View 1 6 CS 2 5 SDATA 3 4 SCLK V A GND V IN 1 6 CS 2 5 SDATA 3 4 SCLK Pin Functions PIN NO. NAME TYPE (1) DESCRIPTION 1 VA P Positive supply pin. This pin must be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with a 1-µF capacitor and a 0.1-µF monolithic capacitor located within 1 cm of the power pin. 2 GND G The ground return for the supply and signals. 3 VIN I Analog input. This signal can range from 0 V to VA. 4 SCLK I Digital clock input. This clock directly controls the conversion and readout processes. 5 SDATA O Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. CS I Chip select. On the falling edge of CS, a conversion process begins. GND G For package suffix CISD(X) only. TI recommends connecting the center pad to ground. 6 PAD (1) G = Ground, I = Input, O = Output, P = Power Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 Submit Documentation Feedback 3 ADC121S101, ADC121S101-Q1 SNAS304H – JANUARY 2006 – REVISED APRIL 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN MAX UNIT Analog supply voltage, VA –0.3 6.5 V Voltage on any digital pin to GND –0.3 6.5 V Voltage on any analog pin to GND –0.3 VA + 0.3 V ±10 mA ±20 mA 150 °C 150 °C Input current at any pin (4) Package input current (4) See (5) Power consumption at TA = 25°C Junction temperature, TJ Storage temperature, Tstg (1) (2) (3) (4) (5) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are measured with respect to GND = 0 V (unless otherwise specified). If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin must be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute Maximum Ratings does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification. The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDmax = (TJmax − TA) / θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (that is, when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions must always be avoided. 7.2 ESD Ratings: ADC121S101 VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT ±3500 Machine model (MM) V ±300 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 7.3 ESD Ratings: ADC121S101-Q1 VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±3500 Charged-device model (CDM), per AEC Q100-011, all pins ±300 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN VA Supply voltage Digital input pins voltage (regardless of supply voltage) Analog input pins voltage Clock frequency (1) 4 MAX UNIT 2.7 5.25 V –0.3 5.25 V 0 VA V 25 20000 kHz 125 °C Up to 1 Msps Sample rate TA NOM Operating temperature –40 All voltages are measured with respect to GND = 0 V (unless otherwise specified). Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 ADC121S101, ADC121S101-Q1 www.ti.com SNAS304H – JANUARY 2006 – REVISED APRIL 2016 7.5 Thermal Information ADC121S101 THERMAL METRIC (1) NGF (WSON) DBV (SOT-23) 6 PINS 6 PINS UNIT RθJA Junction-to-ambient thermal resistance 94 265 °C/W RθJC(top) Junction-to-case (top) thermal resistance 118 151 °C/W RθJB Junction-to-board thermal resistance 69 30 °C/W ψJT Junction-to-top characterization parameter 6.5 30 °C/W ψJB Junction-to-board characterization parameter 69 29 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 15 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.6 Electrical Characteristics VA = 2.7 V to 5.25 V, GND = 0 V, fSCLK = 10 MHz to 20 MHz, CL = 15 pF, fSAMPLE = 500 ksps to 1 Msps, and TA = 25°C (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN (2) TYP MAX (2) UNIT STATIC CONVERTER Resolution with no missing codes INL VA = 2.7 V to 3.6 V, –40°C ≤ TA ≤ 125°C –40°C ≤ TA ≤ 85°C, VA = 2.7 V to 3.6 V SOT-23 –1 ±0.4 1 WSON –1.2 ±0.4 1 TA = 125°C, VA = 2.7 V to 3.6 V SOT-23 –1.1 WSON –1.3 Integral non-linearity DNL –40°C ≤ TA ≤ 85°C, VA = 2.7 V to 3.6 V Differential non-linearity TA = 125°C, VA = 2.7 V to 3.6 V VOFF GE –40°C ≤ TA ≤ 125°C, VA = 2.7 V to 3.6 V Offset error 1 –0.9 Bits LSB 1 0.5 1 –0.3 –1 LSB 1 –1.2 ±0.1 1.2 SOT-23 –1.2 ±0.2 1.2 WSON –1.5 ±0.2 1.5 70 72 VA = 2.7 V to 5.25 V, –40°C ≤ TA ≤ 85°C fIN = 100 kHz, –0.02 dBFS 70.8 72.5 VA = 2.7 V to 5.25 V, TA = 125°C fIN = 100 kHz, –0.02 dBFS 70.6 –40°C ≤ TA ≤ 125°C, VA = 2.7 V to 3.6 V Gain error 12 LSB LSB DYNAMIC CONVERTER SINAD Signal-to-noise plus distortion ratio SNR Signal-to-noise ratio VA = 2.7 V to 5.25 V, –40°C ≤ TA ≤ 125°C fIN = 100 kHz, –0.02 dBFS dB dB THD Total harmonic distortion VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS –80 dB SFDR Spurious-free dynamic range VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS 82 dB ENOB Effective number of bits VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS, –40°C ≤ TA ≤ 125°C 11.6 Bits Intermodulation distortion, second order terms VA = 5.25 V, fa = 103.5 kHz, fb = 113.5 kHz –78 dB Intermodulation distortion, third order terms VA = 5.25 V, fa = 103.5 kHz, fb = 113.5 kHz –78 dB IMD FPBW (1) (2) –3-dB full power bandwidth 11.3 VA = 5 V 11 VA = 3 V 8 MHz Tested limits are guaranteed to TI's AOQL (Average Outgoing Quality Level). Data sheet minimum and maximum specification limits are guaranteed by design, test, or statistical analysis. Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 Submit Documentation Feedback 5 ADC121S101, ADC121S101-Q1 SNAS304H – JANUARY 2006 – REVISED APRIL 2016 www.ti.com Electrical Characteristics (continued) VA = 2.7 V to 5.25 V, GND = 0 V, fSCLK = 10 MHz to 20 MHz, CL = 15 pF, fSAMPLE = 500 ksps to 1 Msps, and TA = 25°C (unless otherwise noted)(1) PARAMETER MIN (2) TEST CONDITIONS TYP MAX (2) UNIT ANALOG INPUT VIN Input range IDCL DC leakage current CINA Input capacitance 0 to VA –40°C ≤ TA ≤ 125°C –1 V 1 Track mode 30 Hold mode 4 µA pF DIGITAL INPUT VA = 5.25 V, –40°C ≤ TA ≤ 125°C 2.4 VA = 3.6 V, –40°C ≤ TA ≤ 125°C 2.1 VIH Input high voltage VIL Input low voltage IIN Input current VIN = 0 V or VA, –40°C ≤ TA ≤ 125°C CIND Digital input capacitance –40°C ≤ TA ≤ 125°C V VA = 5 V, –40°C ≤ TA ≤ 125°C 0.8 VA = 3 V, –40°C ≤ TA ≤ 125°C 0.4 –1 V ±0.1 1 µA 2 4 pF DIGITAL OUTPUT VOH Output high voltage VOL Output low voltage ISOURCE = 200 µA, –40°C ≤ TA ≤ 125°C VA – 0.2 ISOURCE = 1 mA 0.03 ISINK = 1 mA –40°C ≤ TA ≤ 125°C COUT –40°C ≤ TA ≤ 125°C TRI-STATE output capacitance V VA – 0.1 ISINK = 200 µA, –40°C ≤ TA ≤ 125°C IOZH, IOZL TRI-STATE leakage current VA – 0.07 0.4 0.1 –10 Output coding V ±0.1 10 µA 2 4 pF Straight (natural) binary POWER SUPPLY VA –40°C ≤ TA ≤ 125°C Supply voltage 2.7 5.25 V VA = 5.25 V, fSAMPLE = 1 Msps, –40°C ≤ TA ≤ 125°C 2.0 3.2 VA = 3.6 V, fSAMPLE = 1 Msps, –40°C ≤ TA ≤ 125°C 0.6 1.5 Supply current, shutdown (CS high) fSCLK = 0 MHz, VA = 5 V, fSAMPLE = 0 ksps 500 nA fSCLK = 20 MHz, VA = 5 V, fSAMPLE = 0 ksps 60 µA Power consumption, normal mode (operational, CS low) VA = 5 V, –40°C ≤ TA ≤ 125°C 10 16 VA = 3 V, –40°C ≤ TA ≤ 125°C 2.0 4.5 Power consumption, shutdown (CS high) fSCLK = 0 MHz, VA = 5 V, fSAMPLE = 0 ksps 2.5 fSCLK = 20 MHz, VA = 5 V, fSAMPLE = 0 ksps 300 fSCLK Clock frequency (3) –40°C ≤ TA ≤ 125°C (4) 10 20 MHz fS Sample rate –40°C ≤ TA ≤ 125°C (4) 500 1000 ksps DC SCLK duty cycle fSCLK = 20 MHz, –40°C ≤ TA ≤ 125°C tACQ Minimum time required for acquisition –40°C ≤ TA ≤ 125°C tQUIET Quiet time –40°C ≤ TA ≤ 125°C (5) tAD Aperture delay 3 ns tAJ Aperture jitter 30 ps Supply current, normal mode (operational, CS low) IA PD mA mW µW AC (3) (4) (5) 6 40% 50% 60% 350 50 ns ns This condition is for fSCLK = 20 MHz. This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under Operating Ratings. Minimum quiet time required by bus relinquish and the start of the next conversion. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 ADC121S101, ADC121S101-Q1 www.ti.com SNAS304H – JANUARY 2006 – REVISED APRIL 2016 7.7 Timing Requirements VA = 2.7 V to 5.25 V, GND = 0 V, fSCLK = 10 MHz to 20 MHz, CL = 25 pF, fSAMPLE = 500 ksps to 1 Msps, and TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX tCS Minimum CS pulse width –40°C ≤ TA ≤ 125°C 10 tSU CS to SCLK setup time –40°C ≤ TA ≤ 125°C 10 tEN Delay from CS until SDATA TRI-STATE disabled (1) –40°C ≤ TA ≤ 125°C 20 VA = 2.7 V to 3.6 V, –40°C ≤ TA ≤ 125°C 40 VA = 4.75 V to 5.25 V, –40°C ≤ TA ≤ 125°C 20 Data access time after SCLK falling edge (2) tACC UNIT ns ns ns ns tCL SCLK low pulse width –40°C ≤ TA ≤ 125°C 0.4 × tSCLK ns tCH SCLK high pulse width –40°C ≤ TA ≤ 125°C 0.4 × tSCLK ns VA = 2.7 V to 3.6 V, –40°C ≤ TA ≤ 125°C 7 VA = 4.75 V to 5.25 V, –40°C ≤ TA ≤ 125°C 5 VA = 2.7 V to 3.6 V, –40°C ≤ TA ≤ 125°C 6 25 VA = 4.75 V to 5.25 V, –40°C ≤ TA ≤ 125°C 5 25 tH SCLK to data valid hold time tDIS SCLK falling edge to SDATA high impedance tPOWER-UP (1) (2) (3) (3) ns ns Power-up time from full power down 1 µs Measured with the timing test circuit and defined as the time taken by the output signal to cross 1 V. Measured with the timing test circuit and defined as the time taken by the output signal to cross 1 V or 2 V. tDIS is derived from the time taken by the outputs to change by 0.5 V with the timing test circuit. The measured number is then adjusted to remove the effects of charging or discharging the output capacitance. This means that tDIS is the true bus relinquish time, independent of the bus loading. IOL 200 PA To Output Pin 1.6 V CL 25 pF IOH 200 PA Figure 1. Timing Test Circuit Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 Submit Documentation Feedback 7 ADC121S101, ADC121S101-Q1 SNAS304H – JANUARY 2006 – REVISED APRIL 2016 www.ti.com Hold Track | CS tCS tSU tACQ tCL 1 2 3 4 12 13 14 15 17 16 Z1 Z0 3 leading zero bits DB11 18 19 20 tQUIET tCH | Z2 5 tACC tEN SDATA | SCLK tH tDIS TRI-STATE DB3 DB2 DB1 DB0 12 data bits Figure 2. Serial Timing Diagram 8 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 ADC121S101, ADC121S101-Q1 www.ti.com SNAS304H – JANUARY 2006 – REVISED APRIL 2016 7.8 Typical Characteristics TA = 25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 10 MHz to 20 MHz, and fIN = 100 kHz (unless otherwise noted) Figure 3. DNL, fSCLK = 10 MHz Figure 4. INL, fSCLK = 10 MHz Figure 5. DNL, fSCLK = 20 MHz Figure 6. INL, fSCLK = 20 MHz Figure 7. DNL vs Clock Frequency Figure 8. INL vs Clock Frequency Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 Submit Documentation Feedback 9 ADC121S101, ADC121S101-Q1 SNAS304H – JANUARY 2006 – REVISED APRIL 2016 www.ti.com Typical Characteristics (continued) TA = 25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 10 MHz to 20 MHz, and fIN = 100 kHz (unless otherwise noted) 10 Figure 9. SNR vs Clock Frequency Figure 10. SINAD vs Clock Frequency Figure 11. SFDR vs Clock Frequency Figure 12. THD vs Clock Frequency Figure 13. Spectral Response VA = 5.25 V, fSCLK = 10 MHz Figure 14. Spectral Response VA = 5.25 V, fSCLK = 20 MHz Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 ADC121S101, ADC121S101-Q1 www.ti.com SNAS304H – JANUARY 2006 – REVISED APRIL 2016 Typical Characteristics (continued) TA = 25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 10 MHz to 20 MHz, and fIN = 100 kHz (unless otherwise noted) Figure 15. Power Consumption vs Throughput, fSCLK = 20 MHz Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 Submit Documentation Feedback 11 ADC121S101, ADC121S101-Q1 SNAS304H – JANUARY 2006 – REVISED APRIL 2016 www.ti.com 8 Detailed Description 8.1 Overview The ADC121S101 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter core. Simplified schematics of the ADC121S101 in both track and hold modes are shown in Figure 16 and Figure 17, respectively. In Figure 16, the device is in track mode: switch SW1 connects the sampling capacitor to the input, and SW2 balances the comparator inputs. The device is in this state until CS is brought low, at which point the device moves to hold mode. Figure 17 shows the device in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the chargeredistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The device moves from hold mode to track mode on the 13th rising edge of SCLK. CHARGE REDISTRIBUTION DAC VIN SAMPLING CAPACITOR SW1 SW2 GND + - CONTROL LOGIC VA 2 Figure 16. ADC121S101 in Track Mode CHARGE REDISTRIBUTION DAC VIN SAMPLING CAPACITOR SW1 SW2 GND + - CONTROL LOGIC VA 2 Figure 17. ADC121S101 in Hold Mode 12 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 ADC121S101, ADC121S101-Q1 www.ti.com SNAS304H – JANUARY 2006 – REVISED APRIL 2016 8.2 Functional Block Diagram T/H VIN 12-BIT SUCCESSIVE APPROXIMATION ADC SCLK CONTROL LOGIC CS SDATA Copyright © 2016, Texas Instruments Incorporated 8.3 Feature Description See the Functional Block Diagram for the serial interface timing diagram for the ADC. CS is chip select, which initiates conversions on the ADC and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is found as a serial data stream. Basic operation of the ADC begins with CS going low, which initiates a conversion process and data transfer. Subsequent rising and falling edges of SCLK are labelled with reference to the falling edge of CS; for example, the third falling edge of SCLK shall refer to the third falling edge of SCLK after CS goes low. At the fall of CS, the SDATA pin comes out of TRI-STATE, and the converter moves from track mode to hold mode. The input signal is sampled and held for conversion on the falling edge of CS. The converter moves from hold mode to track mode on the 13th rising edge of SCLK (see Figure 2). The interval for the tACQ specification begins at this point. At least 350 ns must pass between the 13th rising edge of SCLK and the next falling edge of CS. The SDATA pin is placed back into TRI-STATE after the 16th falling edge of SCLK, or at the rising edge of CS, whichever occurs first. After a conversion is completed, the quiet time tQUIET must be satisfied before bringing CS low again to begin another conversion. Sixteen SCLK cycles are required to read a complete sample from the ADC. The sample bits (including leading zeroes) are clocked out on falling edges of SCLK, and are intended to be clocked in by a receiver on subsequent falling edges of SCLK. The ADC produces three leading zero bits on SDATA, followed by twelve data bits, most significant first. If CS goes low before the rising edge of SCLK, an additional (fourth) zero bit may be captured by the next falling edge of SCLK. 8.3.1 Determining Throughput Throughput depends on the frequency of SCLK and how much time is allowed to elapse between the end of one conversion and the start of another. At the maximum specified SCLK frequency, the maximum guaranteed throughput is obtained by using a 20-SCLK frame. As shown in Figure 2, the minimum allowed time between CS falling edges is determined by 1) 12.5 SCLKs for Hold mode, 2) the larger of two quantities: either the minimum required time for Track mode (tACQ) or 2.5 SCLKs to finish reading the result and 3) 0, 1/2 or 1 SCLK padding to ensure an even number of SCLK cycles so there is a falling SCLK edge when CS next falls. For example, at the fastest rate for this family of parts, SCLK is 20MHz and 2.5 SCLKs are 125 ns, so calculate the minimum time between CS falling edges using Equation 1. 12.5 × 50 ns + 350 ns + 0.5 × 50 ns = 1000 ns (1) (12.5 SCLKs + tACQ + 1/2 SCLK) which corresponds to a maximum throughput of 1 MSPS. At the slowest rate for this family, SCLK is 1 MHz. Using a 20 cycle conversion frame as shown in Figure 2 yields a 20-µs time between CS falling edges for a throughput of 50 KSPS. Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 Submit Documentation Feedback 13 ADC121S101, ADC121S101-Q1 SNAS304H – JANUARY 2006 – REVISED APRIL 2016 www.ti.com Feature Description (continued) It is possible, however, to use fewer than 20 clock cycles provided the timing parameters are met. With a 1-MHz SCLK, there are 2500 ns in 2.5-SCLK cycles, which is greater than tACQ. After the last data bit has come out, the clock requires one full cycle to return to a falling edge. Thus the total time between falling edges of CS is 12.5 × 1 µs + 2.5 × 1 µs + 1 × 1 µs = 16 µs, which is a throughput of 62.5 KSPS. 8.3.2 ADC Transfer Function The output format of the ADC is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC is VA/4096. Figure 18 shows the ideal transfer characteristic. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a voltage of VA/8192. Other code transitions occur at steps of one LSB. 111...111 111...000 | | ADC CODE 111...110 1 LSB = VA/4096 011...111 000...010 | 000...001 000...000 0V 0.5 LSB ANALOG INPUT +VA-1.5 LSB Figure 18. Ideal Transfer Characteristic 8.3.3 Analog Inputs Figure 19 shows an equivalent circuit for the ADC's input. Diodes D1 and D2 provide ESD protection for the analog inputs. At no time must the analog input go beyond (VA + 300 mV) or (GND − 300 mV), as these ESD diodes will begin conducting, which could result in erratic operation. For this reason, the ESD diodes must not be used to clamp the input signal. The capacitor C1 in Figure 19 has a typical value of 4 pF, and is mainly the package pin capacitance. Resistor R1 is the on resistance of the track or hold switch, and is typically 500 Ω. Capacitor C2 is the ADC sampling capacitor and is typically 26 pF. The ADC delivers the best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance. This is especially important when using the ADC to sample AC signals. Also important when sampling dynamic signals is an anti-aliasing filter. VA D1 R1 C2 26 pF VIN C1 4 pF D2 Conversion Phase - Switch Open Track Phase - Switch Closed Figure 19. Equivalent Input Circuit 14 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 ADC121S101, ADC121S101-Q1 www.ti.com SNAS304H – JANUARY 2006 – REVISED APRIL 2016 Feature Description (continued) 8.3.4 Digital Inputs and Outputs The ADC digital inputs (SCLK and CS) are not limited by the same maximum ratings as the analog inputs. The digital input pins are instead limited to 5.25 V with respect to GND, regardless of VA, the supply voltage. This allows the ADC to be interfaced with a wide range of logic levels, independent of the supply voltage. 8.4 Device Functional Modes The ADC has two possible modes of operation: normal mode, and shutdown mode. The ADC enters normal mode (and a conversion process is begun) when CS is pulled low. The device enters shutdown mode if CS is pulled high before the tenth falling edge of SCLK after CS is pulled low, or stays in normal mode if CS remains low. Once in shutdown mode, the device stays there until CS is brought low again. By varying the ratio of time spent in the normal and shutdown modes, a system may trade off throughput for power consumption, with a sample rate as low as zero. 8.4.1 Normal Mode The fastest possible throughput is obtained by leaving the ADC in normal mode at all times, so there are no power-up delays. To keep the device in normal mode continuously, CS must be kept low until after the 10th falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low). If CS is brought high after the 10th falling edge, but before the 16th falling edge, the device will remain in normal mode, but the current conversion will be aborted, and SDATA will return to TRI-STATE (truncating the output word). Sixteen SCLK cycles are required to read all of a conversion word from the device. After sixteen SCLK cycles have elapsed, CS may be idled either high or low until the next conversion. If CS is idled low, it must be brought high again before the start of the next conversion, which begins when CS is again brought low. After sixteen SCLK cycles, SDATA returns to TRI-STATE. Another conversion may be started, after tQUIET has elapsed, by bringing CS low again. 8.4.2 Shutdown Mode Shutdown mode is appropriate for applications that either do not sample continuously, or it is acceptable to trade throughput for power consumption. When the ADC is in shutdown mode, all of the analog circuitry is turned off. To enter shutdown mode, a conversion must be interrupted by bringing CS high anytime between the second and tenth falling edges of SCLK, as shown in Figure 20. Once CS has been brought high in this manner, the device will enter shutdown mode; the current conversion will be aborted and SDATA will enter TRI-STATE. If CS is brought high before the second falling edge of SCLK, the device will not change mode; this is to avoid accidentally changing mode as a result of noise on the CS line. Figure 20. Entering Shutdown Mode Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 Submit Documentation Feedback 15 ADC121S101, ADC121S101-Q1 SNAS304H – JANUARY 2006 – REVISED APRIL 2016 www.ti.com Device Functional Modes (continued) Figure 21. Entering Normal Mode To exit shutdown mode, bring CS back low. Upon bringing CS low, the ADC begins powering up (see Timing Requirements for power-up time specifications). This power-up delay results in the first conversion result being unusable. The second conversion performed after power up, however, is valid, as shown in Figure 21. If CS is brought back high before the 10th falling edge of SCLK, the device returns to shutdown mode. This is done to avoid accidentally entering normal mode as a result of noise on the CS line. To exit shutdown mode and remain in normal mode, CS must be kept low until after the 10th falling edge of SCLK. The ADC is fully powered up after 16 SCLK cycles. 16 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 ADC121S101, ADC121S101-Q1 www.ti.com SNAS304H – JANUARY 2006 – REVISED APRIL 2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information Figure 22 shows a typical application of the ADC. In this example, power is provided by TI's LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The power supply pin is bypassed with a capacitor network placed close to the ADC. Because the reference for the ADC is the supply voltage, any noise on the supply degrades the noise performance of the device. To keep noise off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from other circuitry to keep noise off the ADC supply pin. Because of the ADC's low power requirements, it is also possible to use a precision reference as a power supply to maximize performance. The three-wire interface is shown in Figure 22 connected to a microprocessor or DSP. 9.2 Typical Application LP2950 1 PF 0.1 PF 5V 1 PF 0.1 PF VA SCLK VIN ADC121S101 CS SDATA MICROPROCESSOR DSP GND Copyright © 2016, Texas Instruments Incorporated Figure 22. Typical Application Circuit 9.2.1 Design Requirements A positive supply-only, data acquisition system is capable of digitizing a single-ended input signal ranging from 0 V to 5 V with a throughput up to 1 Msps. The ADC121S101 must interface to an MCU whose supply is set at 5 V. 9.2.2 Detailed Design Procedure The signal range requirement forces the design to use 5-V analog supply at VA, analog supply. This follows from the fact that VA is also a reference potential for the ADC. The maximum sampling rate of the ADC121S101 Fs = FSCLK / 20. Noise consideration must be given to the SPI interface, especially when the master MCU is capable of producing fast rising edges on the digital bus signals. Inserting small resistances in the digital signal path may help in reducing the ground bounce, and thus improve the overall noise performance of the system. Take care when the signal source is capable of producing voltages beyond VA. In such instances, the internal ESD diodes may start conducting. The ESD diodes are not intended as input signal clamps. To provide the desired clamping action use Schottky diodes. A 0.1-µF capacitor must be placed close to the supply pin of the ADC121S101. Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 Submit Documentation Feedback 17 ADC121S101, ADC121S101-Q1 SNAS304H – JANUARY 2006 – REVISED APRIL 2016 www.ti.com Typical Application (continued) A small capacitor (1 nF to 10 nF) placed on the input pin can help the internal sampling capacitor settle. If the ADC121S101 is driven by an operational amplifier, a small resistor (50 Ω to 200 Ω) must be placed between the output of the operational amplifier and the junction of the capacitor and the ADC121S101 input pin. 9.2.3 Application Curve 111...111 111...000 | | ADC CODE 111...110 1 LSB = VA/4096 011...111 000...010 | 000...001 000...000 0V 0.5 LSB ANALOG INPUT +VA-1.5 LSB Figure 23. ADC Transfer Characteristic 18 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 ADC121S101, ADC121S101-Q1 www.ti.com SNAS304H – JANUARY 2006 – REVISED APRIL 2016 10 Power Supply Recommendations The power supply pin is bypassed with a capacitor network located close to the ADC. Because the reference for the ADC is the supply voltage, any noise on the supply degrades device noise performance. To keep noise off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from other circuitry to keep noise off the ADC supply pin. Because of the ADC's low power requirements, it is also possible to use a precision reference as a power supply to maximize performance. 10.1 Power Management The ADC takes time to power up, either after first applying VA, or after returning to normal mode from shutdown mode. This corresponds to one dummy conversion for any SCLK frequency within the specifications in this document. After this first dummy conversion, the ADC performs conversions properly. Note that the tQUIET time must still be included between the first dummy conversion and the second valid conversion. When the VA supply is first applied, the ADC may power up in either of the two modes: normal or shutdown. As such, one dummy conversion must be performed after start-up, as described in the previous paragraph. The part may then be placed into either normal mode or the shutdown mode, as described in Normal Mode and Shutdown Mode. When the ADC is operated continuously in normal mode, the maximum throughput is fSCLK / 20 at the maximum specified fSCLK. Throughput may be traded for power consumption by running fSCLK at its maximum specified rate and performing fewer conversions per unit time, raising the ADC CS line after the 10th and before the 15th fall of SCLK of each conversion. Figure 15 shows a plot of typical power consumption versus throughput. To calculate the power consumption for a given throughput, multiply the fraction of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption. Note that the curve of power consumption vs throughput is essentially linear. This is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes. 10.2 Power Supply Noise Considerations The charging of any output load capacitance requires current from the power supply, VA. The current pulses required from the supply to charge the output capacitance causes voltage variations on the supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic low dumps current into the die substrate, which is resistive. Load discharge currents causes ground bounce noise in the substrate that degrades noise performance if that current is large enough. The larger the output capacitance, the more current flows through the die substrate and the greater is the noise coupled into the analog channel, degrading noise performance. To keep noise out of the power supply, keep the output load capacitance as small as practical. It is good practice to use a 100-Ω series resistor at the ADC output, placed as close to the ADC output pin as practical. This limits the charge and discharge current of the output capacitance and improves noise performance. Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 Submit Documentation Feedback 19 ADC121S101, ADC121S101-Q1 SNAS304H – JANUARY 2006 – REVISED APRIL 2016 www.ti.com 11 Layout 11.1 Layout Guidelines Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry. Generally, analog and digital lines must cross each other at 90° to avoid crosstalk. However, to maximize accuracy in high resolution systems, avoid crossing analog and digital lines altogether. The analog input must be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (for example, a filter capacitor) connected between the converter's input pins and ground must be connected to a clean point of the ground. A 0.1-µF capacitor must be placed close to the supply pin of the ADC121S101. 11.2 Layout Example Figure 24. ADC121S101 Sample Layout 20 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 ADC121S101, ADC121S101-Q1 www.ti.com SNAS304H – JANUARY 2006 – REVISED APRIL 2016 12 Device and Documentation Support 12.1 Device Support 12.1.1 Device Nomenclature ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage. Acquisition time is measured backwards from the falling edge of CS when the signal is sampled and the part moves from Track to Hold. The start of the time interval that contains tACQ is the 13th rising edge of SCLK of the previous conversion when the part moves from hold to track. The user must ensure that the time between the 13th rising edge of SCLK and the falling edge of the next CS is not less than tACQ to meet performance specifications. APERTURE DELAY is the time after the falling edge of CS to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. This is from the falling edge of CS when the input signal is sampled to the 16th falling edge of SCLK when the SDATA output goes into TRI-STATE. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF − 1.5 LSB), after adjusting for offset error. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the second and third order intermodulation products to the sum of the power in both of the original frequencies. IMD is usually expressed in dB. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC121S101 is guaranteed not to have any missing codes. OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB). SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic. Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 Submit Documentation Feedback 21 ADC121S101, ADC121S101-Q1 SNAS304H – JANUARY 2006 – REVISED APRIL 2016 www.ti.com Device Support (continued) TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated as 2 THD = 20 ‡ log10 2 Af2 + " + Af6 2 Af1 (2) where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5 harmonic frequencies. THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the acquisition time plus the conversion time. 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: ADC121S101 ADC121S101-Q1 PACKAGE OPTION ADDENDUM www.ti.com 2-Feb-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADC121S101CIMF/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X01C ADC121S101CIMFX/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X01C ADC121S101CISD/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X1C ADC121S101CISDX/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X1C ADC121S101QIMF/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X07Q ADC121S101QIMFX/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X07Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 2-Feb-2016 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF ADC121S101, ADC121S101-Q1 : • Catalog: ADC121S101 • Automotive: ADC121S101-Q1 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Feb-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADC121S101CIMF/NOPB SOT-23 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 ADC121S101CISD/NOPB WSON ADC121S101CIMFX/NOP B NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 ADC121S101QIMF/NOPB SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 ADC121S101CISDX/NOP B ADC121S101QIMFX/NOP B SOT-23 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Feb-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC121S101CIMF/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 SOT-23 DBV 6 3000 210.0 185.0 35.0 ADC121S101CIMFX/NOP B WSON NGF 6 1000 210.0 185.0 35.0 ADC121S101CISDX/NOP B ADC121S101CISD/NOPB WSON NGF 6 4500 367.0 367.0 35.0 ADC121S101QIMF/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 SOT-23 DBV 6 3000 210.0 185.0 35.0 ADC121S101QIMFX/NOP B Pack Materials-Page 2 MECHANICAL DATA NGF0006A www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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