IRF IRS21856SPBF High(dual mode) and low side driver Datasheet

January 16, 2009
Datasheet No. - PD97376
IRS21856S
High(Dual Mode) and Low Side Driver
Product Summary
Features
•
•
•
•
•
•
•
•
High side Programmable ramp gate drive
High side generic gate driver integrated using the
same high side output pin
Low side generic gate driver
Under voltage lockout for VCC & VBS
5V input logic compatible
Tolerant to negative transient voltage on VS
Shoot through prevention
RoHS compliant
Topology
PDP
VOFFSET
≤ 600 V
HO1 SR+
4.5V/us
Io+ & I o- (typical)
tON & tOFF (typical)
0.5A & 0.5A
160ns & 160ns
Package Options
14-Lead SOIC (narrow body)
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IRS21856S
Table of Contents
Page
Description
3
Simplified Block Diagram
4
Typical Application Diagram
5
Qualification Information
7
Absolute Maximum Ratings
8
Recommended Operating Conditions
8
Static Electrical Characteristics
9
DV / Linear (Stepwise) Mode
10
Dynamic Electrical Characteristics
10
Timing Diagram and logic truth table
11
Input/Output Pin Equivalent Circuit Diagram
16
Lead Definitions
17
Lead Assignments
17
Package Details
18
Tape and Reel Details
19
Part Marking Information
20
Ordering information
21
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2
IRS21856S
Description
The IRS21856 is high voltage and programmable ramp slope control gate driver for MOSFET and IGBT with
single high side dual mode driver and low side driver. Proprietary HVIC and latch immune CMOS
technologies enable ruggedized monolithic construction. The logic input is compatible with 5V standard
CMOS or LSTTL output. The output driver features a programmable slope control by external R/C and input
signal. The floating channels can be used to drive an N-channel power MOSFET or IGBT in the high side
configuration, which operates up to 600 volts above the COM ground.
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IRS21856S
Simplified Block Diagram
VB
Conditioning
& OPAMP
Driving
UVLO
HO1
R
R
VSE
S
Pulse
Filter
VREF
Reference
Generating
10V
Regulator
VS
VCC
DV
5V
Regulator
RES
UVLO
COM
LO3
HIN1
HIN2
LIN3
Logic
&
Pulse
Generator
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IRS21856S
Typical Connection Diagrams
A) Linear Ramp driver’s connection diagram
B) Stepwise Linear Ramp driver’s connection diagram
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IRS21856S
C) Exponential Ramp driver’s connection diagram
VSUS
RRES
25V Max
VCC
VB
COM
HO1
HIN1
VSE
HIN2
IRS21856
SON14
RES
LIN3
VS
NC
DV
Optional CC
Panel
RREF
CREF
LO3
VREF
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IRS21856S
Qualification Information†
Qualification Level
Moisture Sensitivity Level
Machine Model
ESD
Human Body Model
IC Latch-Up Test
RoHS Compliant
Industrial††
Comments: This family of ICs has passed JEDEC’s
Industrial qualification. IR’s Consumer qualification
level is granted by extension of the higher Industrial
level.
MSL2††† 260°C
SOIC14N
(per IPC/JEDEC J-STD-020)
Class A
(per JEDEC standard JESD22-A115)
Class 2
(per EIA/JEDEC standard EIA/JESD22-A114)
Class I , Level A
(per JESD78)
Yes
†
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
†† Higher qualification ratings may be available should the user have such requirements. Please contact
your International Rectifier sales representative for further information.
††† Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
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IRS21856S
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All
voltage parameters are absolute voltages referenced to COM.
Symbol
Definition
VCC
Low side supply voltage
VIN
Logic input voltage (HIN1, HIN2, LIN3)
VLO
Low side gate drive output voltage
V DV,
High side inputs voltage
VVREF
VVSE,
High side inputs voltage
VRES
VB
High side floating well supply voltage
VS
High side floating well supply return voltage
VHO1
Floating gate drive output voltage
dVS/dt Allowable VS offset supply transient relative to COM
PD
Package Power Dissipation @ TA<=+25ºC
RθJA
Thermal Resistance, Junction to Ambient
TJ
Junction Temperature
TS
Storage Temperature
TL
Lead temperature (Soldering, 10 seconds)
Min
-0.3
COM-0.3
COM-0.3
Max
25
VCC +0.3
VCC +0.3
Units
V
V
V
VS-0.3
VB+0.3
V
VS-0.3
VB+0.3
V
-0.3
VB-25
VS-0.3
-55
-55
-
625
VB+0.3
VB+0.3
50
1.0
120
150
150
300
V
V
V
V/ns
W
ºC/W
ºC
ºC
ºC
Recommended Operating Conditions
For proper operation, the device should be used within the recommended conditions. All voltage parameters
are absolute voltages referenced to COM. The offset rating are tested with supplies of (VCC-COM) = (VBVS)=15V.
Symbol
VCC
VIN
VLO3
VB
VRES
VDV
V VREF, VSE
VS
VHO1
TA
†
††
Definition
Low side supply voltage
HIN1, HIN2, LIN3 input voltage
Low side gate drive output voltage
High side floating well supply voltage
RES input voltage
DV input voltage
VREF and VSE input voltage
High side floating well supply offset voltage
Floating gate drive output voltage
Ambient Temperature
Min
10
COM
COM
VS+10
VS
VS
VS
Note2††
VS
-40
Max
20
VCC
VCC
VS+20
VB
VB
VB -3
600
VB
125
Units
V
V
V
V
V
V
V
V
V
ºC
VS and VB voltages will be tolerant to short negative transient spikes. These will be defined and
specified in the future.
Logic operation for Vs of -5 to 600V. Logic state held for Vs of -5V to –VBS. (Please refer to Design Tip
DT97-3 for more details).
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IRS21856S
Static Electrical Characteristics
(VCC-COM) = (VB-VS)=15V. TA = 25ºC. The VIN, VIN TH and IIN parameters are referenced to COM. The VO
and IO parameters are referenced to respective VS, COM and are applicable to the respective output leads
HO1, LO3. The VCCUV parameters are referenced to COM. The VBSUV parameters are referenced to VS.
Symbol
VCCUV+
VCCUVVBSUV+
VBSUVILK
IQBS
Definition
VCC supply undervoltage positive going
threshold
VCC supply undervoltage negative
going threshold
VBS supply undervoltage positive going
threshold
VBS supply undervoltage negative
going threshold
High side floating well offset supply
leakage current
Min
Typ
Max
Units
8.1
9.0
9.9
7.5
8.3
9.1
8.1
9.0
9.9
7.5
8.3
9.1
---
---
50
µA
VB = VS = 600V
---
4.7
8.5
mA
IN1, 2 = 5V,
RES=130kohm
---
800
1400
V
Quiescent VBS supply current
µA
IQCC
Quiescent VCC supply current
VIH
Logic “1” input voltage
VIL
Logic “0” input voltage
IIN+
Logic “1” input bias current
IIN -
Logic “0” input bias current
Io+_
Output high short circuit pulsed current
---
VOL _
HO1, LO3
VOH _
HO1, LO3
DV exp+
120
250
---
---
---
---
0.8
---
5
---
3.5
HO1,LO3
Io-_ HO1,LO3
Test Conditions
---
0
---
0.5
---
IN1,2,3 = 0V or 5V
V
VIN =5V
µA
--A
Output low short circuit pulsed current
IN1, 2 = 0V,
RES=130kohm
VO=15V,VIN=5V,
PW<=10us
VO=0V,VIN=0V,
PW<=10us
---
0.5
Low level output voltage
---
35
150
mV
Io=2mA
High level output voltage, Vbias-Vo
---
15
80
mV
Io=2mA
Positive DV input threshold for
exponential ramp
---
9.5
---
V
CREF =1nF, VSE open
RRES =130K
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---
VIN =0V
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IRS21856S
DV / Linear (Stepwise) Mode
Symbol
VREF,
hold
Definition
Min
Typ
Max
0.4
0.5
0.6
DV reference voltage
Units
V
2.82
3
Test Conditions
DV=500mV, CREF =1nF,
VSE open RRES =130K,
DV=3V, CREF =1nF, VSE
open RRES =130K,
3.18
Dynamic Electrical Characteristics
(VCC-COM)= (VB-VS)=15V. TA = 25ºC. CL = 1000pF unless otherwise specified. All parameters are
reference to COM.
Symbol
Definition
Min
Typ
Max Units
Test Conditions
Internal Operational Amplifier Characteristics
110
170
230
µs
CREF =1nF, VSE open, RRES
=130K,
VDV =VS=COM
OTA transconductance
---
12
---
mS
CL_LO=1nF, VDV =VB,
RRES =130K, dc bias 5V
Gopen loop
Open loop gain
45
60
---
dB
Cc =1nF, VDV =VB,
RRES =130K
BWSS
Small signal bandwidth
---
3.5
---
MHz
Cc =1nF VDV =VB,
RRES =130K
VOS
Input offset voltage
---
10
---
mV
VDV =VB, RRES =130K
HO1 SR+
Output positive slew rate
---
4.5
---
V/µs
CL_HO1=1nF, VDV =VB,
RRES =130K
CMRR
Common mode rejection ratio
55
65
---
dB
VDV =VB, RRES =130K
PSRR
Power supply rejection ratio
55
65
---
dB
VDV =VB, RRES =130K
ns
Gate Drive Mode
CL =1nF
t ref_ln_ramp
Linear ramp reference 10% to
90%
Gm
Propagation Delay Characteristics
t on
Turn-on delay (HO1, LO3)
---
150
250
t off
Turn-off delay (HO1, LO3)
---
160
260
tr
Turn-on rise from 10% to 90%
---
30
70
tf
Turn-off fall from 90% to 10%
---
20
70
MT
Delay matching, HO1 & LO3 turnon/off
50
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IRS21856S
Figure 1A1 Input/Output Timing Diagram: Linear Ramp
Figure 1A2 Input/Output Timing Diagram: Linear Ramp with voltage difference
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IRS21856S
Figure 1B
Figure 1C
Input/Output Timing Diagram: Stepwise linear Ramp
Input/Output Timing Diagram: Exponential Ramp
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IRS21856S
VREF
VSE
HIN1
HIN2
LIN3
HO1
DV=VS
LO3
Figure 1D
Input/Output Timing Diagram : HO1/LO3 outputs
Logic Truth Table
HIN1
HIN2
LIN3
LO3
OTA of HO1
Gate driver of HO1
0
0
0
0
High impedance (HIZ)
0
0
0
1
1
High impedance (HIZ)
0
0
1
0
0
High impedance (HIZ)
1
0
1
1
0
High impedance (HIZ)
0
1
1
0
0
Linear/Exp ramp
depend on DV pin
High impedance (HIZ)
1
1
1
0
High impedance (HIZ)
0
1
Step(0/1)
0
0
Stepwise linear
if DV pin is Vs
High impedance (HIZ)
1
Step(0/1)
1
0
High impedance (HIZ)
0
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IRS21856S
Figure 2
Timing Definitions of VREF
Figure 3 Switching Time Waveform Definitions of HO1 and LO3
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IRS21856S
Figure 4 Delay Matching Waveform Definitions
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IRS21856S
Input/Output Pin Equivalent Circuit Diagrams
VB
VB
ESD
Diode
ESD
Diode
VSE,
RES,
VREF,
DV
25V
HO1
ESD
Diode
VS
25V
RESD
ESD
Diode
VS
600V
600V
VCC
VCC
ESD
Diode
ESD
Diode
HIN1,
HIN2,
LIN3
LO3
25V
RESD
ESD
Diode
ESD
Diode
COM
COM
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IRS21856S
Lead Definitions
PIN#
Symbol
Description
1
VCC
Low side supply voltage
2
COM
Low side supply return
3
HIN1
Logic input for HO1 ramp reference control
4
HIN2
Logic input for high side gate driver outputs, in phase
5
LIN3
Logic input for low side gate driver output
6
NC
No Connection
7
LO3
Low side gate driver output
8
VREF
9
DV
10
VS
11
RES
Adjustable current source resistor input
12
VSE
Voltage sense input
13
HO1
High side gate driver output
14
VB
External programmable R/C input for ramp generation
Ramp selection and programmable difference voltage (DV) input
High side gate drive floating supply return
High side gate drive floating supply
Lead Assignments
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IRS21856S
Package Details: SOIC14
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IRS21856S
Tape and Reel Details: SOIC14
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IRS21856S
Part Marking Information
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IRS21856S
Ordering Information
Standard Pack
Base Part Number
IRS21856S
Package Type
SOIC14
Complete Part Number
Form
Quantity
Tube/Bulk
55
IRS21856SPBF
Tape and Reel
2500
IRS21856STRPBF
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no
responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any
infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by
implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are
subject to change without notice. This document supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
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