Allegro A6279ELWTR-T Serial-input constant-current latched led drivers with open led detection Datasheet

A6278 and A6279
Serial-Input Constant-Current Latched
LED Drivers with Open LED Detection
Features and Benefits
Description
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The A6278 and A6279 devices are specifically designed for
LED display applications. Each of these BiCMOS devices
includes a CMOS shift register, accompanying data latches,
and NPN constant-current sink drivers. The A6278 contains
8 sink drivers, while there are 16 in the A6279.
3.0 to 5.5 V logic supply range
Schmitt trigger inputs for improved noise immunity
Power-On Reset (POR)
Up to 90 mA constant-current sinking outputs
LED open circuit detection
Low-power CMOS logic and latches
High data input rate
20 ns typical staggering delay on the outputs
Internal UVLO and thermal shutdown (TSD) circuitry
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, typical serial data-input rates can reach up to 25 MHz.
The LED drive current is determined by the user’s selection of
a single resistor. A CMOS serial data output permits cascading
between multiple devices in applications requiring additional
drive lines. Open LED connections can be detected and signaled
back to the host microprocessor through the SERIAL DATA
OUT pin.
Packages:
16 and 24 pin DIP (suffix A)
16 and 24 pin TSSOP (suffix LP)
16 and 24 pin SOIC (suffix LW)
Three package styles are provided: a DIP (type A) for throughhole applications; and for leaded surface-mount, an SOIC (type
LW) and a TSSOP with exposed thermal pad (type LP). All
package styles for the A6278 are electrically identical to each
other, as are the A6279 package styles. All packages are lead
(Pb) free, with 100% matte tin plated leadframes.
Not to scale
Functional Block Diagram
LOGIC
SUPPLY
UVLO
SERIAL
DATA IN
VDD
CLOCK
VDD
OUTPUT
ENABLE
LATCH
ENABLE
SERIAL
DATA OUT
Serial - Parallel Shift Register
Latches
Control Logic
Block
Output Control Drivers and Open Circuit Detector
REXT
IO
Regulator
Exposed Pad
(LP package)
GND
OUT0 OUT1
OUT7 (A6278)
OUT15 (A6279)
VLED
6278-DS, Rev. 2
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Selection Guide
Part Number
Packing
Package Type
A6278EA-T
25 pieces per tube
A6278ELP-T
96 pieces per tube
A6278ELPTR-T
4000 pieces per 13-in. reel
A6278ELW-T
47 pieces per tube
A6278ELWTR-T
1000 pieces per 13-in. reel
Terminals
LED Drive Lines
16
8
24
16
DIP
A6279EA-T
15 pieces per tube
A6279ELP-T
65 pieces per tube
A6279ELPTR-T
4000 pieces per 13-in. reel
A6279ELW-T
31 pieces per tube
A6279ELWTR-T
1000 pieces per 13-in. reel
TSSOP with exposed thermal pad
SOICW
DIP
TSSOP with exposed thermal pad
SOICW
Absolute Maximum Ratings
Min.
Typ.
LOGIC SUPPLY Voltage Range
Parameter
VDD
–
–
7.0
V
Load Supply Voltage Range
VLED
–0.5
–
17
V
OUTx Current (any single output)
Ground Current
Symbol
Conditions
–
–
90
mA
A6278
–
–
750
mA
A6279
–
–
1475
mA
VDD
+ 0.4
V
IO
IGND
Max. Units
Logic Input Voltage Range
VI
–0.4
Operating Temperature Range (E)
TA
–40
–
85
°C
Junction Temperature
TJ
–
–
150
°C
Storage Temperature Range
TS
–55
–
150
°C
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Pin-out Diagrams
Package A, LW, LP
16-pin
Package A, LW, LP
24-pin
GND
1
24
LOGIC SUPPLY
SERIAL DATA IN
2
23
REXT
CLOCK
3
22
SERIAL DATA OUT
LATCH ENABLE
4
21
OUTPUT ENABLE
12 OUT7
OUT0
5
20
OUT15
6
11 OUT6
OUT1
6
19
OUT14
OUT2
7
10 OUT5
OUT2
7
18
OUT13
OUT3
8
9
OUT3
8
17
OUT12
OUT4
9
16
OUT11
OUT5
10
15
OUT10
OUT6
11
14
OUT9
OUT7
12
13
OUT8
GND
1
16 LOGIC SUPPLY
SERIAL DATA IN
2
15 REXT
CLOCK
3
14 SERIAL DATA OUT
LATCH ENABLE
4
13 OUTPUT ENABLE
OUT0
5
OUT1
EP
OUT4
EP
Terminal List Table
Number
A, LW, LP
A6278 A6279
Name
1
1
GND
2
2
SERIAL DATA IN
3
3
CLOCK
Function
Reference terminal for logic ground and power ground
Serial-data input to the shift-register
Clock input terminal; data is shifted on the rising edge of the clock.
4
4
LATCH ENABLE
5 TO 12
5 TO 20
OUTx
Data strobe input terminal; serial data is latched with a high-level input
13
21
OUTPUT ENABLE
(Active low) Set low to enable output drivers; set high to turn OFF
(blank) all output drivers
14
22
SERIAL DATA OUT
CMOS serial-data output; for cascading to the next device (to that
device SERIAL DATA IN pin); for reading OCD bits.
15
23
REXT
16
24
LOGIC SUPPLY
–
–
NC
No connection
–
–
EP
LP and ET packages only; exposed thermal pad for heat dissipation
Current-sinking output terminals
An external resistor at this terminal establishes the output current for all
of the sink drivers.
(VDD) Logic supply voltage (typically 3.3 or 5.0 V)
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
OPERATING CHARACTERISTICS
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max
Unit
ELECTRICAL CHARACTERISTICS valid at TA = 25°C, VDD = 3.0 to 5.5 V, unless otherwise noted
Operating
3.0
5.0
5.5
V
LOGIC SUPPLY Voltage Range
VDD
VDD = 0.0 → 5.0 V
2.4
–
2.85
V
Undervoltage Lockout
VDD(UV)
VDD = 5.0 → 0.0 V
2.15
–
2.55
V
VCE = 0.7 V, REXT = 225 Ω
64.2
75.5
86.8
mA
Output Current (any single output)
IO
34.1
40.0
45.9
mA
VCE = 0.7 V, REXT = 470 Ω
VCE = 0.6 V, REXT = 3900 Ω
4.25
5.0
5.75
mA
VCE(A) = VCE(B) = 0.7 V, REXT = 225 Ω
–
+1.0
+6.0
%
Output Current Matching (difference between any two
ΔIO
–
+1.0
+6.0
%
VCE(A) = VCE(B) = 0.7 V, REXT = 470 Ω
outputs at the same VCE )
VCE(A) = VCE(B) = 0.6 V, REXT = 3900 Ω
–
+1.0
+6.0
%
Output Leakage Current
ICEX
VOH = 15 V
–
1.0
5.0
μA
VIH
0.7VDD
–
VDD
V
Logic Input Voltage
VIL
GND
–
0.3VDD
V
All digital inputs
200
–
400
mV
Logic Input Voltage Hysteresis
VIhys
VOL
IOL = 500 μA
–
–
0.4
V
SERIAL DATA OUT Voltage
IOH = –500 μA
VDD– 0.4
–
–
V
VOH
OUTPUT ENABLE input, Pull Up
150
300
600
kΩ
Input Resistance
RI
LATCH ENABLE input, Pull Down
100
200
400
kΩ
REXT = open, VOE = 5 V
–
–
1.4
mA
IDD(OFF) REXT = 470 Ω, VOE = 5 V
–
–
5.0
mA
REXT = 225 Ω, VOE = 5 V
–
–
8.0
mA
LOGIC SUPPLY Current
REXT = 3900 Ω, VOE = 0 V
–
–
3.0
mA
REXT = 470 Ω, VOE = 0 V
IDD(ON)
–
–
18.0
mA
REXT = 225 Ω, VOE = 0 V
–
–
32.0
mA
Thermal Shutdown Temperature
TJTSD
Temperature increasing
–
165
–
°C
Thermal Shutdown Hysteresis
TJTSDhys
–
15
–
°C
Open LED Detection Threshold
VCE(ODC) IO > 5 mA, VCE ≥ 0.6 V
–
0.30
–
V
SWITCHING CHARACTERISTICS valid at TA = 25°C, VDD = VIH = 3.0 to 5.5 V, VCE = 0.7 V, VIL = 0 V, REXT = 470 Ω, IO = 40 mA, VLED = 3 V, RLED =
58 Ω, CLED = 10 pF, unless otherwise noted
CLOCK Pulse Width
thigh, tlow
20
–
–
ns
10
–
–
ns
SERIAL DATA IN Setup Time
tSU(D)
SERIAL DATA IN Hold Time
tH(D)
10
–
–
ns
20
–
–
ns
LATCH ENABLE Setup Time
tSU(LE)
LATCH ENABLE Hold Time
tH(LE)
20
–
–
ns
OUTPUT ENABLE Set Up Time
tSU(OE)
40
–
–
ns
Normal Mode
OUTPUT ENABLE Hold Time
tH(OE)
20
–
–
ns
600
–
–
ns
OUTPUT ENABLE Pulse Width
tW(OE)
CLOCK to SERIAL DATA OUT Propagation Delay Time
tP(DO)
30
–
–
ns
OUTPUT ENABLE to OUT0 Propagation Delay Time
tP(OE)
–
75
–
ns
Staggering Delay (between consecutive outputs)
tD
10
20
40
ns
Total Delay Time (15 × tD)
tDtotal
–
300
–
ns
CLOCK Pulse Width
thigh, tlow
20
–
–
ns
20
–
–
ns
SERIAL DATA IN Setup Time
tSU(D)
SERIAL DATA IN Hold Time
tH(D)
20
–
–
ns
40
–
–
ns
LATCH ENABLE Setup Time
tSU(LE)
LATCH ENABLE Hold Time
tH(LE)
20
–
–
ns
OUTPUT ENABLE Set Up Time
tSU(OE)
40
–
–
ns
Test Mode, VDD = 4.5 to 5.5 V
OUTPUT ENABLE Hold Time
tH(OE)
20
–
–
ns
OUTPUT ENABLE Pulse Width*
tW(OE)
2.0
–
–
us
30
–
–
ns
CLOCK to SERIAL DATA OUT Propagation Delay Time
tP(DO)
OUTPUT ENABLE to OUT0 Propagation Delay Time
tP(OE)
–
75
–
ns
Staggering Delay (between consecutive outputs)
tD
10
20
40
ns
Total Delay Time (15 × tD)
tDtotal
–
300
–
ns
Output Fall Time
tf
90% to 10% voltage
–
75
150
ns
Output Rise Time
tr
10% to 90% voltage
–
75
150
ns
*See LED Open Circuit Detection (Test) mode timing diagram.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Truth Table
Serial
Data
Input
Clock
Input
Shift Register Contents
I0
I1
I2
…
In-1 In
Serial
Data
Out
H
H R0 R1 …
Rn-2 Rn-1
Rn-1
L
L R0 R1 …
Rn-2 Rn-1
Rn-1
X
R0 R1 R2 …
Rn-1 Rn
Rn
X
X
X X
…
P0 P1 P2 …
X
Pn-1 Pn
Latch
Enable
Input
Latch Contents
I0
I1
I2
…
Output
Enable
Input
In-1 In
Output Contents
I0
I1
I2
…
In-1 In
X
L
R0 R1 R2 …
Rn-1 Rn
Pn
H
P0 P1 P2 …
Pn-1 Pn
L
P0 P1 P2 …
Pn-1 Pn
X
X
H
H
H
X X
…
X
H H
…
H
L = Low logic (voltage) level
H = High logic (voltage) level
X = Don’t care
P = Present state
R = Previous state
n = 7 for the A6278, n = 15 for the A6279
Inputs and Outputs Equivalent Circuits
VDD
IN
VDD
IN
OUTPUT ENABLE
(active low)
VDD
IN
LE
CLOCK and
SERIAL DATA IN
VDD
OUT
LATCH ENABLE
SERIAL DATA OUT
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Normal Mode Timing Requirements
0
CLOCK
1
n
thigh tlow
SERIAL
DATA IN
SERIAL
DATA OUT
SDI n
SDI n-1
SDI 0
tSU(D) tH(D)
SDO n
Don't Care
tp(DO)
LATCH
ENABLE
A6278, n = 7
A6279, n = 15
tSU(LE) tH(LE)
OUTPUT
ENABLE
tW(OE)
tW(OE)
tSU(OE)
OUT0
Don't Care
tP(OE)
OUT1
tP(OE)
Don't Care
Logic Levels: VDD and GND
tD
tD
Don't Care
OUTn
tD(Total)
tD(Total)
LED Open Circuit Detection (Test) Mode Timing Requirements
(A) To enter LED OCD mode, a minimum of one CLOCK pulse is required after LATCH ENABLE is brought back low.
CLOCK
1
thigh tlow
OUTPUT
ENABLE
tSU(OE1)
tH(OE1)
LATCH
ENABLE
tSU(LE1)
tH(LE1)
(B) To output the latched error code, OUTPUT ENABLE must be held low a minimum of 3 CLOCK cycles.
CLOCK
3
2
1
tW(OE1)
OUTPUT
ENABLE
A6278, n = 7
A6279, n = 15
SERIAL
DATA OUT
SDO n
Don't Care
SDO n-1
SDO n-2
SDO 0
(C) When returning to Normal mode, a minimum of three CLOCK pulses is required after OUTPUT ENABLE is brought back high.
CLOCK
OUTPUT
ENABLE
Logic Levels: VDD and GND
thigh tlow
tSU(OE1)
1
2
3
tH(OE1)
LATCH
ENABLE
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Functional Description
Normal Mode
Serial data present at the SERIAL DATA IN input is transferred
to the shift register on the logic 0-to-logic 1 transition of the
CLOCK input pulse. On succeeding CLOCK pulses, the register
shifts data towards the SERIAL DATA OUT pin. The serial data
must appear at the input prior to the rising edge of the CLOCK
input waveform.
Data present in any register is transferred to the respective latch
when the LATCH ENABLE input is high (serial-to-parallel conversion). The latches continue to accept new data as long as the
LATCH ENABLE input is held high.
Applications where the latches are bypassed (LATCH ENABLE
tied high) will require that the OUTPUT ENABLE input be high
during serial data entry. When the OUTPUT ENABLE input is
high, the output sink drivers are disabled (OFF).
The data stored in the latches is not affected by the OUTPUT
ENABLE input. With the OUTPUT ENABLE input active (low),
the outputs are controlled by the state of their respective latches.
Open circuit detection does not take place until the sequence in
Panel B on page 7 is performed. During this sequence, the OE
pin must be held low for a minimum of 2 μs (t W(OE1)) to ensure
proper settling of the output currents and be given a minimum of
three CLOCK pulses. During the period that the OE pin is low
(active), OCD testing begins. The VCE voltage on each of the
output pins is compared to the Open LED Detection Theshold,
VCE(OCD). If the VCE of an enabled output is lower than VCE(OCD),
an error bit value of 0 is set in the corresponding shift register. A
value of 1 will be set if no error is detected. If a particular output
is not enabled, a 0 will be set. The error codes are summarized in
the following table:
Output State Test Condition Error Code Meaning
Output State
Test Condition
Error Code
Meaning
OFF
N/A
0
N/A
VCE < VCE(OCD)
0
Open/TSD
VCE ≥ VCE(OCD)
1
Normal
ON
LED Open Circuit Detection (Test) Mode
The LED Open Circuit Detection (OCD) mode, or Test mode,
is entered by clocking in the LED OCD mode initialization
sequence on the OUTPUT ENABLE (OE) and LATCH ENABLE
(LE) pins. In Normal mode, the OE and LE pins do not change
states while the CLOCK signal is cycling. The initialization
sequence is shown in panel A of the LED OCD timing requirements diagram on page 7.
Note: Each step event during mode sequencing happens on the
leading edge of the CLOCK signal. Five step events (CLOCK
pulses) are required to enter OCD mode and five step events are
required to return to Normal mode.
A pattern, such as all highs, should first be loaded into the registers and latched leaving LE low. The device is then sequenced
into LED OCD mode. It should be noted that data is still being
sent through the shift registers while entering the LED OCD
mode. However, this data is not latched when the LE pin goes
high and sees a CLOCK pulse during the initialization sequence.
After the testing process, setting the OE pin high causes the shift
registers to latch the error code data where it can then be clocked
out of the SERIAL DATA OUT pin. The OCD latching sequence
(OE low, 3 CLOCK pulses, OE high as shown in panel B of the
LED OCD timing diagram) can then be repeated if necessary to
look for intermittent contact problems.
The state of the outputs can be programmed with new data at any
time while in LED OCD mode (the same as in Normal mode).
This allows specific patterns to be tested for open circuits. The
pattern that is latched will then be tested during the OCD latching
sequence and the resulting bit values can be clocked out of the
SERIAL DATA OUT pin.
Note: LED Open Circuit Detection will not work properly if the
current is being externally limited by resistors to within the set
current limit for the device.
To return to Normal mode, perform the clocking sequence shown
in panel C of the timing diagram on the OE and LE pins.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Constant Current (REXT)
The A6278 and A6279 allow the user to set the magnitude of
the constant current to the LEDs. Once set, the current remains
constant regardless of the LED voltage variation, the supply
voltage variation, or other circuit parameters that could otherwise
affect LED current. The output current is determined by the value
of an external current-control resistor (REXT). The relationship of
these parameters is shown in figure 1. Typical characteristics for
output current and VCE are shown in figure 2 for common values
of REXT.
Figure 1. Output Current versus Current Control Resistance
TA= 25°C, VCE = 0.7 V
90
80
IO (mA/Bit)
70
60
50
40
30
20
10
0
100
100
200
300
300
500
500
700
1k1K
2k2K
3k
3K
5k
5K
REXT (Ω)
Figure 2. Output Current versus Device Voltage Drop
TA= 25°C
90
80
REXT = 225 Ω
IO (mA/Bit)
70
60
50
REXT = 470 Ω
40
30
20
REXT = 3900 Ω
10
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VCE (V)
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
8
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Undervoltage Lockout
The 20 ns delays are cumulative across all the outputs. Under any
The A6278 and A6279 include an internal under-voltage lockout
of the above conditions, the state of OUT0 gets set after a typical
(UVLO) circuit that disables the outputs in the event that the
propagation delay, tP(OE). OUT1 will get set 20 ns after OUT0,
logic supply voltage drops below a minimum acceptable level.
and so forth. In the A6279, OUT15 will get set after 300 ns (15 ×
This feature prevents the display of erroneous information, a
20 ns) plus tP(OE).
necessary function for some critical applications.
Note: The maximum CLOCK frequency is reduced in applica-
Upon recovery of the logic supply voltage after a UVLO event,
and on power-up, all internal shift registers and latches are set
to 0. The A6278/A6279 is then in Normal mode.
Output Staggering Delay
The A6278/A6279 has a 20 ns delay between each output. The
staggering of the outputs reduces the in-rush of currents onto the
power and ground planes. This aids in power supply decoupling
tions where both the OUTPUT ENABLE pin is held low and the
LATCH ENABLE pin is held high continuously, and the outputs
change state on the CLOCK edges. The staggering delay could
cause spurious output responses at CLOCK speeds greater than
1 MHz.
Thermal Shutdown
When the junction temperature of the A6278/A6279 reaches the
thermal shutdown temperature threshold, TJTSD (165°C typical),
and EMI/EMC reduction.
the outputs are shut off until the junction temperature cools down
The output staggering delay occurs under the following condi-
below the recovery threshold, TJTSD– TJTSDhys (15°C typical).
tions:
The shift register and output latches will remain active during
• OUTPUT ENABLE is pulled low
• OUTPUT ENABLE is held low and LATCH ENABLE is
pulled high
• OUTPUT ENABLE is held low, LATCH ENABLE is held high,
and CLOCK is pulled high
a TSD event. Therefore, there is no need to reset the data in the
output latches.
In LED OCD mode, if the junction temperature reaches the Thermal Shut Down threshold, the outputs will turn off, as in Normal
mode operation. However, all of the shift registers will be set
with 0, the error bit value.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
9
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Application Information
Load Supply Voltage (VLED)
These devices are designed to operate with driver voltage
drops (VCE) of 0.7 to 3V, with an LED forward voltage, VF , of
1.2 to 4.0 V. If higher voltages are dropped across the driver,
package power dissipation will increase significantly. To minimize package power dissipation, it is recommended to use the
lowest possible load supply voltage, VLED, or to set any series
voltage dropping, VDROP , according to the following formula:
VDROP = VLED – VF – VCE ,
with VDROP = IO× RDROP for a single driver or for a Zener diode
(VZ), or for a series string of diodes (approximately 0.7 V per
diode) for a group of drivers (see figure 3). If the available voltage source, VLED, will cause unacceptable power dissipation and
series resistors or diodes are undesirable, a voltage regulator can
be used to provide supply voltages.
For reference, typical LED forward voltages are:
LED Type
VF (V)
White
3.5 to 4.0
Blue
3.0 to 4.0
Green
1.8 to 2.2
Yellow
2.0 to 2.1
Amber
1.9 to 2.65
Red
1.6 to 2.25
Infrared
1.2 to 1.5
Pattern Layout
This device has a common logic ground and power ground
terminal, GND. For the LP package, the GND pin should be tied
to the exposed metal pad, EP, allowing the ground plane copper
to be used to dissipate heat. If the ground pattern layout contains
large common mode resistance, and the voltage between the
system ground and the LATCH ENABLE, OUTPUT ENABLE,
or CLOCK terminals exceeds 2.5 V (because of switching noise),
these devices may not work properly.
Package Power Dissipation (PD)
The maximum allowable package power dissipation based on
package type is determined by:
PD(max) = (150 – TA) / RθJA ,
where RθJA is the thermal resistance of the package, determined
experimentally. Power dissipation levels based on the package
are shown in the Package Thermal Characteristics section (see
page 14).
The actual package power dissipation is determined by:
PD(act) = DC × (VCE × IO× 16) + (VDD× IDD) ,
where DC is the duty cycle. The value 16 represents the maximum number of available device outputs for the A6279, used for
the worst-case scenario (displaying all 16 LEDs; this would be 8
for the A6278).
When the load suppy voltage, VLED, is greater than 3 to 5 V, and
PD(act) > PD(max), an external voltage reducer (VDROP) must be
used (see figure 3).
Reducing the percent duty cycle, DC, will also reduce power dissipation. Typical results are shown on the following pages.
VLED
VLED
VLED
VDROP
VDROP
VDROP
VF
VF
VF
VCE
VCE
VCE
Figure 3. Typical appplications for voltage drops
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Allowable Output Current versus Duty Cycle, A6278
VDD = 5 V
A Package, TA = 25°C
A Package, TA = 50°C
90
90
IO (mA/Bit)
90
A Package, TA = 85°C
0
0
0
100
0
0
DC (%)
100
0
DC (%)
LP Package, TA = 25°C
LP Package, TA = 50°C
LP Package, TA = 85°C
90
90
IO (mA/Bit)
90
100
DC (%)
0
0
100
0
0
0
DC (%)
100
0
100
DC (%)
LW Package, TA = 25°C
DC (%)
LW Package, TA = 50°C
90
LW Package, TA = 85°C
90
IO (mA/Bit)
90
0
0
0
100
DC (%)
0
0
100
DC (%)
0
100
DC (%)
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Allowable Output Current versus Duty Cycle, A6279
VDD = 5 V
A Package, TA = 25°C
A Package, TA = 50°C
90
90
IO (mA/Bit)
90
A Package, TA = 85°C
0
0
0
0
100
0
DC (%)
100
0
DC (%)
LP Package, TA = 25°C
LP Package, TA = 50°C
LP Package, TA = 85°C
90
90
IO (mA/Bit)
90
100
DC (%)
0
0
100
0
0
0
DC (%)
100
0
DC (%)
LW Package, TA = 25°C
LW Package, TA = 50°C
LW Package, TA = 85°C
90
90
IO (mA/Bit)
90
100
DC (%)
0
0
0
100
DC (%)
0
0
100
DC (%)
0
100
DC (%)
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Package Thermal Characteristics
Characteristic
Symbol
Package Thermal Resistance
RθJA
Value
Unit
A package, 16-pin, measured on 4-layer board based on JEDEC standard
Test Conditions*
38
°C/W
A package, 24-pin, measured on 4-layer board based on JEDEC standard
26
°C/W
LP package, 16-pin, measured on 4-layer board based on JEDEC standard
34
°C/W
LP package, 24-pin, measured on 4-layer board based on JEDEC standard
28
°C/W
LW package, 16-pin, measured on 4-layer board based on JEDEC standard
48
°C/W
LW package, 24-pin, measured on 4-layer board based on JEDEC standard
44
°C/W
*Additional thermal information is available on the Allegro Web site.
A6278
A6279
5.0
Allowable Package Power Dissipation (W)
Allowable Package Power Dissipation (W)
5.0
4.0
LP
,R
θJ
3.0
A,
LW
2.0
R
θJ
,R
A
θJA
A
34
38
°C
°C
48
/W
/W
°C
/W
1.0
0
25
50
75
100
125
Ambient Temperature, TA (°C)
150
A,
4.0
R
QJ
LP
3.0
LW
26
,R
QJ
2.0
A
,R
QJA
A
28
44
°C
°C
°C
/W
/W
/W
1.0
0
25
50
75
100
125
Ambient Temperature, TA (°C)
150
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Package A, 16-pin DIP (A6278)
.775 19.69
.735 18.67
A
.014 0.36
.008 0.20
B
16
.280 7.11
.240 6.10
.430 10.92
MAX
.300 .7.62
A
1
2
.195 4.95
.115 2.92
.015 0.38
MIN
.005 0.13
MIN
.070 1.78
.045 1.14
.100 .2.54
16X
.150 3.81
.115 2.92
.022 .056
.014 .036
SEATING
PLANE
C
Preliminary dimensions, for reference only
Dimensions in inches
Metric dimensions (mm) in brackets, for reference only
(reference JEDEC MS-001 BB)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
.010 [0.25] M C
Package A, 24-pin DIP (A6279)
1.280 32.51
1.230 31.24
A
.014 0.36
.008 0.20
B
24
.280 7.11
.240 6.10
.300 .7.62
.430 10.92
MAX
A
1
2
.195 4.95
.115 2.92
.015 0.38
MIN
.005 0.13
MIN
.100 .2.54
.070 1.78
.045 1.14
24X
.022 .056
.014 .036
.150 3.81
.115 2.92
SEATING
PLANE
C
Preliminary dimensions, for reference only
Dimensions in inches
Metric dimensions (mm) in brackets, for reference only
(reference JEDEC MS-001 AF)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
.010 [0.25] M C
14
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Package LP, 16-pin TSSOP with Exposed Thermal Pad (A6278)
5.10 .201
4.90 .193
16
8º
0º
A
B
0.20 .008
0.09 .004
4.5
4.3
B
.177
.169
3 .118
NOM
6.6
6.2
A
1
1 .039
REF
2
3 .118
NOM
0.25 .010
16X
SEATING
PLANE
0.10 [.004] C
16X
0.30 .012
0.19 .007
SEATING PLANE
GAUGE PLANE
0.15 .006
0.00 .000
0.65 .026
0.53 .021
REF
C
1.20 .047
MAX
0.10 [.004] M C A B
1.85 .073
NOM
0.75 .030
0.45 .018
.260
.244
0.45 .018
NOM
16
0.65 .026
NOM
3
.118
NOM
C
5.9 .232
NOM
Preliminary dimensions, for reference only
(reference JEDEC MO-153 ABT)
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface) U.S. Customary dimensions controlling
C Reference land pattern layout (reference IPC7351
TSOP65P640X120-17M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
1 2
3 .118
NOM
15
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Package LP, 24-pin TSSOP with Exposed Thermal Pad (A6279)
7.9
7.7
24
.311
.303
8º
0º
A
B
0.20 .008
0.09 .004
4.5
4.3
B
.177
.169
3 .118
NOM
6.6
6.2
A
1
2
1 .039
REF
4.32 .170
NOM
0.25 .010
24X
SEATING
PLANE
0.10 [.004] C
24X
0.30 .012
0.19 .007
0.65 .026
0.53 .021
REF
C
SEATING PLANE
GAUGE PLANE
1.20 .047
MAX
0.10 [.004] M C A B
1.85 .073
NOM
0.75 .030
0.45 .018
.260
.244
0.15 .006
0.00 .000
0.45 .018
NOM
24
0.65 .026
NOM
3
.118
NOM
C
5.9 .232
NOM
Preliminary dimensions, for reference only
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface) U.S. Customary dimensions controlling
C Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
1
2
4.32 .170
NOM
16
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Package LW, 16-pin SOIC (A6278)
10.63 .419
9.97 .393
0.25 [.010] M B M
10.50 .614
10.10 .598
8º
0º
A
B
16
0.33 .013
0.20 .008
7.60 .299
7.40 .291
A
1
1.27 .050
0.40 .016
2
0.25 .010
16X
16X
0.51 .020
0.31 .012
SEATING PLANE
GAUGE PLANE
C
SEATING
PLANE
0.10 [.004] C
Preliminary dimensions, for reference only
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
(reference JEDEC MS-013 AA)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
2.65 .104
2.35 .093
0.25 [.010] M C A B
1.27 .050
0.30 .012
0.10 .004
A Terminal #1 mark area
Package LW, 24-pin SOIC (A6279)
10.63 .419
9.97 .393
0.25 [.010] M B M
15.60 .614
15.20 .598
8º
0º
A
B
24
0.33 .013
0.20 .008
7.60 .299
7.40 .291
A
1
1.27 .050
0.40 .016
2
0.25 .010
24X
SEATING
PLANE
0.10 [.004] C
24X
0.51 .020
0.31 .012
0.25 [.010] M C A B
2.65 .104
2.35 .093
1.27 .050
0.30 .012
0.10 .004
SEATING PLANE
GAUGE PLANE
C
Preliminary dimensions, for reference only
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
(reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
17
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283; 5,389,889;
5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copyright©2005, 2006 Allegro MicroSystems, Inc.
18
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com