Rohm BD9011EKN Step-down, high-efficiency switching regulators (controller type) Datasheet

TECHNICAL NOTE
Large Current External FET Controller Type Switching Regulator
Step-down,
High-efficiency
Switching Regulators
(Controller type)
BD9011EKN , BD9011KV , BD9775FV
■ BD9011EKN, BD9011KV
●Overview
The BD9011EKN/KV is a 2-ch synchronous controller with rectification switching for enhanced power management efficiency.
It supports a wide input range, enabling low power consumption ecodesign for an array of electronics.
●Features
1) Wide input voltage range: 3.9V to 30V
2) Precision voltage references: 0.8V±1%
3) FET direct drive
4) Rectification switching for increased efficiency
5) Variable frequency: 250k to 550kHz (external synchronization to 550kHz)
6) Built-in selected OFF latch and auto remove over current protection
7) Built-in independent power up/power down sequencing control
8) Make various application , step-down , step-up and step-up-down
9) Small footprint packages: HQFN36V, VQFP48C
●Applications
Car audio and navigation systems, CRTTV，LCDTV，PDPTV，STB，DVD，and PC systems，portable CD and DVD players,
etc.
●Absolute Maximum Ratings (Ta=25℃)
Parameter
EXTVCC Voltage
Symbol
EXTVCC
VCCCL1,2 Voltage
VCCCL1,2
CL1,2 Voltage
CL1,2
SW1,2 Voltage
SW1,2
Unit
Parameter
Symbol
34
*1
V
COMP1,2 Voltage
COMP1,2
34
*1
V
DET1,2 Voltage
DET1,2
V
RT､SYNC Voltage
RT､SYNC
Rating
34
34
*1
V
*1
V
VREG5
V
*2
BOOT1,2
40
BOOT1,2-SW1,2
Voltage
BOOT1,2-SW1,2
7
STB, EN1,2 Voltage
STB, EN1,2
VCC
V
VREG5,5A
VREG5,5A
7
V
VREG33
VREG33
VREG5
V
Operating
temperature
Storage temperature
SS1,2､FB1,2
SS1,2､FB1,2
VREG5
V
Junction temperature
V
Unit
0.875
（HQFN36V）
BOOT1,2 Voltage
*1
Rating
Power Dissipation
W
Pd
*2
1.1
（VQFP48C）
W
Topr
-40 to +105
℃
Tstg
-55 to +150
℃
Tj
+150
℃
*1 Regardless of the listed rating, do not exceed Pd in any circumstances.
*2 Mounted on a 70mm x 70mm x 0.8mm glass-epoxy board. De-rated at 7.44mW/℃（HQFN36V） or 8.8mW/℃（VQFP48C）
above 25℃.
Sep. 2008
●Operating conditions (Ta=25℃)
Parameter
Symbol
Min.
3.9
Typ.
Max.
Unit
*1 *2
12
30
V
Input voltage 1
EXTVCC
Input voltage 2
VCC
3.9 *1 *2
12
30
V
BOOT－SW voltage
BOOT－SW
4.5
5
VREG5
V
Carrier frequency
OSC
250
300
550
kHz
Synchronous frequency
SYNC
OSC
-
550
kHz
Synchronous pulse duty
Duty
40
50
60
％
Min OFF pulse
TMIN
-
100
-
nsec
★This product is not designed to provide resistance against radiation.
*1 After more than 4.5V, voltage range.
*2 In case of using less than 6V, Short to VCC, EXTVCC and VREG5.
●Electrical characteristics (Unless otherwise specified, Ta=25℃ VCC=12V STB=5V EN1,2=5V)
Parameter
Symbol
VIN bias current
Shutdown mode current
Limit
Unit
Conditions
Min.
Typ.
Max.
IIN
-
5
10
mA
IST
-
0
10
μA
Feedback reference voltage
VOB
0.792
0.800
0.808
V
Feedback reference voltage
(Ta=-40 to 105℃)
VOB+
0.784
0.800
0.816
V
Open circuit voltage gain
Averr
-
46
-
dB
VO input bias current
IVo+
-
-
1
μA
HG high side ON resistance
HGhon
-
1.5
-
Ω
HG low side ON resistance
HGlon
-
1.0
-
Ω
LG high side ON resistance
LGhon
-
1.5
-
Ω
LG low side ON resistance
LGlon
-
0.5
-
Ω
Carrier frequency
FOSC
270
300
330
kHz
RT=100 kΩ
Synchronous frequency
Fsync
-
500
-
kHz
RT=100 kΩ,SYNC=500kHz
CL threshold voltage
Vswth
70
90
110
ｍV
CL threshold voltage
（Ta=-40 to 105℃）
Vswth+
67
90
113
ｍV
VREG5 output voltage
VREG5
4.8
5
5.2
V
IREF=6mA
VREG33 reference voltage
VREG33
3.0
3.3
3.6
V
IREG=6mA
VREG5 threshold voltage
VREG_UVLO
2.6
2.8
3.0
V
VREG:Sweep down
VREG5 hysteresis voltage
DVREG_UVLO
50
100
200
mV
VREG:Sweep up
ISS
6.5
10
13.5
μA
VSS=1V
14
μA
VSS=1V,Ta=-40 to 105℃
VSTB=0V
［Error Amp Block］
Ta=-40 to 105℃
※
［FET Driver Block］
［Oscillator］
［Over Current Protection Block］
Ta=-40 to 105℃
※
［VREG Block］
［Soft start block］
Charge current
Charge current
ISS+
6
10
(Ta=-40 to 105℃)
Note: Not all shipped products are subject to outgoing inspection.
2/29
※
●Reference data (Unless otherwise specified, Ta=25℃)
100
5.0V
90
5
80
80
70
1.8V
60
2.6V
3.3V
3.3V
1.2V
50
40
30
60
50
40
30
20
20
VIN=12V
10
Io=2A
10
0
1
2
OUTPUT CURRENT：Io[A]
6
3
9
12
15
18
21
INPUT VOLTAGE ： VIN[V]
0.804
0.800
0.796
0.792
0.788
0.784
10
35
60
85
10
20
INPUT VOLTAGE：VIN[V]
330
100
90
80
70
110
AMBIENT TEMPERATURE ： Ta[℃]
5.25
RT=100kΩ
320
310
300
290
280
270
-40
Fig.4 Reference voltage vs.
temperature characteristics
30
Fig.3 Circuit current
60
-15
1
0
OSILATING FREQUENCY ： FOSC[kHz]
過電流検出電圧 ： Vswth[mV]
0.808
-40
2
24
110
0.812
-40℃
3
Fig.2 Efficiency 2
Fig.1 Efficiency 1
0.816
25℃
105℃
4
0
0
0
REFERENCE VOLTAGE ： VOB[V]
5.0V
70
EFFICIENCY[%]
EFFICIENCY[%]
6
90
CIRCUIT CURRENT[mA]
100
-15
10
35
60
85
110
-40
-15
10
35
60
85
110
AMBIENT TEMPERATURE ： Ta[℃]
AMBIENT TEMPERATURE ： Ta[℃]
Fig.5 Over current detection vs.
temperature characteristics
Fig.6 Frequency vs.
temperature characteristics
3.0
6
4.50
4.25
4.00
3.75
VREG33
3.50
2.5
5
VREG5
OUT PUT VOLTAGE ： Vo[V]
4.75
OUT PUT VOLTAGE ： Vo[V]
OUT PUT VOLTAGE ： Vo[V]
5.00
5.0V
4
3
3.3V
2
3.00
-40
-15
10
35
60
85
110
LOFF=H
1.0
LOFF=L
0.0
0
0
AMBIENT TEMPERATURE ： Ta[℃]
1.5
0.5
1
3.25
RCL=15mΩ
2.0
Fig.7 Internal Reg vs.
temperature characteristics
5
10
15
20
INPUT VOLTAGE ： VIN[V]
0
25
1
2
3
4
5
6
OUTPUT CURRENT: Io[A]
Fig.8 Line regulation
Fig.9 Load regulation
OUTPU T VOLTAGE ： Vo[V]
6
50mV/div
5
VOUT
50mV/div
VOUT
4
105℃
3
25℃
2
-40℃
1
IOUT
0
0
2
4
INPUT VOLTAGE：V EN[V]
1A/div
6
Fig.10 EN threshold voltage
Fig.11 Load transient response 1
3/29
IOUT
1A/div
Fig.12 Load transient response 2
●Block diagram
(Parentheses indicate VQFP48C pin numbers)
EXTVCC
STB VCC
RT
SYNC
10
(25)
15
(33)
16
(34)
22
(41)
32
(7)
5V Reg
VREG5
3.3V Reg
24(44)
5(19)
B.G
17(35)
VCCCL2
31(5)
CL2
30(3)
BOOT2
29(2)
OUTH2
28(1)
SW2
27(48)
2.7V
25(46)
DGND2
26(47)
FB2
SS2
21(39)
Set
Set
DRV
Reset
Reset
TSD
UVLO
TSD
UVLO
Q
Reset Set
－
＋
＋
PW M
COMP
Slope
Slope
PW M
COMP
BOOT1
OUTH1
SW
1(13)
SW1
LOGIC
4(17)
VREG5A
3(15)
OUTL1
Q
Set Reset
UVLO
Ｏ
2(14)
DGND1
6(21)
8(23)
FB1
SS1
7(22)
COMP1
0.8V
0.8V
20(38)
VCCCL1
CL1
35(11)
Err Amp
Err Amp
33(8)
34(10)
36(12)
DRV
SW
19(37)
COMP2
OCP
LOGIC
LLM
OSC
OCP
VREG5
OUTL2
TSD
TSD
UVLO
VREG33
SYNC
Q
Q
Set
Reset
Sequence DET
Reset
Set
Sequence DET
0.56V
0.56V
18
(36)
14
(31)
12
(27)
DET2
LOFF
EN2
11
(26)
(30)
13
(29)
9
(24)
EN1 (GNDS) GND
DET1
Fig-13
●Pin configuration
●PIN function table
15 RT
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14 LOFF
14
LOFF
13 GND
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
RT
SYNC
LLM
DET2
SS2
COMP2
FB2
EXTVCC
－
VREG5
OUTL2
DGND2
SW2
OUTH2
BOOT2
CL2
VCCCL2
VCC
VCCCL1
CL1
BOOT1
OUTH1
24
23
SS2
VREG5
25
COMP2
OUTL2
26
FB2
DGND2
27
EXTVCC
SW2
BD9011EKN（HQFN36V）
22
21
20
19
OUTH2 28
18 DET2
BOOT2 29
17 LMM
CL2 30
16 SYNC
VCCCL2 31
VCC 32
VCCCL1 33
4
5
6
7
8
9
DET1
3
SS1
2
COMP1
1
FB1
10 STB
VREG33
OUTH1 36
VREG5A
11 EN1
OUTL1
BOOT1 35
DGND1
12 EN2
SW1
CL1 34
Fig-14
4/29
Pin name
Function
SW1
DGND1
OUTL1
VREG5A
VREG33
FB1
COMP1
SS1
DET1
STB
EN1
EN2
GND
High side FET source pin 1
Low side FET source pin 1
Low side FET gate drive pin 1
FET drive REG input
Reference input REG output
Error amp input 1
Error amp output 1
Soft start setting pin 1
FB detector output 1
Standby ON/OFF pin
Output 1ON/OFF pin
Output 2ON/OFFpin
Ground
Over current protection OFF latch
function ON/OFF pin
Switching frequency setting pin
External synchronous pulse input pin
Built-in pull-down resistor pin
FB detector output 2
Soft start setting pin 2
Error amp output 2
Error amp input 2
External power input pin
N.C.
FET drive REG output
Low side FET gate drive pin 2
Low side FET source pin 2
High side FET source pin 2
Hi side FET gate drive pin 2
OUTH2 driver power pin
Over current detector setting pin 2
Over current detection VCC2
Input power pin
Over current detection VCC1
Over current detector setting pin 1
OUTH1 driver power pin
High side FET gate drive pin 1
●Pin configuration
●Pin function table
DET2
LLM
SYNC
RT
N.C
LOFF
GNDS
GND
N.C
EN2
EN1
STB
BD9011KV（VQFP48C）
36
35
34
33
32
31
30
29
28
27
26
25
24 DET1
SS2 37
23 SS1
COMP2 38
FB2 39
22 COMP1
N.C 40
21 FB1
EXTVCC 41
20 N.C
N.C 42
19 VREG33
N.C 43
18 N.C
17 VREG5A
VREG5 44
16 N.C
N.C 45
OUTL2 46
15 OUTL1
DGND2 47
14 DGND1
13 SW1
1
2
3
4
5
6
7
8
9
10
11
12
OUTH2
BOOT2
CL2
N.C
VCCCL2
N.C
VCC
VCCCL1
N.C
CL1
BOOT1
OUTH1
SW2 48
Fig-15
●Block functional descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Pin name
Function
OUTH2
BOOT2
CL2
N.C
VCCCL2
N.C
VCC
VCCCL1
N.C
CL1
BOOT1
OUTH1
SW1
DGND1
OUTL1
N.C
VREG5A
N.C
VREG33
N.C
FB1
COMP1
SS1
DET1
STB
EN1
EN2
N.C
GND
GNDS
High side FET gate drive pin 2
OUTH2 driver power pin
Over current detection pin 2
Non-connect (unused) pin
Over current detection VCC2
Non-connect (unused) pin
Input power pin
Over current detection CC1
Non-connect (unused) pin
Over current detection setting pin 1
OUTH1 driver power pin
High side FET gate drive pin 1
High side FET source pin 1
Low side FET source pin 1
Low side FET gate drive pin 1
Non-connect (unused) pin
FET drive REG input
Non-connect (unused) pin
Reference input REG output
Non-connect (unused) pin
Error amp input 1
Error amp output 1
Soft start setting pin 1
FB detector output 1
Standby ON/OFF pin
Output 1 ON/OFF pin
Output 2 ON/OFF pin
Non-connect (unused) pin
Ground
Sense ground
Over current protection OFF latch
function ON/OFF pin
Non-connect (unused) pin
Switching frequency setting pin
External synchronous pulse input pin
Built-in pull-down resistor pin
FB detector output 2
Soft start setting pin 2
Error amp output 2
Error amp input 2
Non-connect (unused) pin
External power input pin
Non-connect (unused) pin
Non-connect (unused) pin
FET drive REG output
Non-connect (unused) pin
Low side FET gate drive pin 2
Low side FET source pin 2
High side FET source pin 2
31
LOFF
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
N.C
RT
SYNC
LLM
DET2
SS2
COMP2
FB2
N.C
EXTVCC
N.C
N.C
VREG5
N.C
OUTL2
DGND2
SW2
・Error amp
The error amp compares output feedback voltage to the 0.8V reference voltage and provides the comparison result as COMP voltage, which is
used to determine the switching Duty. COMP voltage is limited to the SS voltage, since soft start at power up is based on SS pin voltage.
・Oscillator (OSC)
Oscillation frequency is determined by the switching frequency pin (RT) in this block. The frequency can be set between 250kHz and 550kHz.
・ SLOPE
The SLOPE block uses the clock produced by the oscillator to generate a triangular wave, and sends the wave to the PWM comparator.
・PWM COMP
The PWM comparator determines switching Duty by comparing the COMP voltage, output from the error amp, with the triangular wave from the
SLOPE block. Switching duty is limited to a percentage of the internal maximum duty, and thus cannot be 100% of the maximum.
・Reference voltage (5Vreg，33Vreg)
This block generates the internal reference voltages: 5V and 3.3V.
・External synchronization (SYNC)
Determines the switching frequency, based on the external pulse applied.
・Over current protection (OCP)
Over current protection is activated when the VCCCL-CL voltage reaches or exceeds 90mV. When over current protection is active, Duty is low,
and output voltage also decreases. When LOFF=L, the output voltage has fallen to 70% or below and output is latched OFF. The OFF latch
mode ends when the latch is set to STB, EN.
・Sequence control (Sequence DET)
Compares FB voltage with reference voltage (0.56V) and outputs the result as DET.
・Protection circuits (UVLO/TSD)
The UVLO lock out function is activated when VREG falls to about 2.8V, while TSD turns outputs OFF when the chip temperature reaches or
exceeds 150℃. Output is restored when temperature falls back below the threshold value.
5/29
●Application circuit example (Parentheses indicate VQFP48C pin numbers)
VIN(12V)
100uF
36
35
34
33
32
31
30
29
28
(12)
(11)
(10)
(8)
(7)
(5)
(3)
(2)
(1)
CL1
VCC
VCCCL2
CL2
BOOT2
OUTH1
OUTL1
OUTL2
25(46)
4(17)
VREG5A
VREG5
24(44)
5(19)
VREG33
6(21)
FB1
7(22)
COMP1
8(23)
SS1
9(24)
DET1
STB
0.1uF
(SLF12565：TDK)
0.1
uF
EXTVCC
22(41)
FB2
21(39)
COMP2
20(38)
19(37)
SS2
DET2
10
11
12
13
14
15
16
17
18
(25)
(26)
(27)
(29)
(31)
(33)
(34)
(35)
(36)
10uH
Vo(3.3V/3A)
RB051
L-40
220uF
(OS ｺﾝ)
47kΩ
1uF
23
LLM
39kΩ
26(47)
DGND1
SYNC
13kΩ
DGND2
2(14)
3(15)
RT
1uF
27(48)
LOFF
1uF
SW2
GND
(OS ｺﾝ)
SW1
EN2
220uF
1(13)
RB160
VA-40
OUTH2
EN1
RB051
L-40
SP8K2
VCCCL1
0.1
uF
10uH
100Ω
1nF
BOOT1
RB160
VA-40
15000pF
uF
1nF
(SLF12565：TDK)
68kΩ
15mΩ
10
Ω
0.33
100Ω
SP8K2
Vo(5V/3A)
15mΩ
0.33uF
15kΩ
39kΩ
15000pF
0.1uF
100kΩ
Fig-16A（Step-Down：Cout=OS Capacitor）
There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics.
Please verify and confirm using practical applications.
VIN(12V)
100uF
1kΩ
30
29
28
(5)
(3)
(2)
(1)
VCCCL1
VCC
VCCCL2
CL2
BOOT2
1(13)
SW1
2(14)
DGND1
3(15)
4(17)
5(19)
VREG33
6(21)
FB1
7(22)
COMP1
8(23)
0.1uF
9(24)
RB160
VA-40
OUTH2
SW2
27(48)
DGND2
26(47)
OUTL1
OUTL2
25(46)
VREG5A
VREG5
24(44)
23
SS1
EXTVCC
22(41)
FB2
21(39)
COMP2
20(38)
19(37)
LLM
10000pF
31
(7)
OUTH1
330pF
12kΩ
32
(8)
SYNC
1uF
33
RT
1uF
34
(10)
LOFF
(C2012JB
0J106K
：TDK)
35
(11)
GND
30uF
36
(12)
EN2
15kΩ
150Ω
SP8K2
CL1
RB051
L-40
3300pF
100Ω
1nF
BOOT1
RB160
VA-40
0.1
uF
10uH
uF
1nF
EN1
Vo(1.8V/2A)
23mΩ
10
Ω
0.33
100Ω
SP8K2
(SLF10145：TDK)
23mΩ
SS2
DET2
10
11
12
13
14
15
16
17
18
(25)
(26)
(27)
(29)
(31)
(33)
(34)
(35)
(36)
DET1
STB
(SLF10145：TDK)
0.1
uF
10uH
Vo(2.5V/2A)
RB051
L-40
30uF
1uF
43
kΩ
(C2012JB
0J106K
：TDK)
1000pF
510Ω
0.33uF
330pF
20kΩ
3.3kΩ 3300pF
0.1uF
100kΩ
Fig-16B（Step-Down：Cout=Ceramic Capacitor）
There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics.
Please verify and confirm using practical applications.
6/29
VIN(12V)
100uF
0.33
100Ω
uF
＊REGSPIC
100Ω
1nF
33
32
31
30
29
28
(8)
(7)
(5)
(3)
(2)
(1)
4(17)
VREG5A
5(19)
VREG33
6(21)
FB1
7(22)
COMP1
9(24)
VCC
VCCCL2
DGND2
26(47)
OUTL2
25(46)
VREG5
SS1
24(44)
22(41)
FB2
21(39)
COMP2
20(38)
SS2
DET2
11
12
13
14
15
16
17
18
(25)
(26)
(27)
(29)
(31)
(33)
(34)
(35)
(36)
Vo(12V/1A)
Co2
EXTVCC
10
DET1
STB
(SLF12565：TDK)
L2
27uH Do3
0.1
uF
1uF
91
kΩ
220
uF
RB051
L-40
23
LLM
8(23)
0.1uF
CL1
OUTL1
27(48)
SYNC
10kΩ
DGND1
SW2
RT
1000pF
2(14)
3(15)
OUTH2
LOFF
1uF
SW1
GND
1uF
1(13)
RB160
VA-40
EN2
5.1kΩ
22000pF
34
(10)
OUTH1
680
kΩ
23.5kΩ
35
(11)
VCCCL1
1uF
220uF
1000pF
36
(12)
BOOT1
RSS
065N03
EN1
Co1
TM
SP8K2
1nF
CL2
RB051L-40
10mΩ
10
Ω
BOOT2
Vo(24V/1A)
10mΩ
L1 (SLF12565：TDK)
27uH
3300pF
10kΩ
0.33uF
1000pF
6.2kΩ
4.7kΩ
19(37)
22000pF
0.1uF
＊
100kΩ
REGSPICTM is
Trade Mark of RHOM
Fig-16C（Step-Down：Low Input Voltage）
There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics.
Please verify and confirm using practical applications.
VIN(5V)
100uF
4700pF
3.3kΩ
30
29
28
(5)
(3)
(2)
(1)
CL1
VCC
VCCCL2
CL2
BOOT2
OUTH1
1(13)
SW1
2(14)
DGND1
3(15)
OUTL1
4(17)
VREG5A
5(19)
VREG33
6(21)
FB1
7(22)
COMP1
8(23)
0.1uF
9(24)
SW2
27(48)
DGND2
26(47)
OUTL2
25(46)
VREG5
24(44)
23
SS1
EXTVCC
22(41)
FB2
21(39)
COMP2
20(38)
SS2
DET2
10
11
12
13
14
15
16
17
18
(25)
(26)
(27)
(29)
(31)
(33)
(34)
(35)
(36)
DET1
STB
RB160
VA-40
0.1uF
OUTH2
LLM
100pF
12kΩ
31
(7)
SYNC
1uF
32
(8)
RT
1uF
33
LOFF
100Ω
34
(10)
GND
(ｾﾗｺﾝ)
35
(11)
EN2
30uF
36
VCCCL1
0.1uF
SP8K2
EN1
15kΩ
100Ω
1nF
(12)
BOOT1
RB160
VA-40
RB051
L-40
3300pF
uF
1nF
(SLF10145：TDK)
6.8uH
23mΩ
10
Ω
0.33
100Ω
SP8K2
Vo(1.8V/2A)
23mΩ
(SLF10145：TDK)
6.8uH
Vo(2.5V/2A)
RB051
L-40
30uF
(ｾﾗｺﾝ)
1uF
1000pF
300Ω
0.33uF
33pF
19(37)
43
kΩ
20kΩ
10kΩ
2200pF
0.1uF
100kΩ
Fig-16D（Step-Up：and Step-Up-Down）
There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics.
Please verify and confirm using practical applications.
7/29
●Application component selection
(1) Setting the output L value
The coil value significantly influences the output ripple current.
Thus, as seen in equation (5), the larger the coil, and the higher
the switching frequency, the lower the drop in ripple current.
ΔIL
Fig-17
ΔIL =
（VCC-VOUT）×VOUT
L×VCC×f
[A]・・・
（5）
VCC
IL
The optimal output ripple current setting is 30% of maximum current.
ΔIL = 0.3×IOUTmax.[A]・・・（6）
VOUT
L
Co
L=
Fig-18
（VCC-VOUT）×VOUT
ΔIL×VCC×f
（ΔIL：output ripple current
Output ripple current
[H]・・・
（7）
f：switching frequency）
※Outputting a current in excess of the coil current rating will cause magnetic saturation of the coil and decrease
efficiency.
Please establish sufficient margin to ensure that peak current does not exceed the coil current rating.
※Use low resistance (DCR, ACR) coils to minimize coil loss and increase efficiency.
(2) Setting the output capacitor Co value
Select the output capacitor with the highest value for ripple voltage (VPP) tolerance and maximum drop voltage
(at rapid load change). The following equation is used to determine the output ripple voltage.
Vo
ΔIL
Step down
ΔVPP = ΔIL × RESR +
1
×
Co
×
f
Vcc
[V]
Note: f：switching frequency
Be sure to keep the output Co setting within the allowable ripple voltage range.
※Please allow sufficient output voltage margin in establishing the capacitor rating. Note that low-ESR capacitors enable
lower output ripple voltage.
Also, to meet the requirement for setting the output startup time parameter within the soft start time range, please factor
in the conditions described in the capacitance equation (9) for output capacitors, below.
Co ≦
TSS × (Limit – IOUT)
Tss： soft start time
・・・ （9）
VOUT
ILimit：over current detection value（2/16）reference
Note: less than optimal capacitance values may cause problems at startup.
(3) Input capacitor selection
VIN
Cin
VOUT
L
Co
The input capacitor serves to lower the output impedance of the power
source connected to the input pin (VCC). Increased power supply output
impedance can cause input voltage (VCC) instability, and may negatively
impact oscillation and ripple rejection characteristics. Therefore, be
certain to establish an input capacitor in close proximity to the VCC and
GND pins. Select a low-ESR capacitor with the required ripple current
capacity and the capability to withstand temperature changes without
wide tolerance fluctuations. The ripple current IRMSS is determined
using equation (10).
IRMS = IOUT ×
Fig-19
Input capacitor
VOUT（VCC - VOUT）
[A]・・・
（10）
VCC
Also, be certain to ascertain the operating temperature, load range and
MOSFET conditions for the application in which the capacitor will be used,
since capacitor performance is heavily dependent on the application’s
input power characteristics, substrate wiring and MOSFET gate drain
capacity.
8/29
(4) Feedback resistor design
Please refer to the following equation in determining the proper feedback resistance. The recommended setting is in a range
between 10kΩ and 330kΩ. Resistance less than 10kΩ risks decreased power efficiency, while setting the resistance value
higher than 330kΩ will result in an internal error amp input bias current of 0.2uA increasing the offset voltage.
Vo
Internal ref. 0.8V
Vo =
R8
R8 +R9
R9
× 0.8 [V] ・・・（11）
FB
R9
Fig-20
(5) Setting switching frequency
The triangular wave switching frequency can be set by connecting a resistor to the RT 15(33) pin. The RT sets the frequency
by adjusting the charge/discharge current in relation to the internal capacitor. Refer to the figure below in determining proper
RT resistance, noting that the recommended resistance setting is between 50kΩ and 130kΩ. Settings outside this range
may render the switching function inoperable, and proper operation of the controller overall cannot be guaranteed when
unsupported resistance values are used.
550
周波数 [ kHz ]
500
450
400
350
300
250
50
60
70
80
90
RT [ kΩ]
100
110
120
130
Fig-21 RT vs. switching frequency
(6) Setting the soft start delay
The soft start function is necessary to prevent an inrush of coil current and output voltage overshoot at startup. The figure
below shows the relation between soft start delay time and capacitance, which can be calculated using equation (12) at right.
DELAY TIME[ms]
10
1
0.8V(typ.)×CSS
TSS =
[sec]・・・(12)
ISS(10μA Typ.)
0.1
0.01
0.001
0.01
0.1
SS CAPACITANCE[uF]
Fig-22 SS capacitance vs. delay time
Recommended capacitance values are between 0.01uF and 0.1uF. Capacitance lower than 0.01uF may generate output
overshoots. Please use high accuracy components (such as X5R) when implementing sequential startups involving other
power sources. Be sure to test the actual devices and applications to be used, since the soft start time varies, depending on
input voltage, output voltage and capacitance, coils and other characteristics.
9/29
(7) Setting over current detection values
The current limit value（ILimit）is determined by the resistance of the RCL established between CL and VCCCL.
VCCCL
VIN
Over current detection point
IL
RCL
CL
IL
Vo
ILimit =
L
Fig-23
90m
RCL
[A]・・・(13)
Fig-24
There are 2 current limit function (ON/OFF control type and OFF latch type) toggled by LOFF pin.
・LOFF=L (0<LOFF<1V): Off Latch Type Current Limit
The output becomes OFF and latched when SS=H and, current limit operation, and the output voltage is less than or equal
to 70% of Vo. The OFF latch is deactivated by re-inputting EN signal or VCC control input (switch OFF and ON once more).
・LOFF=H (1<LOFF<VREG5): ON/OFF Control Type Current Limit
When the current goes beyond the threshold value, the current can be limited by reducing the ON Duty Cycle. When the load
goes back to the normal operation, the output voltage also becomes back on to the specific level.
The current limit value
Vo
LOFF=L
（OFF Latch）
Vo×70%
LOFF=H
Io
Fig-25
(8) Method for determining phase compensation
Conditions for application stability
Feedback stability conditions are as follows:
・When gain is 1 (0dB) and phase shift is 150° or less (i.e., phase margin is at least 30°):
a dual-output high-frequency step-down switching regulator is required
Additionally, in DC/DC applications, sampling is based on the switching frequency; therefore, overall GBW may be set at no
more than 1/10 the switching frequency. In summary, target characteristics for application stability are:
・Phase shift of 150° or less (i.e., phase margin of 30° or more) with gain of 1 (0dB)
・GBW (i.e., gain 0dB frequency) no more than 1/10 the switching frequency.
Stability conditions mandate a relatively higher switching frequency, in order to limit GBW enough to increase response.
The key to achieving successful stabilization using phase compensation is to cancel the secondary phase margin/delay
(-180°) generated by LC resonance, by employing a dual phase lead. In short, adding two phase leads stabilizes the
application.
GBW (the frequency at gain 1) is determined by the phase compensation capacitor connected to the error amp. Thus, a larger
capacitor will serve to lower GBW if desired.
①
General use integrator (low-pass filter)
Feedback
A
R
COMP
②
Gain
[dB]
Integrator open loop characteristics
A
(a)
-20dB/decade
18 0
GBW(b)
90
0
Phase 0
[deg] -90
-9 0
C
-18 0
-180
1
2πRCA
point (b) fa = GBW
0
FB
point (a) fa =
-90°
Phase margin
Fig-26
1.25[Hz]
1
2πRC
[Hz]
-180°
Fig-27
The error amp is provided with phase compensation similar to that depicted in figures ① and ② above and thus serves
as the system’s low-pass filter.
In DC/DC converter applications, R is established parallel to the feedback resistance.
10/29
When electrolytic or other high-ESR output capacitors are used:
Phase compensation is relatively simple for applications employing high-ESR output capacitors (on the order of several
Ω). In DC/DC converter applications, where LC resonance circuits are always incorporated, the phase margin at these
locations is -180°. However, wherever ESR is present, a 90° phase lead is generated, limiting the net phase margin to -90°
in the presence of ESR. Since the desired phase margin is in a range less than 150°, this is a highly advantageous
approach in terms of the phase margin. However, it also has the drawback of increasing output voltage ripple components.
③ LC resonance circuit
④ ESR connected
Vcc
Vcc
Vo
Vo
L
fr =
L
C
1
2π√LC
RESR
C
Fig-28
Fig-29
resonance point1
[Hz]：Resonance Point
2π√LC
1
fESR =
[Hz] :Zero
2πRESRC
fr =
[Hz]
Resonance point phase margin -180°
-90°:Pole
Since ESR changes the phase characteristics, only one phase lead need be provided for high-ESR applications. Please choose
one of the following methods to add the phase lead.
⑤
Add C to feedback resistor
⑥
Vo
Add R3 to aggregator
Vo
C2
C1
R3
C2
R1
R1
FB
FB
A
R2
COMP
Fig-30
Phase lead fz =
COMP
A
R2
Fig-31
1
2πC1R1
[Hz]
Phase lead fz =
1
2πC2R3
[Hz]
Set the phase lead frequency close to the LC resonance frequency in order to cancel the LC resonance.
When using ceramic, OS-CON, or other low-ESR capacitors for the output capacitor:
Where low-ESR (on the order of tens of mΩ) output capacitors are employed, a two phase-lead insertion scheme is
required, but this is different from the approach described in figure ③~⑥, since in this case the LC resonance gives rise
to a 180° phase margin/delay. Here, a phase compensation method such as that shown in figure ⑦ below can be
implemented.
⑦
Phase compensation provided by secondary (dual) phase lead
Vo
R1
C1
Phase lead fz1 =
C2
R3
Phase lead fz2 =
FB
A
COMP
1
2πR1C1
1
2πR3C2
LC resonance frequency fr =
R2
[Hz]
[Hz]
1
2π√LC
[Hz]
Fig-32
Once the phase-lead frequency is determined, it should be set close to the LC resonance frequency.
This technique simplifies the phase topology of the DCDC Converter. Therefore, it might need a certain amount
of trial-and-error process. There are many factors(The PCB board layout, Output Current, etc.)that can affect
the DCDC characteristics. Please verify and confirm using practical applications.
11/29
（9）MOSFET selection
VCC
VDS
IL
Vo
VGSM1
VDS
VGSM2
FET uses Nch MOS
・VDS＞Vcc
・VGSM1＞BOOT-SW interval voltage
・VGSM2＞VREG5
・Allowable current＞voltage current + ripple current
※Should be at least the over current protection value
※Select a low ON-resistance MOSFET for highest efficiency
Fig-33
（10）Schottky barrier diode selection
VCC
Vo
VR
Fig-34
・ Reverse voltage VR＞Vcc
・ Allowable current＞voltage current + ripple current
※Should be at least the over current protection value
※Select a low forward voltage, fast recovery diode for highest
efficiency
・ The shoot-through may happen when the input parasitic
capacitance of FET is extremely big or the Duty ratio is less
than or equal to 10%. Less than or equal to 1000pF input
parasitic capacitance is recommended. Please confirm
operation on the actual application since this character is
affected by PCB layout and components.
（11）Sequence function
●Circuit diagram
●Timing chart
When EN1 stays ”H” and EN2 returns to ”H”, DET1 is in
open state; thus SS2 is asserted, and Vo2 output starts.
If Vo2 is 76% of the voltage setting or higher, DET2 goes
open and SS1 is asserted, starting Vo1 output.
With EN1, 2 at ”H” level, when EN1 goes ”L”,
Vo1 turns OFF, but Vo2 output continues.
VREG5
VCC VREG5
EN1
EN2
Vo1
OUTH1 BOOT1 VCC BOOT2 OUTH2
SW1
Vo2
SW2
OUTL1
OUTL2
DGND1
DGND2
DET2
SS1
FB1
0.61V
FB2
FB1
COMP1
COMP2
SS1
Vo1
over 76%
SS2
DET2
STB
DET1
SS2
DET1
EN1
EN2 GND
FB2
Vo2
0.56V
under 70%
With EN1,2 at “H” level, if
Vo1 starts at 76% or more of
voltage setting, DET goes
open and SS1 is asserted,
starting Vo2 output.
Fig-35
A
0.56V
over 76%
A
With EN2 set ”L”, if Vo2
goes below 70% the voltage
setting, DET2 shorts and SS1
is asserted, turning Vo1 OFF
Fig-36
12/29
0.61V
over 70%
Same as “A” at left
●Input/Output equivalent circuits
(Items in parentheses apply to VQFP48C)
1(13)，27(48)PIN（SW1，SW2）
2(14)，26(47)PIN（DGND1，DGND2）
29(2)，35(11)PIN（BOOT2，BOOT1） 3(15)，25(46)PIN（OUTL1，OUTL2） 14(31)PIN（LOFF）
28(1)，36(15)PIN（OUTH1，OUTH2） 24(44) VREG5 / 4(17)VREG5A
VREG5
BOOT
OUTL
OUTH
LOFF
172.2k
100k
DGND
SW
135.8k
300k
16(34)PIN（SYNC）
VREG5
/ VREG5A
VREG5
/ VREG5A
VREG5
5k
SYNC
1k
FB
250k
2k
SS
50k
1P
2.5k
10(25)，11(26)，12(27)PIN
（STB，EN1，EN2）
100k
9(24)，18(36)PIN（DET1，DET2）
VCC
STB
EN
8(23)，19(37)PIN（SS1，SS2）
6(21)，21(39)PIN（FB1，FB2）
15(33)PIN（RT）
VREG5
/ VREG5A
172.2k
100k
VREG5
10k
DET
RT
135.8k
30(3)，34(10)PIN（CL2，CL1）
7(22)，20(38)PIN（COMP1，COMP2）
31(5)，33(8)PIN（VCCCL2，VCCCL1）
17(35)PIN（LLM）
VCC
VREG5
/ VREG5A
VREG5A
VCCCL
5k
VCC
LLM
5P
308k
CL
22(41)PIN（EXTV，CC）
24(44)PIN（VREG5）
5kΩ
5kΩ
1k
5(19)PIN（VREG33）
4(17)DIN（VREG5A）
VCC
VCC
EXTVCC
20Ω
COMP
VCC
VREG5A
VCC
150k
150k
VREG5
VREG5A
VREG33
746.32k
746.32k
255k
469.06k
13/29
●Operation notes
1）Absolute maximum ratings
Exceeding the absolute maximum ratings for supply voltage, operating temperature or other parameters can damage or
destroy the IC. When this occurs, it is impossible to identify the source of the damage as a short circuit, open circuit, etc.
Therefore, if any special mode is being considered with values expected to exceed absolute maximum ratings, consider
taking physical safety measures to protect the circuits, such as adding fuses.
2）GND electric potential
Keep the GND terminal potential at the lowest (minimum) potential under any operating condition.
3）Thermal design
Be sure that the thermal design allows sufficient margin for power dissipation (Pd) under actual operating conditions.
4）Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed surface boards. Connection errors may result in damage or
destruction of the IC. The IC can also be damaged when foreign substances short output pins together, or cause shorts
between the power supply and GND.
5）Operation in strong electromagnetic fields
Use caution when operating in the presence of strong electromagnetic fields, as this may cause the IC to malfunction.
6）Testing on application boards
Connecting a capacitor to a low impedance pin for testing on an application board may subject the IC to stress. Be sure to
discharge the capacitors after every test process or step. Always turn the IC power supply off before connecting it to or
removing it from any of the apparatus used during the testing process. In addition, ground the IC during all steps in the
assembly process, and take similar antistatic precautions when transporting or storing the IC.
7) The output FET
The shoot-through may happen when the input parasitic capacitance of FET is extremely big or the Duty ratio is less than
or equal to 10%. Less than or equal to 1000pF input parasitic capacitance is recommended. Please confirm operation on
the actual application since this character is affected by PCB layout and components.
8）This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. Relations between each potential may form as shown in the example below, where a resistor and transistor
are connected to a pin:
○
With the resistor, when GND＞ Pin A, and with the transistor (NPN), when GND＞Pin B:
The P-N junction operates as a parasitic diode
○
With the transistor (NPN), when GND＞ Pin B:
The P-N junction operates as a parasitic transistor by interacting with the N layers of elements in proximity to the
parasitic diode described above.
Parasitic diodes inevitably occur in the structure of the IC. Their operation can result in mutual interference between circuits,
and can cause malfunctions, and, in turn, physical damage or destruction. Therefore, do not employ any of the methods
under which parasitic diodes can operate, such as applying a voltage to an input pin lower than the (P substrate) GND.
Resistor
Transistor（NPN）
(PINA)
(PINB)
B
C
E
(PINB)
P
N
P
P
+
N
P
+
P
N
Parasitic element
GND
P
+
P
N
B
+
N
P substrate
(PINA)
E
GND
Parasitic element
GND
Parasitic element or transistor
Fig-37
C
Fig-38
Parasitic element or transistor
Fig-39
Fig-40
9）GND wiring pattern
When both a small-signal GND and high current GND are present, single-point grounding (at the set standard point) is
recommended, in order to separate the small-signal and high current patterns, and to be sure voltage changes stemming
from the wiring resistance and high current do not cause any voltage change in the small-signal GND. In the same way, care
must be taken to avoid wiring pattern fluctuations in any connected external component GND.
14/29
10）In some application and process testing, Vcc and pin potential may be reversed, possibly causing internal circuit or element
damage. For example, when the external capacitor is charged, the electric charge can cause a Vcc short circuit to the GND.
In order to avoid these problems, limiting output pin capacitance to 100μF or less and inserting a Vcc series countercurrent
prevention diode or bypass diode between the various pins and the Vcc is recommended.
Bypass diode
Countercurrent prevention diode
Vcc
Pin
Fig-41
11）Thermal shutdown (TSD)
This IC is provided with a built-in thermal shutdown (TSD) circuit, which is designed to prevent thermal damage to or
destruction of the IC. Normal operation should be within the power dissipation parameter, but if the IC should run beyond
allowable Pd for a continued period, junction temperature (Tj) will rise, thus activating the TSD circuit, and turning all output
pins OFF. When Tj again falls below the TSD threshold, circuits are automatically restored to normal operation. Note that
the TSD circuit is only asserted beyond the absolute maximum rating. Therefore, under no circumstances should the TSD
be used in set design or for any purpose other than protecting the IC against overheating
12）The SW pin
When the SW pin is connected in an application, its coil counter-electromotive force may give rise to a single electric
potential. When setting up the application, make sure that the SW pin never exceeds the absolute maximum value.
Connecting a resistor of several Ω will reduce the electric potential. (See Fig. 43)
Vcc
BOOT
OUTH
R
SW
Vo
Fig-42
OUTL
DGND
13）Dropout operation
When input voltage falls below approximately output voltage / 0.9 (varying depending on operating frequency) the ON
interval on the OUTL side MOS is lost, making boost applications and wrap operation impossible. If a small differential
between input and output voltage is envisioned for a prospective application, connect the load such that the SW voltage
drops to the GND level. Managing this load requires discharging the SW line capacitance (SW pin capacitance: approx.
500pF; OUTL side MOS D-S capacitance; Schottky capacitance). Supported loads can be calculated using the equation
below.
ILOAD =
Output voltage × SW line capacitance
25n
Note that SW line capacitance is lower with smaller loads, and more stable operation is attained when low voltage bias
circuits are configured as in the example below (Fig. 44). However, the degree to which line capacitance is reduced or
operational stability is attained will vary depending on the board layout and components. Therefore, be certain to confirm
the effectiveness of these design factors in actual operation before entering mass production.
Vcc
VREG
OUT
Vo
SW
OUT
Fig-43
15/29
Vcc
●Power dissipation vs. temperature characteristics
PD(W)
HQFN36V
1.2
0.8
POWER DISSIPATION：Pd [W]
POWER DISSIPATION：Pd [W]
VQFP48C
PD(W)
1.0
②0.875W
0.6
0.4
①0.56W
0.2
1.0
②1.1W
0.8
0.6
①0.75W
0.4
0.2
0.0
0.0
0
25
50
75
0
100 125 150
25
50
75
100 125 150
AMBIENT TEMPERATORE：Ta [℃]
AMBIENT TEMPERATORE：Ta [℃]
①：Stand-alone IC
①：Stand-alone IC
②：Mounted on Rohm standard board
②：Mounted on Rohm standard board
（70mm x 70mm x 1.6mm glass-epoxy board ）
（70mm×70mm×1.6mm glass-epoxy board）
●Part order number
B
D
ROHM part
code
9
0
1
1
K
Type/No.
V
E
－
Package type
KV ： VQFP48C
EKN ： HQFN36V
2
Tape and Reel Information
E2 : Embossed carrier tape
HQFN36V
<Dimension>
<Tape and Reel information>
Embossed carrier tape(with dry pack)
Tape
Quantity
Direction
of feed
2500pcs
E2
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
1234
1234
1pin
1234
1234
1234
1234
Reel
（Unit:mm）
Direction of feed
※When you order , please order in times the amount of package quantity.
VQFP48C
< Packing information >
<Dimension>
Tape
Embossed carrier tape
Quantity
1500pcs
Direction
of feed
E2
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
Reel
（Unit:mm)
1Pin
Direction of feed
※When you order , please order in times the amount of package quantity.
16/29
■BD9775FV (1channel synchronous rectification configuration)
●Description
BD9775FV is Switching Controller with synchronous rectification(BD9775FV is 1channel synchronous rectification) and wide
input range. It can contribute to ecological design(lower power consumption) for most of electronic equipments.
●Features (BD9775FV)
1) 2channel Step-Down DC/DC FET driver
2) Synchronous rectification for channel 2
3) Able to synchronize to an external clock signal
4) Over Current Protection (OCP) by monitoring VDS of P channel FET
5) Short Circuit Protection (SCP) by delay time and latch method
6) Under Voltage Lock Out (UVLO)
7) Thermal Shut Down (TSD)
8) Package : SSOP-B28
●Applications (BD9775FV)
Car navigation system, Car Audio, Display, Flat TV
●Absolute maximum ratings (Ta=25℃)(BD9775FV)
Parameter
Symbol
Limits
Units
Supply Voltage (VCC to GND)
Vcc
36
V
VREF to GND Voltage
Vref
7
V
VREGA to GND Voltage
Vrega
7
V
VREGB to VCC Voltage
Vregb
7
V
OUT1, OUT2H to VCC Voltage
Vouth
7
V
OUT2L to GND Voltage
Voutl
7
V
Power Dissipation
Pd
640(*1)
mW
Operating Temperature Range
Topr
-40 to +85
℃
Storage Temperature Range
Tstg
-55 to +125
℃
Junction Temperature
Tjmax
+125
℃
(*1) Without heat sink, reduce to 6.4mW when Ta=25℃ or above
Pd is 850mW mounted on 70x70x1.6mm, and reduce to 8.5mW/℃ above 25℃.
17/29
●Recommended operating conditions（Ta=-25 to +75℃）(BD9775FV)
Parameter
Limits
Symbol
Units
MIN
TYP
MAX
Supply Voltage
VCC
6.0
-
30.0
V
Oscillating Frequency
ｆosc
30
100
300
KHz
Timing Resistance
RT
10
27
56
KΩ
Timing Capacitance
CT
100
470
4700
pF
●Electrical characteristics （Ta=25℃，VCC=13.2V, fosc=100kHz, CTL1=3V, CTL2=3V）(BD9775FV)
Parameter
Limits
Symbol
Condition
Unit
Min.
Typ.
Max.
Iccst
－
－
5
μA
CTL1,CTL2=0V
Icc
2.5
4.2
7
mA
FB1,FB2=0V
VREF Output Voltage
Vref
2.97
3.00
3.03
V
Line Regulation
DVli
－
－
10
mV
Vcc=7 to 18V,Io=-1mA
Load Regulation
DVlo
－
－
10
mV
Io=-0.1mA to -2mA
Ios
-60
-22
-5
mA
VREGA Output Voltage
Vrega
4.5
5.0
5.5
V
Switching with COUT=5000pF
VREGB Output Voltage
Vregb
VCC-5.5
VCC-5.0
VCC-4.5
V
Switching with COUT=5000pF
VREGB Dropout Voltage
Vdregb
－
1.8
2.2
V
VREGB to GND Voltage
Oscillating Frequency
fosc
90
100
110
kHz
Frequency Tolerance
Dfosc
－
－
2
%
Vcc=7 to 18V
FIN=120kHz
【Whole Device】
Stand-by Current
Circuit Current
【Reference Voltage】
Short Output Current
Io=-1mA
【Internal Voltage Regulator】
【Oscillator】
RT=27kΩ,CT=470pF
【Synchronized Frequency】
Synchronized Frequency
ｆosc2
－
120
－
kHz
FIN Threshold Voltage
Vthfin
1.2
1.4
1.6
V
IFIN
-1
－
1
μA
Threshold Voltage
Vthea
0.98
1.00
1.02
V
INV Input Bias Current
Ibias
-1
－
1
μA
Voltage Gain
Av
－
70
－
dB
Band Width
Bw
－
2.0
－
MHz
Maximum Output Voltage
Vfbh
2.2
2.4
2.6
V
INV=0.5V
Minimum Output Voltage
Vfbl
－
－
0.1
V
INV=1.5V
Output Sink Current
Isink
0.5
2
5.2
mA
FB1,2 Terminal
Isource1
-170
-110
-70
μA
FB1 Terminal
Isource2
-200
-130
-85
μA
FB2 Terminal
FIN Input Current
VFIN=1.4V
【Error Amplifier】
Output Source Current
18/29
DC
Av=0dB
Parameter
Limits
Symbol
Unit
Condition
Min.
Typ.
Max.
Vth0
0.88
0.98
1.08
V
FB Voltage
Vth100
1.88
1.98
2.08
V
FB Voltage
Idtc
-1
－
1
μA
Isink
20
36
58
mA
VDS=0.4V
Isource
-510
-320
-180
mA
VDS=0.4V
RonN
7.0
11.0
17.8
Ω
OUT1,2H,2L : L
RonP
0.7
1.4
2.2
Ω
OUT1,2H,2L : H
Rise Time
Tr
－
20
－
nsec
Switching with COUT=5000pF
Fall Time
Tf
－
100
－
nsec
Switching with COUT=5000pF
ΔDuty
42
45
48
%
Vsync
1.45
1.55
1.65
V
Vths
VCC-0.24
VCC-0.21
VCC-0.18
V
IVSH
-1
－
1
μA
VS1,VS2=PBU
IVSL
-1
－
1
μA
VS1,VS2=0V
Icl
9
10
11
μA
Threshold Voltage
Vctl
1.0
1.5
2.0
V
CL Input Current
Ictl
6
15
30
μA
【PWM Comparator】
Threshold Voltage at 0%
Threshold Voltage
at 100%
DTC Input Bias Current
【FET Driver】
Sink Current
Source Current
ON Resistance
Driver’s Duty Cycle of
Synchronous
Rectification
SYNC Terminal Voltage
RSYNC=30KΩ,
50% of main driver’s duty cycle
Rsync=30KΩ,FB=1.5V
【Over Current Protection (OCP)】
VS Threshold Voltage
VS Input Current
CL Input Current
RCL=21kΩ, the output tern off after
detected 8 cycle
【Stand-by】
CTL1,CTL2=3V
【Short Circuit Protection （SCP）】
Timer Start Voltage
Vtime
0.6
0.7
0.8
V
INV Voltage
Threshold Voltage
Vthscp
1.92
2.00
2.08
V
SCP Voltage
Stand-by Voltage
Vstscp
－
10
100
mV
SCP Voltage
Source current
Isoscp
-4.0
-2.5
-1.5
μA
SCP=1.0V
Vuvlo
5.6
5.7
5.8
V
DVuvlo
0.05
0.1
0.15
V
【Under Voltage Lock Out （UVLO）】
Threshold Voltage
Hysteresis
Voltage Range
19/29
Vcc sweep down
● Pin Description
(BD9775FV)
●PinNo/PinName (BD9775FV)
1
FB1
VS1 28
2
INV1
CL1 27
3
RT
PVCC1 26
4
CT
OUT1 25
5
Fin
VREGB 24
6
GND
OUT2H 23
7
VREF
PVCC2 22
8
DTC1
CL2
21
9
DTC2
VS2
20
10
INV2
SCP
19
11
FB2
VREGA 18
12
CTL1
OUT2L 17
13
CTL2
14
VCC
Pin
No.
Pin
Name
1
FB1
Error amplifier output pin（Channel 1）
2
INV1
Error amplifier negative input pin（Channel 1）
3
RT
Oscillator frequency adjustment pin
connected resistor
4
CT
Oscillator frequency adjustment pin
connected capacitor
5
FIN
Oscillator synchronization pulse signal input pin
6
GND
7
VREF
Reference voltage output pin
8
DTC1
Maximum duty and soft start adjustment
pin（Channel 1）
PGND 16
9
DTC2
Maximum duty and soft start adjustment
pin（Channel 2）
SYNC 15
10
INV2
Error amplifier negative input pin（Channel 2）
11
FB2
Error amplifier output pin（Channel 2）
12
CTL1
Enable/stand-by control input（Channel 1）
13
CTL2
Enable/stand-by control input（Channel 2）
14
VCC
Main power supply pin
15
SYNC
Synchronous rectification timing adjustable pin
16
PGND
Power ground (connected low-side gate driver
and digital ground)
17
OUT2L
Low-side ( synchronous rectifier ) gate driver
output pin（Channel 2）
18
VREGA
Connected capacitor for internal regulator
19
SCP
Delay time of short circuit protection adjustment
pin connected capacitor
20
VS2
Over current detection voltage monitor pin
（connected FET drain, Channel 2）
21
CL2
Over current detection voltage adjustment pin
connected capacitor and resistor（Channel 2）
22
PVCC2
High-side gate driver power supply
input（Channel 2）
23
OUT2H
High-side gate driver output pin（Channel 2）
24
VREGB
Connected capacitor for internal regulator
25
OUT1
26
PVCC1
27
CL1
Over current detection voltage adjustment pin
connected capacitor and resistor（Channel 1）
28
VS1
Over current detection voltage monitor pin
（connected FET drain, Channel 1）
●Block Diagram (BD9775FV)
Fig.1
Description
Low-noise ground
High-side gate driver output pin（Channel 1）
High-side gate driver power supply
input（Channel 1）
●FUNCTION EXPLANATION (BD9775FV)
1.DC/DC Converter
・Reference Voltage
Stable voltage of compensated temperature, is generated from the power supply voltage (VCC). The reference voltage is 3.0V,
the accuracy is ±1％. Place a capacitor with low ESR (several decades mΩ) between VREF and GND.
・Internal Regulator A （VREGA）
5V is generated the power supply voltage. The voltage is for the driver of the synchronous rectification’s MOSFET. Place a
capacitor with low ESR (several decades mΩ) between VREGA and PGND.
20/29
・Internal regulator B （VREGB）
(VCC-5V) is generated from the power supply voltage. The voltage is for the driver of the main MOSFET switch.
Place a capacitor with low ESR (several decades mΩ) between VREGB and PVCC.
・Oscillator
Placing a resistor and a capacitor to RT and CT, respectively, generates two triangle waves for both cannels, and each wave
is opposite phase. The waves are input to the PWM comparators for CH1 and CH2. Also, the oscillating frequency can be
slightly adjusted (less than 20%) by putting external clock pulse into Fin pin, which is higher frequency than the fixed one.
・Error Amplifier
It amplifies the difference, between the establish output voltage and the actual output one detected at INV. And amplified
voltage comes out from FB. The comparing voltage is 1.0V and the accuracy is ±2%. The phase can be compensated
externally by placing a resistor and a capacitor between INV and FB.
・PWM Comparator
It converts the output voltage from error amplifier into PWM waveform, then output to MOSFET driver.
・MOSFET Driver
The main drivers (OUT1, OUT2H) are for P-channel MOSFETs, and the driver (OUT2L) for synchronous rectification is for
N-channel MOSFET. The values of output voltage are clamp to VREGB, VREGA, respectively. All drivers’ output
configurations are push-pull type. In addition, the output current capability is 36mA for the sink current and 320mA
(Vds=0.4V) for the source current.
2.Channel Control
Each output can be individually turned on or off with CTL1 and CTL2. When the CTL is “H” (more than 1.5V), it becomes
turned on.
3.Protection
・Over Current Protection（OCP）
When detected over current (detecting drop voltage of the main MOSFET’s ON resistance), the MOSFET switch becomes
turned off, and the energy on DTC pin is discharged. After discharged, the output restarts automatically. The level of the
OCP detection threshold can be set by the resistance, which is connected between VCC and CL.
・Short Circuit Protection（SCP）
When either output goes down and the voltage on INV pin gets lower than 0.7V, a capacitor placed on SCP is started to
charge.
When the SCP pin becomes more than 2.0V, the main MOSFET switches of both outputs are turned off; then, the outputs are
latched. While they are latched, the IC can be reset by restarting VCC or CTL, or discharging SCP.
・Under Voltage Lock Out（UVLO）
Due to avoiding malfunctions when the IC is started up or the power supply voltage is rapidly disconnected, the main
MOSFET switches become off and DTC is discharged when the supply voltage is less than 5.7V. Also, when the output is
latched because of SCP function, the latch becomes reset. Due to preventing malfunctions in the case the power supply
voltage fluctuate at near UVLO threshold, there is 0.1V hysteresis between the detection and reset voltage of UVLO
threshold.
・Thermal Shut Down（TSD）
Due to preventing breakdown of the IC by heating up, the main MOSFET switches become off and DTC pin is discharged by
detecting over temperature of the chip. Due to preventing malfunctions in the case temperature fluctuate at near TSD
threshold, there is hysteresis between TSD on and off.
21/29
●SETTING UP INFOMATION (BD9775FV)
1)Simultaneously OFF Duty of MOSFETs for Synchronous Rectification
The simultaneously OFF duty of both main MOSFET switch and synchronous rectification MOSFET is determined by
resistance (Rsync) between SYNC and GND. See Fig. 4.
In Synchronous Rectification, insert RFB2-GND (RFB2-GND≒3×Rsync) between FB2 and GND, because it is possible to
reduce overshoot(sea fig.2). RFB2-GND decide following formula.
40
T=-40℃
35
fosc=100kHz
ΔDuty (%)
30
T= 25℃
Δduty=(t1+t2)/t×100 (%)
t
T=105℃
25
t1
t2
20
OUT2H
15
OUT2L
10
5
0
0
20
40
60
80
100
Rsync (kΩ)
Fig.2
・Resistance at FB2-GND setup condition
Threshold Voltage at100%
Vsync
< RFB2-GND < 3xRsync(MIN)
-Output Source Current at FB2
3×Rsync(MAX)
2.08
0.4908
Rsync(MAX)
< RFB2-GND < 3xRsync(MIN)
+80.7x10
※Rsync(MAX)…MAX dispersion range at Rsync
-6
Rsync(MIN)…MIN dispersion range at Rsync
FB2
SYNC
RFB2-GND
Rsync
Short SYNC to VREF if the synchronous rectification function is not needed.
VREF
SYNC
Without Synchronous Rectification（Don’t insert RFB2-GND）
22/29
2) Oscillator Synchronization by External Pulse Signal
At the operation the oscillator is externally synchronized, input the synchronization signal into Fin in addition to connect a
resistor and a capacitor at RT and CT, respectively.
Input the external clock pulse on Fin, which is higher frequency than the fixed one. However, the frequency variation
should be less than 20%.
Also, the duty cycle of the pulse should be set from 10% to 90%.
Fin
： Fixed with RT and CT
CT
： Synchronized
CT Waveform during Synchronized with External Pulse
Short Fin to GND if the function of external synchronization is not needed.
Fin
Without Synchronization Signal
3)Setting the Over Current Threshold Level
The OCP detection level（Iocp）is determined by the ON resistance (RON) of the main MOSFET switch and the resistance
(Rcl) which is placed between CL and VCC.
Iocp ＝
Rcl
RON
×10-5
[A]
（typ.）
To prevent a malfunction caused by noise, place a capacitor（Ccl） parallel to Rcl.
If OCP function is not needed, short VS to VCC, and short CL to GND.
Rcl
VCC
CL
CL
Ccl
VCC
VS
VS
To Main MOSFET Drain
With OCP
Without OCP
CL, VS Pin Connection
23/29
4)Setting the Time for Short Circuit Protection
The time (tscp) from output short to latch activation is determined by the capacitor, Cscp, connected SCP pin.
5
tscp＝7.96×10 ×Cscp
[sec]
（typ.）
Short SCP to GND if SCP function is not being used.
SCP
Without SCP
5)Single Channel Operation
This device can be used as a single output.
The connection is as follows;
DTC,FB,CTL,CL
Short to GND
VS,PVCC
Short to VCC
INV
Short to VREF
DTC
FB
CTL
CL
VCC
VS
PVCC
VREF
INV
Single Channel Operation
6)Setting the Oscillating Frequency
The oscillating frequency can be set by selecting the timing resistor (RRT)and the timing capacitor (CCT).
Ocsillating Frequency vs. Timing Capacitance (RRT)
Ocsillating Frequency vs. Timing Capacitance (CCT)
1000
Oscillating Frequency (kHz)
Oscillating Frequency (kHz)
1000
CCT=100pF
CCT=470pF
100
CCT=1000pF
10
RRT =5.1kΩ
100
RRT =27kΩ
RRT =100kΩ
10
10
100
1000
100
Timing Resistance (kΩ)
1000
Timing Capacitance(pF)
Fig.3
Fig.4
24/29
10000
●Timing Chart (BD9775FV)
・Output ON/OFF, Minimum Input（UVLO）
6.0V
UVLO is activated at 5.7V
VCC
UVLO is inactivated
at 5.8V
CTL1
1.0V
DTC1
Vout1
CTL2
1.0V
DTC2
Vout2
Stand-by
Soft start
Fig.5
・Over Current Protection, Short Circuit Protection, Thermal Shut Down
CTL1,2
Activate SCP
Reset the latch by restarting CTL
2.0V
SCP
DTC1,2
1.0V
0.7×fixed output voltage
Activate TSD
Inactivate TSD
Vout1,2
Half short of output
OCP detection level
Iout1,2
Inactivate half-short
OCP is activated by detecting 8 consecutive cycles
Fig.6
●I/O EQUIVALENT CIRCUIT (BD9775FV)
FB1(1)
VREF
VREF
FB2(11)
VCC
VCC
VREGA
VREGA
VREF
VREF
VREGA
VREGA
RT(3)
VCC
VCC
VREF
VREF
VCC
VCC
FB1
FB1
RT
RT
INV1(2),INV2(10)
VREF
VREF
CT(4)
VREF
VCC
VCC
VREF
FIN(5)
VCC
VCC
VREF
VREG
VCC
VCC
INV1，2
INV1,2
FIN
FIN
Fig.7
Fig.8
25/29
DTC1(8),DTC2(9)
VREGA
VREGA
VREF
VREF
CTL1(12),CTL2(13)
VREGA
VREGA
VCC
VCC
SYNC(15)
VCC
VCC
DTC1,2
DTC1,2
VREF
VREF
VCC
VCC
CTL1,2
CTL1，2
SYNC
SYNC
SCP(19)
OUT2L(17),VREGA(18)
VCC
VREF
VREF
VREF(7)
VCC
VCC
VCC
VCC
VC
VREGA
VREGA
～
～
VREF
VREF
～
～
OUT2L
OUT2L
SCP
SCP
PVCC1(26),PVCC2(22)
OUT1(25),OUT2H(23),VREGB(24)
VS1(28),VS2(20),CL1(27),CL2(21)
VCC
VCC
VCC
VCC
PVCC1，2
PVCC1,2
OUTH1，2H
OUT1,2H
CL1，2
CL1,2
VREGB
VREGB
VS1，2
VS1,2
Fig.8
●Operation Notes (BD9775FV)
1) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC deterioration
or damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered.
A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings
may be exceeded is anticipated.
2) GND potential
Ensure a minimum GND pin potential in all operating conditions. In addition, ensure that no pins other than the GND pin carry a voltage lower
than or equal to the GND pin, including during actual transient phenomena.
3) Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
4) Inter-pin shorts and mounting errors
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC.
Shorts between output pins or between output pins and the power supply and GND pin caused by the presence of a foreign object may result in
damage to the IC.
5) Operation in a strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.
6) Thermal shutdown circuit (TSD circuit)
This IC incorporates a built-in thermal shutdown circuit (TSD circuit). The TSD circuit is designed only to shut the IC off to prevent runaway
thermal operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of the thermal
shutdown circuit is assumed.
7) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge
capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting
or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process.
8) Common impedance
Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize ripple as much as possible
(by making wiring as short and thick as possible or rejecting ripple by incorporating inductance and capacitance).
26/29
9) Applications with modes that reverse VCC and pin potentials may cause
Bypass diode
damage to internal IC circuits.
For example, such damage might occur when VCC is shorted with the
Countercurrent
prevention diode
GND pin while an external capacitor is charged.
It is recommended to insert a diode for preventing back current flow
Vcc
in series with VCC or bypass diodes between VCC and each pin.
Pin
Fig.9
10) Timing resistor and capacitor
Timing resistor(capacitor) connected between RT(CT) and GND, has to be placed near RT(CT) terminal 3pin(4pin). And pattern has to be short
enough.
VCC
VREF
11) The Dead time input voltage has to be set more than 1.1V.
Also, the resistance between DTC and VREF is used more than 30kΩ to work OCP function reliably.
12) The energy on DTC1（8pin）and DTC2（9pin）is discharged when CTL1（12pin）and CTL2（13pin）are OFF, respectively, or VCC（14pin）
is OFF (UVLO activation). However, it is considerable to occur overshoot when CTL and VCC are turned on with remaining more than 1V on
the DTC.
GATE
13) If Gate capacitance of P-channel MOSFET or resistance placed on
Gate is large, and the time from beginning of Gate switching to the end of Drain’s (tsw),
is long, it may not start up due to the OCP malfunction.
To avoid it, select MOSFET or adjust resistance as tsw becomes less than 270nsec.
tsw
DRAIN
Fig.10
14) IC pin input
This monolithic IC contains P+ isolation and PCB layers between adjacent elements in order to keep them isolated.
P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety
of parasitic elements. For example, when a resistor and transistor are connected to pins as shown in following chart,
○the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN).
○Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other adjacent
elements to operate as a parasitic NPN transistor.
The formation of parasitic elements as a result of the relationships of the potentials of different pins is an
inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit
operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is
not used in a way that will trigger the operation of parasitic elements, such as by the application of voltages lower
than the GND (PCB) voltage to input and output pins.
Resistor
Transistor（NPN）
(PINB)
(PINA)
B
C
E
(PINB)
P
P
+
N
N
P
+
P
P
+
Parasitic element
P
P
N
N
B
+
N
P substrate
GND
C
E
GND
Parasitic element
GND
Parasitic element or transistor
Parasitic element or transistor
Fig.11
pd(W)
1.0
②
0.85W
①
0.64W
POWER DISSIPATION ： pd(W）
0.8
0.6
0.4
① 0.587W
0.2
0
①With no heat sink
②Copper laminate area 70 mm×70mm
0
25
50
75
100
AMBIENT TEMPERATURE
125
：
(PINA)
150
Ta(℃)
Fig.12
27/29
●Part order number
B
D
ROHM Part
Code
9
7
7
5
F
Type/No.
V
-
Package type
FV : SSOP-B28
E
2
Tape and Reel Information
E2 : Embossed carrier tape
SSOP-B28
<Dimension>
<Tape and Reel information>
Embossed carrier tape
Tape
Quantity
2000pcs
Direction
of feed
E2
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
1234
1234
1234
1pin
123
1234
123
123
1234
(Unit:mm)
Reel
Direction of feed
※When you order , please order in times the amount of package quantity.
28/29
Catalog No.08T672A '08.9 ROHM ©
Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM
CO.,LTD.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account
when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples
of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to
use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment
or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as
derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your
use of any Product outside of the prescribed scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system
which requires an extremely high level of reliability the failure or malfunction of which may result in a direct
threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment,
aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear
no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under
the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact your nearest sales office.
ROHM Customer Support System
www.rohm.com
Copyright © 2009 ROHM CO.,LTD.
THE AMERICAS / EUROPE / ASIA / JAPAN
Contact us : webmaster @ rohm.co. jp
21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan
TEL : +81-75-311-2121
FAX : +81-75-315-0172
Appendix-Rev4.0