Fairchild FAN5069EMTCX Pwm and ldo controller combo Datasheet

FAN5069
PWM and LDO Controller Combo
Features
Description
■
The FAN5069 combines a high-efficiency Pulse-WidthModulated (PWM) controller and an LDO (Low DropOut)
linear regulator controller. Synchronous rectification provides high efficiency over a wide range of load currents.
Efficiency is further enhanced by using the low-side
MOSFET’s RDS(ON) to sense current.
■
■
■
■
■
■
■
■
■
■
■
General Purpose PWM Regulator and LDO Controller
Input Voltage Range: 3V to 24V
Output Voltage Range: 0.8V to 15V
– VCC
– 5V
Shunt Regulator for 12V Operation
Support for Ceramic Cap on PWM Output
Programmable Current Limit for PWM Output
Programmable Switching Frequency (200KHz to
600KHz)
RDS(ON) Current Sensing
Internal Synchronous Boot Diode
Soft-Start for both PWM and LDO
Multi-Fault Protection with Optional Auto-restart
16-pin TSSOP Package
Both the linear and PWM regulator soft-start are controlled by a single external capacitor, to limit in-rush current from the supply when the regulators are first
enabled. Current limit for PWM is also programmable.
The PWM regulator employs a summing-current-mode
control with external compensation to achieve fast load
transient response and provide design optimization.
FAN5069 is offered in both industrial temperature grade
(-40°C to +85°C) as well as commercial temperature
grade (-10°C to +85°C).
Applications
■
■
■
■
PC/Server Motherboard Peripherals
– VCC_MCH (1.5V), VDDQ (1.5V) and
VTT_GTL (1.25V)
Power Supply for
– FPGA, DSP, Embedded Controllers, Graphic Card
Processor, and Communication Processors
Industrial Power Supplies
High-Power DC-to-DC Converters
Ordering Information
Part Number
Operating Temp. Range Pb-Free
Package
Packing Method
Qty./Reel
FAN5069MTCX
-10°C to +85°C
Yes
16-Lead TSSOP
Tape and Reel
2500
FAN5069EMTCX
-40°C to +85°C
Yes
16-Lead TSSOP
Tape and Reel
2500
Note: Contact Fairchild sales for availability of other package options.
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
September 2006
RVCC
+12V
3 TO 24V
VCC
15
FAN5069
C9
+5V
EN
SS
C3
R4
ILIM
R5
R(T)
AGND
11
7
3
LDO OUT
R7
C8
FBLDO
BOOT
C5
Q1
C4
10
PWM
2
9
1
L1
SW
PWM OUT
Q2
13
16
C7
HDRV
8
12
GLDO
R8
R(RAMP)
4
PWM OUT
Q3
14
6
ULDO
CONTROL
C6
LDRV
R1
PGND
FB
C2
5
COMP
C1
R3
R2
R6
Figure 1. Typical Application Diagram
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
2
FAN5069 PWM and LDO Controller Combo
Typical Application
FBLDO
1
16
GLDO
R(T )
2
15
VCC
ILIM
3
14
R(RAMP)
SS
4
13
LDRV
COMP
5
12
PGND
FB
6
11
BOOT
EN
7
10
HDRV
AGND
8
9
FAN5069
SW
Figure 2. Pin Assignment
Pin Description
Pin #
Name
Description
1
FBLDO
2
R(T)
Oscillator Set Resistor. This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased.
3
ILIM
Current Limit. A resistor from this pin to GND sets the current limit.
4
SS
5
COMP
6
FB
Feedback. This pin is the inverting input of the internal error amplifier. Use this pin, in combination with the COMP pin, to compensate the feedback loop of the converter.
7
EN
Enable. Enables operation when pulled to logic high. Toggling EN resets the regulator after a
latched fault condition. This is a CMOS input whose state is indeterminate if left open and
needs to be properly biased at all times.
8
AGND
Analog Ground. The signal ground for IC. All internal control voltages are referred to this pin.
Tie this pin to the ground island/plane through the lowest impedance connection available.
9
SW
Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect
to source of high-side MOSFET and drain of low-side MOSFET.
10
HDRV
High-Side Gate Drive Output. Connect to the gate of the high-side power MOSFETs. This
pin is also monitored by the adaptive shoot-through protection circuitry to determine when the
high-side MOSFET is turned off.
11
BOOT
Bootstrap Supply Input. Provides a boosted voltage to the high-side MOSFET driver.
Connect to bootstrap capacitor as shown in Figure 1.
12
PGND
Power Ground. The return for the low-side MOSFET driver. Connect to the source of the lowside MOSFET.
13
LDRV
Low-Side Gate Drive Output. Connect to the gate of the low-side power MOSFETs. This pin
is also monitored by the adaptive shoot-through protection circuitry to determine when the
lower MOSFET is turned off.
14
R(RAMP)
Ramp Resistor. A resistor from this pin to VIN sets the ramp amplitude and provides voltage
feed-forward.
15
VCC
VCC. Provides bias power to the IC and the drive voltage for LDRV. Bypass with a ceramic
capacitor as close to this pin as possible. This pin has a shunt regulator which draws current
when the input voltage is above 5.6V.
16
GLDO
LDO Feedback. This node is regulated to VREF.
Soft-Start. A capacitor from this pin to GND programs the slew rate of the converter and the
LDO during initialization. It also sets the time by which the converter delays when restarting
after a fault occurs. SS has to reach 1.2V before fault shutdown feature is enabled. The LDO
is enabled when SS reaches 2.2V.
COMP. The output of the error amplifier drives this pin.
Gate Drive for the LDO. Turned off (low) until SS is greater than 2.2V.
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
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FAN5069 PWM and LDO Controller Combo
Pin Assignment
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The
device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are
not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines the conditions for actual device operation. (1)
Parameter
Min.
Max.
Unit
VCC to PGND
6.0
V
BOOT to PGND
33.0
V
V
SW to PGND
Continuous
-0.5
33.0
Transient (t < 50nS, F < 500kHz)
-3.0
33.0
V
6.0
V
HDRV (VBOOT- – VSW)
LDRV
-0.5
6.0
V
All Other Pins
-0.3
VCC + 0.3
V
150
mA
Maximum Shunt Current for VCC
Electrostatic Discharge Protection (ESD)
Level(2)
HBM
3.5
CDM
1.8
kV
Notes:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at these or any conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are referenced to AGND.
2.
Using Mil Std. 883E, method 3015.7(Human Body Model) and EIA/JESD22C101-A (Charge Device Model).
Thermal Information
Symbol
Max.
Unit
150
°C
Lead Soldering Temperature, 10 Seconds
300
°C
Vapor Phase, 60 Seconds
215
°C
Infrared, 15 Seconds
220
°C
PD
Power Dissipation, TA = 25°C
715
mW
θJC
Thermal Resistance, Junction-to-Case
TSTG
TL
θJA
Parameter
Min.
Storage Temperature
Typ.
-65
Thermal Resistance, Junction-to-Ambient
(3)
37
°C/W
100
°C/W
Notes:
3. Junction-to-ambient thermal resistance, θJA, is a strong function of PCB material, board thickness, thickness and
number of copper planes, number of vias used, diameter of vias used, available copper surface, and attached heat
sink characteristics.
Recommended Operating Conditions
Symbol
VCC
Parameter
Supply Voltage
TA
Ambient Temperature
TJ
Junction Temperature
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
Conditions
Min.
Typ.
Max.
Unit
VCC to GND
4.5
5.0
5.5
V
Commercial
-10
85
°C
Industrial
-40
85
°C
125
°C
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FAN5069 PWM and LDO Controller Combo
Absolute Maximum Ratings
Unless otherwise noted, VCC = 5V, TA = 25°C, using circuit in Figure 1.
The ‘•’ denotes that the specifications apply to the full ambient operating temperature range. See Notes 4 and 5.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
2.6
3.2
3.8
mA
200
400
μA
10
15
mA
5.9
V
Supply Current
IVCC
VCC Current (Quiescent)
HDRV, LDRV Open
•
•
IVCC(SD)
VCC Current (Shutdown)
EN = 0V, VCC = 5.5V
IVCC(OP)
VCC Current (Operating)
EN = 5V, VCC = 5.0V,
QFET = 20nC, FSW = 200kHz
VSHUNT
VCC Voltage(6)
Sinking 1mA to 100mA at VCC
Pin
5.5
Under-Voltage Lockout (UVLO)
UVLO(H) Rising VCC UVLO Threshold
•
4.00
4.25
4.50
V
UVLO(L) Falling VCC UVLO Threshold
VCC UVLO Threshold
Hysteresis
•
3.60
3.75
4.00
V
0.50
V
Current
10
μA
VLDOSTART LDO Start Threshold
2.2
V
1.2
V
Soft-Start
ISS
VSSOK
PWM Protection Enable
Threshold
Oscillator
FOSC
Frequency
R(T) = 56KΩ ± 1%
240
300
360
KHz
R(T) = Open
160
200
240
KHz
600
KHz
Frequency Range
ΔVRAMP
160
Ramp Amplitude
(Peak-to-Peak)
R(RAMP) = 330KΩ
0.4
V
Minimum ON Time
F = 200kHz
200
nS.
Reference
VREF
Reference Voltage
(Measured at FB Pin)
TA = 0°C to 70°C
•
790
800
810
mV
TA = -40°C to 85°C
•
788
800
812
mV
Current Amplifier Reference
(at SW node)
160
mV
80
dB
Error Amplifier
DC Gain
GBWP
S/R
IFB
Gain-BW Product
Slew Rate
10pF across COMP to GND
Output Voltage Swing
No Load
•
FB Pin Source Current
25
MHz
8
V/μS.
0.5
4.0
V
μA
1
Gate Drive
RHUP
HDRV Pull-up Resistor
Sourcing
•
1.8
3.0
Ω
RHDN
HDRV Pull-down Resistor
Sinking
•
1.8
3.0
Ω
RLUP
LDRV Pull-up Resistor
Sourcing
•
1.8
3.0
Ω
RLDN
LDRV Pull-down Resistor
Sinking
•
1.2
2.0
Ω
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
5
FAN5069 PWM and LDO Controller Combo
Electrical Characteristics
Unless otherwise noted, VCC = 5V, TA = 25°C, using circuit in Figure 1.
The ‘•’ denotes that the specifications apply to the full ambient operating temperature range. See Notes 4 and 5.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
9
10
11
μA
Protection/Disable
ILIM
ILIMIT Source Current
ISWPD
SW Pull-down Current
SW = 1V, EN = 0V
VUV
Under-Voltage Threshold
As % of set point; 2μS noise filter
•
65
75
2
80
mA
%
VOV
Over-Voltage Threshold
As % of set point; 2μS noise filter
•
110
115
120
%
TSD
Thermal Shutdown
160
Enable Threshold Voltage
Enable Condition
•
Enable Threshold Voltage
Disable Condition
•
Enable Source Current
VCC = 5V
°C
2.0
V
0.8
V
μA
50
(7)
LDO
VLDOREF
Reference Voltage (mea- TA = 0°C to 70°C
sured at FBLDO pin)
TA = -40°C to 85°C
Regulation
VLDO_DO Drop out Voltage
External Gate Drive
0A ≤ ILOAD ≤ 5A
•
775
800
825
mV
•
770
800
830
mV
•
1.17
1.2
1.23
V
0.3
V
ILOAD ≤ 5A and RDS-ON < 50mΩ
VCC = 4.75V
•
4.5
V
VCC = 5.6V
•
5.3
V
Gate Drive Source Current
1.2
mA
Gate Drive Sink Current
400
μA
Notes:
4. All limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality
control.
5.
AC specifications guaranteed by design/characterization (not production tested).
6.
For a case when VCC is higher than the typical 5V VCC; voltage observed at VCC pin when the internal shunt
regulator is sinking current to keep voltage on VCC pin constant.
7.
Test Conditions: VLDO_IN = 1.5V and VLDO_OUT = 1.2V
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
6
FAN5069 PWM and LDO Controller Combo
Electrical Characteristics (Continued)
Figure 3. Dead Time Waveform
Figure 6. PWM Load Transient (0 to 15A)
Figure 4. PWM Load Transient (0 to 5A)
Figure 7. LDO Load Transient (0 to 2A)
Figure 5. PWM Load Transient (0 to 10A)
Figure 8. LDO Load Transient (0 to 5A)
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
7
FAN5069 PWM and LDO Controller Combo
Typical Performance Characteristics
Figure 9. PWM/LDO Power Up
Figure 12. Enable ON (IPWM = 5A)
Figure 10. PWM/LDO Power Down
Figure 13. Enable OFF (IPWM = 5A)
Figure 11. Auto Restart
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
Typical Performance Characteristics (Continued)
PWM Line Regulation (VOUT = 1.5V)
IL = 0A
IL = 5A
IL = 10A
1.52
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.54
LDO Load Regulation (VOUT = 1.203V)
1.210
1.50
1.48
1.205
1.200
VIN = 8V
VIN = 12V
VIN = 15V
VIN = 20V
1.195
1.46
1.190
6
8
10
16
12
14
INPUT VOLTAGE (V)
18
0
20
Figure 14. PWM Line Regulation
4
5
Master Clock Frequency
700
IL = 0A
IL = 2A
IL = 5A
600
1.205
FREQUENCY (kHz)
OUTPUT VOLTAGE (V)
2
3
LOAD CURRENT (A)
Figure 17. LDO Load Regulation
Load Line Regulation (VOUT = 1.203V)
1.210
1
1.200
1.195
500
400
300
200
100
1.190
8
10
12
14
16
INPUT VOLTAGE (V)
18
20
0
Figure 15. LDO Line Regulation
Efficiency vs. Input Voltage
80
EFFICIENCY (%)
OUTPUT VOLTAGE (V)
400
300
100
VIN = 8V
VIN = 12V
VIN = 15V
VIN = 20V
1.505
200
RT (kΩ)
Figure 18. RT vs. Frequency
PWM Load Regulation (VOUT = 1.50V)
1.510
100
1.500
VIN = 8V
VIN = 12V
VIN = 15V
VIN = 20V
60
40
1.495
20
1.490
0
0
2
4
6
LOAD CURRENT (A)
8
10
0
Figure 16. PWM Load Regulation
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
2
6
4
LOAD CURRENT (A)
8
10
Figure 19. 1.5V PWM Efficiency
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9
FAN5069 PWM and LDO Controller Combo
Typical Performance Characteristics (Continued)
Shunt Reg
RILIM
CBOOT
Internal Vcc 5.6V Max.
Vcc
BOOT
Internal
Boot Diode
10μA
Current Limit
Comparator
ILIM
VIN
COMP
PW M
Error
Amplifier
FB
PWM
Comparator
R Q
S
Vref
Vcc
10μA
HDRV
Adaptive
Gate Drive
Circuit
LO
Vout
SW
OSC
CO
SS
VIN
RRAMP
Summing
LDRV
Σ
Ramp
Generator
R(RAMP)
EN
Current
Sense
Amplifier
PGND
Amplifier
Enable
Figure 20. Block Diagram
Detailed Operation Description
Choose a resistor such that:
FAN5069 combines a high-efficiency, fixed-frequency
PWM controller designed for single-phase synchronous
buck Point-Of-Load converters with an integrated LDO
controller to support GTL-type loads. This controller is
ideally suited to deliver low-voltage, high-current power
supplies needed in desktop computers, notebooks,
workstations, and servers. The controller comes with an
integrated boot diode which helps reduce component
cost and increase space savings. With this controller, the
input to the power supply can be varied from 3V to 24V
and the output voltage can be set to regulate at 0.8V to
15V on the switcher output. The LDO output can be configured to regulate between 0.8V to 3V and the input to
the LDO can be from 1.5V to 5V, respectively. An internal
shunt regulator at the VCC pin facilitates the controller
operation from either a 5V or 12V power source.
■
■
RVCC Selection (IC)
The selection of RVCC is dependent on:
■
■
■
■
■
Variation of the 12V supply
Gate charge of the top and bottom FETs (QFET)
Switching frequency (FSW)
Shunt regulator minimum current (1mA)
Quiescent current of the IC (IQ)
Calculate RVCC based on the minimum input voltage for
the VCC:
Vin MIN – 5.6
R VCC = ----------------------------------------------------------------------------------------–3
( I Q + 1 • 10 + Q FET • F SW • 1.2 )
VCC Bias Supply
FAN5069 can be configured to operate from 5V or 12V
for VCC. When 5V supply is used for VCC, no resistor is
required to be connected between the supply and the
VCC. When the 12V supply is used, a resistor RVCC is
connected between the 12V supply and the VCC, as
shown in Figure 1. The internal shunt regulator at the
VCC pin is capable of sinking 150mA of current to
ensure that the controller’s internal VCC is maintained at
5.6V maximum.
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
It is rated to handle the power dissipation.
Current sunk within the controller is minimized to
prevent IC temperature rise.
(EQ. 1)
For a typical example, where: VinMIN = 11.5V, IQ = 3mA,
QFET = 30nC, FSW = 300KHz, RVCC is calculated to be
398.65Ω.
PWM Section
The FAN5069’s PWM controller combines the conventional voltage mode control and current sensing through
lower MOSFET RDS_ON to generate the PWM signals.
This method of current sensing is loss-less and cost
effective. For more accurate current sense requirements,
an optional external resistor can be connected with the
bottom MOSFET in series.
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10
FAN5069 PWM and LDO Controller Combo
Block Diagram
age varies. The RRAMP also has an effect on the current
limit, as can be seen in the RLIM equation (EQ. 5). The
RRAMP value can be approximated using the following
equation:
Refer to Figure 20 for the PWM control mechanism. The
FAN5069 uses the summing mode method of control to
generate the PWM pulses. The amplified output of the
current-sense amplifier is summed with an internally
generated ramp and the combined signal is amplified
and compared with the output of the error amplifier to get
the pulse width to drive the high-side MOSFET. The
sensed current from the previous cycle is used to modulate the output of the summing block. The output of the
summing block is also compared against the voltage
threshold set by the RLIM resistor to limit the inductor current on a cycle-by-cycle basis. The controller facilitates
external compensation for enhanced flexibility.
V IN – 1.8
R RAMP = --------------------------------------------KΩ
–8
6.3 • 10 • Fosc
where FOSC is in Hz. For example, for FOSC = 300kHz
and VIN = 12V, RRAMP ≈ 540KΩ.
Gate Drive Section
The adaptive gate control logic translates the internal
PWM control signal into the MOSFET gate drive signals
and provides necessary amplification, level shifting, and
shoot-through protection. It also has functions that help
optimize the IC performance over a wide range of operating conditions. Since the MOSFET switching time can
vary dramatically from device to device and with the
input voltage, the gate control logic provides adaptive
dead time by monitoring the gate-to-source voltages of
both upper and lower MOSFETs. The lower MOSFET
drive is not turned on until the gate-to-source voltage of
the upper MOSFET has decreased to less than approximately 1V. Similarly, the upper MOSFET is not turned on
until the gate-to-source voltage of the lower MOSFET
has decreased to less than approximately 1V. This
allows a wide variety of upper and lower MOSFETs to be
used without a concern for simultaneous conduction, or
shoot-through.
Initialization
When the PWM is disabled, the SW node is connected
to GND through an internal 500Ω MOSFET to slowly discharge the output. As long as the PWM controller is
enabled, this internal MOSFET remains OFF.
Soft-Start (PWM and LDO)
When VCC exceeds the UVLO threshold and EN is high,
the circuit releases SS and enables the PWM regulator.
The capacitor connected to the SS pin and GND is
charged by a 10µA internal current source, causing the
voltage on the capacitor to rise. When this voltage
exceeds 1.2V, all protection circuits are enabled. When
this voltage exceeds 2.2V, the LDO output is enabled.
The input to the error amplifier at the non-inverting pin is
clamped by the voltage on the SS pin until it crosses the
reference voltage.
A low impedance path between the driver pin and the
MOSFET gate is recommended for the adaptive deadtime circuit to work properly. Any delay along this path
reduces the delay generated by the adaptive dead-time
circuit, thereby increasing the chances for shoot-through.
The time it takes the PWM output to reach regulation
(TRise) is calculated using the following equation:
T RISE = 8 × 10
–2
× C SS (CSS is in μf)
(EQ. 4)
(EQ. 2)
Oscillator Clock Frequency (PWM)
Protection
The clock frequency on the oscillator is set using an
external resistor, connected between R(T) pin and
ground. The frequency follows the graph, as shown in
Figure 18. The minimum clock frequency is 200KHz,
which is when R(T) pin is left open. Select the value of
R(T) as shown in the equation below. This equation is
valid for all FOSC > 200kHz.
In the FAN5069, the converter is protected against
extreme overload, short-circuit, over-voltage, and undervoltage conditions. All of these conditions generate an
internal “fault latch” which shuts down the converter. For
all fault conditions both the high-side and the low-side
drives are off except in the case of OVP where the lowside MOSFET is turned on until the voltage on the FB pin
goes below 0.4V. The fault latch can be reset either by
toggling the EN pin or recycling VCC to the chip.
9
5 × 10
R ( T ) = --------------------------------------------------Ω
( F OSC – 200 × 10 3 )
(EQ. 3)
Over Current Limit (PWM)
where FOSC is in Hz.
The PWM converter is protected against overloading
through a cycle-by-cycle current limit set by selecting
RILIM resistor. An internal 10µA current source sets the
threshold voltage for the output of the summing amplifier.
When the summing amplifier output exceeds this threshold level, the current limit comparator trips and the PWM
starts skipping pulses. If the current limit tripping occurs
for 16 continuous clock cycles, a fault latch is set and the
controller shuts down the converter. This shutdown fea-
For example, for FOSC = 300kHz, R(T) = 50KΩ.
RRAMP Selection and Feed-Forward Operation
The FAN5069 provides for input voltage feed-forward
compensation through RRAMP. The value of RRAMP effectively changes the slope of the internal ramp, minimizing
the variation of the PWM modulator gain when input volt© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
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11
FAN5069 PWM and LDO Controller Combo
PWM Operation
To achieve current limit, the FAN5069 monitors the
inductor current during the OFF time by monitoring and
holding the voltage across the lower MOSFET. The voltage across the lower MOSFET is sensed between the
PGND and the SW pins.
EN Pin
PWM/Restart
Pull to GND
OFF
VCC
No restart after fault
Cap to GND
Restart after TDELAY (Sec.) =
0.85 x C where C is in μF
The fault latch can also be reset by recycling the VCC to
the controller.
The output of the summing amplifier is a function of the
inductor current, RDS_ON of the bottom FET and the gain
of the current sense amplifier. With the RDS_ON method
of current sensing, the current limit can vary widely from
unit to unit. RDS_ON not only varies from unit to unit, but
also has a typical junction temperature coefficient of
about 0.4%/°C (consult the MOSFET datasheet for
actual values). The set point of the actual current limit
decreases in proportion to increase in MOSFET die temperature. A factor of 1.6 in the current limit set point typically compensates for all MOSFET RDS_ON variations,
assuming the MOSFET's heat sinking keeps its operating die temperature below 125°C.
Under Voltage Protection (PWM)
The PWM converter output is monitored constantly for
under voltage at the FB pin. If the voltage on the FB pin
stays lower than 75% of internal Vref for 16 clock cycles,
the fault latch is set and the converter shuts down. This
shutdown feature is disabled during startup until the voltage on the SS capacitor reaches 1.2V.
Over Voltage Protection (PWM)
The PWM converter output voltage is monitored constantly at the FB pin for over voltage. If the voltage on the
FB pin stays higher than 115% of internal VREF for two
clock cycles, the controller turns OFF the upper MOSFET and turns ON the lower MOSFET. This crowbar
action stops when the voltage on the FB pin reaches
0.4V to prevent the output voltage from becoming negative. This over-voltage protection (OVP) feature is active
as soon as the voltage on the EN pin becomes high.
For more accurate current limit setting, use resistor
sensing. In a resistor sensing scheme, an appropriate
current sense resistor is connected between the source
terminal of the bottom MOSFET and PGND.
Set the current limit by choosing RILIM as follows:
3
11
K1 • I MAX • R DSON • 10
⎛
Vout • 33.32 • 10 ⎛
1.8
- + ⎜ ⎛ 1 – ---------⎞ • ---------------------------------------------------- ⎜
R ILIM = 128 + ----------------------------------------------------------------⎝
⎠
F
•
R
Vin
1.43
⎝
⎝
SW
RAMP
Turning ON the low-side MOSFETs on an OVP condition
pulls down the output, resulting in a reverse current,
which starts to build up in the inductor. If the output overvoltage is due to failure of the high-side MOSFET, this
crowbar action pulls down the input supply or blows its
fuse, protecting the system, which is very critical.
(EQ. 5)
where RILIM is in KΩ.
IMAX is the maximum load current.
K1 is a constant to accommodate for the variation of
MOSFET RDS(ON) (typically 1.6).
During soft-start, if the output overshoots beyond 115%
of VREF, the output voltage is brought down by the lowside MOSFET until the voltage on the FB pin goes below
0.4V. The fault latch is NOT set until the voltage on the
SS pin reaches 1.2V. Once the fault latch is set, the converter shuts down.
With K1 = 1.6, IMAX = 20A, RDS(ON) = 7mΩ, VIN = 24V,
VOUT = 1.5V, FSW = 300 KHz, RRAMP = 400 KΩ, RILIM
calculates to be 323.17KΩ.
Auto Restart (PWM)
115% Vref
The FAN5069 supports two modes of response when the
internal fault latch is set. The user can configure it to
keep the power supply latched in the OFF state OR in
the Auto Restart mode. When the EN pin is tied to VCC,
the power supply is latched OFF. When the EN pin is terminated with a 100nF to GND, the power supply is in
Auto Restart mode. The table below describes the relationship between PWM restart and setting on EN pin. Do
not leave the EN pin open without any capacitor.
ILIM
UV
Delay
2 Clks
FB
S
OV
V SS >1.2V
Q
EN
Fault
Latch
R
S
Q
0.4V
LS Drive
R
Figure 21. Over-Voltage Protection
Thermal Fault Protection
The FAN5069 features thermal protection where the IC
temperature is monitored. When the IC junction temperature exceeds +160°C, the controller shuts down and
when the junction temperature gets down to +125°C, the
converter restarts.
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
12
FAN5069 PWM and LDO Controller Combo
ture is disabled during the start-up until the voltage on
the SS capacitor crosses 1.2V.
operate at the boundary of continuous and discontinuous
conduction modes.
The LDO controller is designed to provide ultra low voltages, as low as 0.8V for GTL-type loads. The regulating
loop employs a very fast response feedback loop and
small capacitors can be used to keep track of the changing output voltage during transients. For stable operation, the minimum capacitance on the output needs to be
100µF and the typical ESR needs to be around 100mΩ.
Setting the Output Voltage (PWM)
The internal reference for the PWM controller is at 0.8V.
The output voltage of the PWM regulator can be set in
the range of 0.8V to 90% of its power input by an external resistor divider. The output is divided down by an
external voltage divider to the FB pin (for example, R1
and RBIAS as in Figure 24). The output voltage is given
by the following equation:
The maximum voltage at the gate drive for the MOSFET
can reach close to 0.5V below the VCC of the controller.
For example, for a 1.2V output, the minimum enhancement voltage required with 4.75V on VCC is 3.05V
(4.75V-0.5V-1.2V = 3.05V). The drop-out voltage for the
LDO is dependent on the load current and the MOSFET
chosen. It is recommended to use low enhancement
voltage MOSFETs for the LDO. In applications where
LDO is not needed, pull up the FBLDO pin (Pin #1)
higher than 1V to disable the LDO.
R1
V OUT = 0.8V × ⎛⎝ 1 + ----------------⎞⎠
R BIAS
(EQ. 6)
To minimize noise pickup on this node, keep the resistor
to GND (RBIAS) below 10KΩ.
Inductor Selection (PWM)
When the ripple current, switching frequency of the converter, and the input-output voltages are established,
select the inductor using the following equation:
The soft-start on the LDO output (ramp) is controlled by
the capacitor on the SS pin to GND. The LDO output is
enabled only when the voltage on the SS pin reaches
2.2V. Refer to Figure 9 for start-up waveform.
2
V OUT
⎛V
– -------------- ⎞
⎝ OUT V IN ⎠
= -------------------------------------------I Ripple × F SW
Design Section
L MIN
General Design Guidelines
where IRipple is the ripple current.
Establishing the input voltage range and maximum current loading on the converter before choosing the switching frequency and the inductor ripple current is highly
recommended. There are design trade-offs in choosing
an optimum switching frequency and the ripple current.
This number typically varies between 20% to 50% of the
maximum steady-state load on the converter.
When selecting an inductor from the vendors, select the
inductance value which is close to the value calculated at
the rated current (including half the ripple current).
The input voltage range should accommodate the worstcase input voltage with which the converter may ever
operate. This voltage needs to account for the cable drop
encountered from the source to the converter. Typically,
the converter efficiency tends to be higher at lower input
voltage conditions.
Input Capacitor Selection (PWM)
The input capacitors must have an adequate RMS current rating to withstand the temperature rise caused by
the internal power dissipation. The combined RMS current rating for the input capacitor should be greater than
the value calculated using the following equation:
When selecting maximum loading conditions, consider
the transient and steady-state (continuous) loading separately. The transient loading affects the selection of the
inductor and the output capacitors. Steady state loading
affects the selection of MOSFETs, input capacitors, and
other critical heat-generating components.
⎛ V OUT V OUT 2⎞
I INPUT ( RMS ) = I LOAD ( MAX ) × ⎜ -------------- – ⎛ --------------⎞ ⎟ (EQ. 8)
⎝ V IN ⎝ V IN ⎠ ⎠
Common capacitor types used for such application
include aluminum, ceramic, POS CAP, and OSCON.
The selection of switching frequency is challenging.
While higher switching frequency results in smaller components, it also results in lower efficiency. Ideal selection
of switching frequency takes into account the maximum
operating voltage. The MOSFET switching losses are
directly proportional to FSW and the square function of
the input voltage.
Output Capacitor Selection (PWM)
The output capacitors chosen must have low enough
ESR to meet the output ripple and load transient requirements. The ESR of the output capacitor should be lower
than both of the values calculated below to satisfy both
the transient loading and steady-state ripple conditions
as given by the following equation:
When selecting the inductor, consider the minimum and
maximum load conditions. Lower inductor values produce better transient response, but result in higher ripple
and lower efficiency due to high RMS currents. Optimum
minimum inductance value enables the converter to
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
(EQ. 7)
V STEP
ESR ≤ ---------------------------------- and
ΔI LOAD ( MAX )
V Ripple
ESR ≤ ------------------I Ripple
(EQ. 9)
www.fairchildsemi.com
13
FAN5069 PWM and LDO Controller Combo
LDO Section
CGD
RD
RGATE
G
SW
Figure 23. Drive Equivalent Circuit
For stable operation, the minimum capacitance of 100µF
with ESR around 100mΩ is recommended. For other values, contact the factory.
The upper graph in Figure 22 represents Drain-toSource Voltage (VDS) and Drain Current (ID) waveforms.
The lower graph details Gate-to-Source Voltage (VGS)
vs. time with a constant current charging the gate. The xaxis is representative of Gate Charge (QG). CISS = CGD
+ CGS and it controls t1, t2, and t4 timing. CGD receives
the current from the gate driver during t3 (as VDS is falling). Obtain the gate charge (QG) parameters shown on
the lower graph from the MOSFET datasheets.
Power MOSFET Selection (PWM)
The FAN5069 is capable of driving N-Channel MOSFETs
as circuit switch elements. For better performance,
MOSFET selection must address these key parameters:
■ The
maximum Drain-to-Source Voltage (VDS) should
be at least 25% higher than worst-case input voltage.
■ The MOSFETs should have low QG, QGD, and QGS.
■ The RDS_ON of the MOSFETs should be as low as possible.
In typical applications for a buck converter, the duty
cycles are lower than 20%. To optimize the selection of
MOSFETs for both the high-side and low-side, follow different selection criteria. Select the high-side MOSFET to
minimize the switching losses and the low-side MOSFET
to minimize the conduction losses due to the channel
and the body diode losses. Note that the gate drive
losses also affect the temperature rise on the controller.
Assuming switching losses are about the same for both
the rising edge and falling edge, Q1's switching losses
occur during the shaded time when the MOSFET has
voltage across it and current through it.
Losses are given by (EQ. 10), (EQ. 11), and (EQ. 12):
PUPPER = PSW + PCOND
V DS × I L
P SW = ⎛ --------------------- × 2 × t s⎞ F SW
⎝
⎠
2
V OUT
2
× R DS ( ON )
P COND = ⎛ --------------⎞ × I OUT
⎝ V IN ⎠
For loss calculation, refer to Fairchild's Application Note
AN-6005 and the associated spreadsheet.
(EQ. 10)
(EQ. 11)
(EQ. 12)
where PUPPER is the upper MOSFET's total losses and
PSW and PCOND are the switching and conduction losses
for a given MOSFET. RDS(ON) is at the maximum junction
temperature (TJ) and tS is the switching period (rise or
fall time) and equals t2+t3 (Figure 22.).
High-Side Losses
Losses in the MOSFET can be understood by following
the switching interval of the MOSFET in Figure 22. MOSFET gate drive equivalent circuit is shown in Figure 23.
CGD
HDRV
CGS
Output Capacitor Selection (LDO)
CISS
VIN
5V
The driver's impedance and CISS determine t2 while t3's
period is controlled by the driver's impedance and QGD.
Since most of tS occurs when VGS = VSP, assume a constant current for the driver to simplify the calculation of tS
using the following equation:
CISS
VDS
Q G ( SW )
Q G ( SW )
t s = -------------------- ≈ ---------------------------------------------I Driver ⎛ V CC – V SP ⎞
---------------------------------------⎝ R Driver + R Gate⎠
ID
(EQ. 13)
Most MOSFET vendors specify QGD and QGS. QG(SW)
can be determined as:
QGS
QGD
QG(SW) = QGD + QGS – QTH where QTH is the gate
charge required to reach the MOSFET threshold (VTH).
4.5V
VSP
VTH
Note that for the high-side MOSFET, VDS equals VIN,
which can be as high as 20V in a typical portable application. Include the power delivered to the MOSFET's
(PGATE) in calculating the power dissipation required for
the FAN5069.
QG(SW)
VGS
t1
t2
t3
t4
t5
Figure 22. Switching Losses and QG
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
14
FAN5069 PWM and LDO Controller Combo
In the case of aluminum and polymer based capacitors,
the output capacitance is typically higher than normally
required to meet these requirements. While selecting the
ceramic capacitors for the output; although lower ESR
can be achieved easily, higher capacitance values are
required to meet the VOUT(MIN) restrictions during a load
transient. From the stability point of view, the zero
caused by the ESR of the output capacitor plays an
important role in the stability of the converter.
R-C components for the snubber are selected as follows:
(EQ. 14)
P Gate = Q G × V CC × F SW
a) Measure the SW node ringing frequency (Fring) with a
low capacitance scope probe.
where QG is the total gate charge to reach VCC.
b) Connect a capacitor (CSNUB) from SW node to GND
so that it reduces this ringing by half.
Low-Side Losses
Q2 switches on or off with its parallel schottky diode
simultaneously conducting, so the VDS ≈ 0.5V. Since
PSW is proportional to VDS, Q2's switching losses are
negligible and Q2 is selected based on RDS(ON) alone.
c) Place a resistor (RSNUB) in series with this capacitor.
RSNUB is calculated using the following equation:
2
R SNUB = ----------------------------------------------(EQ. 17)
π × F ring × C SNUB
Conduction losses for Q2 are given by the equation:
2
(EQ. 15)
P COND = ( 1 – D ) × I OUT × R DS ( ON )
d) Calculate the power dissipated in the snubber resistor
as shown in the following equation:
where RDS(ON) is the RDS(ON) of the MOSFET at the
highest operating junction temperature and D=VOUT/VIN
is the minimum duty cycle for the converter.
2
P R ( SNUB ) = C SNUB × V IN ( MAX ) × F SW
where, VIN(MAX) is the maximum input voltage and FSW
is the converter switching frequency.
Since DMIN < 20% for portable computers, (1-D) ≈ 1 produces a conservative result, simplifying the calculation.
The snubber resistor chosen should be de-rated to handle the worst-case power dissipation. Do not use wirewound resistors for RSNUB.
The maximum power dissipation (PD(MAX)) is a function
of the maximum allowable die temperature of the lowside MOSFET, the θJA, and the maximum allowable
ambient temperature rise. PD(MAX) is calculated using
the following equation:
T J ( MAX ) – T A ( MAX )
P D ( MAX ) = ------------------------------------------------θ JA
(EQ. 18)
Loop Compensation
Typically, the closed loop crossover frequency (Fcross),
where the overall gain is unity, should be selected to
achieve optimal transient and steady-state response to
disturbances in line and load conditions. It is recommended to keep Fcross below fifth of the switching frequency of the converter. Higher phase margin tends to
have a more stable system with more sluggish response
to load transients. Optimum phase margin is about 60°, a
good compromise between steady state and transient
responses. A typical design should address variations
over a wide range of load conditions and over a large
sample of devices.
(EQ. 16)
θJA depends primarily on the amount of PCB area
devoted to heat sinking.
Selection of MOSFET Snubber Circuit
The Switch node (SW) ringing is caused by fast switching transitions due to the energy stored in the parasitic
elements. This ringing on the SW node couples to other
circuits around the converter if they are not handled
properly. To dampen this ringing, an R-C snubber is connected across the SW node and the source of the lowside MOSFET.
VIN
VIN
Current
Sense
Amplifier
RRAMP
Ramp
Generator
Summing
Σ
Q1
L
PWM
&
DRIVER
RDC
C
Q2
Amplifier
VOUT
RES
RL
C2
C1
R2
RBIAS
Reference
C3
R3
R1
Figure 24. Closed-Loop System with Type-3 Network
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
15
FAN5069 PWM and LDO Controller Combo
PGATE is determined by the following equation:
For further information about Type-2 compensation
networks, refer to:
■
Venable, H. Dean, "The K factor: A new mathematical
tool for stability analysis and synthesis,” Proceedings
of Powercon, March 1983.
Note: For critical applications requiring wide loop
bandwidth using very low ESR output capacitors,
use Type-3 compensation.
Type 3 Feedback Component Calculations
Use the following steps to calculate feedback components:
Notation:
C 0 = Net Output Filter capacitance
G p ( s ) = Net Gain of Plant = control-to-output transfer function
L = Inductor Value
R DSON = ON-state Drain-to Source Resistance of Low-side MOSFET
R es = Net ESR of the Output Filter Capacitors
R L = Load Resistance
T s = Switching Period
V IN = Input Voltage
F SW = Switching Frequency
Equations:
Effective current sense resistance = R i = 7 × R DSON
(EQ. 19)
RL
Current modulator DC gain = M i = ------Ri
(EQ. 20)
( V IN – 1.8 ) × T s
Effective ramp amplitude = V m = 3.33 × 10 10 × ---------------------------------------R ramp
(EQ. 21)
V IN
Voltage modulator DC gain = M v = --------Vm
(EQ. 22)
Mv × Mi
Plant DC gain = M o = M v || M i = -------------------Mv + Mi
(EQ. 23)
π
Sampling gain natural frequency = ω n = -----Ts
(EQ. 24)
–2
Sampling gain quality factor (damping) = Q z = -----π
(EQ. 25)
MO
Mv × Ri
Effective inductance = L e = -------- × ⎛ L + --------------------⎞
Mv ⎝
ω n × Q z⎠
(EQ. 26)
Mv × Ri × RL
R p = --------------------------------- = ( M v × R i ) || R L
Mv × Ri + RL
(EQ. 27)
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
16
FAN5069 PWM and LDO Controller Combo
FAN5069 has a high gain error amplifier around which
the loop is closed. Figure 24 shows a Type-3 compensation network. For Type-2 compensation, R3 and C3 are
not used. Since the FAN5069 architecture employs summing current mode, Type-2 compensation can be used
for most applications.
1
Plant zero frequency = f z = -----------------------------------------2 × π × C o × R es
(EQ. 28)
1
Plant 1st pole frequency = f p1 = ----------------------------------------------------------Le
2 × π × ⎛⎝ C o × R p + -------⎞⎠
RL
(EQ. 29)
Rp
1
1
Plant 2nd pole frequency = f p2 = ------------ × ⎛ -------------------- + -------⎞
⎝
2×π
Co × RL Le ⎠
(EQ. 30)
2
ωn × Le
Plant 3rd pole frequency = f p3 = -------------------------2 × π × Rp
(EQ. 31)
Plant gain (magnitude) response:
f 2
1 + ⎛ ----⎞
⎝ f z⎠
G p (f) = 20 × log M 0 + 10 × log --------------------------------------------------------------------------------------------------------f 2
f 2
f 2
1 + ⎛⎝ -------⎞⎠ × 1 + ⎛⎝ -------⎞⎠ × 1 + ⎛⎝ -------⎞⎠
f p2
f p3
f p1
(EQ. 32)
Plant phase response:
–1 f
–1 f
–1 f
–1 f
∠G P (f) = tan ⎛ ----⎞ – tan ⎛ -------⎞ – tan ⎛ -------⎞ – – tan ⎛ -------⎞
⎝ f z⎠
⎝ f p1⎠
⎝ f p2⎠
⎝ f p3⎠
(EQ. 33)
Choose R1, RBIAS to set the output voltage using EQ.6. Choose the zero crossover frequency Fcross of the overall
loop. Typically Fcross should be less than fifth of Fsw. Choose the desired phase margin; typically between 60° to 90°.
Calculate plant gain at Fcross using EQ.34 by substituting Fcross in place of f. The gain that the amplifier needs to provide to get the required crossover is given by:
1
(EQ. 34)
G AMP = -------------------------------G p (F cross )
The phase boost required is calculated as given in (EQ. 35)
Phase Boost = M – ∠G P (F cross ) – 90°
(EQ. 35)
where M is the desired phase margin in degrees.
The feedback component values are calculated as given in equations below:
2
⎧
⎫
Boost
K = ⎨ Tan ⎛ ----------------⎞ + 45 ⎬
⎝ 4 ⎠
⎩
⎭
(EQ. 36)
1
C2 = -----------------------------------------------------------------------2 × π × F cross × G AMP × R1
(EQ. 37)
C1 = C2 × ( K – 1 )
(EQ. 38)
1
C3 = ---------------------------------------------------------------2 × π × F cross × K × R3
(EQ. 39)
K
R2 = -------------------------------------------------2 × π × F cross × C1
(EQ. 40)
R1
R3 = -----------------(K – 1)
(EQ. 41)
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
17
FAN5069 PWM and LDO Controller Combo
Poles and Zeros of Plant Transfer Function:
Layout Considerations
Fairchild application note AN-6010 provides a PSPICE
model and spreadsheet calculator for the PWM regulator, simplifying external component selections and verifying loop stability. The topics covered provide an
understanding of the calculations in the spreadsheet.
The switching power converter layout needs careful
attention and is critical to achieving low losses and clean
and stable operation. Below are specific recommendations for good board layout:
■
The spreadsheet calculator, which is part of AN-6010,
can be used to calculate all external component values
for designing around FAN5069. The spreadsheet provides optimized compensation components and generates a Bode Plot to ensure loop stability.
■
■
Based on the input values entered, AN-6010’s PSPICE
model can be used to simulate Bode Plots (for loop stability) as well as transient analysis to help customize the
design for a wide range of applications.
■
■
Use Fairchild Application Note AN-6005 for prediction of
the losses and die temperatures for the power semiconductors used in the circuit.
■
AN-6010 and AN-6005 can be downloaded from
www.fairchildsemi.com/apnotes/.
■
■
■
■
■
■
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
Keep the high-current traces and load connections as
short as possible.
Use thick copper boards whenever possible to
achieve higher efficiency.
Keep the loop area between the SW node, low-side
MOSFET, inductor, and the output capacitor as small
as possible.
Route high dV/dt signals, such as SW node, away
from the error amplifier input/output pins. Keep components connected to these pins close to the pins.
Place ceramic de-coupling capacitors very close to the
VCC pin.
All input signals are referenced with respect to AGND
pin. Dedicate one layer of the PCB for a GND plane.
Use at least four layers for the PCB.
Minimize GND loops in the layout to avoid EMI-related
issues.
Use wide traces for the lower gate drive to keep the
drive impedances low.
Connect PGND directly to the lower MOSFET source
pin.
Use wide land areas with appropriate thermal vias to
effectively remove heat from the MOSFETs.
Use snubber circuits to minimize high-frequency ringing at the SW nodes.
Place the output capacitor for the LDO close to the
source of the LDO MOSFET.
www.fairchildsemi.com
18
FAN5069 PWM and LDO Controller Combo
Design Tools
VIN = 3 to 24V; VOUT =1.5V at 20A.
+5V or +12V
Vcc
J1
R9
220
U1
C7
0.22µF
PWM OUT
3-24V
15
J7
LDO_Out
16
R8
C17
+
C4
0.1µF
1
5K
GLDO
HDRV
FBLDO
BOOT
R4
2
Q2
3
243K
L1
FDD6606
Q3
13
TP1
J3
GND
J4
SW_Out
C14
+ C15
560µF 560µF 560µF
C12
0.1µF
+
C13
+
C16
3.3nF
4
SS
PGND
EN
COMP
C1
1500pF
7
5
AGND
R2
FB
825
C2
220pF
6
C3
R3
12.7k
0.01µF
8
J5
GND
12
0.1µF
C9
820µF
1.8µH
R11
2.2
Q4
C5
TP2
820µF
0.1µF
9
LDRV
IL IM
C11 +
PWM OUT
FDD6606
R5
+
11
SW
R(T)
C10
C6
C8
0.22µF
50K
J2
VIN
453K
10
R7 10K
560µF
J6
GND
R6
14
R(RAMP)
FDD6296
Q1
FDD6530A
LDO
VCC
3300pF
R1
5.11K
R10
FAN5069
5.83K
Figure 25. Application Board Schematic
Bill of Materials
Part Description
Capacitor, 1500pF, 20%, 25V, 0603,X7R
Quantity
1
Designator
Vendor
C1
Panasonic
Vendor Part #
PCC1774CT-ND
Capacitor, 220pF, 5%, 50V, 0603,NPO
1
C2
Panasonic
PCC221ACVCT-ND
Capacitor, 3300pF, 10%, 50V, 0603,X7R
1
C3
Panasonic
PCC1778CT-ND
Capacitor, 0.1µF, 10%, 25V, 0603,X7R
4
C4, C5, C6, C15
Panasonic
PCC2277CT-ND
Capacitor, 0.22µF, 20%, 25V, 0603,X7R
2
C7, C8
Panasonic
PCC1767CT-ND
Capacitor, 0.01µF, 10%, 50V, 0603,X7R
1
C9
Panasonic
PCC1784CT-ND
Capacitor, 820µF, 20%, 10X20, 25V,20mOhm,1.96A
2
C10, C11
Nippon-Chemicon
KZH25VB820MHJ20
Capacitor, 820µF, 20%, 8X8, 2.5V,7mOhm,6.1A
1
C17
Nippon-Chemicon
PSC2.5VB820MH08
Capacitor, 560µF, 20%, 8X11.5, 4V,7mOhm,5.58A
3
C12, C13, C14
Nippon-Chemicon
PSA4VB560MH11
Capacitor, 3300pF, 10%, 50V, 0603,X7R
1
C16
Panasonic
PCC332BNCT-ND
Connector Header 0.100 Vertical, Tin - 2 Pin
1
J1
Molex
WM6436-ND
Terminal Quickfit Male .052"Dia.187" Tab
6
J2 - J7
Keystone
1212K-ND
Inductor, 1.8µH, 20%, 26Amps Max, 3.24mOhm
1
L1
Inter-Technical
SC5018-1R8M
MOSFET N-CH, 32 mΩ, 20V, 21A, D-PAK, FSID: FDD6530A
1
Q1
Fairchild Semiconductor
FDD6530A
MOSFET N-CH, 8.8 mΩ, 30V, 50A, D-PAK, FSID: FDD6296
1
Q2
Fairchild Semiconductor
FDD6296
MOSFET N-CH, 6 mΩ, 30V, 75A, D-PAK, FSID: FDD6606
2
Q3, Q4
Fairchild Semiconductor
FDD6606
Resistor, 5.11K, 1%, 1/16W
1
R1
Panasonic
P5.11KHCT-ND
Resistor, 12.7K, 1%, 1/16W
1
R2
Panasonic
P12.7KHCT-ND
Resistor, 825Ω, 1%, 1/16W
1
R3
Panasonic
P825HCT-ND
Resistor, 49.9K, 1%, 1/16W
1
R4
Panasonic
P49.9KHCT-ND
Resistor, 243K, 1%, 1/16W
1
R5
Panasonic
P243KHCT-ND
Resistor,453K, 1%, 1/16W
1
R6
Panasonic
P453KHCT-ND
Resistor,10K, 1%, 1/16W
1
R7
Panasonic
P10.0KHCT-ND
Resistor, 4.99K, 1%, 1/16W
1
R8
Panasonic
P4.99KHCT-ND
P200FCT-ND
Resistor, 220Ω, 1%, 1/4W
1
R9
Panasonic
Resistor, 5.90K, 1%, 1/16W
1
R10
Panasonic
P5.90KHCT-ND
Resistor, 2.2Ω, 1%, 1/4W
1
R11
Panasonic
P2.2ECT-ND
Connector Header 0.100 Vertical, Tin - 1 Pin
3
TP1,TP2, Vcc
Molex
WM6436-ND
IC, System Regulator, TSSOP16, FSID: FAN5069
1
U1
Fairchild Semiconductor
FAIRCHILD
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
19
FAN5069 PWM and LDO Controller Combo
Application Board Schematic
FAN5069 PWM and LDO Controller Combo
Typical Application Board Layout
Figure 26. Assembly Diagram
Figure 29. Mid Layer 2
Figure 27. Top Layer
Figure 30. Bottom Layer
Figure 28. Mid Layer 1
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
20
FAN5069 PWM and LDO Controller Combo
Mechanical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 31. 16-Lead TSSOP
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
21
FAN5069 PWM and LDO Controller Combo
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
22