MK2771-13 VCXO and Set-Top Clock Source Description Features The MK2771-03 is a low cost, low jitter, high performance VCXO and clock synthesizer designed for set-top boxes. The on-chip Voltage Controlled Crystal Oscillator accepts a 0 to 3V input voltage to cause the output clocks to vary by ±100 ppm. Using ICS/MicroClock’s patented VCXO and analog Phase-Locked Loop (PLL) techniques, the device uses an inexpensive 13.5 MHz crystal input to produce multiple output clocks including a selectable processor clock, a selectable audio clock, a fixed 33.33 MHz or 24.576 MHz, two low skew copies of the 27MHz, and a fixed 13.5 MHz. All clocks are frequency locked to the 27.00MHz output (and to each other) with zero ppm error, so any output can be used as the VCXO output. • Packaged in 20 pin SOIC • Pin for pin and functional upgrade to MK2771-03 • Ideal for systems using Oak’s MPEG decoders • On-chip patented VCXO with pull range of 200ppm This chip directly replaces the MK2771-03 when a 13.5 MHz input crystal is substituted for the 14.31818 MHz used on the -03. Additionally, the -13 adds 25 MHz to the processor clock selection, and 24.576 MHz on the BCLK. Block Diagram VDD PCS1:0 ACS1:0 • VCXO tuning voltage of 0 to 3V • Processor frequency of 16.67 MHz, 20 MHz, 25 MHz, 32 MHz, 40 MHz, or 50 MHz • Audio clocks of 8.192, 11.2896, and 12.288 MHz • Zero ppm synthesis error in all clocks (all exactly track 27MHz VCXO) - patented • Uses an inexpensive 13.5 MHz crystal • 25mA output drive capability at TTL levels • Advanced, low power, sub-micron CMOS process • 5V operating voltage GND 3 3 2 Output Buffer Processor Clock 2 Output Buffer Audio Clock Clock Synthesis Circuitry BCS Output Buffer VIN 13.5 MHz pullable crystal X1 X2 Voltage Controlled Crystal Oscillator Output Buffers ÷2 Output Buffer 33.3 MHz or 24.576 MHz 2 27.000 MHz 13.500 MHz 1 Revision 110298 Printed 11/16/00 Integrated Circuit Systems • 525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com MDS 2771-13 A MK2771-13 VCXO and Set-Top Clock Source Pin Assignment PCS0 X2 X1 VDD VIN VDD GND PCLK BCLK ACLK 1 2 3 4 5 6 7 8 9 10 Processor Clock Select Table 20 19 18 17 16 15 14 13 12 11 ACS1 ACS0 BCS GND 27M VDD GND 27M PCS1 13.5M PCS1 0 0 M M 1 1 PCS0 0 1 0 1 0 1 PCLK (MHz) 50.000 16.667 25.000 32.000 40.000 20.000 0 = connect directly to ground, 1 = connect directly to VDD, M = leave floating or unconnected Audio Clock Table ACS1 ACS0 ACLK (MHz) 0 0 8.192 0 1 11.2896 1 0 12.288 1 1 5.6448 Bus Clock Table BCS 0 1 BCLK (MHz) 33.333 24.576 Pin Descriptions Number 1 2 3 4, 6, 15 5 7, 14, 17 8 9 10 11 12 13 16 18 19 20 Name PCS0 X2 X1 VDD VIN GND PCLK BCLK ACLK 13.5M PCS1 27M 27M BCS ACS0 ACS1 Type I XO XI P I P O O O O TI O O P I I Description Processor Clock Select 0. Selects PCLK on pin 8. See table above. Crystal connection. Connect to a pullable 13.5 MHz crystal. Crystal connection. Connect to a pullable 13.5 MHz crystal. Connect to +5V. Voltage Input to VCXO. Zero to 3V signal which controls the frequency of the VCXO. Connect to ground. Processor clock output determined by status of PCS1,0. See table above. 33.33MHz or 24.576 MHz Bus Clock output. See table above. Audio clock output determined by status of ACS1,0. See table above. 13.5 MHz clock output. Divide by two of the 27MHz VCXO output. Processor Clock Select 1. Selects PCLK on pin 8. See table above. 27.00 MHz VCXO clock output. 27.00 MHz VCXO clock output. Bus Clock Select . Selects BCLK on pin 9. See table above. Audio Clock Select 0. Selects ACLK on pin 10. See table above. Audio Clock Select 1. Selects ACLK on pin 10. See table above. Key: I = Input, TI = Tri-level input, O = output, P = power supply connection 2 Revision 110298 Printed 11/16/00 Integrated Circuit Systems • 525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com MDS 2771-13 A MK2771-13 VCXO and Set-Top Clock Source Electrical Specifications Parameter Conditions Minimum Typical Maximum Units 7 VDD+0.5 70 260 150 V V °C °C °C 5.25 V V V V V V V V V V mA mA pF ppm V ABSOLUTE MAXIMUM RATINGS (note 1) Supply voltage, VDD Inputs and Clock Outputs Ambient Operating Temperature Soldering Temperature Storage temperature Referenced to GND Referenced to GND -0.5 0 Max of 10 seconds -65 DC CHARACTERISTICS (VDD = 5.0V unless noted) Operating Voltage, VDD Input High Voltage, VIH, X1 pin only Input Low Voltage, VIL, X1 pin only Input High Voltage, VIH (except PCS1) Input Low Voltage, VIL (except PCS1) Input High Voltage, VIH, PCS1 only Input Low Voltage, VIL, PCS1 only Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH, CMOS level Operating Supply Current, IDD Short Circuit Current Input Capacitance Frequency synthesis error VIN, VCXO control voltage 4.75 3.5 2.5 2.5 1.5 2 0.8 VDD-0.5 0.5 IOH=-25mA IOL=25mA IOH=-8mA No Load, note 2 Each output 2.4 0.4 VDD-0.4 60 ±100 7 All clocks 0 0 3 AC CHARACTERISTICS (VDD = 5.0V unless noted) Input Frequency 13.500000 MHz Output Clock Rise Time 0.8 to 2.0V 1.5 ns Output Clock Fall Time 2.0 to 0.8V 1.5 ns Output Clock Duty Cycle At 1.4V 40 60 % Maximum Absolute Jitter, short term 200 ps Skew of 27 MHz outputs Rising edges at 1.4V -500 0 500 ps 27 MHz output pullability, note 3 0V ≤ VIN ≤ 3V ±100 ppm Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. With PCLK at 50 MHz. 3. With a pullable crystal that conforms to ICS’ specifications External Components The MK2771-13 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.1µF should be connected between VDD and GND on pins 4 and 7, 6 and 7, and 15 and 14, as close to the MK2771-13 as possible. A series termination resistor of 33Ω may be used for each clock output.The 13.500 MHz crystal must be connected as close to the chip as possible. The crystal should be a parallel mode, pullable, with load capacitance of 14pF. Consult MicroClock for recommended suppliers. See MAN05 for recommended layout of the chip and external components. 3 Revision 110298 Printed 11/16/00 Integrated Circuit Systems • 525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com MDS 2771-13 A MK2771-13 VCXO and Set-Top Clock Source Package Outline and Package Dimensions 20 pin SOIC E H h x 45° D c Q e Symbol A b c D E H e h Q Inches Min Max 0.092 0.104 0.014 0.019 0.009 0.012 0.490 0.512 0.290 0.300 0.394 0.419 .050 BSC 0.016 0.003 0.011 Millimeters Min Max 2.3368 2.6416 0.356 0.483 0.229 0.305 12.446 13.005 7.366 7.620 10.008 10.643 1.27 BSC 0.406 0.076 0.279 A b Ordering Information Part/Order Number MK2771-13S MK2771-13STR Marking MK2771-13S MK2771-13S Shipping packaging tubes tape and reel Package 20 pin SOIC 20 pin SOIC Temperature 0-70°C 0-70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 4 Revision 110298 Printed 11/16/00 Integrated Circuit Systems • 525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com MDS 2771-13 A