PD-97508 IR3832WMPbF SupIRBuck TM HIGHLY EFFICIENT INTEGRATED SYNCHRONOUS BUCK REGULATOR FOR DDR APPLICATIONS Features Description • • • • • The IR3832W SupIRBuckTM is an easy-to-use, fully integrated and highly efficient DC/DC regulator. The MOSFETS co-packaged with the on-chip PWM controller make IR3832W a spaceefficient solution, providing accurate power delivery for DDR memory applications. • • • • • • • • • • • • Wide Input Voltage Range 1.0V to 16V Wide Output Voltage Range 0.6V to 0.9*Vin Continuous 4A Load Capability Integrated Bootstrap-diode High Bandwidth E/A for excellent transient performance Programmable Switching Frequency up to 1.5 MHz Programmable Over Current Protection PGood output Hiccup Current Limit Programmable Soft-Start Enable Input with Voltage Monitoring Capability Enhanced Pre-Bias Start-up Vp input for DDR Tracking applications -40oC to 125oC operating junction temperature Thermal Protection 5mm x 6mm Power QFN Package, 0.9 mm height Halogen Free, Lead Free and RoHS Compliant IR3832W is configured to generate termination voltage (VTT) for DDR memory applications. IR3832W offers programmability of start up time, switching frequency and current limit while operating in wide input and output voltage range. The switching frequency is programmable from 250kHz to 1.5MHz for an optimum solution. It also features important protection functions, such as Pre-Bias startup, hiccup current limit and thermal shutdown to give required system level security in the event of fault conditions. Applications • • • • • Server Applications Storage Applications Embedded Telecom Systems Distributed Point of Load Power Architectures Netcom Applications 1.0V <Vin<16V 4.5V <Vcc<5.5V Enable VDDQ Vin Boot Vo Vcc SW PGood PGood OCSet Vp Fb Rt SS/ SD Gnd PGnd Comp Fig. 1. Typical application diagram Rev 4.0 1 PD-97508 IR3832WMPbF ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND unless otherwise specified) • Vin ……………………………………………………. -0.3V to 25V • Vcc ……………….….…………….……..……….…… -0.3V to 8V (Note2) • Boot ……………………………………..……….…. -0.3V to 33V • SW …………………………………………..……… -0.3V to 25V(DC), -4V to 25V(AC, 100ns) • Boot to SW • OCSet • Input / output Pins • PGND to GND ……………...………………………….. -0.3V to +0.3V • Storage Temperature Range ................................... -55°C To 150°C • Junction Temperature Range ................................... -40°C To 150°C (Note2) • ESD Classification …………………………… ……… JEDEC Class 1C • Moisture sensitivity level………………...………………JEDEC Level 3@260 °C ……..…………………………….…..….. -0.3V to Vcc+0.3V (Note1) ………………………………………….……. -0.3V to 30V ……………………………….. ... -0.3V to Vcc+0.3V (Note1) Note1: Must not exceed 8V Note2: Vcc must not exceed 7.5V for Junction Temperature between -10oC and -40oC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PACKAGE INFORMATION SW 5mm x 6mm POWER QFN VIN 11 12 10 PGnd θJA = 35 o C / W θJ -PCB = 2 o C / W Boot 13 Enable 14 1 ORDERING INFORMATION Rev 4.0 Vp 2 15 Gnd 3 4 5 9 VCC 8 PGood 7 6 FB COMP Gnd Rt SS OCSet PACKAGE DESIGNATOR PACKAGE DESCRIPTION PIN COUNT PARTS PER REEL M IR3832WMTRPbF 15 4000 M IR3832WMTR1PbF 15 750 2 PD-97508 IR3832WMPbF Block Diagram Fig. 2. Simplified block diagram of the IR3832W Rev 4.0 3 PD-97508 IR3832WMPbF Pin Description Pin Name Description Track pin. Use External resistors from VDDQ rail. The Vp voltage can be set to 0.9V for DDR2 application and 0.75 or 0.6V for DDR3 application. Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to Fb pin to provide loop compensation. 1 Vp 2 Fb 3 Comp 4 Gnd 5 Rt Set the switching frequency. Connect an external resistor from this pin to Gnd to set the switching frequency. 6 SS/SD ¯¯ Soft start / shutdown. This pin provides user programmable soft-start function. Connect an external capacitor from this pin to Gnd to set the start up time of the output voltage. The converter can be shutdown by pulling this pin below 0.3V. 7 OCSet Current limit set point. A resistor from this pin to SW pin will set the current limit threshold. 8 PGood Power Good status pin. Output is open drain. Connect a pull up resistor from this pin to Vcc. If unused, it can be left open. 9 VCC 10 PGnd 11 SW Switch node. This pin is connected to the output inductor. 12 VIN Input voltage connection pin. 13 Boot 14 Enable 15 Gnd Rev 4.0 Signal ground for internal reference and control circuitry. This pin powers the internal IC and drivers. A minimum of 1uF high frequency capacitor must be connected from this pin to the power ground (PGnd). Power Ground. This pin serves as a separated ground for the MOSFET drivers and should be connected to the system’s power ground plane. Supply voltage for high side driver. Connect a 0.1uF capacitor from this pin to SW. Enable pin to turn on and off the device. Signal ground for internal reference and control circuitry. 4 PD-97508 IR3832WMPbF Recommended Operating Conditions Symbol Vin Vcc Boot to SW Vo Io Fs Tj Definition Input Voltage Supply Voltage Supply Voltage Output Voltage Output Current Switching Frequency Junction Temperature Min Max 1.0 4.5 4.5 0.6 0 225 -40 16 5.5 5.5 0.90*Vin 4 1650 125 Units V A kHz o C Electrical Specifications Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vp=0.6V, Vin=12V, 0oC<Tj< 125oC. Typical values are specified at Ta = 25oC. Parameter Symbol Test Condition Min TYP MAX Units Power Loss Power Loss Ploss Vcc=5V, Vin=12V, Vo=0.75V, Io=4A, Fs=400kHz, L=1.5uH, Note4 0.51 W MOSFET Rds(on) Top Switch Rds(on)_Top Bottom Switch o VBoot -Vsw =5V, ID=10A, Tj=25 C o Rds(on)_Bot Vcc=5V, ID=10A, Tj=25 C ICC(Standby) SS=0V, No Switching, Enable low 22.6 29 15.1 20 mΩ Supply Current VCC Supply Current (Standby) Vcc Supply Current (Dyn) ICC(Dyn) 500 SS=3V, Vcc=5V, Fs=500kHz Enable high 10 μA mA Under Voltage Lockout VCC-Start-Threshold VCC_UVLO_Start Vcc Rising Trip Level 3.95 4.15 4.35 VCC-Stop-Threshold VCC_UVLO_Stop Vcc Falling Trip Level 3.65 3.85 4.05 Enable-Start-Threshold Enable_UVLO_Start Supply ramping up 1.14 1.2 1.36 Enable-Stop-Threshold Enable_UVLO_Stop Supply ramping down 0.9 1.0 1.06 Enable leakage current Ien Enable=3.3V Rev 4.0 15 V μA 5 PD-97508 IR3832WMPbF Electrical Specifications (continued) Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vp=0.6V, Vin=12V, 0oC<Tj< 125oC. Typical values are specified at Ta = 25oC. Parameter Symbol Test Condition Min TYP MAX Units 0.625 0.7 0.775 V Rt=59K 225 250 275 Rt=28.7K 450 500 550 Rt=9.31K, Note4 1350 1650 Oscillator Rt Voltage Frequency FS Vramp Note4 1500 1.8 Ramp Offset Ramp (os) Note4 0.6 Min Pulse Width Dmin(ctrl) Note4 50 Note4 130 Ramp Amplitude Fixed Off Time Max Duty Cycle Dmax Fs=250kHz 92 Vfb-Vp Vp=0.6V -5 kHz Vp-p V 200 ns % Error Amplifier Input Offset Voltage Vos 0 +5 Input Bias Current IFb(E/A) -1 +1 Input Bias Current IVp(E/A) -1 +1 Isink(E/A) 0.40 0.85 12 Isource(E/A) 8 10 13 Sink Current Source Current Slew Rate Gain-Bandwidth Product DC Gain mV μA mA SR Note4 7 12 20 V/μs GBWP Note4 20 30 40 MHz Gain Note4 100 110 120 dB Vcc=4.5V 3.4 3.5 3.75 V 120 220 mV 1 V μA Maximum Voltage Vmax(E/A) Minimum Voltage Vmin(E/A) Note4 Common Mode Voltage 0 Soft Start/SD Soft Start Current Soft Start Clamp Voltage Shutdown Output Threshold ISS Source Vss(clamp) 14 20 26 2.7 3.0 3.3 SD 0.3 V Over Current Protection OCSET Current OC Comp Offset Voltage SS off time IOCSET VOFFSET Fs=250kHz 20.8 23.6 26.4 Fs=500kHz 43 48.8 54.6 Fs=1500kHz 136 154 172 Note4 -10 0 +10 SS_Hiccup 4096 μA mV Cycles Bootstrap Diode Forward Voltage I(Boot)=30mA 180 260 470 mV 5 10 30 ns Deadband Deadband time Rev 4.0 Note4 6 PD-97508 IR3832WMPbF Electrical Specifications (continued) Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vp=0.6V, Vin=12V, 0oC<Tj< 125oC. Typical values are specified at Ta = 25oC. Parameter SYM Test Condition Min TYP MAX Units Thermal Shutdown Thermal Shutdown Note4 140 Hysteresis Note4 20 o C Power Good Power Good upper Threshold Upper Threshold Delay Power Good lower Threshold Lower Threshold Delay Delay Comparator Threshold Delay Comparator Hysteresis PGood Voltage Low Leakage Current VPG(upper) Fb Rising VPG(upper)_Dly Fb Rising VPG(lower) Fb Falling VPG(lower)_Dly Fb Falling PG(Delay) Relative to charge voltage, SS rising Delay(hys) Note4 PG(voltage) IPGood=-5mA Ileakage 0.660 0.690 0.720 256/Fs 0.480 0.510 V S 0.540 256/Fs V s 2 2.1 2.3 V 260 300 340 mV 0 0.5 V 10 μA Switch Node SW Bias Current SW=0V, Enable=0V Isw SW=0V,Enable=high,SS=3V,Vp=0V, Note4 6 μA Note3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. Note4: Guaranteed by Design but not tested in production. Rev 4.0 7 PD-97508 IR3832WMPbF TYPICAL OPERATING CHARACTERISTICS (-40oC - 125oC) Fs=500 kHz Icc(Standby) Icc(Dyn) 10.5 290 10.4 270 10.3 10.2 250 [mA] [uA] 10.1 230 210 10.0 9.9 9.8 190 9.7 170 9.6 150 9.5 -40 -20 0 20 40 60 80 100 120 -40 o -20 0 20 Temp[ C] 52.0 520 51.0 510 50.0 [uA] [kHz] 80 100 120 80 100 120 80 100 120 80 100 120 53.0 530 500 490 49.0 48.0 47.0 480 46.0 470 45.0 460 44.0 43.0 450 -40 -20 0 20 40 60 80 100 -40 120 -20 0 20 60 Temp[ C] Vcc(UVLO) Start 4.46 40 o o Temp[ C] Vcc(UVLO) Stop 4.16 4.41 4.11 4.36 4.06 4.31 4.01 [V] [V] 60 54.0 540 4.26 3.96 4.21 3.91 4.16 3.86 4.11 3.81 4.06 3.76 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 Temp[ oC] 40 60 Temp[ oC] Enable(UVLO) Start 1.36 Enable(UVLO) Stop 1.06 1.34 1.04 1.32 1.30 1.02 1.28 1.00 1.26 [V] [V] o IOCSET(500kHz) FREQUENCY 550 40 Temp[ C] 1.24 0.98 1.22 0.96 1.20 0.94 1.18 0.92 1.16 1.14 0.90 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 ο Temp[ oC] Temp[ C] ISS 26.0 24.0 [uA] 22.0 20.0 18.0 16.0 14.0 -40 -20 0 20 40 o 60 80 100 120 Temp[ C] Rev 4.0 8 PD-97508 IR3832WMPbF Rdson of MOSFETs Over Temperature at Vcc=5V 30 28 Resistance [mΩ] 26 24 22 20 18 16 14 12 -40 -20 0 20 40 60 80 100 120 140 Temperature [°C] Sync-FET Rev 4.0 Ctrl-FET 9 PD-97508 IR3832WMPbF Typical Efficiency and Power Loss Curves Vin=12V, Vcc=5V, Vo=0.75V, Io=0.5A-4A, Fs=400kHz, L=1.5uH (MPO104-1R5 from Delta), Room Temperature, No Air Flow 89 88 Efficiency (%) 87 86 85 84 83 82 81 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.0 3.5 4.0 Load Current (A) 0.55 0.50 Power Loss (W) 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.5 1.0 1.5 2.0 2.5 Load Current (A) Rev 4.0 10 PD-97508 IR3832WMPbF Typical Efficiency and Power Loss Curves Vin=5V, Vcc=5V, Vo=0.75V, Io=0.5A-4A, Fs=400kHz, L=1.5uH (MPO104-1R5 from Delta), Room Temperature, No Air Flow 90 Efficiency (%) 89 88 87 86 85 84 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.0 3.5 4.0 Load Current (A) 0.50 0.45 Power Loss (W) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.5 1.0 1.5 2.0 2.5 Load Current (A) Rev 4.0 11 PD-97508 IR3832WMPbF Circuit Description THEORY OF OPERATION Introduction The IR3832W uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The switching frequency is programmable from 250kHz to 1.5MHz and provides the capability of optimizing the design in terms of size and performance. IR3832W provides precisely regulated output voltage programmed via two external resistors from 0.7V to 0.9*Vin. If the input to the Enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be ensured that the IR3832W does not turn on until the bus voltage reaches the desired level. Only after the bus voltage reaches or exceeds this level will the voltage at Enable pin exceed its threshold, thus enabling the IR3832W. Therefore, in addition to being a logic input pin to enable the IR3832W, the Enable feature, with its precise threshold, also allows the user to implement an Under-Voltage Lockout for the bus voltage Vin. This is desirable particularly for high output voltage applications, where we might want the IR3832W to be disabled at least until Vin exceeds the desired output voltage level. The IR3832W operates with an external bias supply from 4.5V to 5.5V, allowing an extended operating input voltage range from 1.0V to 16V. The device utilizes the on-resistance of the low side MOSFET as current sense element, this method enhances the converter’s efficiency and reduces cost by eliminating the need for external current sense resistor. IR3832W includes two low Rds(on) MOSFETs using IR’s HEXFET technology. These are specifically designed for high efficiency applications. Under-Voltage Lockout and POR The under-voltage lockout circuit monitors the input supply Vcc and the Enable input. It assures that the MOSFET driver outputs remain in the off state whenever either of these two signals drop below the set thresholds. Normal operation resumes once Vcc and Enable rise above their thresholds. The POR (Power On Ready) signal is generated when all these signals reach the valid logic level (see system block diagram). When the POR is asserted the soft start sequence starts (see soft start section). Enable The Enable features another level of flexibility for start up. The Enable has precise threshold which is internally monitored by Under-Voltage Lockout (UVLO) circuit. Therefore, the IR3832W will turn on only when the voltage at the Enable pin exceeds this threshold, typically, 1.2V. Rev 4.0 Fig. 3a. Normal Start up, Device turns on when the Bus voltage reaches 10.2V Figure 3b. shows the recommended start-up sequence for the non-tracking operation of IR3832W, when Enable is used as a logic input. Fig. 3b. Recommended startup sequence, Non-Tracking operation 12 PD-97508 IR3832WMPbF Figure 3c. shows the recommended startup sequence for tracking operation of IR3832W with Enable used as logic input. Fig. 5. Pre-Bias startup pulses Soft-Start Fig. 3c. Recommended startup sequence, Sequenced operation Pre-Bias Startup IR3832W is able to start up into pre-charged output, which prevents oscillation and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET off until the first gate signal for control MOSFET is generated. Figure 4 shows a typical Pre-Bias condition at start up. The IR3832W has a programmable soft-start to control the output voltage rise and limit the current surge at the start-up. To ensure correct start-up, the soft-start sequence initiates when the Enable and Vcc rise above their UVLO thresholds and generate the Power On Ready (POR) signal. The internal current source (typically 20uA) charges the external capacitor Css linearly from 0V to 3V. Figure 6 shows the waveforms during the soft start. The start up time can be estimated by: Tstart = V p * CSS 20μA - - - - - - - - - - - - - - - - - - - - (1) During the soft start the OCP is enabled to protect the device for any short circuit and over current condition. The synchronous MOSFET always starts with a narrow pulse width and gradually increases its duty cycle with a step of 25%, 50%, 75% and 100% until it reaches the steady state value. The number of these startup pulses for the synchronous MOSFET is internally programmed. Figure 5 shows a series of 32, 16, 8 startup pulses. Fig. 6. Theoretical operation waveforms during soft-start Fig. 4. Pre-Bias startup Rev 4.0 13 PD-97508 IR3832WMPbF Operating Frequency The switching frequency can be programmed between 250kHz – 1500kHz by connecting an external resistor from Rt pin to Gnd. Table 1 tabulates the oscillator frequency versus Rt. Table 1. Switching Frequency and IOCSet vs. External Resistor (Rt) Rt (kΩ) 47.5 35.7 28.7 23.7 20.5 17.8 15.8 14.3 12.7 11.5 10.7 9.76 9.31 Fs (kHz) 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 Iocset (μA) 29.4 39.2 48.7 59.07 68.2 78.6 88.6 97.9 110.2 121.7 130.8 143.4 150.3 Shutdown The IR3832W can be shutdown by pulling the Enable pin below its 1 V threshold. This will tristate both, the high side driver as well as the low side driver. Alternatively, the output can be shutdown by pulling the soft-start pin below 0.3V. Normal operation is resumed by cycling the voltage at the Soft Start pin. Over-Current Protection The over current protection is performed by sensing current through the RDS(on) of low side MOSFET. This method enhances the converter’s efficiency and reduces cost by eliminating a current sense resistor. As shown in figure 7, an external resistor (ROCSet) is connected between OCSet pin and the switch node (SW) which sets the current limit set point. An internal current source sources current (IOCSet ) out of the OCSet pin. This current is a function of the switching frequency and hence, of Rt. Rev 4.0 I OCSet (μA ) = 1400 .......... .......... ...............( 2) R t (kΩ) Table 1. shows IOCSet at different switching frequencies. The internal current source develops a voltage across ROCSet. When the low side MOSFET is turned on, the inductor current flows through the Q2 and results in a voltage at OCSet which is given by: VOCSet = ( IOCSet ∗ ROCSet ) − ( RDS(on) ∗ I L ) ...........(3) Fig. 7. Connection of over current sensing resistor An over current is detected if the OCSet pin goes below ground. Hence, at the current limit threshold, VOCset=0. Then, for a current limit setting ILimit, ROCSet is calculated as follows: ROCSet = R DS (on) * I Limit IOCSet ........................ (4) An overcurrent detection trips the OCP comparator, latches OCP signal and cycles the soft start function in hiccup mode. The hiccup is performed by shorting the soft-start capacitor to ground and counting the number of switching cycles. The Soft Start pin is held low until 4096 cycles have been completed. The OCP signal resets and the converter recovers. After every soft start cycle, the converter stays in this mode until the overload or short circuit is removed. The OCP circuit starts sampling current typically 160 ns after the low gate drive rises to about 3V. This delay functions to filter out switching noise. 14 PD-97508 IR3832WMPbF Thermal Shutdown Temperature sensing is provided inside IR3832W. The trip threshold is typically set to 140oC. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs and discharges the soft start capacitor. Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 20oC hysteresis in the thermal shutdown threshold. Power Good Output The IC continually monitors the output voltage via Feedback (Fb pin). The Power Good signal is flagged when the Fb pin voltage is above 0.5V and between 85% to 115 % of Vp. This pin is open drain and it needs to be externally pulled high. High state indicates that output is in regulation. Fig. 8a shows the PGood timing diagram for non-tracking operation. In this case, during startup, PGood goes high after the SS voltage reaches 2.1V if the Fb voltage is within the PGood comparator window. Fig. 8a. and Fig 8b. also show a 256 cycle delay between the Fb voltage entering within the thresholds defined by the PGood window and PGood going high. TIMING DIAGRAM OF PGOOD FUNCTION Fig.4A IR3832W Non-Tracking Operation Fig.8b IR3832W Tracking Operation Rev 4.0 15 PD-97508 IR3832WMPbF Minimum on time Considerations Maximum Duty Ratio Considerations The minimum ON time is the shortest amount of time for which the Control FET may be reliably turned on, and this depends on the internal timing delays. For the IR3832W, the typical minimum on-time is specified as 50 ns. Any design or application using the IR3832W must ensure operation with a pulse width that is higher than this minimum on-time and preferably higher than 100 ns. This is necessary for the circuit to operate without jitter and pulseskipping, which can cause high inductor current ripple and high output voltage ripple. A fixed off-time of 200 ns maximum is specified for the IR3832W. This provides an upper limit on the operating duty ratio at any given switching frequency. It is clear, that higher the switching frequency, the lower is the maximum duty ratio at which the IR3832W can operate. To allow a margin of 50ns, the maximum operating duty ratio in any application using the IR3832W should still accommodate about 250 ns off-time. Fig 9. shows a plot of the maximum duty ratio v/s the switching frequency, with 250 ns off-time. = M a x Duty Cycle D Fs Vout Vin × Fs In any application that uses the IR3832W, the following condition must be satisfied: t on (min) ≤ t on ∴ t on (min) ≤ Vout t on(min) The minimum output voltage for the IR3832W is limited to Vout(min) = 0.6 V. ∴ Vin × Fs ≤ 95 90 85 80 75 70 65 60 55 250 Vout Vin × Fs ∴ Vin × Fs ≤ Max D uty C ycle (% ) t on = 450 650 850 1050 1250 1450 1650 S w itching Frequency (kH z ) Fig. 9. Maximum duty cycle v/s switching frequency. Vout (min) ∴ Vin × Fs ≤ t on (min) 0.6 V = 6 × 10 6 V/s 100 ns Furthermore, for the IR3832W, especially for active bus termination applications, it is strongly recommended to use a switching frequency of 400 kHz to obtain clean and jitter free operation in sourcing as well as sinking modes. Therefore, the maximum input voltage that may be stepped down to 0.6V at 400 kHz without jitter or pulse skipping is 15 V. Rev 4.0 16 PD-97508 IR3832WMPbF When an external resistor divider is connected to the output as shown in figure 10. Equation (5) can be rewritten as: Application Information Design Example: The following example is a typical application for IR3832W. The application circuit is shown on page 23. Vin = 12 V ( 13.2V max) Vo = 0.75 V Io = 4 A ⎛ Vp ⎞ ⎟ ..................................(8) R9 = R8 ∗ ⎜ ⎜ V o−Vp ⎟ ⎠ ⎝ For low voltage applications, such as this design, it is often advisable to eliminate the bias resistor R9 from Fb to ground. For the calculated value of R8 see feedback compensation section. ΔVo ≤ 22.5mV Fs = 400 kHz Enabling the IR3832W As explained earlier, the precise threshold of the Enable lends itself well to implementation of a UVLO for the Bus Voltage. V in IR3832W Enable R1 Fig. 10. Typical application of the IR3832W for programming the output voltage R2 Further, the tracking reference Vp may be itself derived from some master reference by means of a resistive divider as shown in Fig. 9. This is common in active bus termination circuits such as Voltage Tracking Termination (VTT) where the tracking reference Vp may be obtained as half of the master reference VDDQ which forms the input to one or more memory banks. In this design, VDDQ=1.5V Rp1=Rp2=1.5 kΩ Vp=0.75V For a typical Enable threshold of VEN = 1.2 V Vin(min) * R2 = VEN = 1.2 .......... (5) R1 + R 2 R 2 = R1 VEN .......... (6) Vin( min ) − VEN For a Vin (min)=10.2V, R1=49.9K and R2=7.50K is a good choice. Programming the frequency For Fs = 400 kHz, select Rt = 35.7 kΩ, using Table. 1. Output Voltage Programming Output voltage is programmed by the tracking reference voltage at Vp and external voltage divider. The divider is ratioed such that the voltage at the Fb pin is equal to the voltage at the Vp pin pin when the output is at its desired value. The output voltage is defined by using the following equation: ⎛ R ⎞ Vo = Vp ∗ ⎜⎜1 + 8 ⎟⎟ ...................................(7) ⎝ R9 ⎠ Rev 4.0 Soft-Start Programming The soft-start timing can be programmed by selecting the soft-start capacitance value. From (1), for a desired start-up time of the converter, the soft start capacitor can be calculated by using: C SS (μF) = Tstart ( ms ) × 0.02857 .......... (9) Where Tstart is the desired start-up time (ms). For tracking applications the output is generally required to track Vp even at start-up. Hence, it is necessary to ensure that the SS pin is already up to 3 V before the tracking reference signal is applied to the Vp pin. This can be done by choosing a small value for the soft-start capacitor to ensure that the voltage at the SS pin rises to 3 V quickly. A 0.022 uF capacitor is chosen for this purpose. 17 PD-97508 IR3832WMPbF Bootstrap Capacitor Selection To drive the Control FET, it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW pin, which is connected the source of the Control FET . This is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (C6), as shown in Fig. 11.. The operation of the circuit is as follows: When the lower MOSFET is turned on, the capacitor node connected to SW is pulled down to ground. The capacitor charges towards Vcc through the internal bootstrap diode, which has a forward voltage drop VD. The voltage Vc across the bootstrap capacitor C6 is approximately given as Vc ≅ Vcc − VD ........................................ (10) When the upper MOSFET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage Vin. However, if the value of C6 is appropriately chosen, the voltage Vc across C6 remains approximately unchanged and the voltage at the Boot pin becomes VBoot ≅ Vin + Vcc − VD ........................................ (11) D= Vo ................................ (13) Vin Where: D is the Duty Cycle IRMS is the RMS value of the input capacitor current. Io is the output current. For Io=4 A and D = 0.0625, the IRMS = 0.97 A Ceramic capacitors are recommended due to their peak current capabilities. They also feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is advisable to have 2x10uF 16V ceramic capacitors ECJ-3YB1C106M from Panasonic. In addition to these, although not mandatory, a 330uF 25V SMD capacitor EEV-FK1E332P from Panasonic may be used as a bulk capacitor, and is recommended if the input power supply is not located close to the converter. Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor value results in a smaller size and faster response to a load transient but poor efficiency and high output noise due to large ripple current. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor (Δi ) . The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: Δi 1 ; Δt = D ∗ Δt Fs .......... .......... ... (14) Vo L = (Vin − Vo ) ∗ Vin ∗ Δi * Fs Vin − Vo = L ∗ Fig. 11. Bootstrap circuit to generate Vc voltage A bootstrap capacitor of value 0.1uF is suitable for most applications. Input Capacitor Selection The ripple current generated during the on time of the upper MOSFET should be provided by the input capacitor. The RMS value of this ripple is expressed by: IRMS = Io ∗ D ∗ (1 − D) ........................(12) Rev 4.0 Where: Vin = Maximum input voltage Vo = Output Voltage Δi = Inductor ripple current F s = Switching frequency Δt = Turn on time D = Duty cycle If Δi ≈ 30%(Io), then the output inductor is calculated to be 1.46μH. Select L=1.50 μH. The MPO104-1R5 from Delta provides a compact, low profile inductor suitable for this application. 18 PD-97508 IR3832WMPbF Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors type and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the : actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components. These components can be described as ΔVo = ΔVo ( ESR ) + ΔVo ( ESL ) + ΔVo ( C ) ⎛ V − Vo ⎞ ΔVo ( ESL ) = ⎜ in ⎟ * ESL ⎝ L ⎠ 1 2 ∗ π Lo ∗ Co ................................ (16) Phase Gain ......................... (15) Δ IL 8 * Co * Fs 0 dB 00 -40dB/decade ΔVo = Output voltage ripple ΔIL = Inductor ripple current Since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. The IR3832W can perform well with all types of capacitors. As a rule, the capacitor must have low enough ESR to meet output ripple and load transient requirements. The goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. Therefore it is advisable to select ceramic capacitors due to their low ESR and ESL and small size. Six of the Panasonic ECJ2FB0J226ML (22uF, 6.3V, 3mOhm) capacitors is a good choice. Feedback Compensation The IR3832W is a voltage mode controller. The control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed-loop transfer function with the highest 0 dB crossing frequency and adequate phase margin (greater than 45o). Rev 4.0 FLC = Figure 12 shows gain and phase of the LC filter. Since we already have 180o phase shift from the output filter alone, the system runs the risk of being unstable. ΔVo ( ESR ) = ΔIL * ESR ΔVo ( C ) = The output LC filter introduces a double pole, –40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180o (see figure 12). The resonant frequency of the LC filter is expressed as follows: -1800 FLC Frequency FLC Frequency Fig. 12. Gain and Phase of LC filter The IR3832W uses a voltage-type error amplifier with high-gain (110dB) and wide-bandwidth. The output of the error amplifier is available for DC gain control and AC phase compensation. The error amplifier can be compensated either in type II or type III compensation. Local feedback with Type II compensation is shown in Fig. 13. This method requires that the output capacitor should have enough ESR to satisfy stability requirements. In general the output capacitor’s ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin. The ESR zero of the output capacitor is expressed as follows: FESR = 1 .......... .......... ....... (17) 2 ∗ π*ESR*C o 19 PD-97508 IR3832WMPbF VOUT Z IN C POLE R3 C4 R8 Zf Fb R9 Gain(dB) E/A Comp Ve To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: Fz = 75%FLC VREF Fz = 0.75* H(s) dB FZ F POLE Frequency Fig. 13. Type II compensation network and its asymptotic gain plot The transfer function (Ve/Vo) is given by: Ve 1 + sR3C4 Z = H(s) = − f = − .....(18) ZIN sR8C4 Vo The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: H(s) = Where: Vin = Maximum Input Voltage Vosc = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R8 = Feedback Resistor R3 ......................................(19) R8 1 Fz = ............................(20) 2π * R3 * C4 First select the desired zero-crossover frequency (Fo): Fo > FESR and Fo ≤ (1/5 ~ 1/10) * Fs Vosc * Fo * FESR * R8 2 Vin * FLC ...........................(21) FP = .....................................(22) 1 .................................(23) C4 * CPOLE 2π * R3 * C4 + CPOLE The pole sets to one half of the switching frequency which results in the capacitor CPOLE: CPOLE = 1 1 π*R3*Fs − C4 ≅ 1 ......................(24) *R π 3*Fs For a general solution for unconditional stability for any type of output capacitors, and a wide range of ESR values, we should implement local feedback with a type III compensation network. The typically used compensation network for voltage-mode controller is shown in figure 14. Again, the transfer function is given by: Ve Z = H(s) = − f Vo ZIN By replacing Zin and Zf according to figure 14, the transfer function can be expressed as: H(s) = − Rev 4.0 2π Lo * Co Use equations (20), (21) and (22) to calculate C4. One more capacitor is sometimes added in parallel with C4 and R3. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: Use the following equation to calculate R3: R3 = 1 (1 + sR3C4 )[1 + sC7 (R8 + R10 )] ⎡ ⎛ C * C3 ⎞⎤ ⎟⎥(1 + sR10C7 ) sR8 (C4 + C3 )⎢1 + sR3 ⎜⎜ 4 ⎟ ⎝ C4 + C3 ⎠⎦⎥ ⎣⎢ ....(25) 20 PD-97508 IR3832WMPbF VOUT ZIN C3 C7 R3 R10 C4 R8 Zf Fb R9 Gain(dB) E/A Comp Ve FZ2 FP2 FP3 Frequency Fig.14. Type III Compensation network and its asymptotic gain plot The compensation network has three poles and two zeros and they are expressed as follows: FP1 = 0 ..................................................................(26) FP 2 = 1 ...............................................(27) 2π * R10 * C7 1 FP3 = FZ1 ≅ 1 ...............(28) 2π * R3 * C3 ⎛ C * C3 ⎞ ⎟ 2π * R3 ⎜⎜ 4 ⎟ ⎝ C4 + C3 ⎠ 1 = .............................................(29) 2π * R3 * C4 FZ 2 = 1 1 ≅ ..........(30) 2π * C7 * (R8 + R10 ) 2π * C7 * R8 Cross over frequency is expressed as: Fo = R3 * C7 * Vin 1 * ................................(31) Vosc 2π * Lo * Co Based on the frequency of the zero generated by the output capacitor and its ESR, relative to crossover frequency, the compensation type can be different. The table below shows the compensation types and location of the crossover frequency. Rev 4.0 FESR vs Fo Output Capacitor Type II FLC<FESR<Fo<Fs/2 Electrolytic Tantalum Type III FLC<Fo<FESR Tantalum Ceramic VREF H(s) dB FZ1 Compensator Type The higher the crossover frequency, the potentially faster the load transient response. However, the crossover frequency should be low enough to allow attenuation of switching noise. Typically, the control loop bandwidth or crossover frequency is selected such that Fo ≤ (1/5 ~ 1/10) * Fs The DC gain should be large enough to provide high DC-regulation accuracy. The phase margin should be greater than 45o for overall stability. For this design we have: Vin=12V Vo=0.75V Vosc=1.8V Vp=0.75V Lo=1.5 uH Co=6x22uF, ESR=3mOhm each It must be noted here that the value of the capacitance used in the compensator design must be the small signal value. For instance, the small signal capacitance of the 22uF capacitor used in this design is 12uF at 0.75 VDC bias and 400 kHz frequency. It is this value that must be used for all computations related to the compensation. The small signal value may be obtained from the manufacturer’s datasheets, design tools or SPICE models. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency FLC and using equation (16) to compute the small signal Co. These result to: FLC=15.31 kHz FESR=4.4 MHz Fs/2=200 kHz Select crossover frequency: Fo= 60 kHz Since FLC<Fo<Fs/2<FESR, TypeIII is selected to place the pole and zeros. 21 PD-97508 IR3832WMPbF Detailed calculation of compensation TypeIII Desired Phase Margin Θ =70 o FZ2 = Fo 1− sin Θ =10.58 kHz 1+ sin Θ FP2 = Fo 1+ sin Θ = 340.28 kHz 1− sin Θ Select: FZ1 = 0.5* FZ2 = 5.29 kHz and FP3 = 0.5* Fs = 200 kHz Select: C7 = 2.2nF Calculate R3 , C3 and C4 : R3 = 2π * Fo * Lo * Co * Vosc ;R3 = 2.78 kΩ C7 * Vin Select: R3 = 3.48 kΩ C4 = 1 ; C4 =10.75nF, Select: C4 =10 nF 2π * FZ1 * R3 C3 = 1 ; C3 = 228 pF, Select: C3 = 220 pF 2π * FP3 * R3 Calculate R10, R8 and R9 : R10 = R8 = 1 ; R10 = 215 Ω, Select: R10 = 210 Ω 2π * C7 * FP2 Programming the Current-Limit The Current-Limit threshold can be set by connecting a resistor (ROCSET) from the SW pin to the OCSet pin. The resistor can be calculated by using equation (4). This resistor ROCSET must be placed close to the IC. The RDS(on) has a positive temperature coefficient and it should be considered for the worst case operation. ISET = IL (critical) = ROCSet∗ IOCSet .......................(32) RDS(on) RDS( on) = 14.3mΩ *1.25 = 17.87 mΩ ISET ≅ Io( LIM) = 4 A *1.5 = 6 A (50% over nominal output current) IOCSet = 39.22μA (at Fs = 400kHz) ROCSet = 2.73kΩ Select R7 = 2.74 kΩ Setting the Power Good Threshold A window comparator internally sets a lower Power Good threshold at 85% of Vp and an upper Power Good threshold at 115% of Vp. When the voltage at the FB pin is within the window set by these thresholds, PGood is asserted. The PGood is an open drain output. Hence, it is necessary to use a pull up resistor RPG from PGood pin to Vcc. The value of the pull-up resistor must be chosen such as to limit the current flowing into the PGood pin, when the output voltage is not in regulation, to less than 5 mA. A typical value used is 10kΩ. 1 - R10; R8 = 6.63 kΩ, 2π * C7 * FZ2 Select: R8 = 6.65 kΩ Rev 4.0 22 PD-97508 IR3832WMPbF Application Diagram: Fig. 15. Application circuit diagram for a 12V to 0.75 V, 4 A Point Of Load Converter Suggested Bill of Materials for the application circuit: Part Reference Cin Lo Co R1 R2 Rt Rocset RPG Css R3 C3 C6 C4 R8 R10 C7 Cp2 CVcc U1 Rev 4.0 Quantity 1 2 1 1 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value 330uF 10uF 0.1uF 1.5uH 22uF 49.9k 7.5k 35.7k 2.74k 10k 0.022uF 3.48k 220pF 0.1uF 2200pF 6.65k 210 2200pF 10nF 1.0uF IR3832W Description SMD Elecrolytic, Fsize, 25V, 20% 1206, 16V, X5R, 20% 0603, 25V, X7R, 10% 11.5x10x4mm, 20%, 1.7mOhm 0805, 6.3V, X5R, 20% Thick Film, 0603,1/10 W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% 0603, 25V, X7R, 10% Thick Film, 0603,1/10W,1% 50V, 0603, NPO, 5% 0603, 25V, X7R, 10% 0603, 50V, X7R, 10% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% 0603, 50V, X7R, 10% 0603, 50V, X7R, 10% 0603, 16V, X5R, 20% SupIRBuck, 4A, PQFN 5x6mm Manufacturer Panasonic TDK Panasonic Delta Panasonic Rohm Rohm Rohm Rohm Rohm Panasonic Rohm Panasonic Panasonic Panasonic Rohm Rohm Panasonic Panasonic Panasonic International Rectifier Part Number EEV-FK1E331P C3216X5R1E106M ECJ-1VB1E104K MPO104-1R5 ECJ-2FB0J226ML MCR03EZPFX4992 MCR03EZPFX7501 MCR03EZPFX3572 MCR03EZPFX2741 MCR03EZPFX1002 ECJ-1VB1E223K MCR03EZPFX3481 ECJ-1VC1H221J ECJ-1VB1E104K ECJ-1VB1H223K MCR03EZPFX6651 ERJ-3EKF2100V ECJ-1VB1H222K ECJ-1VB1H103K ECJ-BVB1C105M IR3832WMPbF 23 PD-97508 IR3832WMPbF TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=5V, Vo=0.75V, Io=0- ±4A, Room Temperature, No Air Flow Fig. 16: Start up at 4A, sourcing current Ch1:PGood, Ch2:Vout, Ch3:VDDQ, Ch4:SS Fig. 17: Start up with Prebias, 0A Load Ch1:PGood, Ch2:Vout,Ch3:VDDQ, Ch4:SS Fig. 18: Inductor node at 4A, sourcing current, Ch3:SW, Ch4:Iout Fig. 19: Inductor node at -3A, sinking current, Ch3:SW , Ch4:Iout Fig. 20: Output Voltage Ripple, 4A, sourcing current, Ch2: Vout Fig. 21: Short (Hiccup) Recovery Ch2:Vout, Ch3:VSS , Ch4:PGood Rev 4.0 24 PD-97508 IR3832WMPbF TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=0.75V, Room Temperature, No Air Flow Fig. 22: Tracking 4A, sourcing current, Ch2:Vout, Ch3:VDDQ, Ch4:PGood Fig. 23: Tracking -3A load, sinking current, Ch2:Vout, Ch3:VDDQ, Ch4:PGood Fig. 24: Transient Response, 1A/us -0.5A to +0.5A load , Ch2:Vout, Ch4:Io Rev 4.0 25 PD-97508 IR3832WMPbF TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=0.75V, Io=+4A, Room Temperature, No Air Flow Fig.25: Bode Plot at 4A load (sourcing current) shows a bandwidth of 65kHz and phase margin of 60 degrees Rev 4.0 26 PD-97508 IR3832WMPbF Layout Considerations The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Make all the connections for the power components in the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The inductor, output capacitors and the IR3832W should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly at the Vin pin of IR3832W. The feedback part of the system should be kept away from the inductor and other noise sources. The critical bypass components such as capacitors for Vcc should be close to their respective pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. The connection between the OCSet resistor and the Sw pin should not share any trace with the connection between the bootstrap capacitor and the Sw pin. Instead, it is recommended to use a Kelvin connection of the trace from the OCSet resistor and the trace from the bootstrap Vin capacitor at the Sw pin. PGnd In a multilayer PCB use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not Vout interfere with the more sensitive analog control AGnd function. These two grounds must be connected together on the PC board layout at a single point. The Power QFN is a thermally enhanced package. Based on thermal performance it is recommended to use at least a 4-layers PCB. To effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. Figure 26 illustrates the implementation of the layout guidelines outlined above, on a 4 layer board. Vin PGnd Vout AGnd Enough copper & minimum length ground path between Input and Output PGnd Compensation parts should be placed as close as possible to the Comp pin. Vin Vin Resistors Rt and Rocset should be placed as close as possible to their pins. All bypass caps should be placed as close as possible to their connecting pins. PGnd AGnd AGnd Vout Vout Fig. 26a. IR3832W layout considerations – Top Layer Rev 4.0 27 PD-97508 IR3832WMPbF PGnd Feedback trace should be kept away form noise sources Fig. 26b. IR3832W layout considerations – Bottom Layer Analog Ground plane Power Vin Ground Plane Single point connection between AGND & PGND, should be close to the SupIRBuck, kept away from noise sources. AGnd Fig. 26c. IR3832W layout considerations – Mid Layer 1 Use separate traces for connecting Boot cap and Rocset to the switch node and with the minimum length traces. Avoid big loops. Fig. 26d. IR3832W layout considerations – Mid Layer 2 Rev 4.0 28 PD-97508 IR3832WMPbF PCB Metal and Components Placement Lead lands (the 11 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large and inspectable toe fillet. Pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper and no less than 0.23mm for 3 oz. Copper. Rev 4.0 29 PD-97508 IR3832WMPbF Solder Resist It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist mis-alignment. Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. Rev 4.0 30 PD-97508 IR3832WMPbF Stencil Design • • The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will be open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. Rev 4.0 31 PD-97508 IR3832WMPbF BOTTOM VIEW IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (320) 252-7105 TAC Fax: (320) 252-7903 This product has been designed and qualified for the Consumer market Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 11/10 Rev 4.0 32