a FEATURES Fast (2.4 s) 14-Bit ADC Four Simultaneously Sampled Inputs Four Track/Hold Amplifiers 0.35 s Track/Hold Acquisition Time 2.4 s Conversion Time per Channel HW/SW Select of Channel Sequence for Conversion Single Supply Operation Selection of Input Ranges: 10 V, 5 V and 2.5 V, 0 V to 5 V and 0 V to 2.5 V High Speed Parallel Interface Which Also Allows Interfacing to 3 V Processors Low Power, 115 mW Typ Power Saving Mode, 15 W Typ Overvoltage Protection on Analog Inputs Four-Channel, Simultaneous Sampling, Fast, 14-Bit ADC AD7865 FUNCTIONAL BLOCK DIAGRAM VREF AVDD STBY VIN1A VIN1B VIN2A VIN2B VIN3A VIN3B VIN4A VIN4B VREFAGND 6k VDRIVE +2.5V REFERENCE TRACK/HOLD 4 DGND AD7865 SIGNAL SCALING SIGNAL SCALING DVDD AGND RD MUX SIGNAL SCALING 14-BIT ADC OUTPUT LATCH CHANNEL SELECT REGISTER SIGNAL SCALING DB13 DB0 DB0–DB3 CS WR FRSTDATA APPLICATIONS AC Motor Control Uninterruptible Power Supplies Industrial Power Meters/Monitors Data Acquisition Systems Communications GENERAL DESCRIPTION The AD7865 is a fast, low power, four-channel simultaneous sampling 14-bit A/D converter that operates from a single 5 V supply. The part contains a 2.4 µs successive approximation ADC, four track/hold amplifiers, 2.5 V reference, on-chip clock oscillator, signal conditioning circuitry and a high speed parallel interface. The input signals on four channels are sampled simultaneously thus preserving the relative phase information of the signals on the four analog inputs. The part accepts analog input ranges of ± 10 V, ± 5 V, ± 2.5 V, 0 V to 2.5 V and 0 V to 5 V. The part allows any subset of the four channels to be converted in order to maximize the throughput rate on the selected sequence. The channels to be converted can be selected either via hardware (channel select input pins) or via software (programming the channel select register). A single conversion start signal (CONVST) simultaneously places all the track/holds into hold and initiates conversion sequence for the selected channels. The EOC signal indicates the end of each individual conversion in the selected conversion sequence. The BUSY signal indicates the end of the conversion sequence. Data is read from the part via a 14-bit parallel data bus using the standard CS and RD signals. Maximum throughput for a single channel is 350 kSPS. For all four channels the maximum throughput is 100 kSPS. BUSY EOC CONVERSION CONTROL LOGIC CONVST INT/EXT CLOCK SELECT INT CLOCK SL3 SL4 H/S CLK IN INT/EXT AGND AGND SEL /SL1 CLK/SL2 The AD7865 is available in a small (0.3 sq. inch area) 44-lead PQFP. PRODUCT HIGHLIGHTS 1. The AD7865 features four Track/Hold amplifiers and a fast (2.4 µs) ADC allowing simultaneous sampling and then conversion of any subset of the four channels. 2. The AD7865 operates from a single 5 V supply and consumes only 115 mW typ, making it ideal for low power and portable applications. 3. The part offers a high speed parallel interface for easy connection to microprocessors, microcontrollers and digital signal processors. 4. The part is offered in three versions with different analog input ranges. The AD7865-1 offers the standard industrial ranges of ± 10 V and ± 5 V; the AD7865-2 offers a unipolar range of 0 V to 2.5 V or 0 V to 5 V and the AD7865-3 offers the common signal processing input range of ± 2.5 V. 5. The part features very tight aperture delay matching between the four input sample and hold amplifiers. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 (VDD = 5 V 5%, AGND = DGND = 0 V, VREF = Internal. Clock = Internal; all specifiMIN to TMAX unless otherwise noted.) AD7865–SPECIFICATIONS cations T Parameter A, Y Versions1 B Version Unit SAMPLE AND HOLD –3 dB Full Power Bandwidth Aperture Delay Aperture Jitter Aperture Delay Matching 3 20 50 4 3 20 50 4 MHz typ ns max ps typ ns max DYNAMIC PERFORMANCE2 Signal to (Noise + Distortion) Ratio 3 @ 25°C AD7865-1, AD7865-3 AD7865-2 TMIN to TMAX AD7865-1, AD7865-3 AD7865-2 Total Harmonic Distortion 3, 4 Peak Harmonic or Spurious Noise 3, 4 Intermodulation Distortion3 2nd Order Terms 3rd Order Terms Channel-to-Channel Isolation 3, 5 DC ACCURACY Resolution Relative Accuracy (INL)3 Differential Nonlinearity (DNL) 3 AD7865-1 Positive Gain Error3 Positive Gain Error Match3 Negative Gain Error3 Negative Gain Error Match3 Bipolar Zero Error Bipolar Zero Error Match AD7865-2 Positive Gain Error3 Positive Gain Error Match3 Unipolar Offset Error3 Unipolar Offset Error Match3 AD7865-3 Positive Gain Error3 Positive Gain Error Match3 Negative Gain Error3 Negative Gain Error Match3 Bipolar Zero Error Bipolar Zero Error Match ANALOG INPUTS AD7865-1 Input Voltage Range Input Current AD7865-2 Input Voltage Range Input Current AD7865-3 Input Voltage Range Input Current Test Conditions/Comments fIN = 100 kHz, fS = 350 kSPS 78 77 78 77 dB min dB min Typically 80 dB Typically 78 dB 77 76 –86 –86 77 76 –86 –86 dB min dB min dB max dB max –95 –95 –88 –95 –95 –88 dB typ dB typ dB max 14 ±2 ±1 14 ± 1.5 ±1 Bits LSB max LSB max Typically 0.6 LSBs No Missing Codes Guaranteed ± 10 8 ± 10 8 ± 12 6 ±8 8 ±8 8 ± 10 6 LSB max LSB max LSB max LSB max LSB max LSB max Typically ± 2 LSBs Typically 2 LSBs Typically ± 2 LSBs Typically 2 LSBs Typically ± 2 LSBs Typically 1.5 LSBs ± 16 8 ± 10 10 ± 16 8 ± 10 10 LSB max LSB max LSB max LSB max Typically ± 2 LSBs Typically 2 LSBs Typically ± 2 LSBs Typically 2 LSBs ± 16 8 ± 16 8 ± 14 8 ± 14 8 ± 14 8 ± 12 6 LSB max LSB max LSB max LSB max LSB max LSB max Typically ± 6 LSBs Typically 2 LSBs Typically ± 6 LSBs Typically 2 LSBs Typically ± 5 LSBs Typically 2 LSBs ± 5, ± 10 1, 1 ± 5, ± 10 1, 1 Volts mA max 0 V to 2.5 V, 0 V to 5 V 10 1 0 V to 2.5 V, 0 V to 5 V 10 1 Volts µA max mA max VIN = 2.5 V, 0 V to 2.5 V Range, Typ 1 µA VIN = 5 V, 0 V to 5 V Range, Typ 0.7 mA ± 2.5 1 ± 2.5 1 Volts mA max VIN = –2.5 V, Typically 0.7 mA fa = 49 kHz, fb = 50 kHz fIN = 50 kHz Sine Wave Any Channel –2– VIN = –5 V and –10 V Respectively, Typically 0.7 mA REV. B AD7865 Parameter A, Y Versions1 B Version Unit Test Conditions/Comments REFERENCE INPUT/OUTPUT VREF IN Input Voltage Range VREF IN Input Capacitance 6 VREF OUT Output Voltage VREF OUT Error @ 25°C VREF OUT Error TMIN to TMAX VREF OUT Temperature Coefficient VREF OUT Output Impedance 2.375/2.625 10 2.5 ± 10 ± 20 25 6 2.375/2.625 10 2.5 ± 10 ± 20 25 6 VMIN/VMAX pF max V nom mV max mV max ppm/°C typ kΩ typ 2.5 V ± 5% LOGIC INPUTS Input High Voltage, V INH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN6 2.4 0.8 ± 10 10 2.4 0.8 ± 10 10 V min V max µA max pF max VDD = 5 V ± 5% VDD = 5 V ± 5% 4.0 0.4 4.0 0.4 V min V max ISOURCE = 400 µA ISINK = 1.6 mA ± 10 10 ± 10 10 µA max pF max LOGIC OUTPUTS Output High Voltage, V OH Output Low Voltage, V OL DB13–DB0 High Impedance Leakage Current Capacitance6 Output Coding AD7865-1, AD7865-3 AD7865-2 CONVERSION RATE Conversion Time Track/Hold Acquisition Time 2, 3 Throughput Time POWER REQUIREMENTS VDD IDD AD7865-1 Normal Mode Standby Mode AD7865-2 Normal Mode Standby Mode AD7865-3 Normal Mode Standby Mode Power Dissipation AD7865-1 Normal Mode Standby Mode AD7865-2 Normal Mode Standby Mode AD7865-3 Normal Mode Standby Mode Two’s Complement Straight (Natural) Binary 2.4 0.35 350 100 2.4 0.35 350 100 µs max µs max kSPS max kSPS max For Single Channel For All Four Channels 5 5 V nom ± 5% for Specified Performance 32 20 32 20 mA max µA max 30 20 30 20 mA max µA max 32 20 32 20 mA max µA max 160 100 160 100 mW max µW max Typically 115 mW. VDD = 5 V Typically 15 µW 150 100 150 100 mW max µW max Typically 100 mW. VDD = 5 V Typically 15 µW 160 100 160 100 mW max µW max Typically 115 mW. VDD = 5 V Typically 15 µW For Single Channel Typically 23 mA, Logic Inputs = 0 V or VDD Typically 20 mA, Logic Inputs = 0 V or VDD Typically 23 mA, Logic Inputs = 0 V or VDD NOTES 1 Temperature ranges are as follows : A, B Versions: –40°C to +85°C, Y Version: –40°C to +105°C. 2 Performance measured through full channel (SHA and ADC). 3 See Terminology. 4 Total Harmonic Distortion and Peak Harmonic or Spurious Noise are specified at –83 dBs for the AD7865-2. 5 Measured between any two channels with the other two channels grounded. 6 Sample tested @ 25°C to ensure compliance. Specifications subject to change without notice. REV. B See Reference Section –3– AD7865 TIMING CHARACTERISTICS1, 2 (VDD = 5 V 5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; all specifications TMIN to TMAX unless otherwise noted.) Parameter A, B, Y Versions Unit Test Conditions/Comments tCONV 2.4 3.2 0.35 No. of Channels × (tCONV) 1 35 70 µs max µs max µs max µs max µs max ns min ns min Conversion Time, Internal Clock Conversion Time, External Clock (5 MHz) Acquisition Time Selected Number of Channels Multiplied by tCONV 0 0 35 35 40 5 30 15 120 180 70 15 0 ns min ns min ns min ns max ns max ns min ns max ns min ns min ns max ns max ns max ns min CS to RD Setup Time CS to RD Hold Time Read Pulsewidth Data Access Time after Falling Edge of RD, VDRIVE = 5 V Data Access Time after Falling Edge of RD, VDRIVE = 3 V Bus Relinquish Time after Rising Edge of RD 20 0 0 5 5 ns min ns min ns min ns min ns min WR Pulsewidth CS to WR Setup Time WR to CS Hold Time Input Data Setup Time of Rising Edge of WR Input Data Hold Time 200 ns min CONVST Falling Edge to CLK Rising Edge tACQ tBUSY tWAKE-UP —External VREF3 t1 t2 Read Operation t3 t4 t5 t6 4 t7 5 t8 t9 t10 t11 t12 Write Operation t13 t14 t15 t16 t17 External Clock t18 STBY Rising Edge to CONVST Rising Edge CONVST Pulsewidth CONVST Rising Edge to BUSY Rising Edge Time Between Consecutive Reads EOC Pulsewidth RD Rising Edge to FRSTDATA Edge (Rising or Falling) EOC Falling Edge to FRSTDATA Falling Delay EOC to RD Delay NOTES 1 Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figures 6, 7 and 8. 3 Refer to the Standby Mode Operation section. The MAX specification of 1 µs is valid when using a 0.1 µF decoupling capacitor on the V REF pin. 4 Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 5 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications subject to change without notice. 1.6mA TO OUTPUT PIN 1.6V 50pF 400A Figure 1. Load Circuit for Access Time and Bus Relinquish Time –4– REV. B AD7865 ABSOLUTE MAXIMUM RATINGS* Operating Temperature Range Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C Automotive (Y Version) . . . . . . . . . . . . . . –40°C to +105°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C PQFP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C (TA = 25°C unless otherwise noted) VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VDRIVE to DGND . . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V Analog Input Voltage to AGND AD7865-1 (± 10 V Input Range) . . . . . . . . . . . . . . . . ± 18 V AD7865-1 (± 5 V Input Range) . . . . . . . . . . . . . . . . . . ± 9 V AD7865-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to +18 V AD7865-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . –4 V to +18 V Reference Input Voltage to AGND . . . –0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V Digital Output Voltage to DGND . . . . –0.3 V to VDD + 0.3 V *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Input Ranges Relative Accuracy Temperature Ranges Package Description Package Option AD7865AS-1 AD7865BS-1 AD7865YS-1 AD7865AS-2 AD7865BS-2 AD7865YS-2 AD7865AS-3 AD7865BS-3 AD7865YS-3 ± 5 V, ± 10 V ± 5 V, ± 10 V ± 5 V, ± 10 V 0 V to 2.5 V, 0 V to 5 V 0 V to 2.5 V, 0 V to 5 V 0 V to 2.5 V, 0 V to 5 V ± 2.5 V ± 2.5 V ± 2.5 V ± 2 LSB ± 1.5 LSB ± 2 LSB ± 2 LSB ± 1.5 LSB ± 2 LSB ± 2 LSB ± 1.5 LSB ± 2 LSB –40°C to +85°C –40°C to +85°C –40°C to +105°C –40°C to +85°C –40°C to +85°C –40°C to +105°C –40°C to +85°C –40°C to +85°C –40°C to +105°C Plastic Lead Quad Flatpack Plastic Lead Quad Flatpack Plastic Lead Quad Flatpack Plastic Lead Quad Flatpack Plastic Lead Quad Flatpack Plastic Lead Quad Flatpack Plastic Lead Quad Flatpack Plastic Lead Quad Flatpack Plastic Lead Quad Flatpack S-44 S-44 S-44 S-44 S-44 S-44 S-44 S-44 S-44 DVDD DB6 DGND VDRIVE DB5 DB3 DB4 DB2 DB1 EOC DB0 PIN CONFIGURATION 44 43 42 41 40 39 38 37 36 35 34 BUSY 1 FRSTDATA 2 33 DB7 PIN 1 IDENTIFIER 32 DB8 CONVST 3 31 DB9 CS 4 30 DB10 RD 5 AD7865 29 DB11 WR 6 TOP VIEW (Not to Scale) 28 DB12 CLK IN/SL1 7 INT/EXT CLK/SL2 27 DB13 8 26 AGND SL3 9 25 AVDD SL4 10 24 VREF H/S SEL 11 23 AGND VIN1A STBY VIN1B VIN2B VIN2A AGND VIN3A VIN3B VIN4A VIN4B AGND 12 13 14 15 16 17 18 19 20 21 22 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7865 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –5– WARNING! ESD SENSITIVE DEVICE AD7865 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description 1 BUSY 2 FRSTDATA 3 CONVST 4 5 CS RD 6 WR 7 CLK IN/SL1 8 INT/EXT CLK/SL2 9, 10 SL3, SL4 11 H/S SEL 12 AGND 13–16 17 VIN4x, VIN3x AGND 18–21 22 VIN2x, VIN1x STBY 23 AGND Busy Output. The busy output is triggered high by the rising edge of CONVST and remains high until conversion is completed on all selected channels. First Data Output. FRSTDATA is a logic output which, when high, indicates that the Output Data Register Pointer is addressing Register 1—See Accessing the Output Data Registers. Convert Start Input. Logic Input. A low-to-high transition on this input puts all track/holds into their hold mode and starts conversion on the selected channels. In addition, the state of the Channel Sequence Selection is also latched on the rising edge of CONVST. Chip Select Input. Active low logic input. The device is selected when this input is active. Read Input. Active low logic input which is used in conjunction with CS low to enable the data outputs. Ensure the WR pin is at logic high while performing a read operation. Write Input. A rising edge on the WR input, with CS low and RD high, latches the logic state on DB0 to DB3 into the channel select register. Conversion Clock Input/Hardware Channel Select. The function of this pin depends upon the H/S SEL input. When the H/S SEL input is high (choosing software control of the channel selection sequence), this pin assumes its CLK IN function. CLK IN is an externally applied clock (that is only necessary when INT/EXT CLK is high) this allows the user to control the conversion rate of the AD7865. Each conversion needs 16 clock cycles in order for the conversion to be completed. The clock should have a duty cycle that is no greater than 60/40. See Using an External Clock. When the H/S SEL input is low (choosing hardware control of the channel conversion sequence), this pin assumes its Hardware Channel Select function. The SL1 input determines whether Channel 1 is included in the channel conversion sequence. The selection is latched on the rising edge of CONVST. See Selecting a Conversion Sequence. Internal/External Clock/Hardware Channel Select. The function of this pin depends upon the H/S SEL input. When the H/S SEL input is high (choosing software control of the channel selection sequence), this pin assumes its INT/EXT CLK function. When INT/EXT CLK is at a Logic 0, the AD7865 uses its internally generated master clock. When INT/EXT CLK is at Logic 1, the master clock is generated externally to the device and applied to CLK IN. When the H/S SEL input is low (choosing hardware control of the channel conversion sequence), this pin assumes its Hardware Channel Select function. The SL2 input determines whether Channel 2 is included in the channel conversion sequence. The selection is latched on the rising edge of CONVST. When H/S is at Logic 1 these pins have no function and can be tied to Logic 1 or Logic 0. See Selecting a Conversion Sequence. Hardware Channel Select. When the H/S SEL input is at Logic 0, the SL3 input determines whether Channel 3 is included in the channel conversion sequence while SL4 determines whether Channel 4 is included in the channel conversion sequence. When the pin is at Logic 1, the channel is included in the conversion sequence. When the pin is at Logic 0, the channel is excluded from the conversion sequence. The selection is latched on the rising edge of CONVST. See Selecting a Conversion Sequence. Hardware/Software Select Input. When this pin is at a Logic 0, the AD7865 conversion sequence selection is controlled via the SL1–SL4 input pins and runs off an internal clock. When this pin is at Logic 1, the conversion sequence is controlled via the channel select register and allows the ADC to run with an internal or external clock. See Selecting a Conversion Sequence. Analog Ground. General Analog Ground. This AGND pin should be connected to the system’s AGND plane. Analog Inputs. See Analog Input section. Analog Ground. Analog Ground reference for the attenuator circuitry. This AGND pin should be connected to the system’s AGND plane. Analog Inputs. See Analog Input section. Standby Mode Input. This pin is used to put the device into the power save or standby mode. The STBY input is high for normal operation and low for standby operation. Analog Ground. General Analog Ground. This AGND pin should be connected to the system’s AGND plane. –6– REV. B AD7865 Pin Mnemonic Description 24 VREF 25 AVDD 26 AGND 27–34 DB13–DB6 35 DVDD 36 VDRIVE 37 DGND 38, 39 40–43 DB5, DB4 DB3–DB0 44 EOC Reference Input/Output. This pin provides access to the internal reference (2.5 V ± 20 mV) and also allows the internal reference to be overdriven by an external reference source (2.5 V ± 5%). A 0.1 µF decoupling capacitor should be connected between this pin and AGND. Analog Positive Supply Voltage, 5.0 V ± 5%. A 0.1 µF decoupling capacitor should be connected between this pin and AGND. Analog Ground. General Analog Ground. This AGND pin should be connected to the system’s AGND plane. Data Bit 13 is the MSB, followed by Data Bit 12 to Data Bit 6. Three-state TTL outputs. Output coding is twos complement for AD7865-1 and AD7865-3, and straight binary for AD7865-2. Positive Supply Voltage for Digital section, 5.0 V ± 5%. A 0.1 µF decoupling capacitor should be connected between this pin and AGND. Both DVDD and AVDD should be externally tied together. This pin provides the positive supply voltage for the output drivers (DB0 to DB13), BUSY, EOC and FRSTDATA. It is normally tied to DVDD. VDRIVE should be decoupled with a 0.1 µF capacitor. It allows improved performance when reading during the conversion sequence. Also, the output data drivers may be powered by a 3 V ± 10% supply to facilitate interfacing to 3 V processors and DSPs. Digital Ground. Ground reference for Digital circuitry. This DGND pin should be connected to the system’s DGND plane. The system’s DGND and AGND planes should be connected together at one point only, preferably at an AGND pin. Data Bit 5 to Data Bit 4. Three-state TTL outputs. Data Bit 3 to Data Bit 0. Bidirectional data pins. When a read operation takes place, these pins are three-state TTL outputs. The channel select register is programmed with the data on the DB0–DB3 pins with standard CS and WR signals. DB0 represents Channel 1 and DB3 represents Channel 4. End-of-Conversion. Active low logic output indicating conversion status. The end of each conversion in a conversion sequence is indicated by a low going pulse on this line. REV. B –7– AD7865 TERMINOLOGY Channel-to-Channel Isolation Signal to (Noise + Distortion) Ratio Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale 10 kHz sine wave signal to one channel and a 50 kHz signal to another channel and measuring how much of that signal is coupled onto the first channel. The figure given is the worst case across all four channels of the AD7865. This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Relative Accuracy Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus for a 14-bit converter, this is 86.04 dB. Differential Nonlinearity Total Harmonic Distortion This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7865 it is defined as: ( ) THD dB = 20 log Positive Gain Error (AD7865-1, AD7865-3) This is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal 4 × VREF – 3/2 LSB (AD7865 at ± 10 V), 2 × V REF – 3/2 LSB (AD7865 at ± 5 V range) or VREF – 3/2 LSB (AD7865 at ± 2.5 V range), after the Bipolar Offset Error has been adjusted out. V22 + V32 + V42 + V52 + V62 V1 where V1 is the rms amplitude of the fundamental and V2, V3, V4 and V5 are the rms amplitudes of the second through the fifth harmonics. Positive Gain Error (AD7865-2) This is the deviation of the last code transition (111 . . . 110 to 111 . . . 111) from the ideal 2 × VREF – 3/2 LSB (AD7865 at 0 V to 5 V), VREF – 3/2 LSB (AD7865 at 0 V to 2.5 V) after the Unipolar Offset Error has been adjusted out. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. Unipolar Offset Error (AD7865-2) This is the deviation of the first code transition (000 . . . 000 to 000 . . . 001) from the ideal AGND + 1/2 LSB. Bipolar Zero Error (AD7865-1, AD7865-3) This is the deviation of the midscale transition (all 0s to 1s) from the ideal AGND – 1/2 LSB. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). Negative Gain Error (AD7865-1, AD7865-3) This is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal –4 × VREF + 1/2 LSB (AD7865 at ± 10 V), –2 × VREF + 1/2 LSB (AD7865 at ± 5 V range) or –VREF + 1/2 LSB (AD7865 at ± 2.5 V range), after Bipolar Zero Error has been adjusted out. Track/Hold Acquisition Time The AD7865 is tested using two input frequencies. In this case, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ± 1/2 LSB, after the end of conversion (the point at which the track/hold returns to track mode). It also applies to situations where there is a step input change on the input voltage applied to the selected VINxA/VINxB input of the AD7865. It means that the user must wait for the duration of the track/hold acquisition time after the end of conversion or after a step input change to VINxA/VINxB before starting another conversion, to ensure that the part operates to specification. –8– REV. B AD7865 CONVERTER DETAILS Track/Hold Section The AD7865 is a high speed, low power, four-channel simultaneous sampling 14-bit A/D converter that operates from a single 5 V supply. The part contains a 2.4 µs successive approximation ADC, four track/hold amplifiers, an internal 2.5 V reference and a high speed parallel interface. There are four analog inputs which can be sampled simultaneously, thus preserving the relative phase information of the signals on all four analog inputs. Thereafter, conversions will be completed on the selected subset of the four channels. The part accepts an analog input range of ± 10 V or ± 5 V (AD7865-1), 0 V to 2.5 V or 0 V to 5 V (AD7865-2) and ± 2.5 V (AD7865-3). Overvoltage protection on the analog inputs for the part allows the input voltage to go to ±18 V (AD7865-1 with ± 10 V input range), ±9 V (AD7865-1 with ± 5 V input range), –1 V to +18 V (AD7865-2) and –4 V to +18 V (AD7865-3) without causing damage or effecting the conversion result of another channel. The AD7865 has two operating modes Reading Between Conversions and Reading after the Conversion Sequence. These modes are discussed in more detail in the Timing and Control section. A conversion is initiated on the AD7865 by pulsing the CONVST input. On the rising edge of CONVST, all four on-chip track/ holds are simultaneously placed into hold and the conversion sequence is started on all the selected channels. Channel selection is made via the SL1–SL4 pins if H/S SEL is logic zero, or via the channel select register if H/S SEL is logic one—see Selecting a Conversion Sequence. The channel select register is programmed via the bidirectional data lines DB0–DB3 and a standard write operation. The selected conversion sequence is latched on the rising edge of CONVST so changing a selection will only take effect once a new conversion sequence is initiated. The BUSY output signal is triggered high on the rising edge of CONVST and will remain high for the duration of the conversion sequence. The conversion clock for the part is generated internally using a laser-trimmed clock oscillator circuit. There is also the option of using an external clock, by tying the INT/EXT CLK pin logic high and applying an external clock to the CLKIN pin. However, the optimum throughput is obtained by using the internally generated clock— see Using an External Clock. The EOC signal indicates the end of each conversion in the conversion sequence. The BUSY signal indicates the end of the full conversion sequence and at this time all four Track and Holds return to tracking mode. The conversion results can either be read at the end of the full conversion sequence (indicated by BUSY going low) or as each result becomes available (indicated by EOC going low). Data is read from the part via a 14-bit parallel data bus with standard CS and RD signals—see Timing and Control. The track/hold amplifiers on the AD7865 allows the ADCs to accurately convert an input sine wave of full-scale amplitude to 14-bit accuracy. The input bandwidth of the track/hold is greater than the Nyquist rate of the ADC even when the ADC is operated at its maximum throughput rate of 350 kSPS (i.e., the track/hold can handle input frequencies in excess of 175 kHz). Conversion time for each channel of the AD7865 is 2.4 µs and the track/hold acquisition time is 0.35 µs. To obtain optimum performance from the part, the read operation should not occur during a channel conversion or during the 100 ns prior to the next CONVST rising edge. This allows the part to operate at throughput rates up to 100 kHz for all four channels and achieve data sheet specifications. REV. B The track/hold amplifiers acquire input signals to 14-bit accuracy in less than 350 ns. The operation of the track/holds are essentially transparent to the user. The four track/hold amplifiers sample their respective input channels simultaneously, on the rising edge of CONVST. The aperture time for the track/ holds (i.e., the delay time between the external CONVST signal and the track/hold actually going into hold) are typically 15 ns and, more importantly, is well matched across the four track/ holds on one device and also well matched from device to device. This allows the relative phase information between different input channels to be accurately preserved. It also allows multiple AD7865s to sample more than four channels simultaneously. At the end of a conversion sequence, the part returns to its tracking mode. The acquisition time of the track/hold amplifiers begins at this point. The autozero section of the track/hold circuit is designed to work with input slew rates of up to 4 × π × (Full-Scale Span). This corresponds to a full-scale sine wave of up to 4 MHz for any input range. Slew rates above this level within the acquisition time may cause an incorrect conversion result to be returned from the AD7865. Reference Section The AD7865 contains a single reference pin, labelled VREF, which either provides access to the part’s own 2.5 V reference or allows an external 2.5 V reference to be connected to provide the reference source for the part. The part is specified with a 2.5 V reference voltage. The AD7865 contains an on-chip 2.5 V reference. To use this reference as the reference source for the AD7865, simply connect a 0.1 µF disc ceramic capacitor from the VREF pin to AGND. The voltage that appears at this pin is internally buffered before being applied to the ADC. If this reference is required for use external to the AD7865, it should be buffered as the part has a FET switch in series with the reference output, resulting in a source impedance for this output of 6 kΩ nominal. The tolerance on the internal reference is ± 10 mV at 25°C with a typical temperature coefficient of 25 ppm/°C and a maximum error over temperature of ± 20 mV. If the application requires a reference with a tighter tolerance or the AD7865 needs to be used with a system reference, the user has the option of connecting an external reference to this VREF pin. The external reference will effectively overdrive the internal reference and thus provide the reference source for the ADC. The reference input is buffered before being applied to the ADC with the maximum input current of ± 100 µA. Suitable reference sources for the AD7865 include the AD680, AD780, REF192 and REF43 precision 2.5 V references. –9– AD7865 CIRCUIT DESCRIPTION Analog Input Section The AD7865 is offered as three part types, the AD7865-1 where each input can be configured for ± 10 V or a ± 5 V input voltage range, the AD7865-3 which handles input voltage range ± 2.5 V and the AD7865-2 which has an input voltage range of 0 V to 2.5 V or 0 V to 5 V. The amount of current flowing into the analog input will depend on the analog input range and the analog input voltage. The maximum current flows when negative full scale is applied. AD7865-1 Figure 2 shows the analog input section of the AD7865-1. Each input can be configured for ± 5 V or ± 10 V operation on the AD7865-1. For ± 5 V operation, the VINxA and VINxB inputs are tied together and the input voltage is applied to both. For ± 10 V operation, the VINxB input is tied to AGND and the input voltage is applied to the VINxA input. The VINxA and VINxB inputs are symmetrical and fully interchangeable. Thus for ease of PCB layout on the ± 10 V range, the input voltage may be applied to the VINxB input while the VINxA input is tied to AGND. 2.5V REFERENCE NOTES 1 FSR is full-scale range and is 20 V for the ± 10 V range and 10 V for the ± 5 V range, with VREF = 2.5 V. 2 1 LSB = FSR/16384 = 1.22 mV (± 10 V—AD7865-1) and 610.4 mV (± 5 V— AD7865-1) with VREF = 2.5 V. AD7865-2 Figure 3 shows the analog input section of the AD7865-2. Each input can be configured for 0 V to 5 V operation or 0 V to 2.5 V operation. For the 0 V to 5 V operation, the VINxB input is tied to AGND and the input voltage is applied to VINxA input. For 0 V to 2.5 V operation, the VINxA and VINxB inputs are tied together and the input voltage is applied to both. The VINxA and VINxB inputs are symmetrical and fully interchangeable. Thus for ease of PCB layout on the 0 V to 5 V range the input voltage may be applied to the VINxB input while the VINxA input is tied to AGND. For the AD7865-2, R1 = 4 kΩ and R2 = 4 kΩ. Once again, the designed code transitions occur on successive integer LSB values. Output coding is straight (natural) binary with 1 LSB = FSR/16384 = 2.5 V/16384 = 0.153 mV, and 5 V/16384 = 0.305 mV, for 0 V to 2.5 V and 0 V to 5 V options respectively. Table II shows the ideal input and output transfer function for the AD7865-2. AD7865-1 2.5V REFERENCE 6k TO ADC REFERENCE CIRCUITRY VREF 6k TO ADC REFERENCE CIRCUITRY R1 R2 VREF TO INTERNAL COMPARATOR VINxA R3 R1 TRACK/ HOLD VINxB AD7865-2 TO INTERNAL COMPARATOR VINxA R2 R4 VINxB TRACK/ HOLD GND Figure 3. AD7865-2 Analog Input Structure Figure 2. AD7865-1 Analog Input Structure For the AD7865-1, R1 = 4 kΩ, R2 = 16 kΩ, R3 = 16 kΩ and R4 = 8 kΩ. The resistor input stage is followed by the high input impedance stage of the track/hold amplifier. The designed code transitions take place midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs etc.) LSB size is given by the formula, 1 LSB = FSR/16384. For the ±5 V range, 1 LSB = 10 V/16384 = 610.4 µV. For the ± 10 V range, 1 LSB = 20 V/16384 = 1.22 mV. Output coding is twos complement binary with 1 LSB = FSR/16384. The ideal input/ output transfer function for the AD7865-1 is shown in Table I. Table I. Ideal Input/Output Code Table for the AD7865-1 Analog Input1 Digital Output Code Transition 2 +FSR/2 – 3/2 LSB +FSR/2 – 5/2 LSB +FSR/2 – 7/2 LSB 011 . . . 110 to 011 . . . 111 011 . . . 101 to 011 . . . 110 011 . . . 100 to 011 . . . 101 AGND + 3/2 LSB AGND + 1/2 LSB AGND – 1/2 LSB AGND – 3/2 LSB 000 . . . 001 to 000 . . . 010 000 . . . 000 to 000 . . . 001 111 . . . 111 to 000 . . . 000 111 . . . 110 to 111 . . . 111 –FSR/2 + 5/2 LSB –FSR/2 + 3/2 LSB –FSR/2 + 1/2 LSB 100 . . . 010 to 100 . . . 011 100 . . . 001 to 100 . . . 010 100 . . . 000 to 100 . . . 001 Table II. Ideal Input/Output Code Table for the AD7865-2 Analog Input1 Digital Output Code Transition 2 +FSR/2 – 3/2 LSB +FSR/2 – 5/2 LSB +FSR/2 – 7/2 LSB 111 . . . 110 to 111 . . . 111 111 . . . 101 to 111 . . . 110 111 . . . 100 to 111 . . . 101 AGND + 5/2 LSB AGND + 3/2 LSB AGND – 1/2 LSB 000 . . . 010 to 000 . . . 011 000 . . . 001 to 000 . . . 010 000 . . . 000 to 000 . . . 001 NOTES 1 FSR is full-scale range and is 0 V to 2.5 V and 0 V to 5 V for AD7865-2 with VREF = 2.5 V. 2 1 LSB = FSR/16384 and is 0.153 mV (0 V to 2.5 V) and 0.305 mV (0 V to 5 V) for AD7865-2) with VREF = 2.5 V. –10– REV. B AD7865 AD7865-3 Figure 4 shows the analog input section of the AD7865-3. The analog input range is ± 2.5 V on the VINxA input. The VINxB input can be left unconnected but if it is connected to a potential then that potential must be AGND. 2.5V REFERENCE AD7865-3 6k TO ADC REFERENCE CIRCUITRY VREF R1 R2 TO INTERNAL COMPARATOR VINxA VINxB TRACK/ HOLD Figure 4. AD7865-3 Analog Input Structure For the AD7865-3, R1 = 4 kΩ and R2 = 4 kΩ. As a result, the VINxA input should be driven from a low impedance source. The resistor input stage is followed by the high input impedance stage of the track/hold amplifier. The designed code transitions take place midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs etc.) LSB size is given by the formula, 1 LSB = FSR/16384. Output coding is twos complement binary with 1 LSB = FSR/ 16384 = 5 V/16384 = 610.4 µV. The ideal input/output transfer function for the AD7865-3 is shown in Table III. Figure 5 shows the arrangement used. The H/S SEL controls a multiplexer that selects the source of the conversion sequence information, i.e., from the hardware channel select pins (SL1 to SL4) or from the channel selection register. When a conversion is started the output from the multiplexer is latched until the end-of-the conversion sequence. The data bus bits DB0 to DB3 (DB0 representing Channel 1 through DB3 representing Channel 4) are bidirectional and become inputs to the channel select register when RD is logic high and CS and WR are logic low. The logic state on DB0 to DB3 is latched into the channel select register when WR goes logic high. Figure 6 shows the loading sequence for channel selection using software control. When using software control to select the conversion sequence a write is only required each time the conversion sequence needs changing. This is because the channel select register will hold its information until different information is written to it. It should be noted that the hardware select Pins SL1 and SL2 are dual function. When H/S SEL is logic high (selecting the conversion sequence using software control) they take the functions CLK IN and INT/EXT CLK respectively. Therefore, the logic inputs on these pins must be set according to the type of operation required (see Using an External Clock). Also when H/S SEL is high, the SL3 and SL4 logic inputs have no function and can be tied either high or low, but should not be left floating. H/S HARDWARE CHANNEL SELECT PINS DATA BUS Table III. Ideal Input/Output Code Table for the AD7865-3 D3 D2 D1 D0 Analog Input1 Digital Output Code Transition +FSR/2 – 3/2 LSB2 +FSR/2 – 5/2 LSB +FSR/2 – 7/2 LSB 011 . . . 110 to 011 . . . 111 011 . . . 101 to 011 . . . 110 011 . . . 100 to 011 . . . 101 AGND + 3/2 LSB AGND + 1/2 LSB AGND – 1/2 LSB AGND – 3/2 LSB 000 . . . 001 to 000 . . . 010 000 . . . 000 to 000 . . . 001 111 . . . 111 to 000 . . . 000 111 . . . 110 to 111 . . . 111 –FSR/2 + 5/2 LSB –FSR/2 + 3/2 LSB –FSR/2 + 1/2 LSB 100 . . . 010 to 100 . . . 011 100 . . . 001 to 100 . . . 010 100 . . . 000 to 100 . . . 001 SELECT INDIVIDUAL TRACK-AND-HOLDS FOR CONVERSION SL1 SL2 SL3 SL4 CHANNEL SELECT REGISTER MULTIPLEXER SEQUENCER WR TRANSPARENT WHILE WAITING FOR CONVST. LATCHED ON THE RISING EDGE OF CONVST AND DURING A CONVERSION SEQUENCE. CS WR Figure 5. Channel Select Inputs and Registers RD t 13 WR NOTES 1 FSR is full-scale range is 5 V, with V REF = 2.5 V. 2 1 LSB = FSR/16384 = 610.4 µV (± 2.5 V—AD7865-3) with V REF = 2.5 V. t 14 t 15 CS t 16 SELECTING A CONVERSION SEQUENCE DATA Any subset of the four channels VIN1 to VIN4 can be selected for conversion. The selected channels are converted in an ascending order. For example if the channel selection includes VIN4, VIN1 and VIN3 then the conversion sequence will be VIN1, VIN3 and then VIN4. The conversion sequence selection may be made by using either the hardware channel select input pins SL1 through SL4 (if H/S is tied low) or programming the channel select register (if H/S is tied high). A logic high on a hardware channel select pin (or logic one in the channel select register) when CONVST goes logic high, marks the associated analog input channel for inclusion in the conversion sequence. REV. B LATCH t 17 DATA IN Figure 6. Channel Selection via Software Control –11– AD7865 TIMING AND CONTROL Reading Between Each Conversion in the Conversion Sequence Figure 7 shows the timing and control sequence required to obtain the optimum throughput rate from the AD7865. To obtain the optimum throughput from the AD7865 the user must read the result of each conversion as it becomes available. The timing diagram in Figure 7 shows a read operation each time the EOC signal goes logic low. The timing in Figure 7 shows a conversion on all four analog channels (SL1 to SL4 = 1, see Selecting a Conversion Sequence), hence there are four EOC pulses and four read operations to access the result of each of the four conversions. A conversion is initiated on the rising edge of CONVST. This places all four track/holds into hold simultaneously. New data from this conversion sequence is available for the first channel selected (AIN1) 2.4 µs later. The conversion on each subsequent channel is completed at 2.4 µs intervals. The end of each conversion is indicated by the falling edge of the EOC signal. The BUSY output signal indicates the end of conversion for all selected channels (four in this case). Data is read from the part via a 14-bit parallel data bus with standard CS and RD signals. The CS and RD inputs are internally gated to enable the conversion result onto the data bus. The data lines DB0 to DB13 leave their high impedance state when both CS and RD are logic low. Therefore, CS may be permanently tied logic low and the RD signal used to access the conversion result. Since each conversion result is latched into its output data register at the same time EOC goes logic low a further option would be to tie the EOC and RD pins together with CS tied logic low and use the rising edge of EOC to latch the conversion result. Although the AD7865 has some special features that permit reading during a conversion (e.g., a separate supply for the output data drivers, VDRIVE), for optimum performance it is recommended that the read operation be completed when EOC is logic low, i.e., before the start of the next conversion. Although Figure 7 shows the read operation taking place during the EOC pulse, a read operation can take place at any time. Figure 7 shows a timing specification called “Quiet Time.” This is the amount of time that should be left after a read operation and before the next conversion is initiated. The quiet time heavily depends on data bus capacitance but a figure of 50 ns to 150 ns is typical. The signal labeled FRSTDATA (First Data Word) indicates to the user that the pointer associated with the output data registers is pointing to the first conversion result by going logic high. The pointer is reset to point to the first data location (i.e., first conversion result,) at the end of the first conversion just prior to EOC going low. The pointer is incremented to point to the next register (next conversion result) by a rising edge of RD only if that conversion result is available. If a read takes place before the next conversion is complete (as shown in Figure 7) then the pointer is incremented at the end of that conversion when the EOC pulse goes low. Hence, FRSTDATA in Figure 7 is seen to go low just after to the second EOC pulse. Repeated read operations during a conversion will continue to access the data at the current pointer location until the pointer is incremented at the end of that conversion. Note: FRSTDATA has an indeterminate logic state after initial power-up. This means that for the first conversion sequence after power-up, the FRSTDATA logic output may already be logic high before the end of the first conversion. This condition is indicated by the dashed line in Figure 7. Also the FRSTDATA logic output may already be high as a result of the previous read sequence as is the case after the fourth read in Figure 7. The fourth read (rising edge of RD) resets the pointer to the first data location. There, however, FRSTDATA is already high when the next conversion sequence is initiated. t ACQ t1 CONVST BUSY t BUSY QUIET TIME t2 t CONV t CONV t9 EOC t 11 t 10 FRSTDATA t 12 RD t3 t4 t5 CS t6 VIN1 DATA t7 VIN2 VIN3 VIN4 100ns H/S SEL 100ns SL1–SL4 Figure 7. Timing Diagram for Reading During Conversion –12– REV. B AD7865 data bus as described in Reading Between Conversions in the Conversion Sequence. The pointer is reset to point to Register 1 on the rising edge of the RD signal when the last conversion result in the sequence is being read. In the example shown in Figure 8, this means that the pointer is set to Register 1 when the contents of Register 3 are read. Accessing the Output Data Registers There are four Output Data Registers, one for each of the four possible conversion results from a conversion sequence. The result of the first conversion in a conversion sequence is placed in Register 1 and the second result is placed in Register 2 and so on. For example if the conversion sequence VIN1, VIN3 and VIN4 is selected (see Selecting a Conversion Sequence) the results of the conversion on VIN1, VIN3 and VIN4 are placed in Registers 1 to 3 respectively. The Output Data register pointer is reset to point to Register 1 at the end of the first conversion in the sequence, just prior to EOC going low. At this point the logic output FRSTDATA will go logic high to indicate that the output data register pointer is addressing Register 1. When CS and RD are both logic low the contents of the addressed register are enabled onto the data bus (DB0–DB13). DECODE POINTER* Figure 9 shows the same conversion sequence as Figure 7. In this case, however, the results of the four conversions (on VIN1 to VIN4 ) are read after all conversions have finished, i.e., when BUSY goes logic low. The FRSTDATA signal goes logic high at the end of the first conversion just prior to EOC going logic low. As mentioned previously FRSTDATA has an indeterminate state after initial power up, therefore FRSTDATA may already be logic high. Unlike the case when reading during a conversion the output data register pointer is incremented on the rising edge of RD because the next conversion result is available in this case. This means FRSTDATA will go logic low after the first rising edge on RD. FRSTDATA OUTPUT DATA REGISTERS 2-BIT COUNTER Reading after the Conversion Sequence VDRIVE OE #1 (VIN1) OE #2 (VIN3) O/P DRIVERS OE #3 (VIN4) OE Successive read operations will access the remaining conversion results in ascending channel order. Each read operation increments the output data register pointer. The read operation that accesses the last conversion result causes the output data register pointer to be reset so that the next read operation will access the first conversion result again. This is shown in Figure 8 with the fifth read after BUSY goes low accessing the result of the conversion on VIN1. Thus the output data registers acts as a circular buffer in which the conversion results may be continually accessed. The FRSTDATA signal will go high when the first conversion result is available. DB0 TO DB13 OE #4 NOT VALID RESET AD7865 RD CS *THE POINTER WILL NOT BE INCREMENTED BY A RISING EDGE ON RD UNTIL THE CONVERSION RESULT IS IN THE OUTPUT DATA REGISTER. THE POINTER IS RESET WHEN THE LAST CONVERSION RESULT IS READ Figure 8. Output Data Registers When reading the output data registers after a conversion sequence, i.e., when BUSY goes low, the register pointer is incremented on the rising edge of the RD signal as shown in Figure 8. However, when reading the conversion results between conversions in a conversion sequence the pointer will not be incremented until a valid conversion result is in the register to be addressed. In this case the pointer is incremented when the conversion has ended and the result has been transferred to the output data register. This happens when EOC goes low, therefore EOC may be used to enable the register contents onto the Data is enabled onto the data bus DB0 to DB13 using CS and RD. Both CS and RD have the same functionality as described in the previous section. There are no restrictions or performance implications associated with the position of the read operations after BUSY goes low, however there is a minimum time between read operations that must be adhered to. Notice also that a “Quiet Time” is needed before the start of the next conversion sequence. t1 CONVST t BUSY BUSY QUIET TIME t2 EOC t8 RD t3 t4 CS t7 t6 DATA VIN1 VIN2 VIN3 VIN4 VIN1 t 10 t 10 FRSTDATA Figure 9. Timing Diagram, Reading after the Conversion Sequences REV. B –13– AD7865 t 18 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 15 16 CLK CONVST FRSTDATA EOC FIRST CONVERSION COMPLETE RD LAST CONVERSION COMPLETE BUSY Figure 10. Using an External Clock With the H/S SEL and INT/EXT CLK pins tied to Logic 1, the AD7865 will expect to be driven from an external clock. The highest external clock frequency allowed is 5 MHz. This means a conversion time of 3.2 µs compared to 2.4 µs using the internal clock. In some instances, however, it may be useful to use an external clock when high throughput rates are not required. For example, two or more AD7865s may be synchronized by using the same external clock for all devices. In this way there is no latency between output logic signals like EOC due to differences in the frequency of the internal clock oscillators. Figure 10 shows how the various logic outputs are synchronized to the CLK signal. The first falling edge of CLKIN must not occur until 200 ns after a conversion has been initiated (rising edge of CONVST), at which point BUSY will go high. The AD7865 will then convert the analog input signal on the first selected channel (see Selecting a Conversion Sequence) at a rate determined by the CLKIN. No external events will occur until the 14th falling edge of CLKIN. The data register output address is then reset to point to Data Register 1 and FRSTDATA goes high. This first conversion is complete on the 15th falling edge of the CLKIN (indicated by EOC going low) and the result from this conversion is loaded into Data Register 1. EOC goes high again on the 16th falling edge of CLKIN. Figure 10 shows a RD pulse occurring when EOC is low, enabling the conversion result in Data Register 1 onto the data bus. The next 16 pulses of CLKIN will convert the analog input signal on the second selected channel and so on until all selected channels have been converted. BUSY and EOC will go low on the 15th falling edge of the last conversion sequence and EOC will return high on the 16th falling edge. still operational while the AD7865 is in standby. This means the user can still continue to access the conversion results while the AD7865 is in standby. This feature can be used to reduce the average power consumption in a system using low throughput rates. To reduce the average power consumption the AD7865 can be placed in standby at the end of each conversion sequence, i.e., when BUSY goes low and taken out of standby again prior to the start of the next conversion sequence. The time it takes the AD7865 to come out of standby is called the “wake-up” time. This wake-up time will limit the maximum throughput rate at which the AD7865 can be operated when powering down between conversions. The AD7865 will wake up in less than 1 µs when using an external reference. When the internal reference is used, the wake-up time depends on the amount of time the AD7865 spends in standby mode. For standby times of less than 10 ms the AD7865 will wake up in less than 5 µs (see Figure 11). For standby times greater than this some or all of the charge on the external reference capacitor will have leaked away and the wake-up time will be dependent on how long it takes to recharge. For standby times less than one second the wake-up time will be less than 1 ms. Even if the charge has been completely depleted the wake-up time will typically be less than 10 ms. 5 WAKE-UP TIME – s Using an External Clock Standby Mode Operation The AD7865 has a Standby Mode whereby the device can be placed in a low current consumption mode (3 µA typ). The AD7865 is placed in standby by bringing the logic input STBY low. The AD7865 can be powered up again for normal operation by bringing STBY logic high. The output data buffers are 2.5 0 0 2500 5000 STANDBY TIME – s 7500 10000 Figure 11. Wake-Up Time vs. Standby Time Using the OnChip Reference –14– REV. B AD7865 100s CONVST tBUSY t BUSY 7s BUSY tWAKEUP I DD = 3A STBY Figure 12. Power-Down between Conversion Sequences When operating the AD7865 in a standby mode between conversions, the power savings can be significant. For example, with a throughput rate of 10 kSPS and external reference, the AD7865 will be powered up 11 µs out of every 100 µs (1 µs for wake-up time and 9.6 µs to convert four channels. Therefore, the average power consumption drops to (115 mW × 10.6%) or 12.2 mW approximately. Positive Full-Scale Adjust Apply a voltage of 9.9982 V (FS/2 – 3/2 LSB) at V1. Adjust R2 until the ADC output code flickers between 01 1111 1111 1110 and 01 1111 1111 1111. Negative Full-Scale Adjust OFFSET AND FULL-SCALE ADJUSTMENT In most Digital Signal Processing (DSP) applications, offset and full-scale errors have little or no effect on system performance. Offset error can always be eliminated in the analog domain by ac coupling. Full-scale error effect is linear and does not cause problems as long as the input signal is within the full dynamic range of the ADC. Invariably, some applications will require that the input signal span the full analog input dynamic range. In such applications, offset and full-scale error will have to be adjusted to zero. Figure 13 shows a typical circuit that can be used to adjust the offset and full-scale errors on the AD7865 (V1 on the AD7865-1 version is shown for example purposes only). Where adjustment is required, offset error must be adjusted before full-scale error. This is achieved by trimming the offset of the op amp driving the analog input of the AD7865 while the input voltage is 1/2 LSB below analog ground. The trim procedure is as follows: apply a voltage of –610 µV (–1/2 LSB) at V1 and adjust the op amp offset voltage until the ADC output code flickers between 1111 1111 1111 and 0000 0000 0000. Gain error can be adjusted at either the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). The trim procedures for both cases are as follows. INPUT RANGE = 10V V1 Apply a voltage of –9.9998 V (–FS + 1/2 LSB) at V1 and adjust R2 until the ADC output code flickers between 10 0000 0000 0000 and 10 0000 0000 0001. An alternative scheme for adjusting full-scale error in systems that use an external reference is to adjust the voltage at the VREF pin until the full-scale error for any of the channels is adjusted out. The good full-scale matching of the channels will ensure small full-scale errors on the other channels. DYNAMIC SPECIFICATIONS The AD7865 is specified and 100% tested for dynamic performance specifications as well as traditional dc specifications such as Integral and Differential Nonlinearity. These ac specifications are required for such signal processing applications as phased array sonar, adaptive filters and spectrum analysis. These applications require information on the ADC’s effect on the spectral content of the input signal. Hence, the parameters for which the AD7865 is specified include SNR, harmonic distortion, intermodulation distortion and peak harmonics. These terms are discussed in more detail in the following sections. Signal-to-Noise Ratio (SNR) SNR is the measured signal-to-noise ratio at the output of the ADC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fS/2) excluding dc. SNR is dependent upon the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to noise ratio for a sine wave input is given by R1 10k SNR = (6.02N + 1.76) dB R2 500 where N is the number of bits. VINxA R4 10k R3 10k R5 10k AD7865* AGND *ADDITIONAL PINS OMITTED FOR CLARITY Thus for an ideal 14-bit converter, SNR = 86.04 dB. Figure 14 shows a histogram plot for 8192 conversions of a dc input using the AD7865 with 5 V supply. The analog input was set at the center of a code transition. It can be seen that most of the codes appear in the one output bin, indicating very good noise performance from the ADC. Figure 13. Full-Scale Adjust Circuit REV. B (1) –15– AD7865 14 7000 –55C 13 12 6000 +25C 11 10 5000 ENOB COUNTS 9 4000 3000 +125C 8 7 6 5 4 2000 3 1000 2 0 0 1 0 ADC CODE Figure 14. Histogram of 8192 Conversions of a DC Input Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3 . . ., etc. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb) while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). The AD7865 is tested using two input frequencies. In this case the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. In this case, the input consists of two, equal amplitude, low distortion sine waves. Figure 17 shows a typical IMD plot for the AD7865. 0 –20 fs = 350kHz fIN = 100kHz SNR = 80.5dB dBs –60 –80 –100 –120 –140 10000 Figure 16. Effective Numbers of Bits vs. Frequency The output spectrum from the ADC is evaluated by applying a sine wave signal of very low distortion to the analog input. A Fast Fourier Transform (FFT) plot is generated from which the SNR data can be obtained. Figure 15 shows a typical 4096point FFT plot of the AD7865 with an input signal of 100 kHz and a sampling frequency of 350 kHz. The SNR obtained from this graph is 80.5 dB. It should be noted that the harmonics are taken into account when calculating the SNR. –40 100 1000 INPUT FREQUENCY – kHz 0 0 35000 70000 105000 FREQUENCY – Hz 140000 175000 f a = 49.113kHz f b = 50.183kHz fs = 350kHz –20 Figure 15. FFT Plot –40 Effective Number of Bits N= SNR −1.76 6.02 –60 dBs The formula given in Equation 1 relates the SNR to the number of bits. Rewriting the formula, as in Equation 2, it is possible to obtain a measure of performance expressed in effective number of bits (N). –80 –100 (2) –120 The effective number of bits for a device can be calculated directly from its measured SNR. Figure 16 shows a typical plot of effective number of bits versus frequency for an AD7865-2. –140 0 25000 50000 75000 100000 125000 150000 175000 FREQUENCY – Hz Figure 17. IMD Plot –16– REV. B AD7865 AC Linearity Plots ADSP-21xx The plots shown in Figure 18 below show typical DNL and INL for the AD7865. ADDRESS DECODE AD7865 DNL – LSBs 0.60 A0–A13 DMS VIN1 CS VIN2 VIN3 VIN4 RD RD WR WR D0–D13 DB0–DB13 0 BUSY IRQn CONVST –0.60 0 4000 8000 ADC – Code 12000 Figure 19. AD7865–ADSP-21xx Interface 16383 AD7865–TMS320C5x Interface 0.60 iNL – LSBs DT1/F0 0 –0.60 0 4000 8000 ADC – Code 12000 16383 Figure 18. Typical DNL and INL Plots Figure 20 shows an interface between the AD7865 and the TMS320C5x. As with the previous interfaces, conversion can be initiated from the TMS320C5x or from an external source and the processor is interrupted when the conversion sequence is completed. The CS signal to the AD7865 derived from the DS signal and a decode of the address bus. This maps the AD7865 into external data memory. The RD signal from the TMS320 is used to enable the ADC data onto the data bus. The AD7865 has a fast parallel bus so there are no wait state requirements. The following instruction is used to read the conversion results from the AD7865: IN D,ADC MICROPROCESSOR INTERFACING where D is Data Memory address and ADC is the AD7865 address. The high speed parallel interface of the AD7865 allows easy interfacing to most DSPs and microprocessors. The AD7865 interface of the AD7865 consists of the data lines (DB0 to DB13), CS, RD, WR, EOC and BUSY. TMS320C5x ADDRESS DECODE AD7865 AD7865–ADSP-21xx Interface VIN1 VIN2 VIN3 VIN4 Figure 19 shows an interface between the AD7865 and the ADSP-210x. The CONVST signal can be generated by the ADSP-210x or from some other external source. Figure 19 shows the CS being generated by a combination of the DMS signal and the address bus of the ADSP-2100. In this way the AD7865 is mapped into the data memory space of the ADSP-210x. The AD7865 BUSY line provides an interrupt to the ADSP210x when the conversion sequence is complete on all the selected channels. The conversion results can then be read from the AD7865 using successive read operations. Alternately, one can use the EOC pulse to interrupt the ADSP-210x when the conversion on each channel is complete when reading between each conversion in the conversion sequence (Figure 8). The AD7865 is read using the following instruction MR0 = DM(ADC) where MR0 is the ADSP-210x MR0 register and ADC is the AD7865 address. REV. B A0–A13 DS CS RD RD WR WR DB0–DB13 BUSY CONVST D0–D13 INTn PA0 Figure 20. AD7865–TMS320C5x Interface AD7865–MC68000 Interface An interface between the AD7865 and the MC68000 is shown in Figure 21. The conversion can be initiated from the MC68000 or from an external source. The AD7865 BUSY line can be used to interrupt the processor or, alternatively, software delays can ensure that conversion has been completed before a read to the AD7865 is attempted. Because of the nature of its interrupts, the 68000 requires additional logic (not shown in Figure 21) to allow it to be interrupted correctly. For further information on 68000 interrupts, consult the 68000 users manual. –17– AD7865 The MC68000 AS and R/W outputs are used to generate a separate RD input signal for the AD7865. CS is used to drive the 68000 DTACK input to allow the processor to execute a normal read operation to the AD7865. The conversion results are read using the following 68000 instruction: Once again, the relative phase of the two channels is important. A DSP microprocessor is used to perform the mathematical transformations and control loop calculations on the information fed back by the AD7865. MOVE.W ADC,D0 DSP MICROPROCESSOR TORQUE AND FLUX CONTROL LOOP CALCULATIONS AND TWO-TO-THREEPHASE INFORMATION DAC ADDRESS DECODE VIN1 VIN2 VIN3 VIN4 IB DRIVE CIRCUITRY IA 3PHASE MOTOR VB VA DAC MC68000 AD7865 IC DAC where D0 is the 68000 D0 register and ADC is the AD7865 address. TORQUE SETPOINT A0–A15 ISOLATION AMPLIFIERS FLUX SETPOINT CS VIN1 DTACK AS RD VIN2 TRANSFORMATION TO TORQUE AND FLUX CURRENT COMPONENTS R/W AD7865* VIN3 D0–D13 DB0–DB13 VIN4 CONVST CLOCK VOLTAGE ATTENUATORS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 21. AD7865–MC68000 Interface Figure 22. Vector Motor Control Using the AD7865 Vector Motor Control The current drawn by a motor can be split into two components: one produces torque and the other produces magnetic flux. For optimal performance of the motor, these two components should be controlled independently. In conventional methods of controlling a three-phase motor, the current (or voltage) supplied to the motor and the frequency of the drive are the basic control variables. However, both the torque and flux are functions of current (or voltage) and frequency. This coupling effect can reduce the performance of the motor because, for example, if the torque is increased by increasing the frequency, the flux tends to decrease. Vector control of an ac motor involves controlling phase in addition to drive and current frequency. Controlling the phase of the motor requires feedback information on the position of the rotor relative to the rotating magnetic field in the motor. Using this information, a vector controller mathematically transforms the three phase drive currents into separate torque and flux components. The AD7865, with its four-channel simultaneous sampling capability, is ideally suited for use in vector motor control applications. MULTIPLE AD7865s IN A SYSTEM Figure 23 shows a system where a number of AD7865s can be configured to handle multiple input channels. This type of configuration is common in applications such as sonar, radar, etc. The AD7865 is specified with maximum limits on aperture delay match. This means that the user knows the difference in the sampling instant between all channels. This allows the user to maintain relative phase information between the different channels. The AD7865 has a maximum aperture delay matching of ± 4 ns. All AD7865s use the same external SAR clock (5 MHz). Therefore, the conversion time for all devices will be the same and so all devices may be read simultaneously. In the example shown in Figure 23, the data outputs of two AD7865s are enabled onto a 32-bit wide data bus when EOC goes low. AD7865 AD780 A block diagram of a vector motor control application using the AD7865 is shown in Figure 22. The position of the field is derived by determining the current in each phase of the motor. Only two phase currents need to be measured because the third can be calculated if two phases are known. VIN1 and VIN2 of the AD7865 are used to digitize this information. VIN1 VIN2 VIN3 VIN4 EOC 32 14 VREF CS CLK IN RD ADSP-2106x RD AD7865 Simultaneous sampling is critical to maintain the relative phase information between the two channels. A current sensing isolation amplifier, transformer or Hall-effect sensor is used between the motor and the AD7865. Rotor information is obtained by measuring the voltage from two of the inputs to the motor. VIN3 and VIN4 of the AD7865 are used to obtain this information. –18– VIN1 VIN2 VIN3 VIN4 14 VREF CS CLK IN RD ADDRESS DECODE 5MHz Figure 23. Multiple AD7865s in Multichannel System REV. B AD7865 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.548 (13.925) 0.546 (13.875) 0.398 (10.11) 0.390 (9.91) 0.096 (2.44) MAX 0.037 (0.94) 0.025 (0.64) 8 0.8 33 23 34 22 SEATING PLANE TOP VIEW C01342a–0–12/00 (rev. B) 44-Lead Plastic Quad Flatpack (S-44) (PINS DOWN) 44 0.040 (1.02) 0.032 (0.81) 0.040 (1.02) 0.032 (0.81) 12 1 11 0.033 (0.84) 0.029 (0.74) 0.016 (0.41) 0.012 (0.30) PRINTED IN U.S.A. 0.083 (2.11) 0.077 (1.96) REV. B –19–