Micron MT4C4M4E8 4 meg x 4 edo dram Datasheet

4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
MT4LC4M4E8, MT4C4M4E8
MT4LC4M4E9, MT4C4M4E9
DRAM
FEATURES
PIN ASSIGNMENT (Top View)
• Industry-standard x4 pinout, timing, functions and
packages
• State-of-the-art, high-performance, low-power CMOS
silicon-gate process
• Single power supply (+3.3V ±0.3V or +5V ±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, HIDDEN and CAS#BEFORE-RAS# (CBR)
• Optional Self Refresh (S) for low-power data retention
• 11 row, 11 column addresses (2K refresh) or
12 row, 10 column addresses (4K refresh)
• Extended Data-Out (EDO) PAGE MODE access cycle
• 5V-tolerant inputs and I/Os on 3.3V devices
OPTIONS
24/26-Pin TSOP
(DB-2)
24/26-Pin SOJ
(DA-2)
VCC
DQ1
DQ2
WE#
RAS#
*NC/A11
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
26
25
24
23
22
21
VSS
DQ4
DQ3
CAS#
OE#
A9
8
9
10
11
12
13
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
VCC
DQ1
DQ2
WE#
RAS#
*NC/A11
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
26
25
24
23
22
21
VSS
DQ4
DQ3
CAS#
OE#
A9
8
9
10
11
12
13
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
MARKING
• Voltages
3.3V
5V
* NC on 2K refresh and A11 on 4K refresh options.
Note: The “#” symbol indicates signal is active LOW.
LC
C
4 MEG x 4 EDO DRAM PART NUMBERS
• Refresh Addressing
2,048 (i.e. 2K) Rows
4,096 (i.e. 4K) Rows
E8
E9
• Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
DJ
TG
• Timing
50ns access
60ns access
-5
-6
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
PART NUMBER
MT4LC4M4E8DJ
MT4LC4M4E8DJS
MT4LC4M4E8TG
MT4LC4M4E8TGS
MT4LC4M4E9DJ
MT4LC4M4E9DJS
MT4LC4M4E9TG
MT4LC4M4E9TGS
MT4C4M4E8DJ
MT4C4M4E8DJS
MT4C4M4E8TG
MT4C4M4E8TGS
MT4C4M4E9DJ
MT4C4M4E9DJS
MT4C4M4E9TG
MT4C4M4E9TGS
None
S
• Part Number Example: MT4LC4M4E8DJ-6
Note: The 4 Meg x 4 EDO DRAM base number differentiates the offerings in
two places - MT4LC4M4E8. The third field distinguishes the low voltage
offering: LC designates VCC = 3.3V and C designates VCC = 5V. The fifth field
distinguishes various options: E8 designates a 2K refresh and E9 designates a
4K refresh for EDO DRAMs.
Vcc
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
5V
5V
5V
5V
5V
5V
5V
5V
REFRESH
2K
2K
2K
2K
4K
4K
4K
4K
2K
2K
2K
2K
4K
4K
4K
4K
PACKAGE
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
REFRESH
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
KEY TIMING PARAMETERS
SPEED
-5
-6
tRC
tRAC
tPC
tAA
t CAC
tCAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
GENERAL DESCRIPTION
The 4 Meg x 4 DRAM is a randomly accessed, solid-state
memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11
bits for 2K and first 12 bits for 4K). Once the page has been
opened by RAS#, CAS# is used to latch the column address
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
GENERAL DESCRIPTION (continued)
(the latter 11 bits for 2K and the latter 10 bits for 4K, address
pins A10 and A11 are “don’t care”). READ and WRITE
cycles are selected with the WE# input.
A logic HIGH on WE# dictates READ mode, while a logic
LOW on WE# dictates WRITE mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. An EARLY WRITE occurs
when WE# is taken LOW prior to CAS# falling. A LATE
WRITE or READ-MODIFY-WRITE occurs when WE# falls
after CAS# is taken LOW. During EARLY WRITE cycles,
the data outputs (Q) will remain High-Z regardless of the
state of OE#. During LATE WRITE or READ-MODIFYWRITE cycles, OE# must be taken HIGH to disable the data
outputs prior to applying input data. If a LATE WRITE or
READ-MODIFY-WRITE is attempted while keeping OE#
LOW, no write will occur, and the data outputs will drive
read data from the accessed location.
The four data inputs and the four data outputs are routed
through four pins using common I/O, and pin direction is
controlled by WE# and OE#.
with a row address strobed-in by RAS#, followed by a
column address strobed-in by CAS#. CAS# may be
toggled-in by holding RAS# LOW and strobing-in different
column addresses, thus executing faster memory cycles.
Returning RAS# HIGH terminates the PAGE MODE of
operation, i.e., closes the page.
EDO PAGE MODE
The 4 Meg x 4 EDO DRAM provides EDO PAGE MODE,
which is an accelerated FAST PAGE MODE cycle. The
primary advantage of EDO is the availability of data-out
even after CAS# returns HIGH. EDO allows CAS# precharge
time (tCP) to occur without the output data going invalid.
This elimination of CAS# output control allows pipeline
READs.
FAST PAGE MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO PAGE MODE DRAMs operate like FAST
PAGE MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, provided RAS# and OE# are held LOW. If OE# is pulsed while
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z (refer to
PAGE ACCESS
PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row addressdefined page boundary. The PAGE cycle is always initiated
RAS#
V IH
V IL
,, ,,, ,,,,,, ,,,,, ,,,,,, ,,,,
,
, , ,
CAS#
ADDR
V IH
V IL
V IH
V IL
DQ V IOH
V IOL
ROW
COLUMN (A)
OPEN
COLUMN (B)
,,
VALID DATA (A)
VALID DATA (A)
t OD
OE#
V IH
V IL
COLUMN (C)
,,, ,,
VALID DATA (C)
VALID DATA (B)
t OD
t OES
COLUMN (D)
t OEHC
t OE
t OEP
The DQs go back to
Low-Z if tOES is met.
The DQs remain High-Z
until the next CAS# cycle
if tOEHC is met.
,
VALID DATA (D)
t OD
,
,,,
The DQs remain High-Z
until the next CAS# cycle
if tOEP is met.
DON’T CARE
,,
UNDEFINED
Figure 1
OE# CONTROL OF DQs
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
fresh cycle and holding RAS# LOW for the specified tRASS.
Additionally, the “S” option allows for an extended refresh
period of 128ms, or 31.25µs per row for a 4K refresh and
62.5µs per row for a 2K refresh if using distributed CBR
Refresh. This refresh rate can be applied during normal
operation, as well as during a standby or BATTERY BACKUP
mode.
The Self Refresh mode is terminated by driving RAS#
HIGH for a minimum time of tRPS. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS# LOW-to-HIGH transition.
If the DRAM controller uses a distributed refresh sequence, a burst refresh is not required upon exiting
Self Refresh. However, if the DRAM controller utilizes a
RAS#- ONLY or burst refresh sequence, all rows must be
refreshed within the average internal refresh rate, prior to
the resumption of normal operation.
Figure 1). WE# can also perform the function of disabling
the output devices under certain conditions, as shown in
Figure 2.
During an application, if the DQ outputs are wire OR’d,
OE# must be used to disable idle banks of DRAMs. Alternatively, pulsing WE# to the idle banks during CAS# high
time will also High-Z the outputs. Independent of OE#
control, the outputs will disable after tOFF, which is referenced from the rising edge of RAS# or CAS#, whichever
occurs last.
REFRESH
Preserve correct memory cell data by maintaining power
and executing any RAS# cycle (READ, WRITE) or RAS#
refresh cycle (RAS#-ONLY, CBR or HIDDEN) so that all
combinations of RAS# addresses (2,048 for 2K and 4,096 for
4K) are executed within tREF (MAX), regardless of sequence. The CBR and Self Refresh cycles will invoke the
internal refresh counter for automatic RAS# addressing.
An optional Self Refresh mode is also available on the S
version. The “S” option allows the user the choice of a fully
static, low-power data retention mode or a dynamic refresh
mode at the extended refresh period of 128ms. The optional
Self Refresh feature is initiated by performing a CBR Re-
STANDBY
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
The chip is preconditioned for the next cycle during the
RAS# HIGH time.
,, ,,, ,,,,,,, ,,,,, ,,,,,
,
,
,
,,
,
,,
RAS#
V IH
V IL
CAS#
V IH
V IL
ADDR
V IH
V IL
DQ V IOH
V IOL
WE#
V IH
V IL
OE#
V IH
V IL
ROW
COLUMN (A)
OPEN
COLUMN (B)
,,
COLUMN (C)
,
VALID DATA (A)
t WHZ
t WPZ
The DQs go to High-Z if WE# falls and, if tWPZ is met,
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
VALID DATA (B)
COLUMN (D)
,,
INPUT DATA (C)
t WHZ
,,
,,
,,,
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
DON’T CARE
UNDEFINED
Figure 2
WE# CONTROL OF DQs
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
FUNCTIONAL BLOCK DIAGRAM - 2K REFRESH
WE#
CAS#
NO. 2 CLOCK
GENERATOR
DATA-IN
BUFFER
4
DATA-OUT
BUFFER
4
DQ1
DQ2
DQ3
DQ4
4
OE#
11
COLUMN
ADDRESS
BUFFER(11)
10
COLUMN
DECODER
1
1024
REFRESH
CONTROLLER
4
SENSE AMPLIFIERS
I/O GATING
1024
11
2048
2048
ROW TRANSFER
ROW
TRANSFER
(1 OF
2)
(1 OF 2)
11
ROW
ADDRESS
BUFFERS (11)
2048
2048
2048
ROW SELECT
(2 of 4096)
11
COMPLEMENT
SELECT
REFRESH
COUNTER
ROW
DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
4096 x 1024 x 4
MEMORY
ARRAY
NO. 1 CLOCK
GENERATOR
RAS#
VDD
VSS
FUNCTIONAL BLOCK DIAGRAM - 4K REFRESH
WE#
CAS#
NO. 2 CLOCK
GENERATOR
DATA-IN
BUFFER
4
DATA-OUT
BUFFER
4
DQ1
DQ2
DQ3
DQ4
4
OE#
RAS#
10
COLUMN
ADDRESS
BUFFER(10)
COLUMN
DECODER
10
1024
REFRESH
CONTROLLER
4
SENSE AMPLIFIERS
I/O GATING
1024
12
12
4096
NO. 1 CLOCK
GENERATOR
4096
4096
ROW SELECT
(1 of 4096)
12
ROW
ADDRESS
BUFFERS (12)
COMPLEMENT
SELECT
REFRESH
COUNTER
ROW
DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
4096 x 1024 x 4
MEMORY
ARRAY
VDD
VSS
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
TRUTH TABLE
ADDRESSES
DATA-IN/OUT
RAS#
CAS#
WE#
OE#
tR
Standby
H
H→X
X
X
X
X
High-Z
READ
L
L
H
L
ROW
COL
Data-Out
EARLY WRITE
L
L
L
X
ROW
COL
Data-In
FUNCTION
READ WRITE
tC
DQ1-DQ4
L
L
H→L
L→H
ROW
COL
Data-Out, Data-In
EDO-PAGE-MODE
1st Cycle
L
H→L
H
L
ROW
COL
Data-Out
READ
2nd Cycle
L
H→L
H
L
n/a
COL
Data-Out
EDO-PAGE-MODE
1st Cycle
L
H→L
L
X
ROW
COL
Data-In
EARLY WRITE
2nd Cycle
L
H→L
L
X
n/a
COL
Data-In
Any Cycle
L
L→H
H
L
n/a
n/a
Data-Out
EDO-PAGE-MODE
1st Cycle
L
H→L
H→L
L→H
ROW
COL
Data-Out, Data-In
READ-WRITE
2nd Cycle
L
H→L
H→L
L→H
n/a
COL
Data-Out, Data-In
HIDDEN
READ
L→H→L
L
H
L
ROW
COL
Data-Out
REFRESH
WRITE
L→H→L
L
L
X
ROW
COL
Data-In
L
H
X
X
ROW
n/a
High-Z
CBR REFRESH
H→L
L
H
X
X
X
High-Z
SELF REFRESH
H→L
L
H
X
X
X
High-Z
RAS#-ONLY REFRESH
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Pin Relative to VSS:
3.3V ................................................................ -1V to +4.6V
5V ...................................................................... -1V to +7V
Voltage on NC, Inputs or I/O Pins Relative to VSS:
3.3V ................................................................ -1V to +5.5V
5V ...................................................................... -1V to +7V
Operating Temperature, TA (ambient) .......... 0°C to +70°C
Storage Temperature (plastic) .................... -55°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1)
3.3V
PARAMETER/CONDITION
5V
SYMBOL
MIN
MAX
MIN
MAX
UNITS
Supply Voltage
VCC
3.0
3.6
4.5
5.5
V
Input High Voltage:
Valid Logic 1; all inputs, I/Os and any NC
VIH
2.0
5.5
2.4
VCC +1
V
Input Low Voltage:
Valid Logic 0; all inputs, I/Os and any NC
VIL
-1.0
0.8
-0.5
0.8
V
II
-2
2
-2
2
µA
Output High Voltage:
IOUT = -2mA (3.3V), -5mA (5V)
VOH
2.4
-
2.4
-
V
Output Low Voltage:
IOUT = 2mA (3.3V), 4.2mA (5V)
VOL
-
0.4
-
0.4
V
IOZ
-5
5
-5
5
µA
Input Leakage Current:
Any input at VIN (0V ≤ VIN ≤ VIH [MAX]);
all other pins not under test = 0V
Output Leakage Current:
Any output at VOUT (0V ≤ VOUT ≤ 5.5V);
DQ is disabled and in High-Z state
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
6
NOTES
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
Icc OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3)
3.3V
5V
2K
4K
2K
4K
SPEED Refresh Refresh Refresh Refresh UNITS
PARAMETER/CONDITION
SYM
STANDBY CURRENT: TTL
(RAS# = CAS# = VIH)
ICC1
ALL
1
1
1
1
mA
STANDBY CURRENT: CMOS (non-S version only)
(RAS# = CAS# = other inputs = VCC -0.2V)
ICC2
ALL
500
500
500
500
µA
STANDBY CURRENT: CMOS (S version only)
(RAS# = CAS# = other inputs = VCC -0.2V)
ICC2
ALL
150
150
150
150
µA
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
-5
-6
110
100
90
80
140
130
120
110
mA
5, 6
ICC3
OPERATING CURRENT: EDO PAGE MODE
Average power supply current (RAS# = VIL,
CAS#, address cycling: tPC = tPC [MIN])
-5
-6
110
100
100
90
110
100
100
90
mA
5, 6
ICC4
REFRESH CURRENT: RAS#-ONLY
Average power supply current
(RAS# cycling, CAS# = VIH: tRC = tRC [MIN])
-5
-6
110
100
90
80
140
130
120
110
mA
5, 6
ICC5
REFRESH CURRENT: CBR
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
-5
-6
110
100
90
80
140
130
120
110
mA
5, 7
ICC6
REFRESH CURRENT: Extended (S version only)
Average power supply current: CAS# = 0.2V or
CBR cycling; RAS# = tRAS (MIN); WE# =
VCC -0.2V; A0-A11,OE# and DIN = VCC -0.2V or
0.2V (DIN may be left open)
ALL
300
300
300
300
µA
5, 7
ICC7
tRC
62.5
31.25
62.5
31.25
µs
25
REFRESH CURRENT: Self (S version only)
Average power supply current: CBR with
RAS# ≥ tRASS (MIN) and CAS# held LOW; WE# =
VCC -0.2V; A0-A11, OE# and DIN = VCC -0.2V
or 0.2V (DIN may be left open)
ICC8
ALL
300
300
300
300
µA
5, 7
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
7
NOTES
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
CAPACITANCE
PARAMETER
SYMBOL
MAX
UNITS
NOTES
Input Capacitance: Address pins
CI1
5
pF
8
Input Capacitance: RAS#, CAS#, WE#, OE#
CI2
7
pF
8
Input/Output Capacitance: DQ
CIO
7
pF
8
MAX
30
NOTES
18
AC ELECTRICAL CHARACTERISTICS
(Notes: 2, 3, 9, 10, 11, 12, 17) (VCC [MIN] ≤ VCC ≤ VCC [MAX])
AC CHARACTERISTICS
PARAMETER
Access time from column address
Column address setup to CAS# precharge
Column address hold time (referenced to RAS#)
Column address setup time
Row address setup time
Column address to WE# delay time
Access time from CAS#
Column address hold time
CAS# pulse width
CAS# LOW to “don’t care” during Self Refresh
CAS# hold time (CBR Refresh)
CAS# to output in Low-Z
Data output hold after next CAS# LOW
CAS# precharge time
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
Write command to CAS# lead time
Data-in hold time
Data-in setup time
Output disable
Output Enable
OE# hold time from WE# during
READ-MODIFY-WRITE cycle
OE# HIGH hold from CAS# HIGH
OE# HIGH pulse width
OE# LOW to CAS# HIGH setup time
Output buffer turn-off delay
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
-5
-6
SYMBOL
tAA
tACH
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHD
tCHR
tCLZ
tCOH
tCP
tCPA
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
tDS
tOD
tOE
tOEH
MIN
MAX
25
8
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOEHC
5
5
4
0
10
5
5
0
ns
ns
ns
ns
12
38
0
0
42
MIN
15
45
0
0
49
13
8
8
15
8
0
3
8
10,000
15
10
10
15
10
0
3
10
28
5
38
5
28
8
8
0
0
tOEP
tOES
tOFF
8
12
12
12
10,000
35
5
45
5
35
10
10
0
0
15
15
15
13
14
7
15
13
16
16
17
18
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
AC ELECTRICAL CHARACTERISTICS
(Notes: 2, 3, 9, 10, 11, 12, 17) (VCC [MIN] ≤ VCC ≤ VCC [MAX])
AC CHARACTERISTICS
PARAMETER
OE# setup prior to RAS# during
HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
RAS# to column address delay time
Row address hold time
RAS# pulse width
RAS# pulse width (EDO PAGE MODE)
RAS# pulse width during Self Refresh
Random READ or WRITE cycle time
RAS# to CAS# delay time
Read command hold time (referenced to CAS#)
Read command setup time
Refresh period (2,048 cycles)
Refresh period (4,096 cycles)
Refresh period S version
RAS# precharge time
RAS# to CAS# precharge time
RAS# precharge time exiting Self Refresh
Read command hold time (referenced to RAS#)
RAS# hold time
READ WRITE cycle time
RAS# to WE# delay time
Write command to RAS# lead time
Transition time (rise or fall)
Write command hold time
Write command hold time (referenced to RAS#)
WE# command setup time
Output disable delay from WE#
Write command pulse width
WE# pulse to disable at CAS# HIGH
WE# hold time (CBR Refresh)
WE# setup time (CBR Refresh)
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
-5
SYMBOL
tORD
MIN
0
tPC
20
47
tPRWC
tRAC
-6
MAX
MIN
0
25
56
50
tRAD
9
9
50
50
100
84
11
0
0
tRAH
tRAS
tRASP
tRASS
tRC
tRCD
tRCH
tRCS
tREF
10,000
125,000
60
12
10
60
60
100
104
14
0
0
32
64
128
tREF
tREF
tRP
30
5
90
0
13
116
67
13
2
8
38
0
0
5
10
8
8
tRPC
tRPS
tRRH
tRSH
tRWC
tRWD
tRWL
tT
tWCH
tWCR
tWCS
tWHZ
tWP
tWPZ
tWRH
tWRP
9
MAX
50
12
10,000
125,000
32
64
128
40
5
105
0
15
140
79
15
2
10
45
0
0
5
10
10
10
50
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
19
21
22
23
23
13
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
NOTES
1. All voltages referenced to VSS.
2. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (0˚C ≤ TA ≤ 70˚C) is ensured.
3. An initial pause of 100µs is required after power-up,
followed by eight RAS# refresh cycles (RAS#-ONLY
or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the tREF refresh
requirement is exceeded.
4. NC pins are assumed to be left floating and are not
tested for leakage.
5. ICC is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
6. Column address changed once each cycle.
7. Enables on-chip refresh and address counters.
8. This parameter is sampled. VCC = VCCMIN; f = 1 MHz.
9. AC characteristics assume tT = 2.5ns.
10. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
11. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
12. Measured with a load equivalent to two TTL gates
and 100pF; and VOL = 0.8V and VOH = 2V.
13. tWCS, tRWD, tAWD and tCWD are not restrictive
operating parameters. tWCS applies to EARLY
WRITE cycles. tRWD, tAWD and tCWD apply to
READ-MODIFY-WRITE cycles. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If tWCS < tWCS (MIN) and tRWD ≥
tRWD (MIN), tAWD ≥ tAWD (MIN) and tCWD ≥
tCWD (MIN), the cycle is a READ-MODIFY-WRITE
and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. OE# held HIGH
and WE# taken LOW after CAS# goes LOW results in
a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD,
tCWD and tAWD are not applicable in a LATE
WRITE cycle.
14. Requires that tAA and tRAC are not violated.
15. If CAS# is LOW at the falling edge of RAS#, Q will be
maintained from the previous cycle. To initiate a new
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
cycle and clear the data-out buffer, CAS# must be
pulsed HIGH for tCP.
16. These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading edge
in LATE WRITE or READ-MODIFY-WRITE cycles.
17. If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not permissible and should not be attempted. Additionally, WE#
must be pulsed during CAS# HIGH time in order to
place I/O buffers in High-Z.
18. LATE WRITE and READ-MODIFY-WRITE cycles
must have both tOD and tOEH met (OE# HIGH
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE cycle.
The DQs will provide the previously read data if
CAS# remains LOW and OE# is taken back LOW
after tOEH is met. If CAS# goes HIGH prior to OE#
going back LOW, the DQs will remain open.
19. Requires that tAA and tCAC are not violated.
20. tOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL. It is referenced from the
rising edge of RAS# or CAS#, whichever occurs last.
21. The tRAD (MAX) limit is no longer specified. tRAD
(MAX) was specified as a reference point only. If
tRAD was greater than the specified tRAD (MAX)
limit, then access time was controlled exclusively by
tAA (tRAC and tCAC no longer applied). With or
without the tRAD (MAX) limit, tAA, tRAC and tCAC
must always be met.
22. The tRCD (MAX) limit is no longer specified. tRCD
(MAX) was specified as a reference point only. If
tRCD was greater than the specified tRCD (MAX)
limit, then access time was controlled exclusively by
tCAC (tRAC [MIN] no longer applied). With or
without the tRCD limit, tAA and tCAC must always
be met.
23. Either tRCH or tRRH must be satisfied for a READ
cycle.
24. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# is LOW and
OE# is HIGH.
25. The refresh period is extended from 32ms (2K refresh)
or 64ms (4K refresh) to 128ms (both 2K and 4K
refreshes). For 4K refresh, tRC = 31.25µs (128ms/
4,096 rows = 31.25µs) and for 2K refresh, tRC = 62.5µs
(128ms/2,048 rows = 62.5µs).
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
READ CYCLE
tRC
tRP
tRAS
RAS#
V IH
V IL
tCSH
tRRH
tRSH
tRCD
tCRP
tCAS
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,, , ,
, ,
,
,
,,,,,,,,,,,,
,
,
,
,
,
, ,
,,,,
CAS#
V IH
V IL
tAR
tRAD
tASR
tRAH
tASC
tCAH
tACH
ADDR
V IH
V IL
ROW
ROW
COLUMN
tRCH
tRCS
WE#
V IH
V IL
tAA
tRAC
NOTE 1
tOFF
tCAC
tCLZ
DQ
V OH
V OL
OPEN
OE#
OPEN
VALID DATA
t OE
t OD
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
MIN
tAA
-6
MAX
MIN
UNITS
SYMBOL
30
tOFF
tACH
12
15
ns
ns
tAR
38
0
0
45
0
0
ns
ns
ns
tRAD
ns
ns
tRC
ns
ns
ns
tRCH
tRRH
15
ns
ns
15
ns
tASC
tASR
25
-5
MAX
tCAC
13
tCAH
8
tCAS
8
0
5
tCLZ
tCRP
tCSH
tOD
tOE
38
0
15
10
10,000
12
12
10
0
5
45
0
10,000
MAX
MIN
MAX
UNITS
0
12
50
0
15
60
ns
ns
10,000
ns
ns
ns
tRAC
tRAH
tRAS
tRCD
tRCS
tRP
tRSH
-6
MIN
9
9
50
10,000
12
10
60
84
11
104
14
ns
ns
0
0
30
0
0
40
ns
ns
ns
0
13
0
15
ns
ns
NOTE: 1. tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
EARLY WRITE CYCLE
tRC
tRAS
RAS#
tRP
V IH
V IL
tCSH
tRSH
,
,
,, ,,, ,,,,,,
,
,
,
,,,,,,,,,, ,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,
,, ,, ,,
tCRP
CAS#
tRCD
tCAS
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tASC
tCAH
tACH
tRAH
ROW
ROW
COLUMN
tCWL
tRWL
tWCR
tWCS
tWCH
tWP
WE#
V IH
V IL
tDH
tDS
V
DQ V IOH
IOL
OE#
VALID DATA
V IH
V IL
,,
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tACH
tAR
tASC
tASR
tCAH
tCAS
tCRP
MIN
12
-6
MAX
38
0
0
8
8
MIN
15
-5
MAX
45
0
0
10,000
10
10
10,000
UNITS
ns
SYMBOL
tRAH
ns
ns
ns
tRAS
ns
ns
tRP
tRC
tRCD
tRSH
5
38
8
5
45
10
ns
ns
ns
tRWL
10
0
ns
ns
tWCS
tDS
8
0
tRAD
9
12
ns
tCSH
tCWL
tDH
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
tWCH
tWCR
tWP
12
-6
MIN
9
MAX
MIN
10
MAX
UNITS
ns
50
84
11
10,000
60
104
14
10,000
ns
ns
ns
30
13
40
15
ns
ns
13
8
38
15
10
45
ns
ns
ns
0
5
0
5
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC
tRAS
RAS#
tRP
V IH
V IL
tCSH
tRSH
,
,
,
,
,
,
,
,
,,, ,,, ,, , ,, ,
,,,,,
,,,,,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,, , , , ,, , ,
,,
tCRP
CAS#
tRCD
V IH
V IL
tAR
tRAD
tASR
ADDR
tCAS
V IH
V IL
tASC
tCAH
tACH
tRAH
ROW
COLUMN
tRCS
WE#
ROW
tRWD
tCWL
tCWD
tRWL
tAWD
tWP
V IH
V IL
tAA
tRAC
tCAC
tDS
t CLZ
V
DQ V IOH
IOL
VALID D OUT
OPEN
tOE
OE#
tDH
VALID D IN
tOD
OPEN
tOEH
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
MIN
tAA
-6
MAX
MIN
UNITS
SYMBOL
30
tOD
MAX
MIN
MAX
UNITS
0
12
12
0
15
15
ns
ns
60
ns
ns
ns
tACH
12
15
tAR
45
0
49
ns
ns
ns
tOEH
tAWD
38
0
42
tRAD
9
tASR
0
0
ns
ns
tRAH
9
50
ns
ns
ns
tRCD
tCAC
tCAH
tCAS
tCLZ
tCRP
13
8
8
0
10,000
15
10
10
0
10,000
tOE
tRCS
tRP
5
38
5
45
ns
ns
tRSH
35
10
10
ns
ns
ns
tRWD
tDH
28
8
8
tDS
0
0
ns
tCSH
tCWD
tCWL
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
8
tRAC
tRAS
tRWC
tRWL
tWP
13
-6
MIN
ns
ns
tASC
25
-5
MAX
10
50
12
10,000
10
60
10,000
ns
ns
11
0
30
14
0
40
ns
ns
ns
13
116
15
140
ns
ns
67
13
5
79
15
5
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
EDO-PAGE-MODE READ CYCLE
tRASP
tRP
V IH
V IL
RAS#
tCSH
tRSH
tCAS
tPC
,,, ,,,, ,,, ,,,
,,,,,,
,
,
,,,,,,,,, ,
, ,
tCRP
tRCD
tCAS
tCAS
tCP
tCP
V IH
V IL
CAS#
tAR
tRAD
tASR
V IH
V IL
ADDR
tACH
tACH
tASC
tRAH
ROW
tCAH
tASC
COLUMN
tCAH
tACH
tASC
COLUMN
tAA
tRAC
tCPA
tCAC
tCAC
tCOH
tCLZ
DQ
V OH
V OL
VALID
DATA
OPEN
OE#
tCPA
tCAC
tCLZ
tOFF
tOEHC
VALID
DATA
OPEN
tOE
tOD
tOES
V IH
V IL
tRRH
tAA
VALID
DATA
tOE
ROW
tRCH
V IH
V IL
tAA
,
,
,
,, ,,
,, ,
,,,,, ,
,, ,
tCAH
COLUMN
tRCS
WE#
tCP
tOD
tOES
tOEP
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tAA
tACH
-6
12
15
45
0
ns
ns
tOES
tASC
38
0
tASR
0
ns
ns
ns
tPC
tRAD
9
ns
ns
tRAH
9
50
ns
ns
tRCD
ns
ns
ns
tRCS
ns
ns
tCAC
8
tCAS
8
0
tCOH
tCP
tCSH
tOD
tOE
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
15
10
10,000
10
0
10,000
3
10
28
5
38
0
MAX
30
0
3
8
tCPA
tCRP
MIN
13
tCAH
tCLZ
MAX
25
-5
UNITS
ns
ns
tAR
MIN
35
5
45
12
12
0
15
15
SYMBOL
tOEHC
tOEP
tOFF
MIN
5
5
4
0
MIN
10
5
5
0
MAX
15
25
50
60
12
125,000
10
60
125,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
0
14
0
ns
ns
tRRH
0
30
0
0
40
0
ns
ns
ns
tRSH
13
15
ns
tRCH
tRP
14
12
20
tRAC
tRASP
-6
MAX
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
EDO-PAGE-MODE EARLY WRITE CYCLE
tRP
tRASP
RAS#
V IH
V IL
tCSH
tPC
tRSH
,
,
,
,
,
,,,,, ,,, ,, , ,
,
,
,
,
,
,
,
,
,
,
,,,,, , ,, ,, ,,,,,,
,, ,,,,,,,,,,,,,,,,,
,
, ,,
tCRP
CAS#
tRCD
tCAS
tCP
tCAS
tCP
tCAS
tCP
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tACH
tASC
ROW
tACH
tCAH
tASC
COLUMN
tCAH
COLUMN
tCWL
tWCH
tWCS
tWCS
tWCH
tWP
tWP
V IH
V IL
tWCR
tDS
V
DQ V IOH
IOL
OE#
ROW
tCWL
tWCH
tWP
WE#
tASC
COLUMN
tCWL
tWCS
tACH
tCAH
tDH
tDS
VALID DATA
tDH
tRWL
tDH
tDS
VALID DATA
VALID DATA
V IH
V IL
,
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tACH
tAR
tASC
tASR
tCAH
tCAS
tCP
MIN
12
-6
MAX
MIN
15
-5
MAX
UNITS
ns
SYMBOL
tPC
38
0
45
0
ns
ns
tRAD
0
8
8
0
10
10
ns
ns
ns
tRASP
10,000
10,000
tRAH
tRCD
tRP
8
5
10
5
ns
ns
tRSH
45
10
10
ns
ns
ns
tWCH
tDH
38
8
8
tDS
0
0
ns
tWP
tCRP
tCSH
tCWL
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
tRWL
tWCR
tWCS
15
MIN
20
-6
MAX
9
9
50
11
30
MIN
25
MAX
12
10
125,000
60
14
40
UNITS
ns
ns
ns
125,000
ns
ns
ns
13
13
15
15
ns
ns
8
38
0
10
45
0
ns
ns
ns
5
5
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP
RAS#
tRP
V IH
V IL
tCSH
tPRWC NOTE 1
t PC
tRSH
,
,
,
,
,
,
, , ,,, ,, ,, ,
,
,
,
,
,
,, ,
,,
,,
,,
,
,
,
,
,
,,
,
,
,
,
,, ,, ,,
,
,
,
,,,
tCRP
CAS#
tRCD
tCAS
tCP
tCAS
tCP
tCAS
tCP
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tASC
ROW
tCAH
tASC
COLUMN
tCAH
tASC
COLUMN
tCAH
COLUMN
ROW
tRWD
tRCS
WE#
tRWL
tCWL
tCWL
tWP
tAWD
tCWD
tWP
tAWD
tCWD
tAA
tCWD
tAA
tDH
tDS
V IOH
V IOL
tCPA
tCAC
tCAC
tCLZ
tCLZ
VALID
D OUT
OPEN
tAA
tDH
tDS
tDH
tCPA
tDS
tCAC
tCLZ
VALID
D IN
VALID
D OUT
tOD
VALID
D IN
VALID
D OUT
tOD
tOE
OE#
tAWD
V IH
V IL
tRAC
DQ
tCWL
tWP
VALID
D IN
OPEN
tOD
tOE
tOE
tOEH
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tAA
tAR
-6
38
45
0
0
ns
ns
tOEH
tASR
0
0
tPC
8
20
tAWD
42
ns
ns
ns
tPRWC
47
tRAD
9
ns
ns
tRAH
9
50
tRCD
tCAC
MAX
25
MIN
-5
UNITS
ns
ns
tASC
MIN
49
13
tCAH
8
tCAS
tCLZ
8
0
tCP
8
MAX
30
15
10
10,000
10
0
10,000
tRASP
tCRP
5
5
tCSH
38
28
45
35
ns
ns
tRSH
8
8
10
10
ns
ns
tRWL
tDH
tDS
0
0
ns
tCWD
tCWL
28
35
MIN
0
tRAC
ns
ns
ns
tCPA
10
SYMBOL
tOD
tOE
tRCS
tRP
tRWD
tWP
-6
MAX
12
12
MIN
0
MAX
15
15
10
25
ns
ns
56
50
60
12
125,000
10
60
UNITS
ns
ns
125,000
ns
ns
ns
ns
ns
11
0
30
14
0
40
ns
ns
ns
13
67
15
79
ns
ns
13
5
15
5
ns
ns
NOTE: 1. tPC is for LATE WRITE cycles only.
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
t RP
t RASP
RAS#
V IH
V IL
t CSH
t PC
t CRP
t RCD
t RSH
t PC
t CP
t CAS
t CP
t CAS
t CP
t CAS
,,,,, ,,, ,,,, ,,,
,
,, ,,
,,,,,,,,
,
,
,
,
CAS#
V IH
V IL
t AR
t RAD
tASR
ADDR
V IH
V IL
t ACH
t RAH
t ASC
ROW
t CAH
t ASC
COLUMN (A)
t CAH
COLUMN (B)
V IH
V IL
t WCS
ROW
t WCH
t AA
t AA
t CPA
t RAC
t CAC
t CAC
t COH
DQ V IOH
V IOL
t CAH
COLUMN (N)
t RCH
t RCS
WE#
t ASC
OPEN
VALID DATA (A)
t DS
t DH
t WHZ
VALID
DATA (B)
VALID DATA
IN
t OE
OE#
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tAA
tACH
-6
12
15
45
0
ns
ns
tRAC
tASC
38
0
tRAD
9
tASR
0
0
ns
ns
ns
tRAH
9
50
ns
ns
tRCH
ns
ns
tRP
tWCH
tCAC
MIN
13
tCAH
8
tCAS
tCOH
8
3
tCP
8
tCPA
tCRP
MAX
25
-5
UNITS
ns
ns
tAR
MIN
MAX
30
15
10
10,000
10
3
10,000
10
28
35
tDH
5
38
8
5
45
10
ns
ns
ns
tDS
0
0
ns
tCSH
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
SYMBOL
MIN
tOE
tPC
tRASP
tRCD
tRCS
tRSH
tWCS
tWHZ
17
-6
MAX
MIN
12
20
MAX
UNITS
15
ns
60
ns
ns
ns
25
50
12
125,000
10
60
125,000
ns
ns
11
0
0
14
0
0
ns
ns
ns
30
13
40
15
ns
ns
8
0
0
10
0
0
ns
ns
ns
12
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
READ CYCLE
(With WE#-controlled disable)
RAS#
V IH
V IL
tCSH
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,, , ,
,
,
,
,
,, ,,,,,,,,,
,
,
,
,
, ,
,,, ,
tRCD
tCRP
CAS#
tCAS
tCP
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tASC
ROW
tCAH
tASC
COLUMN
COLUMN
tRCS
WE#
tRCH
tWPZ
tRCS
V IH
V IL
tAA
tRAC
tCAC
tWHZ
tCLZ
DQ
V OH
V OL
OPEN
VALID DATA
t OE
OE#
tCLZ
OPEN
t OD
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tAA
tAR
tASC
tASR
MIN
38
0
tCAS
tCLZ
tCP
MIN
0
13
8
8
0
-5
MAX
30
45
0
0
tCAC
tCAH
-6
MAX
25
10,000
15
10
10
0
10,000
UNITS
ns
ns
ns
ns
ns
tRAD
ns
ns
ns
tRCD
tWHZ
tCRP
8
5
10
5
ns
ns
tCSH
38
45
ns
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
SYMBOL
tOD
tOE
tRAC
tRAH
tRCH
tRCS
tWPZ
18
MIN
0
-6
MAX
12
12
50
MIN
0
MAX
15
15
60
UNITS
ns
ns
ns
9
9
12
10
ns
ns
11
0
0
14
0
0
ns
ns
ns
0
10
12
0
10
15
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
RAS#-ONLY REFRESH CYCLE
(OE# and WE# = DON’T CARE)
tRC
tRAS
CAS#
ADDR
,
,
,
,
,,,,, ,,
V IH
V IL
,,
RAS#
tRP
tCRP
tRPC
V IH
V IL
tASR
tRAH
V IH
V IL
ROW
V
DQ V OH
OL
ROW
OPEN
CBR REFRESH CYCLE
(Addresses and OE# = DON’T CARE)
tRP
RAS#
tRAS
tRP
tRAS
V IH
V IL
tRPC
,,,,,,,,,,,,,,,,,,,,
,
,,,
tCP
CAS#
V IH
V IL
DQ
V OH
V OL
tCSR
tCHR
OPEN
tWRP
WE#
tRPC
tCHR
tCSR
tWRH
tWRP
tWRH
V IH
V IL
,
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tASR
tCHR
MIN
0
-6
MAX
MIN
0
-5
MAX
UNITS
ns
SYMBOL
tRAS
8
8
10
10
ns
ns
tRC
5
5
5
5
ns
ns
tRPC
tCSR
tRAH
9
10
ns
tCP
tCRP
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
-6
MAX
10,000
MIN
60
MAX
10,000
UNITS
ns
84
30
104
40
ns
ns
tWRH
5
8
5
10
ns
ns
tWRP
8
10
ns
tRP
19
MIN
50
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
HIDDEN REFRESH CYCLE 24
(WE# = HIGH; OE# = LOW)
tRAS
tRP
tRAS
V IH
V IL
,
,
,
,
,
,
,,
,
,
,
,
,
, ,, , , , , ,
,
,
,
,
,
,
,
,
,
,
,
,
,
, , ,,
,,, ,
,
RAS#
tCRP
CAS#
tRSH
tRCD
tCHR
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tASC
ROW
tCAH
COLUMN
tAA
tRAC
tOFF
tCAC
tCLZ
V
DQ V OH
OL
OPEN
VALID DATA
OPEN
tOD
tOE
tORD
V
OE# V IH
IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
MIN
tAA
tAR
tASC
tASR
-6
MAX
MIN
25
38
0
0
tCAC
-5
MAX
UNITS
30
ns
ns
ns
ns
tOE
tRAD
45
0
0
tORD
8
10
tCHR
10
0
5
ns
ns
ns
tRAS
tCRP
8
0
5
tOD
0
ns
tRSH
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
0
15
MIN
tRAH
tRCD
tRP
20
-6
MAX
MIN
12
0
0
tRAC
tCAH
12
15
tOFF
ns
ns
tCLZ
13
SYMBOL
12
0
0
50
9
9
50
11
30
13
MAX
UNITS
15
ns
15
ns
ns
60
ns
ns
ns
10,000
ns
ns
12
10
10,000
60
14
40
15
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
SELF REFRESH CYCLE
(Addresses and OE# = DON’T CARE)
RAS#
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,, , ,, ,, ,, ,
V IH
V IL
V IH
V IL
DQ
V OH
V OL
WE#
((
))
tRPC
tCP
CAS#
NOTE 1
tRASS
tRP
NOTE 2
tRPC
((
))
tCSR
tRPS
((
))
tCP
tCHD
((
))
((
))
((
))
tWRP
OPEN
tWRP
tWRH
tWRH
((
))
((
))
V IH
V IL
,,
,,
DON'T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tCHD
tCP
tCSR
tRASS
tRP
MIN
15
8
5
100
30
-6
MAX
MIN
15
10
5
100
40
-5
MAX
UNITS
ns
ns
ns
µs
ns
SYMBOL
tRPC
tRPS
tWRH
tWRP
MIN
5
90
8
8
-6
MAX
MIN
5
105
10
10
MAX
UNITS
ns
ns
ns
ns
NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter Self Refresh mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
24/26-PIN PLASTIC SOJ (300 mil)
DA-2
.679 (17.25)
.673 (17.09)
.305 (7.75)
.299 (7.59)
.340 (8.64)
.330 (8.38)
PIN #1 INDEX
.050 (1.27) TYP
.600 (15.24) TYP
.037 (0.94) MAX
DAMBAR PROTRUSION
.032 (0.81)
.026 (0.66)
.142 (3.61)
.132 (3.35)
SEATING PLANE
.020 (0.51)
.015 (0.38)
NOTE:
.109 (2.77)
.094 (2.39)
.040 (1.02)
R
.030 (0.76)
.275 (6.99)
.260 (6.60)
.025 (0.64)
MIN
MAX
or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
1. All dimensions in inches (millimeters)
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
24/26-PIN PLASTIC TSOP (300 mil)
DB-2
.678 (17.23)
.672 (17.07)
SEE DETAIL A
.037 (0.95)
.367 (9.32)
.359 (9.12)
.302 (7.67)
.298 (7.57)
.007 (0.18)
.005 (0.13)
PIN #1 INDEX
.050 (1.27)
TYP
.020 (0.50)
.012 (0.30)
.010 (0.25)
.004 (0.10)
.047 (1.20)
MAX
SEATING PLANE
.006 (0.15)
.002 (0.05)
DETAIL A
NOTE:
GAGE PLANE
.024 (0.60)
.016 (0.40)
.032 (0.80)
TYP
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900, Micron DataFax: 208-368-5800
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.