Megawin MG74PG1A08 Interrupt controller Datasheet

8051-Based MCU
MG74PG1A08
Data Sheet
Version: 0.25
This document contains information on a new product under development by Megawin. Megawin reserves the right to change or
discontinue this product without notice.
 Megawin Technology Co., Ltd. 2005 All rights reserved.
2016/11 version 0.25
Features

1-T 80C51 Central Processing Unit

MG74PG1A08 with 8K Bytes OTP ROM
━ Code protection for OTP memory access
━ OTP data retention: 10 years at 85°C

On-chip 256 bytes scratch-pad RAM

Interrupt controller
━ 6 sources, two-level-priority interrupt capability
━ Two external interrupt inputs, nINT0 and nINT1
━ All external interrupts support High/Low level or Rising/Falling edge trigger

Two 16-bit timer/counters, Timer 0 and Timer 1
━ T0CKO on P1.4, T1CKO on P1.5
━ X12 mode enabled for T0/T1

Programmable 16-bit counter/timer Array (PCA) with one capture/compare module.
━ Capture mode, 16-bit software timer mode and High speed output mode
━ 8-bit PWM mode, 16-bit PWM, double channel 8-bit PWM

Keypad Interrupt function on all GPIO.

Enhanced UART0 (S0)
━ Framing Error Detection
━ Speed improvement mechanism (X2 mode)
━ SPI master/Slave support in mode 4/6

Two wire interface Start/Stop detection (STWI, IIC compatible)

USB Device Controller
━ USB Full speed (12Mbps) operation and USB specification 2.0 compliant
━ Intel 8X931 like USB control flow
━ Built-in USB transceiver and 3.3V regulator
━ Integrated clock recovery, no external crystal required
━ 8-bytes FIFO for EP0 control In/Out
━ 8-bytes FIFO for EP1 INT/BULK In
━ 16-bytes FIFO for EP2 INT/BULK In/Out (default: In)
━ Software-controlled USB connection/disconnection mechanism

Programmable Watchdog Timer, clock sourced from ILRCO (64KHz)
━ One time enabled by CPU or power-on
━ Interrupt CPU or Reset CPU on WDT overflow
━ Support WDT function in power down mode (watch mode)

Maximum 11 GPIOs in SOP16 package
━ P3 can be configured to quasi-bidirectional, push-pull output, open-drain output and analog-input-only
━ P1 can be configured to open-drain with pull-up resistor, push-pull output, open-drain and
analog-input-only

Multiple power control modes: idle mode, power-down mode, slow mode, sub-clock mode, watch mode and
monitor mode.
━ All interrupts can wake up IDLE mode
━ 8 sources to wake up Power-Down mode
━ Slow mode and sub-clock mode support low speed MCU operation
━ Watch mode supports WDT to resume CPU in power down

One POR & Two Brown-Out Detectors
━ POR: detect 1.95V (2.3V Select by SFR)
━ BOD0: detect 2.1V (2.6V Select by SFR)
2
MG74PG1A08 Data Sheet
MEGAWIN
━
━
BOD1: detect 3.6V
Interrupt CPU or reset CPU

Operating voltage range(with LDO): 2.3V – 5.5V (RMLS=0)

Operating voltage range(without LDO, for battery): 2.0V – 3.6V (RMLS=0)

Operation frequency range: 12MHz(max)
━ 0 – 6MHz @ 2.0V – 5.5V, 0 – 12MHz @ 2.4V – 5.5V, 0 – 24MHz @ 2.7V – 5.5V
━ CPU up to 3MHz @ 2.0V – 5.5V, up to 6MHz @ 2.4V – 5.5V and up to 12MHz @ 2.7V – 5.5V

Clock Sources
━ Internal 12MHz oscillator (IHRCO) with USB clock recovery enabled: ±0.25% accuracy
━ Internal 12MHz oscillator (IHRCO) without USB clock recovery: factory calibrated to ±1%, typical
━ Internal Low frequency RC Oscillator (ILRCO) support: about 64KHz
━ External clock input (ECKI) on P1.7
━ Internal Oscillator output (ICKO) on p1.7
━ On-chip Clock Multiplier (CKM) to provide high speed clock source

Operating Temperature:
━ Industrial (-40℃ to +85℃)*

Package Types:
━ DICE: MG74PG1A08AH
━ SOP16: MG74PG1A08AS16
━ QFN16: MG74PG1A08AY16 (4X4)
*: Tested by sampling.
MEGAWIN
MG74PG1A08 Data Sheet
3
Content
Features ............................................................................................................ 2
Content ............................................................................................................ 4
1. General Description .................................................................................... 7
2. Block Diagram ............................................................................................ 8
3. Special Function Register ........................................................................... 9
3.1.
3.2.
4.
Pin Configurations .................................................................................... 11
4.1.
4.2.
4.3.
5.
On-Chip Program OTP ........................................................................................ 18
On-Chip Data RAM ............................................................................................. 19
Declaration Identifiers in a C51-Compiler ............................................................ 21
Data Pointer Register (DPTR) .................................................................. 22
System Clock ........................................................................................... 23
8.1.
8.2.
9.
CPU Register ...................................................................................................... 15
CPU Timing ......................................................................................................... 16
CPU Addressing Mode ........................................................................................ 17
Memory Organization ............................................................................... 18
6.1.
6.2.
6.3.
7.
8.
Package Instruction ............................................................................................. 11
Pin Description .................................................................................................... 13
Alternate Function Redirection ............................................................................ 14
8051 CPU Function Description ............................................................... 15
5.1.
5.2.
5.3.
6.
SFR Map ............................................................................................................... 9
SFR Bit Assignment ............................................................................................ 10
Clock Structure .................................................................................................... 24
Clock Register ..................................................................................................... 24
Watch Dog Timer (WDT) .......................................................................... 27
9.1.
9.2.
9.3.
9.4.
WDT Structure .................................................................................................... 27
WDT during Idle and Power Down ...................................................................... 27
WDT Register ...................................................................................................... 27
WDT Hardware Option ........................................................................................ 29
10. System Reset ........................................................................................... 30
10.1.
10.2.
10.3.
10.4.
10.5.
10.6.
Reset Source ...................................................................................................... 30
Power-On Reset .................................................................................................. 30
External Reset ..................................................................................................... 31
Software Reset .................................................................................................... 31
Brown-Out Reset ................................................................................................. 32
WDT Reset.......................................................................................................... 33
11. Power Management ................................................................................. 34
11.1. Brown-Out Detector............................................................................................. 34
11.2. Power Saving Mode ............................................................................................ 35
11.2.1. Slow Mode ................................................................................................................. 35
11.2.2. Sub-Clock Mode ......................................................................................................... 35
11.2.3. Watch Mode ............................................................................................................... 35
11.2.4. Monitor Mode ............................................................................................................. 35
11.2.5. Idle Mode ................................................................................................................... 35
11.2.6. Power-down Mode ..................................................................................................... 36
11.2.7. Interrupt Recovery from Power-down ......................................................................... 37
11.2.8. Reset Recovery from Power-down ............................................................................. 37
4
MG74PG1A08 Data Sheet
MEGAWIN
11.2.9. KBI wakeup Recovery from Power-down.................................................................... 37
11.2.10.
USB wakeup Recovery from Power-down .......................................................... 37
11.3. Power Control Register ....................................................................................... 38
12. Configurable I/O Ports .............................................................................. 40
12.1. IO Structure ......................................................................................................... 40
12.1.1. Port 3 Analog-Input-Only (High Impedance) Structure ................................................ 40
12.1.2. Port 3 Quasi-Bidirectional IO Structure (default) ......................................................... 41
12.1.3. Port 3 Open-Drain Output Structure ........................................................................... 42
12.1.4. Port 3 Push-Pull Output Structure .............................................................................. 42
12.1.5. Port 3 Digital-Input-Only (High Impedance Input) Structure ........................................ 43
12.1.6. DP/DM Structure ........................................................................................................ 43
12.1.7. General Analog-Input-Only (High Impedance) Structure (default)............................... 43
12.1.8. General Open-Drain Output with Pull-up Resistor Structure ....................................... 44
12.1.9. General Open-Drain Output Structure ........................................................................ 44
12.1.10.
General Push-Pull Output Structure.................................................................... 45
12.1.11.
General Digital-Input-Only (High Impedance Input) Structure ............................. 45
12.2. I/O Port Register ................................................................................................. 46
12.2.1. Port 1 Register ........................................................................................................... 46
12.2.2. Port 3 Register ........................................................................................................... 47
13. Interrupt .................................................................................................... 48
13.1.
13.2.
13.3.
13.4.
13.5.
13.6.
13.7.
13.8.
Interrupt Structure ............................................................................................... 48
Interrupt Source .................................................................................................. 50
Interrupt Enable ................................................................................................... 52
Interrupt Priority ................................................................................................... 52
Interrupt Process ................................................................................................. 53
Special Interrupt Vector for TI0 ........................................................................... 53
nINT0/nINT1 Input Source Selection ................................................................... 54
Interrupt Register ................................................................................................ 54
14. Timers/Counters ....................................................................................... 58
14.1. Timer0 and Timer1 .............................................................................................. 58
14.1.1. Mode 0 Structure ........................................................................................................ 58
14.1.2. Mode 1 Structure ........................................................................................................ 59
14.1.3. Mode 2 Structure ........................................................................................................ 60
14.1.4. Mode 3 Structure ........................................................................................................ 61
14.1.5. Timer 0/1 Programmable Clock-Out ........................................................................... 62
14.1.6. Timer0/1 Register ....................................................................................................... 64
15. Programmable Counter Array (PCA) ........................................................ 66
15.1.
15.2.
15.3.
15.4.
PCA Overview ..................................................................................................... 66
PCA Timer/Counter ............................................................................................. 66
Compare/Capture Modules ................................................................................. 70
Operation Modes of the PCA .............................................................................. 71
15.4.1. Capture Mode ............................................................................................................ 71
15.4.2. 16-bit Software Timer Mode ....................................................................................... 72
15.4.3. High Speed Output Mode ........................................................................................... 73
15.4.4. 8-bit PWM Mode (Buffered 8-bit PWM) ...................................................................... 74
15.4.5. 16-bit PWM Mode (Un-Buffered) ................................................................................ 75
15.4.6. Double Channel PWM Mode (Un-Buffered 8-bit PWM) .............................................. 76
16. Serial Port 0 (UART0)............................................................................... 77
16.1.
16.2.
16.3.
16.4.
16.5.
Serial Port 0 Mode 0............................................................................................ 78
Serial Port 0 Mode 1............................................................................................ 80
Serial Port 0 Mode 2 and Mode 3 ........................................................................ 81
Frame Error Detection ......................................................................................... 81
Baud Rate Setting ............................................................................................... 82
MEGAWIN
MG74PG1A08 Data Sheet
5
16.5.1. Baud Rate in Mode 0 .................................................................................................. 82
16.5.2. Baud Rate in Mode 2 .................................................................................................. 82
16.5.3. Baud Rate in Mode 1 & 3 ........................................................................................... 83
16.6. Serial Port 0 Mode 4 (SPI Master) ...................................................................... 85
16.7. Serial Port 0 Mode 6 (SPI Slave) ........................................................................ 87
16.8. Serial Port 0 Register .......................................................................................... 88
17. Keypad Interrupt (KBI) .............................................................................. 91
17.1. Keypad Interrupt Structure .................................................................................. 91
17.2. Keypad Interrupt Register ................................................................................... 92
18. Serial Interface Detection (SID/STWI) ...................................................... 93
18.1. Serial Interface Detection Structure .................................................................... 93
18.2. Serial Interface Detection Register ...................................................................... 94
19. Universal Serial Bus (USB)....................................................................... 95
19.1.
19.2.
19.3.
19.4.
19.5.
19.6.
19.7.
19.8.
19.9.
Features .............................................................................................................. 95
Block Diagram ..................................................................................................... 95
FIFO Management .............................................................................................. 96
Access USB 32 bytes FIFO ................................................................................. 96
USB Initial ........................................................................................................... 97
Access USB SFR ................................................................................................ 98
USB Interrupt ...................................................................................................... 99
USB Special Function Registers ....................................................................... 100
USB Function SFR Mapping ............................................................................. 100
19.9.1. USB Function SFR Bit Assignment........................................................................... 101
20. Protected-Write SFR Access ...................................................................110
21. Hardware Option .....................................................................................111
22. Application Notes ....................................................................................112
22.1.
22.2.
22.3.
22.4.
Power Supply Circuit ......................................................................................... 112
Reset Circuit ...................................................................................................... 113
With USB application Circuit ............................................................................. 114
ICP Interface Circuit .......................................................................................... 115
23. Electrical Characteristics .........................................................................116
23.1.
23.2.
23.3.
23.4.
23.5.
23.6.
23.7.
23.8.
23.9.
Absolute Maximum Rating ................................................................................ 116
DC Characteristics ............................................................................................ 117
USB Transceiver Electrical Characteristics ....................................................... 118
External Clock Characteristics .......................................................................... 119
IHRCO Characteristics ...................................................................................... 119
ILRCO Characteristics....................................................................................... 119
CKM Characteristics.......................................................................................... 120
OTP Characteristics .......................................................................................... 120
Serial Port 0 Timing Characteristics .................................................................. 120
24. Instruction Set .........................................................................................121
25. Package Dimension ................................................................................124
25.1. SOP16............................................................................................................... 124
25.2. QFN16............................................................................................................... 125
26. Revision History ......................................................................................126
27. Disclaimers ..............................................................................................127
6
MG74PG1A08 Data Sheet
MEGAWIN
1. General Description
The MG74PG1A08 is a single-chip micro-controller based on a high performance 1-T architecture 80C51 CPU that
executes instructions in 1~7 clock cycles (about 6~7 times the rate of a standard 8051 device), and has an 8051
compatible instruction set. Therefore at the same performance as the standard 8051, the MG74PG1A08 can
operate at a much lower speed and thereby greatly reduce the power consumption.
The MG74PG1A08 has 8K bytes of embedded OTP memory for CPU execution code. The OTP memory can be
programmed in serial writer mode (via ICP, In-Circuit Programming). ICP allows the user to download new code
without removing the microcontroller from the actual end product.
The MG74PG1A08 retains all features of the standard 80C52 with 256 bytes of scratch-pad RAM, 11 Programmable
I/O pins, two external interrupts, a multi-source 2-level interrupt controller, a serial port 0 (UART0) and two
timer/counters. In addition, the MG74PG1A08 has a full speed USB device function, an one-channel 16-bit PCA,
SPI, STWI, keypad interrupt, an one-time enabled Watchdog Timer, two Brown-out Detectors, an internal high
precision RC oscillator (IHRCO) to fit USB full speed application, an internal low speed RC oscillator (ILRCO) and
an enhanced serial function in UART0 that facilitates SPI master/slave engine and a speed improvement
mechanism (X2 mode).
The MG74PG1A08 has multiple operating modes to reduce the power consumption: idle mode, power down mode,
slow mode, sub-clock mode, watch mode and monitor mode. In the Idle mode the CPU is frozen while the
peripherals and the interrupt system are still operating. In the Power-Down mode the RAM and SFRs’ value are
saved and all other functions are inoperative; most importantly, in the Power-down mode the device can be waked
up by many interrupt or reset sources. In slow mode, the user can further reduce the power consumption by using
the 8-bit system clock pre-scaler to slow down the operating speed. Or select sub-clock mode which clock source is
derived from internal low speed oscillator (ILRCO) for CPU to perform an ultra-low speed operation. In watch mode,
it keeps WDT running in power-down or idle mode and resumes CPU when WDT overflows. Monitor mode provides
the Brown-Out detection in power down mode and resumes CPU when chip VDD reaches the specific detection
level.
MEGAWIN
MG74PG1A08 Data Sheet
7
2. Block Diagram
Figure 2–1. Block Diagram
(P1.7) ICKO/ECKI
Clock
Multiplier
(P1.6/P3.2) nINT0
(P1.4) T0CKO/T0
(P1.5) T1CKO/T1
(P1.6) ECI
(P1.0/P1.2) CEX0
(P1.1/P1.3) PWM0
(P1.0/P3.0) RXD0
(P1.1/P3.1) TXD0
(TXD) SPICLK
(RXD) MOSI
(P3.2) MISO
(P1.6) nSS
(nINT1) STWI_SCL
(P1.1/P1.5/P3.1/P3.6) STWI_SDA
ALL GPIO
VDD
Ext. INT
Timer0
Timer1
PCA
Timer
UART0
(SPI M/S)
WDT
OTP ROM
8K X 8
RAM
256 X 8
Port1
P1.0~P1.7
Port3
P3.0~P3.2
P3.6~P3.7
STWI
STA/STO
Detection
Keypad Int.
BOD0
BOD1
Regulator
3.3V
8
ILRCO
64KHz
8051 CPU (1T)
(P1.7) nRST
(P1.0/P1.4/P3.0/P3.7) nINT1
IHRCO
12MHz
MG74PG1A08 Data Sheet
USB FIFO
USB Control
USB XCVR
DP (P3.7)
DM (P3.6)
MEGAWIN
3. Special Function Register
3.1. SFR Map
Table 3–1. SFR Map
0/8
1/9
F8
CH
-F0
B
-E8
CL
-E0
ACC
WDTCR
D8
CCON
CMOD
D0
PSW
-C8
--C0
--B8
IP0L
-B0
P3M0
P3
A8
IE
-A0
AUXR0
-98
S0CON
S0BUF
90
P1M0
P1
88
TCON
TMOD
80
-SP
0/8
1/9
MEGAWIN
2/A
CCAP0H
-CCAP0L
-CCAPM0
---PCON2
P3M1
USBDAT
AUXR1
-P1M1
TL0
DPL
2/A
3/B
--------CKCON2
-USBADR
AUXR2
--TL1
DPH
3/B
4/C
--------DCON0
-----TH0
-4/C
5/D
--------SPCON0
-XPIE1
---TH1
-5/D
MG74PG1A08 Data Sheet
6/E
---SCMD
-KBIEN0
CLRL
------BOREV
SFIE
-6/E
7/F
------CHRL
CKCON0
-----PCON1
-PCON0
7/F
9
3.2. SFR Bit Assignment
Table 3–2. SFR Bit Assignment
SYMBOL
DESCRIPTION
ADDR
P1
P1M0
P1M1
BOREV
PCON1
S0CON
S0BUF
AUXR0
AUXR1
Stack Pointer
Data Pointer Low
Data Pointer High
Power Control 0
Timer Control
Timer Mode
Timer Low 0
Timer Low 1
Timer High 0
Timer High 1
System Flag INT
Enable
Port 1
P1 Mode Register 0
P1 Mode Register 1
Bit Order Reversed
Power Control 1
Serial 0 Control
Serial 0 Buffer
Auxiliary Register 0
Auxiliary Register 1
AUXR2
Auxiliary Register 2
IE
USBDAT
Interrupt Enable
USB Data Register
USB Indirect
Address
Expanded INT. 1
Enable
Port 3
P3 Mode Register 0
P3 Mode Register 1
Interrupt Priority Low
Power Control 2
Clock Control 2
Device Control 0
SFR Page Control 0
Clock Control 0
PCA base timer Low
Reload register
PCA base timer
High Reload register
Program Status
Word
KBI Enable 0
PCA Control Reg.
PCA Mode Reg.
PCA Module0 Mode
Accumulator
Watch-dog-timer
Control register
ISP Serial
Command
PCA base timer Low
PCA module0
capture Low
B Register
PCA base timer
High
PCA Module0
capture High
SP
DPL
DPH
PCON0
TCON
TMOD
TL0
TL1
TH0
TH1
SFIE
USBADR
XPIE1
P3
P3M0
P3M1
IP0L
PCON2
CKCON2
DCON0
SPCON0
CKCON0
CLRL
CHRL
PSW
KBIEN0
CCON
CMOD
CCAPM0
ACC
WDTCR
SCMD
CL
CCAP0L
B
CH
CCAP0H
10
BIT ADDRESS AND SYMBOL
RESET
VALUE
81H
82H
83H
87H
88H
89H
8AH
8BH
8CH
8DH
Bit-7
.7
.7
.7
SMOD1
TF1
GATE
.7
.7
.7
.7
Bit-6
.6
.6
.6
SMOD0
TR1
C/T
.6
.6
.6
.6
Bit-5
.5
.5
.5
GF
TF0
M1
.5
.5
.5
.5
Bit-4
.4
.4
.4
POF
TR0
M0
.4
.4
.4
.4
Bit-3
.3
.3
.3
GF1
IE1
GATE
.3
.3
.3
.3
Bit-2
.2
.2
.2
GF0
IT1
C/T
.2
.2
.2
.2
Bit-1
.1
.1
.1
PD
IE0
M1
.1
.1
.1
.1
Bit-0
.0
.0
.0
IDL
IT0
M0
.0
.0
.0
.0
00000111
00000000
00000000
00010000
00000000
00000000
00000000
00000000
00000000
00000000
8EH
SIDFIE
--
--
--
KBIFIE
BOF1IE
BOF0IE
WDTFIE
0xxx0000
90H
91H
92H
96H
97H
98H
99H
A1H
A2H
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
11111111
P1M0.7
P1M0.6
P1M0.5
P1M0.4
P1M0.3
P1M0.2
P1M0.1
P1M0.0 00000000
P1M1.7
P1M1.6
P1M1.5
P1M1.4
P1M1.3
P1M1.2
P1M1.1
P1M1.0 00000000
BOREV.7 BOREV.6 BOREV.5 BOREV.4 BOREV.3 BOREV.2 BOREV.1 BOREV.0 00000000
SWRF
EXRF
--KBIF
BOF1
BOF0
WDTF
00xx0000
SM00/FE
SM10
SM20
REN0
TB80
RB80
TI0
RI0
00000000
.7
.6
.5
.4
.3
.2
.1
.0
xxxxxxxx
P17OC1 P17OC0
-T0XL
P1FS1
P1FS0
INT1H
INT0H
00000000
INT1IS1 INT1IS0 INT0IS0
-STAF
STOF
PTCKOE
-00000000
UTIE
BTI
URM0X3
A3H
SM30
T1X12
T0X12
T1CKOE T0CKOE 00000000
(CPHA)
(SSIG) (SMOD2)
A8H
EA
-EXPIE1
ES0
ET1
EX1
ET0
EX0
0x000000
AAH UDAT7
UDAT6
UDAT5
UDAT4
UDAT3
UDAT2
UDAT1
UDAT0
xxxxxxxx
ABH
UBSY
--
USFRA5
USFRA4
USFRA3
USFRA2
USFRA1
USFRA0
0x111111
ADH
EUSB
--
--
--
--
--
EPCA
ESF
0xxxxx00
P3.6
---EBOD1
-USBR
---
---PXPI1L
--ENUSB
-CCKS1
---PSL
-IHRCOE
ENCKM
WRCTL
CCKS0
---PT1L
BO1RE
MCKS1
CKMIS1
---
P3.2
P3M0.2
P3M1.2
PX1L
BO0RE
MCKS0
CKMIS0
CKCTL0
SCKS2
P3.1
P3M0.1
P3M1.1
PT0L
-OSCS1
RSTIO
PWCTL1
SCKS1
P3.0
P3M0.0
P3M1.0
PX0L
RMLS
OSCS0
SWRST
PWCTL0
SCKS0
11xxx111
0xxxx111
0xxxx000
0x000000
01000000
xxx10000
00000110
0xx00000
xx10x001
B0H
P3.7
B1H P3M0.7
B2H P3M1.7
B8H
URXR
BAH AWBOD1
BBH
-BCH
WCKS
BDH
-C7H
-CEH
.7
.6
.5
.4
.3
.2
.1
.0
00000000
CFH
.7
.6
.5
.4
.3
.2
.1
.0
00000000
D0H
CY
AC
F0
RS1
RS0
OV
F1
P
00000000
D6H
D8H
D9H
DAH
E0H
P3HKBI
CF
CIDL
P0INV
ACC.7
P3LKBI
CR
-ECOM0
ACC.6
---CAPP0
ACC.5
---CAPN0
ACC.4
P1HKBI
-CPS2
MAT0
ACC.3
P1LKBI
-CPS1
TOG0
ACC.2
--CPS0
PWM0
ACC.1
-CCF0
ECF
ECCF0
ACC.0
00xx00xx
00xxxxx0
0xxx0000
00000000
00000000
E1H
WREN
NSW
ENW
CLRW
WIDL
PS2
PS1
PS0
00000000
E6H
.7
.6
.5
.4
.3
.2
.1
.0
xxxxxxxx
E9H
.7
.6
.5
.4
.3
.2
.1
.0
00000000
EAH
.7
.6
.5
.4
.3
.2
.1
.0
00000000
F0H
B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
00000000
F9H
.7
.6
.5
.4
.3
.2
.1
.0
00000000
FAH
.7
.6
.5
.4
.3
.2
.1
.0
00000000
MG74PG1A08 Data Sheet
MEGAWIN
4. Pin Configurations
4.1. Package Instruction
Figure 4–1. MG74PG1A08AH Top View
LOGO
1
17
P3.6
16
VSS
15
14
P1.4 13
P1.7 P1.6 P1.5
P1.3 12
2
P3.7
3
VDD5V
4
VDDO
5
V33
DICE
P1.2
11
P1.1
10
P3.0 P3.1 P3.2 P1.0
6
7
8
9
Figure 4–2. MG74PG1A08AS16 Top View
(ECKI/ICKO/nRST) P1.7
VSS
(STWI_SDA/DM) P3.6
(nINT1/STWI_SCL/DP) P3.7
VDD
V33
(nINT1/STWI_SCL/MOSI/RXD0) P3.0
(STWI_SDA/SPICLK/TXD0) P3.1
MEGAWIN
1
2
3
4
5
6
7
8
SOP16
16
15
14
13
12
11
10
9
P1.6 (ECI/nSS/nINT0)
P1.5 (T1/T1CKO/STWI_SDA/PTCKO)
P1.4 (T0/T0CKO/STWI_SCL/nINT1)
P1.3 (PWM0S)
P1.2 (CEX0/VPP)
P1.1 (ICP_SCL/STWI_SDA/TXD0/PWM0S/SPICLK)
P1.0 (ICP_SDA/STWI_SCL/nINT1/RXD0/CEX0/MOSI)
P3.2 (ICP_CMD/nINT0/MISO)
MG74PG1A08 Data Sheet
11
P1.3(PWM0S)
P1.4(T0/T0CKO/STWI_SCL/nINT1)
P1.5(T1/T1CKO/STWI_SDA/PTCKO)
P1.6(ECI/nSS/nINT0)
Figure 4–3. MG74PG1A08AY16 Top View
(ECKI/ICKO/nRST)P1.7
P1.2(CEX0/VPP)
VSS
(TWI_SDA/DM)P3.6
(nINT1/STWI_SCL/DP)P3.7
P1.1(ICP_SCL/STWI_SDA/TXD0/PWM0S/SPICLK)
P1.0(ICP_SDA/STWI_SCL/nINT1/RXD0/CEX0/MOSI)
12
(STWI_SDA/SPICLK/TXD0)P3.1
(nINT1/TWI_SCL/MOSI/RXD0)P3.0
V33
VDD
P3.2(ICP_CMD/nINT0/MISO)
MG74PG1A08 Data Sheet
MEGAWIN
4.2. Pin Description
Table 4–1. Pin Description
PIN NUMBER
MNEMONIC
P3.0
(RXD0)
(STWI_SCL)
(MOSI)
(nINT1)
P3.1
(TXD0)
(SPICLK)
(STWI_SDA)
P3.2
(nINT0)
(MISO)
(ICP_CMD)
P3.6
(DM)
(STWI_SDA)
P3.7
(DP)
(nINT1)
(STWI_SCL)
P1.0
(nINT1)
(RXD0)
(MOSI)
(STWI_SCL)
(CEX0)
(ICP_SDA)
P1.1
(TXD0)
(SPICLK)
(STWI_SDA)
(PWM0S)
(ICP_SCL)
P1.2
(CEX0)
(VPP)
P1.3
(PWM0S)
P1.4
(T0)
(T0CKO)
(nINT1)
(STWI_SCL)
P1.5
(T1)
(T1CKO)
(STWI_SDA)
(PTCKO)
P1.6
(nINT0)
(ECI)
(nSS)
P1.7
(nRST)
(ICKO)
(ECKI)
V33
VDD
VSS
VDDO
MEGAWIN
16-Pin
SOP/
QFN
10-Pin
SOP
dice
I/O
TYPE
7
5
6
I/O
8
--
7
I/O
9
6
8
I/O
3
1
1
I/O
4
2
2
I/O
10
7
9
I/O
11
8
10
I/O
12
9
11
I/O
13
--
12
I/O
14
--
13
I/O
15
--
14
I/O
16
--
15
I/O
1
--
16
I/O
6
5
2
--
4
3
10
--
5
3
17
4
P
P
G
P
DESCRIPTION
* Port 3.0.
* RXD0: UART0 serial input port.
* TWI_SCL: SCL input for STWI Start/Stop detection.
* MOSI: SPI master out & slave in.
* nINT1: external interrupt 1 input.
* Port 3.1.
* TXD0: UART0 serial output port.
* SPICLK: SPI clock, output for master and input for slave.
* STWI_SDA: SDA input for STWI Start/Stop detection.
* Port 3.2.
* nINT0: External interrupt 0 input.
* MISO: SPI master in & slave out.
* ICP_CMD: Serial command of ICP interface.
* Port 3.6.
* DM: USB DM (D-) pin.
* STWI_SDA: SDA input for STWI Start/Stop detection.
* Port 3.7.
* DP: USB DP (D+) pin.
* nINT1: External interrupt 1 input.
* STWI_SCL: SCL input for STWI Start/Stop detection.
* Port 1.0.
* nINT1: External interrupt 1 input.
* RXD0: UART0 serial input port
* MOSI: SPI master out & slave in.
* STWI_SCL: SCL input for TWI Start/Stop detection.
* CEX0: PCA module 0 input/output.
* ICP_SDA: Serial data of ICP interface.
* Port 1.1.
* TXD0: UART0 serial output port
* SPICLK: SPI clock, output for master and input for slave.
* STWI_SDA: SDA input for TWI Start/Stop detection.
* PWM0S: PWM0 Secondary output.
* ICP_SCL: Serial clock of ICP interface.
* Port 1.2.
* CEX0: PCA module 0 input/output.
* VPP: VPP Pad for ICP interface.(attention: VPP voltage is 7.5V)
* Port 1.3.
* PWM0S: PWM0 Secondary output.
* Port 1.4.
* T0: Timer/Counter 0 external input.
* T0CKO: Programmable clock-out from Timer 0.
* nINT1: External interrupt 1 input
* STWI_SCL: SCL input for STWI Start/Stop detection.
* Port 1.5.
* T1: Timer/Counter 1 external input.
* T1CKO: Programmable clock-out from Timer 1.
* STWI_SDA: SDA input for STWI Start/Stop detection.
* PTCKO: PCA Base timer clock output.
* Port 1.6.
* nINT0: External interrupt 0 input.
* ECI: External clock trigger source for PCA
* nSS: SPI Slave select.
* Port 1.7.
* nRST: External reset input, low-active.
* ICKO: Internal clock output.
* ECKI: In external clock input mode, this is clock input pin.
Core power supply. 3.3V input/output.
Power supply input. 5V input.
Ground, 0 V reference.
Power supply for I/O pad.
MG74PG1A08 Data Sheet
13
4.3. Alternate Function Redirection
Many I/O pins, in addition to their normal I/O function, also serve the alternate function for internal peripherals. For
the peripherals UART0, STWI detection, nINT0 and nINT1, Port 1 and Port 3 serve the alternate function in the
default state. However, the user may select other Port to serve their alternate function by setting the corresponding
control bits INT1IS1, INT1IS0 and INT0IS0 in AUXR1 register. P1F1~P1FS0 in AUXR0 register select the
S0/PCA/Timer0/Timer1 function swapped to Port 1. It is especially useful by software programming.
AUXR0: Auxiliary Register 0
SFR Attribute = Normal Read/Write
SFR Address = 0xA1
7
6
5
P17OC1
P17OC0
GF
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
P1FS1
P1FS0
T0XL
R/W
R/W
R/W
1
INT1H
0
INT0H
R/W
R/W
Bit 7~6: P1.7 function configured control bit 1 and 0. The two bits only act when internal RC oscillator (IHRCO or
ILRCO) is selected for system clock source. In external clock input mode, P1.7 is the dedicated clock input pin. In
internal oscillator condition, P1.7 provides the following selections for GPIO or clock source generator. When
P17OC[1:0] index to non-P1.7 GPIO function, P1.7 will drive the on-chip RC oscillator output to provide the clock
source for other devices.
P17OC[1:0]
00
01
10
11
P1.7 function
P1.7
MCK
MCK/2
MCK/4
I/O mode
By P1M0.7 & P1M1.7
By P1M0.7 & P1M1.7
By P1M0.7 & P1M1.7
By P1M0.7 & P1M1.7
Please refer Section “8 System Clock” to get the more detailed clock information. For clock-out on P1.7 function, it is
recommended to set P1M0.7 and P1M1.7 to “11” which selects P1.7 as push-pull output mode.
Bit 2: P1FS1~0, P1.1 and P1.0 alternated function selection.
P1FS[1:0]
P1.1
P1.0
00
Reserved
Reserved
01
TXD0
RXD0
10
PWM0S
CEX0
11
T1/T1CKO
T0/T0CKO
AUXR1: Auxiliary Control Register 1
SFR Attribute = Normal Read/Write
SFR Address = 0xA2
7
6
5
INT1IS1
INT1IS0
INT0IS0
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
GF
STAF
STOF
R/W
R/W
R/W
1
PTCKOE
0
GF
R/W
R/W
Bit 7~6: INT1IS1~0, input selection bits of nINT1, TWI_SCL and TWI_SDA, which function is defined as following
table.
INT1IS.1~0
nINT1 & TWI_SCL
TWI_SDA
00
P1.0
P1.1
01
P1.4
P1.5
10
P3.0
P3.1
11
P3.7
P3.6
Bit 5: INT0IS0, nINT0 input selection bits which function is defined as following table.
INT0IS.0
0
1
14
nINT0
P3.2
P1.6
MG74PG1A08 Data Sheet
MEGAWIN
5. 8051 CPU Function Description
5.1. CPU Register
PSW: Program Status Word
SFR Attribute = Normal Read/Write
SFR Address = 0xD0
7
6
5
CY
AC
F0
R/W
R/W
R/W
RESET = 0000-0000
4
3
RS1
RS0
2
OV
1
F1
0
P
R/W
R/W
R/W
R/W
R/W
CY: Carry bit.
AC: Auxiliary carry bit.
F0: General purpose flag 0.
RS1: Register bank select bit 1.
RS0: Register bank select bit 0.
OV: Overflow flag.
F1: General purpose flag 1.
P: Parity bit.
The program status word (PSW) contains several status bits that reflect the current state of the CPU. The PSW,
shown above, resides in the SFR space. It contains the Carry bit, the Auxiliary Carry(for BCD operation), the two
register bank select bits, the Overflow flag, a Parity bit and two user-definable status flags.
The Carry bit, other than serving the function of a Carry bit in arithmetic operations, also serves as the “Accumulator”
for a number of Boolean operations.
The bits RS0 and RS1 are used to select one of the four register banks shown in Section “6.2 On-Chip Data RAM”.
A number of instructions refer to these RAM locations as R0 through R7.
The Parity bit reflects the number of 1s in the Accumulator. P=1 if the Accumulator contains an odd number of 1s
and otherwise P=0.
SP: Stack Pointer
SFR Attribute = Normal Read/Write
SFR Address = 0x81
7
6
5
SP.7
SP.6
SP.5
R/W
R/W
R/W
RESET = 0000-0111
4
3
2
SP.4
SP.3
SP.2
R/W
R/W
R/W
1
SP.1
0
SP.0
R/W
R/W
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH
operation. The SP register defaults to 0x07 after reset.
DPL: Data Pointer Low
SFR Attribute = Normal Read/Write
SFR Address = 0x82
7
6
5
DPL.7
DPL.6
DPL.6
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
DPL.4
DPL.3
DPL.2
R/W
R/W
R/W
1
DPL.1
0
DPL.0
R/W
R/W
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and Flash
memory.
MEGAWIN
MG74PG1A08 Data Sheet
15
DPH: Data Pointer High
SFR Attribute = Normal Read/Write
SFR Address = 0x83
7
6
5
DPH.7
DPH.6
DPH.5
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
DPH.4
DPH.3
DPH.2
R/W
R/W
1
DPH.1
0
DPH.0
R/W
R/W
R/W
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and Flash
memory.
ACC: Accumulator
SFR Attribute = Normal Read/Write
SFR Address = 0xE0
7
6
5
ACC.7
ACC.6
ACC.5
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
ACC.4
ACC.3
ACC.2
1
ACC.1
0
ACC.0
R/W
R/W
R/W
RESET = 0000-0000
4
3
B.4
B.3
2
B.2
1
B.1
0
B.0
R/W
R/W
R/W
R/W
R/W
R/W
This register is the accumulator for arithmetic operations.
B: B Register
SFR Attribute = Normal Read/Write
SFR Address = 0xF0
7
6
5
B.7
B.6
B.5
R/W
R/W
R/W
R/W
This register serves as a second accumulator for certain arithmetic operations.
5.2. CPU Timing
The MG74PG1A08 is a single-chip microcontroller based on a high performance 1-T architecture 80C51 CPU that
has an 8051 compatible instruction set, and executes instructions in 1~6 clock cycles (about 6~7 times the rate of a
standard 8051 device). It employs a pipelined architecture that greatly increases its instruction throughput over the
standard 8051 architecture. The instruction timing is different than that of the standard 8051.
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles
varying from 2 to 12 clock cycles in length. However, the 1T-80C51 implementation is based solely on clock cycle
timing. All instruction timings are specified in terms of clock cycles. For more detailed information about the
1T-80C51 instructions, please refer Section “24 Instruction Set” which includes the mnemonic, number of bytes, and
number of clock cycles for each instruction.
16
MG74PG1A08 Data Sheet
MEGAWIN
5.3. CPU Addressing Mode
Direct Addressing (DIR)
In direct addressing the operand is specified by an 8-bit address field in the instruction. Only internal data RAM and
SFRs can be direct addressed.
Indirect Addressing (IND)
In indirect addressing the instruction specified a register which contains the address of the operand. Both internal
and external RAM can be indirectly addressed.
The address register for 8-bit addresses can be R0 or R1 of the selected bank, or the Stack Pointer.
The address register for 16-bit addresses can only be the 16-bit data pointer register – DPTR.
Register Instruction (REG)
The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3-bit
register specification within the op-code of the instruction. Instructions that access the registers this way are code
efficient because this mode eliminates the need of an extra address byte. When such instruction is executed, one of
the eight registers in the selected bank is accessed.
Register-Specific Instruction
Some instructions are specific to a certain register. For example, some instructions always operate on the
accumulator or data pointer, etc. No address byte is needed for such instructions. The op-code itself does it.
Immediate Constant (IMM)
The value of a constant can follow the op-code in the program memory.
Index Addressing
Only program memory can be accessed with indexed addressing and it can only be read. This addressing mode is
intended for reading look-up tables in program memory. A 16-bit base register (either DPTR or PC) points to the
base of the table, and the accumulator is set up with the table entry number. Another type of indexed addressing is
used in the conditional jump instruction.
In conditional jump, the destination address is computed as the sum of the base pointer and the accumulator.
MEGAWIN
MG74PG1A08 Data Sheet
17
6. Memory Organization
Like all 80C51 devices, the MG74PG1A08 has separate address spaces for program and data memory. The logical
separation of program and data memory allows the data memory to be accessed by 8-bit addresses, which can be
quickly stored and manipulated by the 8-bit CPU.
Program memory (ROM) can only be read, not written to. There can be up to 8K bytes of program memory. In the
MG74PG1A08, all the program memory are on-chip OTP memory, and without the capability of accessing external
program memory because of no External Access Enable (/EA) and Program Store Enable (/PSEN) signals
designed.
Data memory occupies a separate address space from program memory. In the MG74PG1A08, there is only a 256
bytes of internal scratch-pad RAM and has no any expanded RAM (XRAM).
6.1. On-Chip Program OTP
Program memory is the memory which stores the program codes for the CPU to execute, as shown in Figure 6–1.
After reset, the CPU begins execution from location 0000H, where should be the starting of the user’s application
code. To service the interrupts, the interrupt service locations (called interrupt vectors) should be located in the
program memory. Each interrupt is assigned a fixed location in the program memory. The interrupt causes the CPU
to jump to that location, where it commences execution of the service routine. External Interrupt 0, for example, is
assigned to location 0003H. If External Interrupt 0 is going to be used, its service routine must begin at location
0003H. If the interrupt is not going to be used, its service location is available as general purpose program memory.
The interrupt service locations are spaced at an interval of 8 bytes: 0003H for External Interrupt 0, 000BH for Timer
0, 0013H for External Interrupt 1, 001BH for Timer 1, etc. If an interrupt service routine is short enough (as is often
the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines can use a
jump instruction to skip over subsequent interrupt locations, if other interrupts are in use.
Figure 6–1. Program Memory
Program
Memory
1FFFH for 8K
Interrupt
Locations
001BH
0013H
000BH
8 bytes
0003H
Reset
18
0000H
MG74PG1A08 Data Sheet
MEGAWIN
6.2. On-Chip Data RAM
Figure 6–2 shows the internal and external data memory spaces available to the MG74PG1A08 user. Internal data
memory can be divided into three blocks, which are generally referred to as the lower 128 bytes of RAM, the upper
128 bytes of RAM, and the 128 bytes of SFR space. Internal data memory addresses are always 8-bit wide, which
implies an address space of only 256 bytes. Direct addresses higher than 7FH access the SFR space; and indirect
addresses higher than 7FH access the upper 128 bytes of RAM. Thus the SFR space and the upper 128 bytes of
RAM occupy the same block of addresses, 80H through FFH, although they are physically separate entities.
The lower 128 bytes of RAM are present in all 80C51 devices as mapped in Figure 6–3. The lowest 32 bytes are
grouped into 4 banks of 8 registers. Program instructions call out these registers as R0 through R7. Two bits in the
Program Status Word (PSW) select which register bank is in use. This allows more efficient use of code space,
since register instructions are shorter than instructions that use direct addressing. The next 16 bytes above the
register banks form a block of bit-addressable memory space. The 80C51 instruction set includes a wide selection of
single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit
addresses in this area are 00H through 7FH.
All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing while the Upper 128 can
only be accessed by indirect addressing.
Figure 6–4 gives a brief look at the Special Function Register (SFR) space. SFRs include the Port latches, timers,
peripheral controls, etc. These registers can only be accessed by direct addressing. Sixteen addresses in SFR
space are both byte- and bit-addressable. The bit-addressable SFRs are those whose address ends in 0H or 8H.
Figure 6–2. Data Memory
Internal 256 Bytes
SRAM
SFRs
FFH
FFH
Addressable by
Indirect Addressing
Only
Upper 128
Bytes
Addressable by
Direct Addressing
(SFRs)
80H
7FH
80H
Addressable by
Direct and Indirect
Addressing
Lower 128
Bytes
00H
MEGAWIN
MG74PG1A08 Data Sheet
19
Figure 6–3. Lower 128 Bytes of Internal RAM
Lower 128 Bytes of
internal SRAM
7FH
30H
2FH
Bit Addressable
20H
Four banks of 8
registers R0~R7
18H
Bank 3
1FH
10H
Bank 2
17H
08H
Bank 1
0FH
00H
Bank 0
07H
Reset value of
Stack Pointer
Figure 6–4. SFR Space
FFH
E0H
ACC
D0H
PSW
B0H
Port 3
90H
Port 1
1. I/O ports are register mapping
2. Addresses that end in 0H or
8H are also bit-addressable
- I/O ports
- PSW
- Accumulator
(etc.)
80H
20
MG74PG1A08 Data Sheet
MEGAWIN
6.3. Declaration Identifiers in a C51-Compiler
The declaration identifiers in a C51-compiler for the various MG74PG1A08 memory spaces are as follows:
data
128 bytes of internal data memory space (00h~7Fh); accessed via direct or indirect addressing, using instructions
other than MOVX and MOVC. All or part of the Stack may be in this area.
idata
Indirect data; 256 bytes of internal data memory space (00h~FFh) accessed via indirect addressing using
instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the data
area and the 128 bytes immediately above it.
sfr
Special Function Registers; CPU registers and peripheral control/status registers, accessible only via direct
addressing.
xdata
There is no on-chip XRAM or XRAM interface for xdata access.
pdata
There is no on-chip XRAM or XRAM interface for pdata access.
code
8K bytes of program memory space; accessed as part of program execution and via the “MOVC @A+DTPR”
instruction.
MEGAWIN
MG74PG1A08 Data Sheet
21
7. Data Pointer Register (DPTR)
There is only one set DPTR in MG74PG1A08. MG74PG1A08 does not support external memory access and MOVX
instruction.
22
MG74PG1A08 Data Sheet
MEGAWIN
8. System Clock
There are three clock sources for the system clock: Internal High-frequency RC Oscillator (IHRCO), Internal
Low-frequency RC Oscillator (ILRCO) and External Clock Input. Figure 8–1 shows the structure of the system clock
in MG74PG1A08.
The MG74PG1A08 always boots from IHRCO on 12MHz with divided 2 on system clock. CPU clock divider is
cascaded after system clock with default divided by 4. Software can select the one of the three clock sources by
application required and switches them on the fly. But software needs to settle the clock source stably before clock
switching. In external clock input mode (ECKI), the clock source comes from P1.7 input.
The built-in IHRCO provides the high precision frequency at 12MHz for system clock source. It is the default clock
source in MG74PG1A08 after power-on. To find the detailed IHRCO performance, please refer Section “23.5
IHRCO Characteristics”). In IHRCO mode, P1.7 can be configured to internal MCK output or MCK/2 and MCK/4 for
system application.
The MG74PG1A08 device includes a Clock Multiplier to generate the high speed clock for system clock source. It
generates 4/5.33/8 times frequency of CKM, CKM is shown in Figure 8–1 and its typical input is 6MHz. This function
provides the high speed operation on MCU without external high-frequency clock input. To find the detailed CKM
performance, please refer Section “23.7 CKM Characteristics”).
The built-in ILRCO provides the low power and low speed frequency about 64KHz to WDT and system clock source.
MCU can select the ILRCO to system clock source by software for low power operation. To find the detailed ILRCO
performance, please refer Section “23.6 ILRCO Characteristics”). In ILRCO mode, P1.7 can be configured to
internal MCK output or MCK/2 and MCK/4 for system application.
The system clock, SYSCLK, is obtained from one of these four clock sources through the clock divider, as shown in
Figure 8–1. The user can program the divider control bits SCKS2~SCKS0 (in CKCON0 register) to get the desired
system clock. The default system clock divider is set to “/2” in MG74PG1A08 after power on or reset.
The CPU clock, CPUCLK, divide from system clock. The CPU clock divider, CCKS.1~CCKS.0 default is set to “/4” in
MG74PG1A08 after power on or reset.
MEGAWIN
MG74PG1A08 Data Sheet
23
8.1. Clock Structure
Figure 8–1 presents the principal clock systems in the MG74PG1A08. The system clock can be sourced by the
external oscillator circuit or either internal oscillator.
Figure 8–1. System Clock
clock default path
IHRCOE
enable
1
(CKCON2.4)
12MHz
IHRCO
Reserved
64KHz
ILRCO
0~24MHz
ECKI (P1.7)
OSCS1,0
(CKCON2.1~0)
0
1
OSCin
2
3
00: OSCin = IHRCO
01: OSCin = Reserved
10: OSCin = ILRCO
11: OSCin = ECKI
CKMIS1,0
÷1
÷2
÷4
÷X
(DCON0.3~2) 00: 6MHz
01: 12MHz
10: 24MHz
11: Reserved
MCK
2
24MHz
6MHz
ENCKM
(DCON0.4)
Clock
Multiplier
(CKM)
3
32MHz
SCKS[2:0]
CCKS[1:0]
(CKCON0.2~0)
(CKCON0.5~4)
SYSCLK
(System Clock)
CPUCLK
(CPU Clock)
ENUSB
(DCON0.5)
48MHz
USB Logic
P1.7
SFR
MCKS1,0
(CKCON2.3~2)
enable
Default : ÷4
Default : ÷2
0
0
1
00: OSCin
01: 24MHz
10: 32MHz
11: 48MHz
÷2
÷4
P1.7
2
3
00: P1.7
01: MCK
10: MCK/2
11: MCK/4
AUXR0.7~6
(P17OC[1:0])
8.2. Clock Register
CKCON0: Clock Control Register 0
SFR Attribute = Normal Read/Write or Protected Write
SFR Address = 0xC7
RESET = xx10-x001
7
6
5
4
3
2
--CCKS1
CCKS0
-SCKS2
W
W
R/W
R/W
W
R/W
1
SCKS1
0
SCKS0
R/W
R/W
Bit 7~6: Reserved. Software must write “0” on these bits when CKCON0 is written.
Bit 5~4: CCKS1 ~ CCKS0, CPU Clock Selection.
CCKS[1:0]
CPU Clock Selection
0 0
SYSCLK /1
0 1
SYSCLK /2
SYSCLK /4 (default)
1 0
1 1
SYSCLK /8
Bit 3: Reserved. Software must write “0” on this bit when CKCON0 is written.
Bit 2~0: SCKS2 ~ SCKS0, programmable System Clock Selection. The default value of SCKS[2:0] is set to “001” to
select system clock on OSCin/2.
SCKS[2:0]
System Clock Selection
0 0 0
OSCin /1
OSCin /2 (default)
0 0 1
0 1 0
OSCin /4
0 1 1
OSCin /8
1 0 0
OSCin /16
1 0 1
OSCin /32
1 1 0
OSCin /64
1 1 1
OSCin /128
24
MG74PG1A08 Data Sheet
MEGAWIN
CKCON2: Clock Control Register 2
SFR Attribute = Normal Read and Protected Write
SFR Address = 0xBB
RESET =xxx1-0000
7
6
5
4
3
2
---IHRCOE
MCKS1
MCKS0
W
W
W
R/W
R/W
R/W
1
OSCS1
0
OSCS0
R/W
R/W
Bit 7~5: Reserved. Software must write “0” on these bits when CKCON2 is written.
Bit 4: IHRCOE, Internal High frequency RC Oscillator Enable. The default value is set for MCU clock source.
0: Disable internal high frequency RC oscillator.
1: Enable internal high frequency RC oscillator. If this bit is set by CPU software, it needs 32us to have stable output
after IHRCOE enabled.
Bit 3~2: MCKS[1:0], MCK Source Selection.
MCKS[1:0]
MCK Source Selection
0 0
OSCin
0 1
24MHz (ENCKM must be enabled)
1 0
32MHz (ENCKM must be enabled)
1 1
48MHz (ENCKM must be enabled)
Bit 1~0: OSCS[1:0], OSCin source selection. The default selection of OSCin is IHRCO.
OSCS[1:0]
OSCin source Selection
0 0
IHRCO
0 1
Reserved
1 0
ILRCO
1 1
ECKI, External Clock Input (P1.7) as OSCin.
DCON0: Device Control 0
SFR Attribute = Normal Read and Protected Write
SFR Address = 0xBC
RESET = 0000-0110
7
6
5
4
3
2
WCKS
USBR
ENUSB
ENCKM
CKMIS1
CKMIS0
R/W
R/W
R/W
R/W
R/W
R/W
1
RSTIO
0
SWRST
R/W
R/W
Bit 7: WCKS, WDT Clock selection.
0: Select ILRCO for WDT clock source.
1: Select SYSCLK/12 for WDT clock source.
Bit 6: USBR, Software trigger USB block reset
0: Software end the reset of USB block.
1: Software start the reset of USB block.
Bit 5: ENUSB, Enable USB clock and whole USB function.
0: Disable USB clock and USB function.
1: Enable USB clock and USB function.
Bit 4: ENCKM, Enable clock multiplier (X8)
0: Disable the X8 clock multiplier.
1: Enable the X8 clock multiplier.
Bit 3~2: CKMIS1 ~ CKMIS0, Clock Multiplier Input Selection.
CKMIS[1:0]
Clock Multiplier Input Selection
0 0
6MHz input
0 1
12MHz input (default)
1 0
24MHz input
1 1
Reserved.
MEGAWIN
MG74PG1A08 Data Sheet
25
AUXR0: Auxiliary Register 0
SFR Attribute = Normal Read/Write
SFR Address = 0xA1
7
6
5
P17OC1
P17OC0
GF
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
T0XL
P1FS1
P1FS0
R/W
R/W
R/W
1
INT1H
0
INT0H
R/W
R/W
Bit 7~6: P1.7 function configured control bit 1 and 0. The two bits only act when internal RC oscillator (IHRCO or
ILRCO) is selected for system clock source. In external clock input mode, P1.7 is the dedicated clock input pin. In
internal oscillator condition, P1.7 provides the following selections for GPIO or clock source generator. When
P17OC[1:0] index to non-P1.7 GPIO function, P1.7 will drive the on-chip RC oscillator output to provide the clock
source for other devices.
P17OC[1:0]
00
01
10
11
P1.7 function
P1.7
MCK
MCK/2
MCK/4
I/O mode
By P1M0.7 & P1M1.7
By P1M0.7 & P1M1.7
By P1M0.7 & P1M1.7
By P1M0.7 & P1M1.7
Please refer Section “8 System Clock” to get the more detailed clock information. For clock-out on P1.7 function, it is
recommended to set P1M0.7 and P1M1.7 to “11” which selects P1.7 as push-pull output mode.
26
MG74PG1A08 Data Sheet
MEGAWIN
9. Watch Dog Timer (WDT)
9.1. WDT Structure
The Watch-dog Timer (WDT) is intended as a recovery method in situations where the CPU may be subjected to
software upset. The WDT consists of a 9-bit free-running counter, an 8-bit pre-scaler and a control register
(WDTCR). Figure 9–1 shows the WDT structure in MG74PG1A08.
When WDT is enabled, it derives its time base from the 64 KHz ILRCO or SYSCLK/12. The WDT overflow will set
the WDTF on PCON1.0 which can be configured to generate an interrupt by enabled WDTFIE (SFIE.0) and enabled
ESF (XPIE1.0). The overflow can also trigger a system reset when WREN (WDTCR.7) is set. To prevent WDT
overflow, software needs to clear it by writing “1” to the CLRW bit (WDTCR.4) before WDT overflows.
Once the WDT is enabled by setting ENW bit, there is no way to disable it except through power-on reset or
Protected-Write SFR over-write on ENW, which will clear the ENW bit. The WDTCR register will keep the previous
programmed value unchanged after external reset (nRST-pin), software reset and WDT reset.
WREN, NSW and ENW are implemented to one-time-enabled function, only writing “1” valid in general SFR page.
Protected-Write SFR Access on WDTCR can disable WREN, NSW and ENW, writing “0” on WDTCR.7~5. Please
refer Section “9.3 WDT Register” and Section “20 Protected-Write SFR Access” for more detail information.
Figure 9–1. Watch Dog Timer
EIE1.ESF
ILRCO(64KHz)
0
SYSCLK/12
1
8-bits prescaler
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
WCKS
WIDL
PCON0.IDL
PCON0.PD
SFIE.WDTFIE
WDT Interrupt
IE.EXPIE1
overflow
9-bits WDT
WDTF
PCON1.0
WDT Reset
WREN
WDTCR Register
WREN
NSW
ENW
CLRW
WIDL
PS2
PS1
PS0
9.2. WDT during Idle and Power Down
In the Idle mode, the WIDL bit (WDTCR.3) determines whether WDT counts or not. Set this bit to let WDT keep
counting in the Idle mode. If the hardware option NSWDT is enabled, the WDT always keeps counting regardless of
WIDL bit.
In the Power down mode, the ILRCO won’t stop if the NSW (WDTCR.6) is enabled. That lets WDT keep counting
even in Power down mode (Watch Mode). After WDT overflows, it will wake up the CPU from interrupt or reset by
software configured.
9.3. WDT Register
DCON0: Device Control 0
SFR Attribute = Normal Read and Protected Write
SFR Address = 0xBC
RESET = 0000-0110
7
6
5
4
3
2
WCKS
USBR
ENUSB
ENCKM
CKMIS1
CKMIS0
R/W
R/W
R/W
R/W
R/W
R/W
1
RSTIO
0
SWRST
R/W
R/W
Bit 7: WCKS, WDT Clock selection.
0: Select ILRCO for WDT clock source.
1: Select SYSCLK/12 for WDT clock source.
MEGAWIN
MG74PG1A08 Data Sheet
27
WDTCR: Watch-Dog-Timer Control Register
SFR Attribute = Normal Read/Write or Protected Write
SFR Address = 0xE1
POR = 0000-0000 (xxx0_xxxx by Hardware Option)
7
6
5
4
3
2
1
0
WREN
NSW
ENW
CLRW
WIDL
PS2
PS1
PS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7: WREN, WDT Reset Enable. The initial value can be changed by hardware option, WRENO.
0: The overflow of WDT does not set the WDT reset. The WDT overflow flag, WDTF, may be polled by software or
trigger an interrupt.
1: The overflow of WDT will cause a system reset. Once WREN has been set, it cannot be cleared by software in
normal page. In protected-write access (protect-write key = 8C), software can modify it to “0” or “1”.
Bit 6: NSW. Non-Stopped WDT. The initial value can be changed by hardware option, NSWDT.
0: WDT stop counting while the MCU is in power-down mode.
1: WDT always keeps counting while the MCU is in power-down mode (Watch Mode) or idle mode. Once NSW has
been set, it cannot be cleared by software in normal page. In protected-write access (protect-write key = 8C),
software can modify it to “0” or “1”.
Bit 5: ENW. Enable WDT. The initial value can be changed by hardware option, HWENW.
0: Disable WDT running.
1: Enable WDT while it is set. Once ENW has been set, it cannot be cleared by software in normal page. In
protected-write access (protect-write key = 8C), software can modify it as “0” or “1”.
Bit 4: CLRW. Clear WDT counter.
0: Writing “0” to this bit is no operation in WDT.
1: Writing “1” to this bit will clear the 9-bit WDT counter to 000H. Note this bit has no need to be cleared by writing
“0”.
Bit 3: WIDL. WDT idle control. The initial value can be changed by hardware option, HWWIDL.
0: WDT stops counting while the MCU is in idle mode.
1: WDT keeps counting while the MCU is in idle mode.
Bit 2~0: PS2 ~ PS0, select pre-scaler output for WDT time base input.
WDT Period
PS[2:0]
Pre-scaler Value
ILRCO(64K)
SYSCLK(12Mhz)/12
WCKS=0
WCKS=1
0 0 0
2
15 ms
1ms
0 0 1
4
30 ms
2ms
0 1 0
8
62 ms
4ms
0 1 1
16
124 ms
8ms
1 0 0
32
248 ms
16ms
1 0 1
64
496 ms
32ms
1 1 0
128
992 ms
64ms
1 1 1
256
1.984 S
128ms
PCON1: Power Control Register 1
SFR Attribute = Normal Read/Write or Protected Write
SFR Address = 0x97
POR = 00xx-0000
7
6
5
4
3
SWRF
EXRF
--KBIF
R/W
R/W
W
W
R/W
2
BOF1
1
BOF0
0
WDTF
R/W
R/W
R/W
Bit 0: WDTF, WDT overflow flag.
0: This bit must be cleared by software writing “1” on it. Software writing “:0” is no operation.
1: This bit is only set by hardware when WDT overflows. Writing “1” on this bit will clear WDTF.
28
MG74PG1A08 Data Sheet
MEGAWIN
9.4. WDT Hardware Option
In addition to being initialized by software, the WDTCR register can also be automatically initialized at power-up by
the hardware options WRENO, NSWDT, HWENW, HWWIDL and HWPS[2:0], which should be programmed by a
universal Writer or Programmer, as described below.
If HWENW is programmed to “enabled”, then hardware will automatically do the following initialization for the
WDTCR register at power-up: (1) set ENW bit, (2) load WRENO into WREN bit, (3) load NSWDT into NSW bit, (4)
load HWWIDL into WIDL bit, and (5) load HWPS[2:0] into PS[2:0] bits.
If both of HWENW and WDSFWP are programmed to “enabled”, hardware still initializes the WDTCR register
content by WDT hardware option at power-up. Then, any CPU writing on WDTCR bits will be inhibited except writing
“1” on WDTCR.4 (CLRW), clear WDT, even though access through Protected-Write SFR mechanism.
WRENO:
: Enabled. Set WDTCR.WREN to enable a system reset function by WDTF.
: Disabled. Clear WDTCR.WREN to disable the system reset function by WDTF.
NSWDT: Non-Stopped WDT
: Enabled. Set WDTCR.NSW to enable the WDT running in power down mode (watch mode).
: Disabled. Clear WDTCR.NSW to disable the WDT running in power down mode (disable Watch mode).
HWENW: Hardware loaded for “ENW” of WDTCR.
: Enabled. Enable WDT and load the content of WRENO, NSWDT, HWWIDL and HWPS2~0 to WDTCR after
power-on.
: Disabled. WDT is not enabled automatically after power-on.
HWWIDL, HWPS2, HWPS1, HWPS0:
When HWENW is enabled, the content on these four fused bits will be loaded to WDTCR SFR after power-on.
WDSFWP:
: Enabled. The WDT SFRs, WREN, NSW, ENW, WIDL, PS2, PS1 and PS0 in WDTCR, will be write-protected.
: Disabled. The WDT SFRs, WREN, NSW, ENW, WIDL, PS2, PS1 and PS0 in WDTCR, are free for writing of
software.
MEGAWIN
MG74PG1A08 Data Sheet
29
10. System Reset
During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector,
0000H. The MG74PG1A08 has seven sources of reset: power-on reset, external reset, software reset, illegal
address reset, WDT reset and brown-out 0/1 reset. Figure 10–1 shows the system reset source in MG74PG1A08.
The following sections describe the reset happened source and corresponding control registers and indicating flags.
(IAR only acts reset on CPU)
10.1. Reset Source
Figure 10–1 presents the reset systems in the MG74PG1A08 and all of its reset sources.
Figure 10–1. System Reset Source
POF0
Power-On Reset
EXRF
External Reset
SWRF
Software Reset
Internal System Reset
(SYSRST)
Illegal Addr Reset
Brown-Out
Reset 0
BOD0 Triggered
PCON2.BO0RE
Brown-Out
Reset 1
BOD1 Triggered
PCON2.BO1RE
WDT Reset
WDT Overflow
WDTCR.WREN
10.2. Power-On Reset
Power-on reset (POR) is used to internally reset the CPU during power-up. The CPU will keep in reset state and will
not start to work until the VDD power rises above the voltage of Power-On Reset. And, the reset state is activated
again whenever the VDD power falls below the POR voltage. During a power cycle, VDD must fall below the POR
voltage before power is reapplied in order to ensure a power-on reset
PCON0: Power Control Register 0
SFR Attribute = Normal Read/Write or Write-protected
SFR Address = 0x87
POR = 0001-0000, RESET = 000X-0000
7
6
5
4
3
2
1
POF
SMOD1
SMOD0
GF
GF1
GF0
PD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
IDL
R/W
Bit 4: POF. Power-On Flag.
0: The flag must be cleared by software to recognize next reset type.
1: Set by hardware when VDD rises from 0 to its nominal voltage. POF can also be set by software.
30
MG74PG1A08 Data Sheet
MEGAWIN
The Power-on Flag, POF, is set to “1” by hardware during power up or when VDD power drops below the POR
voltage. It can be clear by firmware and is not affected by any warm reset such as external reset, Brown-Out reset,
software reset and WDT reset. It helps users to check if the running of the CPU begins from power up or not. Note
that the POF must be cleared by firmware.
10.3. External Reset
PCON1: Power Control Register 1
SFR Attribute = Normal Read/Write or Protected Write
SFR Address = 0x97
POR = 00xx-0000
7
6
5
4
3
EXRF
SWRF
--KBIF
R/W
R/W
W
W
R/W
2
BOF1
1
BOF0
0
WDTF
R/W
R/W
R/W
Bit 6: EXRF, External Reset Flag.
0: This bit must be cleared by software writing “1” on it. Software writing “:0” is no operation.
1: This bit is only set by hardware if an External Reset occurs. Writing “1” on this bit will clear EXRF.
DCON0: Device Control 0
SFR Attribute = Normal Read and Protected Write
SFR Address = 0xBC
RESET = 0000-0110
7
6
5
4
3
2
WCKS
USBR
ENUSB
ENCKM
CKMIS1
CKMIS0
R/W
R/W
R/W
R/W
R/W
1
RSTIO
0
SWRST
R/W
R/W
R/W
Bit 1: RSTIO, nRST function on I/O,
1: Select I/O pad function for nRST.
0: Select I/O pad function for GPIO.
10.4. Software Reset
Software can trigger the CPU to restart by software reset, writing “1” on SWRST (DCON0.0), and set the SWRF flag
(PCON1.7).
DCON0: Device Control 0
SFR Attribute = Normal Read and Protected Write
SFR Address = 0xBC
RESET = 0000-0110
7
6
5
4
3
2
WCKS
USBR
ENUSB
ENCKM
CKMIS1
CKMIS0
R/W
R/W
R/W
R/W
R/W
1
RSTIO
0
SWRST
R/W
R/W
2
BOF1
1
BOF0
0
WDTF
R/W
R/W
R/W
R/W
Bit 0: SWRST, software reset trigger control.
0: No operation
1: Generate software system reset. It will be cleared by hardware automatically.
PCON1: Power Control Register 1
SFR Attribute = Normal Read/Write or Protected Write
SFR Address = 0x97
POR = 00xx-0000
7
6
5
4
3
SWRF
EXRF
--KBIF
R/W
R/W
W
W
R/W
Bit 7: SWRF, Software Reset Flag.
0: This bit must be cleared by software writing “1” on it. Software writing “0” is no operation.
1: This bit is only set by hardware if a Software Reset occurs. Writing “1” on this bit will clear SWRF.
MEGAWIN
MG74PG1A08 Data Sheet
31
10.5. Brown-Out Reset
In MG74PG1A08, there are one Power on reset (POR) and two Brown-Out Detectors (BOD0 & BOD1) to monitor
VDD power. POR detects the VDD level by software selecting 1.95V or 2.3V. BOD0 detects the VDD level by
software selecting 2.1V or 2.6V. BOD1 services the fixed detection level at VDD=3.6V. If VDD power drops below
POR, BOD0 or BOD1 monitor level. Associated flag, BOF0 and BOF1, is set. If BO0RE (PCON2.2) is enabled,
BOF0 indicates a BOD0 Reset occurred. If BO1RE (PCON2.3) is enabled, BOF1 indicates a BOD1 Reset occurred.
PCON2: Power Control Register 2
SFR Attribute = Normal Read and Protected Write
SFR Address = 0xBA
POR/RESET = 0100-0000
7
6
5
4
3
2
AWBOD1
EBOD1
BO1RE
BO0RE
--R/W
R/W
W
W
R/W
R/W
1
--
0
RMLS
W
R/W
Bit 7: AWBOD1, Awaked BOD1 in PD mode.
0: BOD1 is disabled in power-down mode.
1: BOD1 keeps operation in power-down mode.
Bit 6: EBOD1, Enable BOD1 that monitors VDD power dropped below 3.6V.
0: Disable BOD1 to slow down the chip power consumption.
1: Enable BOD1 to monitor VDD power dropped.
Bit 5~4: Reserved. Software must write “0” on these bits when PCON2 is written.
Bit 3: BO1RE, BOD1 Reset Enabled.
0: Disable BOD1 to trigger a system reset when BOF1 is set.
1: Enable BOD1 to trigger a system reset when BOF1 is set.
Bit 2: BO0RE, BOD0 Reset Enabled.
0: Disable BOD0 to trigger a system reset when BOF0 is set.
1: Enable BOD0 to trigger a system reset when BOF0 is set (VDD meets 2.1V or 2.6V).
Bit 1: Reserved. Software must write “0” on these bits when PCON2 is written.
Bit 0: RMLS, Power on Reset (POR) and Brown-Out detector 0(BOD0) monitored level Selection. The initial values
of this bit is loaded from RMLSO.
RMLS
0
1
POR detecting level
1.95V
2.3V
PCON1: Power Control Register 1
SFR Attribute = Normal Read/Write or Protected Write
SFR Address = 0x97
POR = 00xx-0000
7
6
5
4
3
SWRF
EXRF
--KBIF
R/W
R/W
W
W
R/W
BOD0 detecting level
2.1V
2.6V
2
BOF1
1
BOF0
0
WDTF
R/W
R/W
R/W
Bit 2: BOF1, BOF1 (Reset) Flag.
0: This bit must be cleared by software writing “1” on it. Software writing “:0” is no operation.
1: This bit is only set by hardware when VDD meets BOD1 monitored level. Writing “1” on this bit will clear BOF1. If
BO0RE (PCON2.3) is enabled, BOF0 indicates a BOD0 Reset occurred.
Bit 1: BOF0, BOF0 (Reset) Flag.
0: This bit must be cleared by software writing “1” on it. Software writing “:0” is no operation.
1: This bit is only set by hardware when VDD meets BOD0 monitored level. Writing “1” on this bit will clear BOF0. If
BO0RE (PCON2.2) is enabled, BOF0 indicates a BOD0 Reset occurred.
32
MG74PG1A08 Data Sheet
MEGAWIN
10.6. WDT Reset
When WDT is enabled to start the counter, WDTF will be set by WDT overflow. If WREN (WDTCR.7) is enabled, the
WDT overflow will trigger a system reset that causes CPU to restart. Software can read the WDTF to recognize the
WDT reset occurred.
PCON1: Power Control Register 1
SFR Attribute = Normal Read/Write or Protected Write
SFR Address = 0x97
POR = 00xx-0000
7
6
5
4
3
SWRF
EXRF
--KBIF
R/W
R/W
W
W
R/W
2
BOF1
1
BOF0
0
WDTF
R/W
R/W
R/W
Bit 0: WDTF, WDT Overflow/Reset Flag.
0: This bit must be cleared by software writing “1” on it. Software writing “:0” is no operation.
1: This bit is only set by hardware when WDT overflows. Writing “1” on this bit will clear WDTF. If WREN (WDTCR.7)
is set, WDTF indicates a WDT Reset occurred.
WDTCR: Watch-Dog-Timer Control Register
SFR Attribute = Normal Read/Write or Protected Write
SFR Address = 0xE1
POR = 0000-0000 (xxx0_xxxx by Hardware Option)
7
6
5
4
3
2
1
0
WREN
NSW
ENW
CLRW
WIDL
PS2
PS1
PS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7: WREN, WDT Reset Enable. The initial value can be changed by hardware option, WRENO.
0: The overflow of WDT does not set the WDT reset. The WDT overflow flag, WDTF, may be polled by software or
trigger an interrupt.
1: The overflow of WDT will cause a system reset. Once WREN has been set, it cannot be cleared by software in
normal page. In protected-write mode, software can modify it to “0” or “1”.
MEGAWIN
MG74PG1A08 Data Sheet
33
11. Power Management
The MG74PG1A08 supports two power monitor modules, Brown-Out Detector 0 (BOD0) and Brown-Out Detector 1
(BOD1), and 6 power-reducing modes: Idle mode, Power-down mode, Slow mode, Sub-Clock mode, Watch mode
and Monitor mode.
BOD0 and BOD1 report the chip power status on the flags, BOF0 and BOF1, which provide the capability to
interrupt CPU or to reset CPU by software configured. The six power-reducing modes provide the different
power-saving scheme for chip application. These modes are accessed through the CKCON0, CKCON2, PCON0,
PCON1, PCON2 and WDTCR register.
11.1. Brown-Out Detector
In MG74PG1A08, there are two Brown-Out Detectors (BOD0 & BOD1) to monitor VDD power. Figure 11–1 shows
the functional diagram of BOD0 and BOD1. BOD0 detects the software selection levels (2.1V/2.6V) and BOD1
services the fixed detection level at VDD=3.6V on Core Power. Associated flag, BOF0 (PCON1.1), is set when
BOD0 meets the detection level. If both of EXPIE1 (IE5), ESF (XPIE1.0) and BOF0IE (SFIE.1) are enabled, a set
BOF0 will generate a system flag interrupt. It can interrupt CPU either CPU in normal mode or idle mode. The BOD1
has the same flag function, BOF1, and same interrupt function. The BOD0 and BOD1 interrupt also wake up CPU in
power down mode if AWBOD1 (PCON2.7) is enabled.
If BO0RE (PCON2.2) is enabled, the BOD0 event will trigger a system reset and set BOF0 to indicate a BOD0 Reset
occurred. The BOD0 reset restart the CPU either CPU in normal mode or idle mode. BOD1 also has the same reset
capability with associated control bit, BO1RE (PCON2.3). The BOD1 also restart CPU in power down mode if
AWBOD1 (PCON2.7) is enabled.
Figure 11–1. Brown-Out Detector 0/1
VDD
BO0RE
BOD0 Reset
(PCON2.2)
2.1V
0
2.6V
1
“1”
Voltage
Comparator
-
Load
ESF
+
(XPIE1.0)
RMLS
BOF0IE
(PCON2.0)
0: 2.1V
1: 2.6V
“0”Enable
BOF0
(Always on)
BOD0 Interrupt
(SFIE.1)
(PCON1.1)
EXPIE1
(IE.5)
VDD
BO1RE
BOD1 Reset
(PCON2.3)
“1”
Voltage
Comparator
3.6V
Load
ESF
+
(XPIE1.0)
BOF1IE
PCON0.PD
Enable
AWBOD1
BOF1
(PCON1.2)
(PCON2.7)
BOD1 Interrupt
(SFIE.2)
EXPIE1
(IE.5)
EBOD1
(PCON2.6)
34
MG74PG1A08 Data Sheet
MEGAWIN
11.2. Power Saving Mode
11.2.1. Slow Mode
The alternative to save the operating power is to slow the MCU’s operating speed by programming SCKS2~SCKS0
bits (in CKCON0 register, see Section “8 System Clock” ) to a non-0/0/0 value. The user should examine which
program segments are suitable for lower operating speed. In principle, the lower operating speed should not affect
the system’s normal function. Then, restore its normal speed in the other program segments.
11.2.2. Sub-Clock Mode
The alternative to slow down the MCU’s operating speed by programming OSCS1~0 can select the ILRCO for
system clock. The 64 KHz ILRCO provides the MCU to operate in an ultra-low speed and low power operation.
Additional programming SCKS2~SCKS0 bits (in CKCON0 register, see Section “8 System Clock”), the user could
put the MCU speed down to 500Hz slowest.
11.2.3. Watch Mode
If Watch-Dog-Timer is enabled and NSW is set, Watch-Dog-Timer will keep running in power down mode, which
named Watch Mode in MG74PG1A08. When WDT overflows, set WDTF and wakeup CPU from interrupt or system
reset by software configured. The maximum wakeup period is about 2 seconds that is defined by WDT pre-scaler.
Please refer Section “9 Watch Dog Timer (WDT)” and Section “13 Interrupt” for more detail information.
11.2.4. Monitor Mode
The BOD0 always keep VDD monitor in power down mode. It is the Monitor Mode in MG74PG1A08. When BOD0
meets the detection level, set BOF0 and wakeup CPU from interrupt or system reset by software configured. Please
refer Section “11.1 Brown-Out Detector” and Section “13 Interrupt” for more detail information.
11.2.5. Idle Mode
Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU state is preserved in
its entirety, including the RAM, stack pointer, program counter, program status word, and accumulator. The Port pins
hold the logical states they had at the time that Idle was activated. Idle mode leaves the peripherals running in order
to allow them to wake up the CPU when an interrupt is generated. Timer 0, Timer 1, UART0, KBI and the BOD0 will
continue to function during Idle mode. The PCA Timer and WDT is conditional enabled during Idle mode to wake up
CPU. Any enabled interrupt source or reset may terminate Idle mode. When exiting Idle mode with an interrupt, the
interrupt will immediately be serviced, and following RETI, the next instruction to be executed will be the one
following the instruction that put the device into Idle.
MEGAWIN
MG74PG1A08 Data Sheet
35
11.2.6. Power-down Mode
Setting the PD bit in PCON enters Power-down mode. Power-down mode stops the oscillator and power down the
OTP memory in order to minimize power consumption. Only the power-on circuitry will continue to draw power
during Power-down. During Power-down the power supply voltage may be reduced to the RAM keep-alive voltage.
The RAM contents will be retained; however, the SFR contents are not guaranteed once VDD has been reduced.
Power-down may be exit by external reset, enabled external interrupts, enabled KBI GPIOs, enabled USB, enabled
BOD0/BOD1 (Monitor mode) or enabled Non-Stop WDT (Watch mode).
The user should not attempt to enter (or re-enter) the power-down mode for a minimum of 4 μs until after one of the
following conditions has occurred: Start of code execution (after any type of reset), or Exit from power-down mode.
Figure 11–2 shows the wakeup mechanism of power-down mode in MG74PG1A08.
Figure 11–2. Wakeup structure of Power Down mode
TCON.IT0=0
nINT0 input
0
nINT0 Wakeup
IE0
1
AUXR0.INT0H
IE.EX0
force to level-sensitive in PD
TCON.IT1=0
nINT1 input
0
nINT1 Wakeup
IE1
1
AUXR0.INT1H
IE.EX1
force to level-sensitive in PD
XPIE1.ESF
Keypad Wakeup
IE.EXPIE1
KBIF
PCON1.3
SFIE.KBIFIE
URSM
XPIE1.EUSB
USB Wakeup
USBSFR: UPCON.1
IE.EXPIE1
Event OR
URST
Clear PCON0.PD
& Wakeup CPU
USBSFR: IEN.EFSR
USBSFR: UPCON.2
XPIE1.ESF
WDT Wakeup
WDTCR.ENW
IE.EXPIE1
SFIE.WDTFIE
En
WDT
ILRCO
Overflow
WDTF
PCON1.0
PCON0.PD
WDTCR.NSW
WDT Reset
WDTCR.WREN
RESET Wakeup
External Reset
PCON2.BO0RE
BOD0 Reset
PCON2.BO1RE
BOD1 Reset
XPIE1.ESF
BOD0 Wakeup
IE.EXPIE1
SFIE.BOF0IE
En
“1”
BOD0
BOF0
PCON1.1
XPIE1.ESF
BOD1 Wakeup
IE.EXPIE1
SFIE.BOF1IE
PCON2.EBOD1
PCON0.PD
En
BOD1
BOF1
PCON1.2
PCON2.AWBOD1
36
MG74PG1A08 Data Sheet
MEGAWIN
11.2.7. Interrupt Recovery from Power-down
Two external interrupts may be configured to terminate Power-down mode. External interrupts nINT0 (P3.2/P1.6),
nINT1 (P1.0/P1.4/P3.0/P3.7) may be used to exit Power-down. To wake up by external interrupt nINT0, nINT1, the
interrupt must be enabled and configured for level-sensitive operation. If the enabled external interrupts are
configured to edge-sensitive operation (Falling or Rising), they will be forced to level-sensitive operation (Low level
or High level) by hardware in power-down mode.
When terminating Power-down by an interrupt, the wake up period is internally timed. At the falling edge on the
interrupt pin, Power-down is exited, the oscillator is restarted, and an internal timer begins counting. The internal
clock will not be allowed to propagate and the CPU will not resume execution until after the timer has reached
internal counter full. After the timeout period, the interrupt service routine will begin. To prevent the interrupt from
re-triggering, the ISR should disable the interrupt before returning. The interrupt pin should be held low until the
device has timed out and begun executing.
11.2.8. Reset Recovery from Power-down
If P1.7 is configured for nRST input pin, wakeup from Power-down through an external reset is similar to the
interrupt. At the rising edge of nRST, Power-down is exited, the oscillator is restarted, and an internal timer begins
counting. The internal clock will not be allowed to propagate to the CPU until after the timer has reached internal
counter full. The nRST pin must be held high for longer than the timeout period to ensure that the device is reset
properly. The device will begin executing once nRST is brought low.
It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution,
from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external memory.
11.2.9. KBI wakeup Recovery from Power-down
All of the GPIOs of MG74PG1A08, P1.7 ~ P1.0, P3.7~P3.6 and P3.2~P3.0 have wakeup CPU capability that are
nibble enabled by the control bit in KBIEN0 and the associated port pin is configured to digital input only mode.
Please refer Section “12.1.5 Port 3 Digital-Input-Only (High Impedance Input) Structure” and Section “12.1.11 Port 3
Digital-Input-Only (High Impedance Input) Structure” for the input mode configuration.
Wakeup from Power-down through an enabled KBI GPIO is similar to the interrupt. At the low-level of enabled KBI
GPIO, Power-down is exited, the oscillator is restarted, and an internal timer begins counting. The internal clock will
not be allowed to propagate to the CPU until after the timer has reached internal counter full. After the timeout period,
CPU will meet a KBI interrupt and execute the interrupt service routine. Please refer Section “17 Keypad Interrupt
(KBI)” for more detail information.
11.2.10. USB wakeup Recovery from Power-down
If USB function is enabled and USB host is connected to MG74PG1A08, USB host reset and resume event will
wake up CPU from power down mode. Wakeup from Power-down through enabled USB function (DCON0.5) and
enabled USB interrupt (IEN.2 in USB SFR) is same to the interrupt. At the active USB interrupt, Power-down is
exited, the oscillator is restarted, and an internal timer begins counting. The internal clock will not be allowed to
propagate to the CPU until after the timer has reached internal counter full. After the timeout period, CPU will meet a
KBI interrupt and execute the interrupt service routine.
MEGAWIN
MG74PG1A08 Data Sheet
37
11.3. Power Control Register
PCON0: Power Control Register 0
SFR Attribute = Normal Read/Write or Protected Write
SFR Address = 0x87
POR = 0001-0000, RESET = 000x-0000
7
6
5
4
3
2
1
POF
PD
SMOD1
SMOD0
GF
GF1
GF0
R/W
R/W
R/W
R/W
R/W
R/W
0
IDL
R/W
R/W
2
BOF1
1
BOF0
0
WDTF
R/W
R/W
R/W
Bit 4: POF, Power-On Flag.
0: This bit must be cleared by software writing “1” to it.
1: This bit is set by hardware if a Power-On Reset occurs.
Bit 1: PD, Power-Down control bit.
0: This bit could be cleared by CPU or any exited power-down event.
1: Setting this bit activates power down operation.
Bit 0: IDL, Idle mode control bit.
0: This bit could be cleared by CPU or any exited idle mode event.
1: Setting this bit activates idle mode operation.
PCON1: Power Control Register 1
SFR Attribute = Normal Read/Write or Protected Write
SFR Address = 0x97
POR = 00xx-0000
7
6
5
4
3
SWRF
EXRF
--KBIF
R/W
R/W
W
W
R/W
Bit 7: SWRF, Software Reset Flag.
0: This bit must be cleared by software writing “1” to it.
1: This bit is set by hardware if a Software Reset occurs.
Bit 6: EXRF, External Reset Flag.
0: This bit must be cleared by software writing “1” to it.
1: This bit is set by hardware if an External Reset occurs.
Bit 5~4: Reserved. Software must write “0” on these bits when PCON1 is written.
Bit 3: KBIF, KBI Flag.
0: This bit must be cleared by software writing “1” to it.
1: This bit is set by hardware if a KBI input event occurs.
Bit 2: BOF1, Brown-Out Detection flag 1.
0: This bit must be cleared by software writing “1” to it.
1: This bit is set by hardware if the operating voltage matches the detection level of Brown-Out Detector 1 (3.6V).
Bit 1: BOF0, Brown-Out Detector flag 0.
0: This bit must be cleared by software writing “1” to it.
1: This bit is set by hardware if the operating voltage matches the detection level of Brown-Out Detector 0
(2.1V/2.6V).
Bit 0: WDTF, WDT overflow flag.
0: This bit must be cleared by software writing “1” to it.
1: This bit is set by hardware if a WDT overflow occurs.
38
MG74PG1A08 Data Sheet
MEGAWIN
PCON2: Power Control Register 2
SFR Attribute = Normal Read and Protected Write
SFR Address = 0xBA
POR/RESET = 0100-0000
7
6
5
4
3
2
AWBOD1
EBOD1
--BO1RE
BO0RE
R/W
R/W
W
W
R/W
R/W
1
--
0
RMLS
W
R/W
Bit 7: AWBOD1, Awaked BOD1 in PD mode.
0: BOD1 is disabled in power-down mode.
1: BOD1 keeps operation in power-down mode.
Bit 6: EBOD1, Enable BOD1 that monitors VDD power dropped below 3.6V.
0: Disable BOD1 to slow down the chip power consumption.
1: Enable BOD1 to monitor VDD power dropped.
Bit 5~4: Reserved. Software must write “0” on these bits when PCON2 is written.
Bit 3: BO1RE, BOD1 Reset Enabled.
0: Disable BOD1 to trigger a system reset when BOF1 is set.
1: Enable BOD1 to trigger a system reset when BOF1 is set.
Bit 2: BO0RE, BOD0 Reset Enabled.
0: Disable BOD0 to trigger a system reset when BOF0 is set.
1: Enable BOD0 to trigger a system reset when BOF0 is set (VDD meets 2.1V or 2.6V).
Bit 1: Reserved. Software must write “0” on these bits when PCON2 is written.
Bit 0: RMLS, Power on Reset (POR) and Brown-Out detector 0(BOD0) monitored level Selection. The initial values
of these two bits are loaded from OR1.RMLSO.
RMLS
0
1
MEGAWIN
POR detecting level
1.95V
2.3V
MG74PG1A08 Data Sheet
BOD0 detecting level
2.1V
2.6V
39
12. Configurable I/O Ports
The MG74PG1A08 has following I/O ports: P1.0~P1.7, P3.0~P3.2 and P3.6~P3.7. nRST pin has a swapped
function on P1.7. The exact number of I/O pins available depends upon the package types. See Table 12–1.
Table 12–1. Number of I/O Pins Available
Package Type
I/O Pins
P1.0~P1.7, P3.0~P3.2, P3.6, P3.7,
16-pin SOP
P1.7 (nRST/ECKI/ICKO)
Number of I/O ports
15 (nRST/ECKI selected) or
14 (USB DP/DM selected) or
13 (nRST/ECKI or USB selected)
12.1. IO Structure
The I/O operating modes are distinguished two groups in MG74PG1A08. The first group is only for Port 3 to support
four configurations on I/O operating. These are: analog-input-only (high-impedance), quasi-bidirectional (standard
8051 I/O port), open-drain output, and push-pull output. The default setting of port 3 is quasi-bidirectional mode.
P3.7 and P3.6 only support open-drain output mode and are shared with USB DP/DM pins.
All other general port pins belong to the second group. They can also be programmed to four operating modes,
analog-input-only (high-impedance), open-drain output with pull-up resistor, open-drain output and push-pull output.
The default setting of this group I/O is analog input only mode, which means the port pins in high impedance state
after power-on or any reset.
Followings describe the configuration of the all types I/O mode.
12.1.1. Port 3 Analog-Input-Only (High Impedance) Structure
Figure 12–1. Port 3 Analog-Input-Only
VDDO
Port
Pin
“1”
I/O
Disabled
Input data
Analog Input
40
MG74PG1A08 Data Sheet
MEGAWIN
12.1.2. Port 3 Quasi-Bidirectional IO Structure (default)
Port 3 pins in quasi-bidirectional mode are similar to the standard 8051 port pins. A quasi-bidirectional port can be
used as an input and output without the need to reconfigure the port. This is possible because when the port outputs
logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin outputs low, it is driven
strongly and able to sink a large current. There are three pull-up transistors in the quasi-bidirectional output that
serve different purposes.
One of these pull-ups, called the “very weak” pull-up, is turned on whenever the port register for the pin contains
logic “1”. This very weak pull-up sources a very small current that will pull the pin high if it is left floating. A second
pull-up, called the “weak” pull-up, is turned on when the port register for the pin contains logic “1” and the pin itself is
also at a logic “1” level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting
a 1. If this pin is pulled low by the external device, this weak pull-up turns off, and only the very weak pull-up remains
on. In order to pull the pin low under these conditions, the external device has to sink enough current to over-power
the weak pull-up and pull the port pin below its input threshold voltage. The third pull-up is referred to as the “strong”
pull-up. This pull-up is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port
register changes from logic “0” to logic “1”. When this occurs, the strong pull-up turns on for one CPU clocks, quickly
pulling the port pin high.
The quasi-bidirectional port configuration on Port 3 is shown in Figure 12–2.
Figure 12–2. Port 3 Quasi-Bidirectional I/O
VDDO
1 clock
delay
VDDO
Strong
Very
weak
VDDO
Weak
Port
Pin
Port latch data
Input data
MEGAWIN
MG74PG1A08 Data Sheet
41
12.1.3. Port 3 Open-Drain Output Structure
The open-drain output configuration on Port 3 turns off all pull-ups and only drives the pull-down transistor of the port
pin when the port register contains logic “0”. To use this configuration in application, a port pin must have an external
pull-up, typically a resistor tied to VDD. The pull-down for this mode is the same as for the quasi-bidirectional mode.
In addition, the input path of the port pin in this configuration is also the same as quasi-bidirectional mode.
The Port 3 open-drain port configuration is shown in Figure 12–3.
Figure 12–3. Port 3 Open-Drain Output
Port
Pin
Port latch data
Input data
12.1.4. Port 3 Push-Pull Output Structure
The push-pull output configuration on Port 3 has the same pull-down structure as both the open-drain and the
quasi-bidirectional output modes, but provides a continuous strong pull-up when the port register contains logic “1”.
The push-pull mode may be used when more source current is needed from a port output. In addition, the input path
of the port pin in this configuration is also the same as quasi-bidirectional mode.
The push-pull port configuration on Port 3 is shown in Figure 12–4.
Figure 12–4. Port 3 Push-Pull Output
VDDO
Port
Pin
Port latch data
Input data
42
MG74PG1A08 Data Sheet
MEGAWIN
12.1.5. Port 3 Digital-Input-Only (High Impedance Input) Structure
A Port pin is configured as a digital input by setting its output mode to “Open-Drain” and writing logic “1” to the
associated bit in the Port Latch Data register. For example, pin P3.2 is configured as a digital input by setting
P3M0.2 and P3M1.2 to “01” as open-drain mode and setting P3.2 Port Latch Data to logic 1. Then, the
digital-input-only configuration on P3.2 is an input without any pull-up resistors on the port pin. If a pull-up resistor is
necessary in the application, software must configure the port pin to quasi-bidirectional I/O mode which enables the
on-chip pull-up resistor.
12.1.6. DP/DM Structure
DP & DM input/output structure is shown in Figure 12–5.
Figure 12–5. Port 3.7(DP) & Port 3.6(DM) structure
V33
PS2
VDD
7K
PS2
DP/DM
Port Pin
Port latch data
Input data
12.1.7. General Analog-Input-Only (High Impedance) Structure (default)
Figure 12–6. General Analog-Input-Only
VDDO
Port
Pin
“1”
I/O
Disabled
Input data
Analog Input
MEGAWIN
MG74PG1A08 Data Sheet
43
12.1.8. General Open-Drain Output with Pull-up Resistor Structure
Figure 12–7. General Open-Drain Output with Pull-up Resistor
VDDO
VDDO
Very
weak
Weak
Port
Pin
Port latch data
Input data
12.1.9. General Open-Drain Output Structure
The open-drain output configuration on general port pins only drives the pull-down transistor of the port pin when the
Port Data register contains logic “0”.
The general open-drain port configuration is shown in Figure 12–8.
Figure 12–8. General Open-Drain Output
Port
Pin
Port latch data
Input data
44
MG74PG1A08 Data Sheet
MEGAWIN
12.1.10. General Push-Pull Output Structure
The push-pull output configuration on general port pins has the same pull-down structure as the open-drain output
modes, but provides a continuous strong pull-up when the port register contains logic “1”. The push-pull mode may
be used when more source current is needed from a port output. In addition, the input path of the port pin in this
configuration is also the same as open-drain mode.
The push-pull port configuration is shown in Figure 12–9.
Figure 12–9. General Push-Pull Output
VDDO
Port
Pin
Port latch data
Input data
12.1.11. General Digital-Input-Only (High Impedance Input) Structure
A Port pin is configured as a digital input by setting its output mode to “Open-Drain” and writing logic “1” to the
associated bit in the Port Latch Data register. For example, P1.2 is configured as a digital input by setting P1M0.2
and P1M1.2 to “01” as open-drain mode and setting P1.2 Port Latch Data to logic 1. Then, the digital-input-only
configuration on P1.2 is an input without any pull-up resistors on the port pin. If a pull-up resistor is necessary in the
application, software must configure the port pin to open-drain output with pull-up resistor mode, {P1M0.2, P1M1.2}
= “10”, which enables the on-chip pull-up resistor.
MEGAWIN
MG74PG1A08 Data Sheet
45
12.2. I/O Port Register
All I/O port pins on the MG74PG1A08 may be individually and independently configured by software to select its
operating mode. Port 3 has four operating modes, as shown in Table 12–2. Two mode registers select the I/O type
for each port 3 pin. Only port 3 supports quasi-bidirectional mode and setting them to quasi-bidirectional mode after
power-on or any reset.
Table 12–2. Port 3 Configuration Settings
P3M0.y
P3M1.y
Port Mode
0
0
Analog Input Only
0
1
Open-Drain Output (support digital-input-only)
Quasi-Bidirectional (default, with pull-up)
1
0
1
1
Push-Pull Output
Where y=0~2 (port pin). The registers P3M0 and P3M1 are listed in each port description.
Table 12–3. Port 37 Configuration Settings
P3M0.7
0
0
1
1
P3M1.7
0
1
0
1
Port Mode
Input Only (default)
XCVR power-down
Open-Drain Output with pull-up (PS2 mode)
Reserve
Other general port pins also support four operating modes, as shown in Table 12–4. Two mode registers select the
I/O type for each port pin and setting to analog-input-only on these port pins after power-on or any reset.
Table 12–4. General Port Configuration Settings
PxM0.y
PxM1.y
Port Mode
Analog-Input-Only (default)
0
0
0
1
Open-Drain Output (support digital-input-only)
1
0
Open-Drain Output with Pull-Up resistor
1
1
Push-Pull Output
Where x= 0, 1… (Port number), and y=0~7 (port pin). The registers PxM0 and PxM1 are listed in each port
description.
12.2.1. Port 1 Register
P1: Port 1 Register
SFR Attribute = Normal Read/Write
SFR Address = 0x90
7
6
5
P1.7
P1.6
P1.5
R/W
R/W
R/W
RESET = 1111-1111
4
3
P1.4
P1.3
2
P1.2
1
P1.1
0
P1.0
R/W
R/W
R/W
R/W
1
P1M0.1
0
P1M0.0
R/W
R/W
R/W
Bit 7~0: P1.7~P1.0 could be only set/cleared by CPU.
P1M0: Port 1 Mode Register 0
SFR Attribute = Normal Read/Write
SFR Address = 0x91
7
6
5
P1M0.7
P1M0.6
P1M0.5
R/W
46
R/W
R/W
RESET = 0000-0000
4
3
2
P1M0.4
P1M0.3
P1M0.2
R/W
R/W
R/W
MG74PG1A08 Data Sheet
MEGAWIN
P1M0: Port 1 Mode Register 1
SFR Attribute = Normal Read/Write
SFR Address = 0x92
7
6
5
P1M1.7
P1M1.6
P1M1.5
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
P1M1.4
P1M1.3
P1M1.2
1
P1M1.1
0
P1M1.0
R/W
R/W
R/W
RESET = 11xx-x111
4
3
---
2
P3.2
1
P3.1
0
P3.0
W
R/W
R/W
R/W
1
P3M0.1
0
P3M0.0
R/W
R/W
1
P3M1.1
0
P3M1.0
R/W
R/W
R/W
R/W
12.2.2. Port 3 Register
P3: Port 3 Register
SFR Attribute = Normal Read/Write
SFR Address = 0xB0
7
6
5
P3.7
P3.6
-R/W
R/W
W
W
Bit 7~0: P3.7~P3.0 could be only set/cleared by CPU.
P3M0: Port 3 Mode Register 0
SFR Attribute = Normal Read/Write
SFR Address = 0xB1
7
6
5
-P3M0.7
-R/W
W
W
P3M1: Port 3 Mode Register 1
SFR Attribute = Normal Read/Write
SFR Address = 0xB2
7
6
5
-P3M1.7
-R/W
MEGAWIN
W
W
RESET = 0xxx-x111
4
3
2
--P3M0.2
W
W
R/W
RESET = 0xxx-x000
4
3
2
--P3M1.2
W
W
R/W
MG74PG1A08 Data Sheet
47
13. Interrupt
The MG74PG1A08 has 6 interrupt sources with a two-level interrupt structure. There are several SFRs associated
with the two-level interrupt. They are the IE, IP0L and XPIE1. The IP0L (Interrupt Priority 0 Low) register makes the
two-level interrupt structure possible. The two priority level interrupt structure allows great flexibility in handling these
interrupt sources.
13.1. Interrupt Structure
Table 13–1 lists all the interrupt sources. The ‘Request Bits’ are the interrupt flags that will generate an interrupt if it
is enabled by setting the ‘Enable Bit’. Of course, the global enable bit EA (in IE register) should have been set
previously. The ‘Request Bits’ can be set or cleared by software, with the same result as though it had been set or
cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled in software. The
‘Priority Bits’ determine the priority level for each interrupt. The ‘Priority within Level’ is the polling sequence used to
resolve simultaneous requests of the same priority level. The ‘Vector Address’ is the entry point of an interrupt
service routine in the program memory.
Figure 13–1 shows the interrupt system. Each of these interrupts will be briefly described in the following sections.
Table 13–1. Interrupt Sources
No
#1
#2
#3
Source Name
External Interrupt 0,
nINT0
Timer 0
External Interrupt 1,
nINT1
Timer 1
Serial Port 0 (UART0)
Enable
Bit
Request
Bits
Priority
Bits
Polling
Priority
Vector
Address
EX0
IE0
[ PX0L ]
(Highest)
0003H
ET0
TF0
[ PT0L ]
…
000Bh
EX1
IE1
[ PX1L ]
…
0013H
…
ET1
TF1
[ PT1L ]
001BH
…
ES0
RI0, TI0
[ PS0L ]
0023H
EXPIE1
(Note 1)
(ESF,
#6
Expanded Interrupt 1
(Note 2)
[ PXPI1L ]
(Lowest)
002Bh
EPCA,
(Note 3)
EUSB)
Note1: The System Flag interrupt flags include: KBIF, BOF1, BOF0 and WDTF in PCON1 register, and, STAF and
STOF in AUXR1 register.
Note2: The PCA interrupt flags include: CF and CCF0 in PCA register, CCON.
Note3: The USB interrupt flags include:
(1) URSTWKP, URST, URSM and USUS: contained in USB register UPCON.
(2) UTXD0, URXD0, UTXD1, UTXD2, URXD2 and SOFIF: contained in USB register UIFLG.
(3) TXNAK and RXNAK: contained in USB register UIFLG1
#4
#5
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MG74PG1A08 Data Sheet
MEGAWIN
Figure 13–1. Interrupt System
Global Enable
(IE.EA)
IP0L
Highest Priority
Level Interrupt
Interrupt Polling
Sequence
TCON.IT0
nINT0
IE.EX0
0
IE0
1
AUXR0.INT0H
IE.ET0
TCON.TF0
TCON.IT1
nINT1
0
IE.EX1
IE1
1
AUXR0.INT1H
IE.ET1
TCON.TF1
S0CON.RI0
IE.ES
AUXR2.BTI
S0CON.TI0
CF
ECF
CCF0
ECCF0
XPIE1.EPCA
XPIE1.EUSB
IE.EXPIE1
USB Interrupt Flags
Lowest Priority
Level Interrupt
S0CON.TI0
SFIE.UTIE
PCON1.WDTF
SFIE.WDTFIE
PCON1.BOF0
SFIE.BOF0IE
PCON1.BOF1
SFIE.BOF1IE
PCON1.KBIF
SFIE.KBIFIE
AUXR1.STAF
AUXR1.STOF
SFIE.SIDFIE
XPIE1.ESF
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MG74PG1A08 Data Sheet
49
13.2. Interrupt Source
Table 13–2. Interrupt flags
No
Source Name
#1
External Interrupt 0,nINT0
#2
Timer 0
#3
External Interrupt 1,nINT1
#4
Timer 1
#5
Serial Port 0(UART0)
#6
Expanded Interrupt 1
Request Bits
IE0
TF0
IE1
TF1
RI0,
TI0
KBIF,
BOF1,
BOF0,
WDTF,
STAF,
STOF,
(TI0),
CF,
CCF0,
(Note 1)
Bit Location
TCON.1
TCON.5
TCON.3
TCON.7
S0CON.0
S0CON.1
PCON1.3
PCON1.2
PCON1.1
PCON1.0
AUXR1.3
AUXR1.2
(S0CON.1)
CCON.7
CCON.0
(Note 1)
Note1: The USB interrupt flags include:
(1) URSTWKP, URST, URSM and USUS: contained in USB register UPCON.
(2) UTXD0, URXD0, UTXD1, UTXD2, URXD2 and SOFIF: contained in USB register UIFLG.
(3) TXNAK, RXNAK: contained in USB register UIFLG1
The external interrupt nINT0 and nINT1 can each be either level-activated or transition-activated, depending on bits
IT0 and IT1 in register TCON. The flags that actually generate these interrupts are bits IE0 and IE1 in TCON. When
an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is
vectored to only if the interrupt was transition –activated, then the external requesting source is what controls the
request flag, rather than the on-chip hardware.
The Timer0 and Timer1 interrupts are generated by TF0 and TF1, which are set by a rollover in their respective
Timer/Counter registers in most cases. When a timer interrupt is generated, the flag that generated it is cleared by
the on-chip hardware when the service routine is vectored to.
The serial port 0(UART0) interrupt is generated by the logical OR of RI0 and TI0. Neither of these flags is cleared by
hardware when the service routine is vectored to. The service routine should poll RI0 and TI0 to determine which
one to request service and it will be cleared by software.
The expanded interrupt 1 is grouping by 3 interrupt source: System Flag interrupt, PCA interrupt and USB interrupt.
Following describes each interrupt source flags.
The System Flag interrupt is generated by STAF, STOF, KBIF, BOF1 BOF0 and WDTF in PCON1. STAF and STOF
are set by serial interface detection. KBIF is set by KBI event. BOF1 and BOF0 are set by on chip
Brownout-Detector (BOD1 and BOD0) met the low voltage event. WDTF is set by Watch-Dog-Timer overflow. They
will not be cleared by hardware when the service routine is vectored to.
Figure 13–2 shows the system flag interrupt configuration.
50
MG74PG1A08 Data Sheet
MEGAWIN
Figure 13–2. System flag interrupt configuration
PCON1.WDTF
SFIE.WDTFIE
PCON1.BOF0
SFIE.BOF0IE
System Flag
Interrupt
PCON1.BOF1
SFIE.BOF1IE
PCON1.KBIF
SFIE.KBIFIE
S0CON.TI0
AUXR2.UTIE
XPIE1.ESF
AUXR1.STAF
AUXR1.STOF
SFIE.SIDFIE
The PCA interrupt is generated by the logical OR of CF, and CCF0 in CCON. Neither of these flags is cleared by
hardware when the service routine is vectored to. The service routine should poll these flags to determine which one
to request service and it will be cleared by software.
The USB interrupt is generate by a grouping of USB event flags in USB SFR, which are set by USB engine detecting
a new bus state or USB function event happened. They will not be cleared by hardware when the service routine is
vectored to.
MEGAWIN
MG74PG1A08 Data Sheet
51
13.3. Interrupt Enable
Table 13–3. Interrupt enable control
No
Source Name
#1
External Interrupt 0,nINT0
#2
Timer 0
#3
External Interrupt 1,nINT1
#4
Timer 1
#5
Serial Port 0(UART0)
#6
Expanded Interrupt 1
Enable Bit
EX0
ET0
EX1
ET1
ES0
EXPIE1
Bit Location
IE.0
IE.1
IE.2
IE.3
IE.4
IE.5
There are 6 interrupt sources available in MG74PG1A08. Each of these interrupt sources can be individually
enabled or disabled by setting or clearing an interrupt enable bit in the register IE. IE also contains a global disable
bit, EA, which can be cleared to disable all interrupts at once. If EA is set to ‘1’, the interrupts are individually enabled
or disabled by their corresponding enable bits. If EA is cleared to ‘0’, all interrupts are disabled.
13.4. Interrupt Priority
The priority scheme for servicing the interrupts is the same as that for the standard 80C51. The Priority Bits (see
Table 13–1) determine the priority level of each interrupt. IP0L determines to two-level priority interrupt. Table 13–4
shows the bit values and priority levels associated with each combination.
Table 13–4. Interrupt priority level
{ IP0L.x}
Priority Level
1
1 (high)
0
2 (low)
Each interrupt source has one corresponding bit to represent its priority which is located in IP0L register.
Higher-priority interrupt will be not interrupted by lower-priority interrupt request. If two interrupt requests of different
priority levels are received simultaneously, the request of higher priority is serviced. If interrupt requests of the same
priority level are received simultaneously, an internal polling sequence determine which request is serviced. Table
13–2 shows the internal polling sequence in the same priority level and the interrupt vector address.
52
MG74PG1A08 Data Sheet
MEGAWIN
13.5. Interrupt Process
Each interrupt flag is sampled at every system clock cycle. The samples are polled during the next system clock. If
one of the flags was in a set condition at first cycle, the second cycle (polling cycle) will find it and the interrupt
system will generate a hardware LCALL to the appropriate service routine as long as it is not blocked by any of the
following conditions.
Block conditions:



An interrupt of equal or higher priority level is already in progress.
The current cycle (polling cycle) is not the final cycle in the execution of the instruction in progress.
The instruction in progress is RETI or any write to the IE and IP0L registers.
Any of these three conditions will block the generation of the hardware LCALL to the interrupt service routine.
Condition 2 ensures that the instruction in progress will be completed before vectoring into any service routine.
Condition 3 ensures that if the instruction in progress is RETI or any access to IE or IP0L, then at least one or more
instruction will be executed before any interrupt is vectored to.
13.6. Special Interrupt Vector for TI0
The serial port 0 interrupt from TI0 flag can be masked by BTI (AUXR2.6). If BTI is set, set TI0 flag will not generate
a serial port 0 interrupt. The serial port 0 interrupt only reflects the RI0 flag.
If UTIE (AUXR2.7) is set, TI0 flag will be combined into System Flag Interrupt. In this mode, TI0 interrupt shares the
interrupt vector with BOF0 and WDTF in System Flag Interrupt.
MEGAWIN
MG74PG1A08 Data Sheet
53
13.7. nINT0/nINT1 Input Source Selection
The MG74PG1A08 provides flexible nINT0 and nINT1 source selection to share the port pin input with on-chip serial
interface. That will support the additional remote wakeup function for communication peripheral in power-down
mode. The nINT0/nINT1 input can be routed to the interface pin to catch port change and set them as an interrupt
input event to wake up MCU. INT0H (AUXR0.0) and INT1H (AUXR0.1) configure the port change detection level on
low/falling or high/rising event. In MCU power-down mode, both of the falling edge or rising edge configurations of
the external interrupts are forced to level-sensitive operation.
Figure 13–3. Configuration of nINT0/nINT1 port pin selection.
P3.2
0
P1.6
TCON.IT0
nINT0 input from GPIO, default
0
IE0
1
1
INT0IS0
AUXR0.INT0H
(AUXR1.5)
P1.0
0
P1.4
1
P3.0
TCON.IT1
nINT1 input from GPIO, default
2
0
IE1
1
3
P3.7
AUXR0.INT1H
INT1IS.1~0
(AUXR1.7~6)
13.8. Interrupt Register
TCON: Timer/Counter Control Register
SFR Attribute = Normal Read/Write
SFR Address = 0x88
RESET = 0000-0000
7
6
5
4
3
IE1
TF1
TR1
TF0
TR0
R/W
R/W
R/W
R/W
R/W
2
IT1
1
IE0
0
IT0
R/W
R/W
R/W
Bit 3: IE1, Interrupt 1 Edge flag.
0: Cleared when interrupt processed on if transition-activated.
1: Set by hardware when external interrupt 1 edge is detected (transmitted or level-activated).
Bit 2: IT1: Interrupt 1 Type control bit.
0: Cleared by software to specify low level triggered external interrupt 1. If INT1H (AUXR0.1) is set, this bit specifies
high level triggered on nINT1.
1: Set by software to specify falling edge triggered external interrupt 1. If INT1H (AUXR0.1) is set, this bit specifies
rising edge triggered on nINT1.
Bit 1: IE0, Interrupt 0 Edge flag.
0: Cleared when interrupt processed on if transition-activated.
1: Set by hardware when external interrupt 0 edge is detected (transmitted or level-activated).
Bit 0: IT0: Interrupt 0 Type control bit.
0: Cleared by software to specify low level triggered external interrupt 0. If INT0H (AUXR0.0) is set, this bit specifies
high level triggered on nINT0.
1: Set by software to specify falling edge triggered external interrupt 0. If INT0H (AUXR0.0) is set, this bit specifies
rising edge triggered on nINT0.
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MG74PG1A08 Data Sheet
MEGAWIN
IE: Interrupt Enable Register
SFR Attribute = Normal Read/Write
SFR Address = 0xA8
7
6
5
EA
-EXPIE1
R/W
W
R/W
RESET = 0x00-0000
4
3
2
ES0
ET1
EX1
1
ET0
0
EX0
R/W
R/W
R/W
2
--
1
EPCA
0
ESF
W
R/W
R/W
R/W
R/W
Bit 7: EA, All interrupts enable register.
0: Global disables all interrupts.
1: Global enables all interrupts.
Bit 6: Reserved. Software must write “0” on this bit when IE is written.
Bit 5: EXPIE1. Enable Expanded Interrupt 1.
0: Disable the interrupt which is grouping of System Flag, PCA and USB.
1: Enable the interrupt which is grouping of System Flag, PCA and USB.
Bit 4: ES0, Serial port 0 interrupt enable register.
0: Disable serial port 0 interrupt.
1: Enable serial port 0 interrupt.
Bit 3: ET1, Timer 1 interrupt enable register.
0: Disable Timer 1 interrupt.
1: Enable Timer 1 interrupt.
Bit 2: EX1, External interrupt 1 enable register.
0: Disable external interrupt 1.
1: Enable external interrupt 1.
Bit 1: ET0, Timer 0 interrupt enable register.
0: Disable Timer 0 interrupt.
1: Enable Timer 1 interrupt.
Bit 0: EX0, External interrupt 0 enable register.
0: Disable external interrupt 0.
1: Enable external interrupt 1.
XPIE1: Expanded Interrupt 1 Enable Register
SFR Attribute = Normal Read/Write
SFR Address = 0xAD
RESET = 0xxx-xx00
7
6
5
4
3
EUSB
----R/W
W
W
W
W
Bit 7: EUSB, Enable USB Interrupt.
0: Disable USB interrupt.
1: Enable USB interrupt.
Bit 6~2: Reserved. Software must write “0” on these bits when XPIE1 is written.
Bit 1: EPCA, Enable PCA interrupt.
0: Disable PCA interrupt.
1: Enable PCA interrupt.
Bit 0: ESF, Enable System Flag interrupt.
0: Disable the interrupt when the group of {KBIF, BOF1, BOF0, WDTF} in PCON1, {STAF, STOF} in AUXR1 or TI0
in S0CON is set
1: Enable the interrupt of the flags of {KBIF, BOF1, BOF0, WDTF} in PCON1, {STAF, STOF} in AUXR1 or TI0 in
S0CON when the associated system flag interrupt is enabled in SFIE.
MEGAWIN
MG74PG1A08 Data Sheet
55
SFIE: System Flag Interrupt Enable Register
SFR Attribute = Normal Read/Write
SFR Address = 0x8E
RESET = 0xxx-0000
7
6
5
4
3
2
SIDFIE
---KBIFIE
BOF1IE
R/W
W
W
W
R/W
1
BOF0IE
0
WDTFIE
R/W
R/W
1
PT0L
0
PX0L
R/W
R/W
1
INT1H
0
INT0H
R/W
R/W
R/W
Bit 7: SIDFIE, Serial Interface Detection Flag Interrupt Enabled.
0: Disable SIDF (STAF or STOF) interrupt.
1: Enable SIDF (STAF or STOF) interrupt.
Bit 5~4: Reserved. Software must write “0” on these bits when SFIE is written.
Bit 3: KBIFIE, Enable KBIF (PCON1.3) Interrupt.
0: Disable KBIF interrupt.
1: Enable KBIF interrupt.
Bit 2: BOF1IE, Enable BOF1 (PCON1.2) Interrupt.
0: Disable BOF1 interrupt.
1: Enable BOF1 interrupt.
Bit 1: BOF0IE, Enable BOF0 (PCON1.1) Interrupt.
0: Disable BOF0 interrupt.
1: Enable BOF0 interrupt.
Bit 0: WDTFIE, Enable WDTF (PCON1.0) Interrupt.
0: Disable WDTF interrupt.
1: Enable WDTF interrupt.
IP0L: Interrupt Priority 0 Low Register
SFR Attribute = Normal Read/Write
SFR Address = 0xB8
RESET = 0x00-0000
7
6
5
4
3
2
URXR
-PXPI1L
PSL
PT1L
PX1L
R/W
W
R/W
R/W
R/W
R/W
Bit 7: URXR, Serial Port 0 eXtension Receive.
Bit 6: Reserved. Software must write “0” on this bit when IP0L is written.
Bit 5: PXPI1L, Expanded interrupt 1 priority-L register.
Bit 4: PSL, Serial port 0 interrupt priority-L register.
Bit 3: PT1L, Timer 1 interrupt priority-L register.
Bit 2: PX1L, external interrupt 1 priority-L register.
Bit 1: PT0L, Timer 0 interrupt priority-L register.
Bit 0: PX0L, external interrupt 0 priority-L register.
AUXR0: Auxiliary Register 0
SFR Attribute = Normal Read/Write
SFR Address = 0xA1
7
6
5
P17OC1
P17OC0
-R/W
R/W
W
RESET = 0000-0000
4
3
2
T0XL
P1FS1
P1FS0
R/W
R/W
R/W
Bit 5: Reserved. Software must write “0” on this bit when AUXR0 is written.
Bit 1: INT1H, INT1 High/Rising trigger enable.
0: Remain INT1 triggered on low level or falling edge on nINT1 port pin.
1: Set INT1 triggered on high level or rising edge on nINT1 port pin.
Bit 0: INT0H, INT0 High/Rising trigger enable.
0: Remain INT0 triggered on low level or falling edge on nINT0 port pin.
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MG74PG1A08 Data Sheet
MEGAWIN
1: Set INT0 triggered on high level or rising edge on nINT0 port pin.
AUXR1: Auxiliary Control Register 1
SFR Attribute = Normal Read/Write
SFR Address = 0xA2
7
6
5
INT1IS1
INT1IS0
INT0IS0
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
-STAF
STOF
W
R/W
R/W
1
PTCKOE
0
--
R/W
W
Bit 7~6: INT1IS1~0, nINT1 input selection bits which function is defined as following table.
INT1IS.1~0
nINT1
00
P1.0
01
P1.4
10
P3.0
11
P3.7
Bit 5: INT0IS0, nINT0 input selection bits which function is defined as following table.
INT0IS.0
nINT0
0
P3.2
1
P1.6
Bit 4: Reserved. Software must write “0” on this bit when AUXR0 is written.
Bit 0: Reserved. Software must write “0” on this bit when AUXR0 is written.
MEGAWIN
MG74PG1A08 Data Sheet
57
14. Timers/Counters
MG74PG1A08 has two Timers/Counters: Timer 0 and Timer 1. Timer0/1 can be configured as timers or event
counters.
In the “timer” function, the timer rate is pre-scaled by 12 clock cycle to increment register value. In other words, it is
to count the standard C51 machine cycle. AUXR2.T0X12 and AUXR2.T1X12 are the function for Timer 0/1 to set the
timer rate on every clock cycle. The AUXR0.T0XL is combined with T0X12 to select additional pre-scaler value,
SYSCLK/48 and SYSCLK/192, for Timer 0 clock input.
In the “counter” function, the register is incremented in response to a 1-to-0 transition at its corresponding external
input pin, T0 or T1. In this function, the external input is sampled by every timer rate cycle. When the samples show
a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the
register at the end of the cycle following the one in which the transition was detected.
14.1. Timer0 and Timer1
14.1.1. Mode 0 Structure
The timer register is configured as a PWM generator. As the count rolls over from all 1s to all 0s, it sets the timer
interrupt flag TFx. The counted input is enabled to the timer when TRx = 1 and either GATE=0 or nINTx = 1. Mode 0
operation is the same for Timer0 and Timer1. The PWM function of Timer 0/1 is shown in Figure 14–1 and Figure
14–2.
Figure 14–1. Timer 0 Mode 0 Structure
SYSCLK /12
0
SYSCLK
1
SYSCLK /48
2
SYSCLK /192
0
T0 Pin
3
Overflow
TL0[7:0]
T0 Interrupt
Port I/O
C/T
[T0XL:T0X12]
TF0
1
Q
00: SYSCLK/12 (default)
01: SYSCLK
10: SYSCLK/48
11: SYSCLK/192
TR0
0
{TL0} >= {TH0}
8-Bit
Comparator
GATE
S
Q
R
Q
T0CKO
1
{TL0} < {TH0}
nINT0 Pin
0
1
TH0[7:0]
AUXR0.INT0H
T0CKOE
Figure 14–2. Timer 1 Mode 0 Structure
SYSCLK /12
0
SYSCLK
1
0
T1 Pin
AUXR2.T1X12
TL1[7:0]
Overflow
TF1
T1 Interrupt
1
Port I/O
C/T
Q
TR1
GATE
nINT1 Pin
0
8-Bit
Comparator
0
{TL1} >= {TH1}
S
Q
R
Q
1
T1CKO
{TL1} < {TH1}
1
AUXR0.INT1H
TH1[7:0]
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MG74PG1A08 Data Sheet
T1CKOE
MEGAWIN
14.1.2. Mode 1 Structure
Timer 0/1 in Mode1 is configured as a 16 bit timer or counter. The function of GATE, nINTx and TRx is same as
mode 0. Figure 14–3 and Figure 14–4 show the mode 1 structure of Timer 0 and Timer 1.
Figure 14–3. Timer 0 Mode 1 Structure
SYSCLK /12
0
SYSCLK
1
SYSCLK /48
2
SYSCLK /192
0
T0 Pin
3
TL0[7:0]
TH0[7:0]
Overflow
TF0
T0 Interrupt
1
C/T
[T0XL:T0X12]
00: SYSCLK/12 (default)
01: SYSCLK
10: SYSCLK/48
11: SYSCLK/192
TR0
GATE
nINT0 Pin
0
1
AUXR0.INT0H
Figure 14–4. Timer 1 Mode 1 Structure
SYSCLK /12
0
SYSCLK
1
0
T1 Pin
AUXR2.T1X12
TL1[7:0]
TH1[7:0]
Overflow
TF1
T1 Interrupt
1
C/T
TR1
GATE
nINT1 Pin
0
1
AUXR0.INT1H
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MG74PG1A08 Data Sheet
59
14.1.3. Mode 2 Structure
Mode 2 configures the timer register as an 8-bit counter (TLx) with automatic reload. Overflow from TLx not only set
TFx, but also reload TLx with the content of THx, which is determined by software. The reload leaves THx
unchanged. Mode 2 operation is the same for Timer0 and Timer1.
Figure 14–5. Timer 0 Mode 2 Structure
SYSCLK /12
0
SYSCLK
1
SYSCLK /48
2
SYSCLK /192
0
T0 Pin
3
Overflow
TL0[7:0]
TF0
T0 Interrupt
1
C/T
[T0XL:T0X12]
Reload
00: SYSCLK/12 (default)
01: SYSCLK
10: SYSCLK/48
11: SYSCLK/192
TH0[7:0]
TR0
GATE
nINT0 Pin
0
1
AUXR0.INT0H
Figure 14–6. Timer 1 Mode 2 Structure
SYSCLK /12
0
SYSCLK
1
0
T1 Pin
AUXR2.T1X12
TL1[7:0]
Overflow
TF1
T1 Interrupt
1
C/T
Reload
TR1
GATE
TH1[7:0]
nINT1 Pin
0
1
AUXR0.INT1H
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MG74PG1A08 Data Sheet
MEGAWIN
14.1.4. Mode 3 Structure
Timer1 in Mode3 simply holds its count, the effect is the same as setting TR1 = 1. Timer0 in Mode 3 enables TL0
and TH0 as two separate 8-bit counters. TL0 uses the Timer0 control bits such like C/T, GATE, TR0, nINT0 and TF0.
TH0 is locked into a timer function (cannot be external event counter) and take over the use of TR1, TF1 from
Timer1. TH0 now controls the Timer1 interrupt.
Figure 14–7. Timer 0 Mode 3 Structure
SYSCLK /12
0
SYSCLK
1
SYSCLK /48
2
SYSCLK /192
0
T0 Pin
3
TL0[7:0]
Overflow
TF0
T0 Interrupt
TF1
T1 Interrupt
1
C/T
[T0XL:T0X12]
00: SYSCLK/12 (default)
01: SYSCLK
10: SYSCLK/48
11: SYSCLK/192
TR0
GATE
nINT0 Pin
0
1
AUXR0.INT0H
SYSCLK /12
0
SYSCLK
1
SYSCLK /48
2
SYSCLK /192
3
TH0[7:0]
Overflow
TR1
[T0XL:T0X12]
00: SYSCLK/12 (default)
01: SYSCLK
10: SYSCLK/48
11: SYSCLK/192
MEGAWIN
MG74PG1A08 Data Sheet
61
14.1.5. Timer 0/1 Programmable Clock-Out
Timer 0 and Timer 1 have a Clock-Out Mode (while C/Tx=0 & TxCKOE=1). In this mode, Timer 0 or Timer 1
operates as 8-bit auto-reload timer for a programmable clock generator with 50% duty-cycle. The generated clocks
come out on P1.4 (T0CKO) and P1.5 (T1CKO) individually. The input clock (SYSCLK/12, SYSCLK, SYSCLK/48 or
SYSCLK/192) increments the 8-bit timer, TL0, in Timer 0 module. The input clock (SYSCLK/12 or SYSCLK)
increments the 8-bit timer, TL1, in Timer 1 module. The timer repeatedly counts to overflow from a loaded value.
Once overflows occur, the contents of (TH0 and TH1) are loaded into (TL0, TL1) for the consecutive counting. The
following formula gives the clock-out frequency:
Figure 14–8. Timer 0 clock out equation
; n=24, if {T0XL,T0X12}=00
; n=2, if {T0XL,T0X12}=01
; n=96, if {T0XL,T0X12}=10
; n=384, if {T0XL,T0X12}=11
; C/T = 0
SYSCLK Frequency
T0 Clock-out Frequency =
n X (256 – THx)
Figure 14–9. Timer 1 clock out equation
; n=24, if T1X12=0
; n=2, if T1X12=1
; C/T = 0
SYSCLK Frequency
T1 Clock-out Frequency =
n X (256 – TH1)
Note:
(1) Timer 0/1 overflow flag, TF0/1, will be set when Timer 0/1 overflows but not generate interrupt.
(2) For SYSCLK=12MHz & TxX12=0, Timer 0/1 has a programmable output frequency range from 1.95KHz to
500KHz.
(3) For SYSCLK=12MHz & TxX12=1, Timer 0/1 has a programmable output frequency range from 23.43KHz to
6MHz.
(4) For SYSCLK=12MHz, T0X12=0 & T0XL=1, Timer 0 has a programmable output frequency range from 488Hz to
125KHz.
(5) For SYSCLK=12MHz, TxX12=1 & T0XL=1, Timer 0 has a programmable output frequency range from 122Hz to
31.25KHz.
Figure 14–10. Timer 0 in Clock Output Mode
SYSCLK /12
0
SYSCLK
1
SYSCLK /48
2
SYSCLK /192
3
Toggle
0
T0 Pin
PORTn for T0CKO
D
Q
1
C/T
[T0XL:T0X12]
Reload
00: SYSCLK/12 (default)
01: SYSCLK
10: SYSCLK/48
11: SYSCLK/192
TH0[7:0]
TR0
GATE=0
nINT0 Pin
TL0[7:0]
Overflow
AUXR2.T0CKOE = 1
0
1
AUXR0.INT0H
62
MG74PG1A08 Data Sheet
MEGAWIN
Figure 14–11. Timer 1 in Clock Output Mode
Toggle
SYSCLK /12
0
SYSCLK
1
AUXR2.T1X12
TL1[7:0]
C/T=0
Overflow
PORTn for T1CKO
D
Q
Reload
TR1
GATE=0
TH1[7:0]
nINT1 Pin
0
AUXR2.T1CKOE = 1
1
AUXR0.INT1H
How to Program Timer 0/1 in Clock-out Mode
• Select AUXR2.T0X12 and AUXR0.T0XL bits decide the Timer 0 clock source. Or select T1X12 in AUXR2 register
to decide the Timer 1 clock source.
• Set T0CKOE/T1CKOE bit in AUXR2 register.
• Clear C/T bit in TMOD register.
• Determine the 8-bit reload value from the formula and enter it in the TH0/TH1 register.
• Enter the same reload value as the initial value in the TL0/TL1 register.
• Set TR0/TR1 bit in TCON register to start the Timer 0/1.
In the Clock-Out mode, Timer 0/1 rollovers will not generate an interrupt. This is similar to when Timer 1 is used as a
baud-rate generator. It is possible to use Timer 1 as a baud rate generator and a clock generator simultaneously.
Note, however, that the baud-rate and the clock-out frequency depend on the same overflow rate of Timer 1.
MEGAWIN
MG74PG1A08 Data Sheet
63
14.1.6. Timer0/1 Register
TCON: Timer/Counter Control Register
SFR Attribute = Normal Read/Write
SFR Address = 0x88
RESET = 0000-0000
7
6
5
4
3
TF1
TR1
TF0
TR0
IE1
R/W
R/W
R/W
R/W
R/W
2
IT1
1
IE0
0
IT0
R/W
R/W
R/W
Bit 7: TF1, Timer 1 overflow flag.
0: Cleared by hardware when the processor vectors to the interrupt routine, or cleared by software.
1: Set by hardware on Timer/Counter 1 overflow, or set by software.
Bit 6: TR1, Timer 1 Run control bit.
0: Cleared by software to turn Timer/Counter 1 off.
1: Set by software to turn Timer/Counter 1 on.
Bit 5: TF0, Timer 0 overflow flag.
0: Cleared by hardware when the processor vectors to the interrupt routine, or cleared by software.
1: Set by hardware on Timer/Counter 0 overflow, or set by software.
Bit 4: TR0, Timer 0 Run control bit.
0: Cleared by software to turn Timer/Counter 0 off.
1: Set by software to turn Timer/Counter 0 on.
TMOD: Timer/Counter Mode Control Register
SFR Attribute = Normal Read/Write
SFR Address = 0x89
RESET = 0000-0000
7
6
5
4
3
GATE
C/T
M1
M0
GATE
R/W
R/W
R/W
R/W
R/W
2
C/T
1
M1
0
M0
R/W
R/W
R/W
|----------------------- Timer1 -------------------------|--------------------------Timer0 ------------------------|
Bit 7/3: Gate, Gating control for Timer1/0.
0: Disable gating control for Timer1/0.
1: Enable gating control for Timer1/0. When set, Timer1/0 or Counter1/0 is enabled only when /INT1 or /INT0 pin is
high and TR1 or TR0 control bit is set.
Bit 6/2: C/T, Timer for Counter function selector.
0: Clear for Timer operation, input from internal system clock.
1: Set for Counter operation, input form T1 input pin.
Bit 5~4/1~0: Operating mode selection.
M1
M0
Operating Mode
0
0
8-bit PWM generator for Timer0 and Timer1
0
1
16-bit timer/counter for Timer0 and Timer1
1
0
8-bit timer/counter with automatic reload for Timer0 and Timer1
1
1 (Timer0)
TL0 is 8-bit timer/counter, TH0 is locked into 8-bit timer
1
1 (Timer1)
Timer/Counter1 Stopped
TL0: Timer Low 0 Register
SFR Attribute = Normal Read/Write
SFR Address = 0x8A
7
6
5
TL0.7
TL0.6
TL0.5
R/W
64
R/W
R/W
RESET = 0000-0000
4
3
2
TL0.4
TL0.3
TL02
R/W
R/W
R/W
MG74PG1A08 Data Sheet
1
TL0.1
0
TL0.0
R/W
R/W
MEGAWIN
TH0: Timer High 0 Register
SFR Attribute = Normal Read/Write
SFR Address = 0x8C
7
6
5
TH0.7
TH0.6
TH0.5
R/W
R/W
R/W
TL1: Timer Low 1 Register
SFR Attribute = Normal Read/Write
SFR Address = 0x8B
7
6
5
TL1.7
TL1.6
TL1.5
R/W
R/W
R/W
TH1: Timer High 1 Register
SFR Attribute = Normal Read/Write
SFR Address = 0x8D
7
6
5
TH1.7
TH1.6
TH1.5
R/W
R/W
R/W
AUXR2: Auxiliary Register 2
SFR Attribute = Normal Read/Write
SFR Address = 0xA3
7
6
5
UTIE
BTI
URM0X3
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
TH0.4
TH0.3
TH0.2
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
TL1.4
TL1.3
TL1.2
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
TH1.4
TH1.3
TH1.2
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
SM30
T1X12
T0X12
R/W
R/W
R/W
1
TH0.1
0
TH0.0
R/W
R/W
1
TL1.1
0
TL1.0
R/W
R/W
1
TH1.1
0
TH1.0
R/W
R/W
1
T1CKOE
0
T0CKOE
R/W
R/W
Bit 3: T1X12, Timer 1 clock source selector while C/T=0.
0: Clear to select SYSCLK/12.
1: Set to select SYSCLK as the clock source.
Bit 2: T0X12, Timer 0 clock source selector while C/T=0.
0: Clear to select SYSCLK/12.
1: Set to select SYSCLK as the clock source.
T0XL, T0X12
0 0
0 1
1 0
1 1
Timer 0 Clock Selection
SYSCLK/12
SYSCLK
SYSCLK/48
SYSCLK/192
Bit 1: T1CKOE, Timer 1 Clock Output Enable.
0: Disable Timer 1 clock output.
1: Enable Timer 1 clock output on P1.5.
Bit 0: T0CKOE, Timer 0 Clock Output Enable.
0: Disable Timer 0 clock output.
1: Enable Timer 0 clock output on P1.4.
MEGAWIN
MG74PG1A08 Data Sheet
65
15. Programmable Counter Array (PCA)
The MG74PG1A08 is equipped with a Programmable Counter Array (PCA), which provides more timing capabilities
with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and
improved accuracy.
15.1. PCA Overview
The PCA consists of a dedicated timer/counter which serves as the time base for an compare/capture modules.
Figure 15–1 shows a block diagram of the PCA. Notice that the PCA timer and module are all 16-bits. If an external
event is associated with a module, that function is shared with the corresponding Port 1 pin. If the module is not
using the port pin, the pin can still be used for standard I/O.
The module can be programmed in any one of the following modes:
- Rising and/or Falling Edge Capture
- Software Timer
- High Speed Output
- Pulse Width Modulator (PWM) Output
All of these modes will be discussed later in detail. However, let's first look at how to set up the PCA timer and
modules.
Figure 15–1. PCA Block Diagram
overflow
16 Bit
16 Bit
PCA Timer/Counter
Module 0
CEX0 (P1.2)
PWM0S (P1.3)
reload
16 bit Reload
Register
15.2. PCA Timer/Counter
The timer/counter for the PCA is an auto-reload 16-bit timer consisting of registers CH, CL (the high and low bytes of
the count values), CHRL, CLRL (the high and low bytes reload registers), as shown in Figure 15–2. CHRL and CLRL
are reloaded to CH and CL at each time overflow on CH+CL counter which can change the PCA cycle time for
variable PWM resolution, such as 16-bit PWM.
It is the common time base for all modules and its clock input can be selected from the following source:
- 1/12 the system clock frequency,
- 1/2 the system clock frequency,
- the Timer 0 overflow, which allows for a range of slower clock inputs to the timer.
- external clock input, 1-to-0 transitions, on ECI pin (P1.6).
- directly from the system clock (SYSCLK) frequency,
- directly from the MCK frequency,
Special Function Register CMOD contains the Count Pulse Select bits (CPS2, CPS1 and CPS0) to specify the PCA
timer input. This register also contains the ECF bit which enables an interrupt when the counter overflows. In
addition, the user has the option of turning off the PCA timer during Idle Mode by setting the Counter Idle bit (CIDL).
This can further reduce power consumption during Idle mode.
66
MG74PG1A08 Data Sheet
MEGAWIN
Figure 15–2. PCA Timer/Counter
SYSCLK/12
(0,0,0)
SYSCLK/2
(0,0,1)
Timer0 Overflow
(0,1,0)
External Input ECI (P1.6)
(0,1,1)
Reserved
(1,0,0)
SYSCLK/1
(1,0,1)
Reserved
(1,1,0)
MCK/1
(1,1,1)
To PCA Module 0
16-bits Up Counter
CH
8 bits
overflow
CL
8 bits
CF
PCA Interrupt
Control
Enable
reload
Toggle
CHRL
CPS[2:0] Indexed
CLRL
PTCKO
AUXR1.PTCKOE
PCON0.IDL
CF
CMOD: PCA Counter Mode Register
SFR Attribute = Normal Read/Write
SFR Address = 0xD9
7
6
5
CIDL
--R/W
W
W
CIDL
--
--
--
CPS2
CPS1
CPS0
ECF
CR
--
--
--
--
--
CCF0
CCON
RESET = 0xxx-0000
4
3
2
-CPS2
CPS1
W
R/W
R/W
CMOD
1
CPS0
0
ECF
R/W
R/W
Bit 7: CIDL, PCA counter Idle control.
0: Lets the PCA counter continue functioning during Idle mode.
1: Lets the PCA counter be gated off during Idle mode.
Bit 6~4: Reserved. Software must write “0” on these bits when CMOD is written.
Bit 3~1: CPS2-CPS0, PCA counter clock source select bits.
CPS2
CPS1
CPS0
PCA Clock Source
0
0
0
Internal clock, SYSCLK/12
0
0
1
Internal clock, SYSCLK/2
0
1
0
Timer 0 overflow
0
1
1
External clock at the ECI pin
1
0
0
Reserved
1
0
1
Internal clock, SYSCLK/1
1
1
0
Reserved
1
1
1
Internal clock, MCK/1
Bit 0: ECF, Enable PCA counter overflow interrupt.
0: Disables an interrupt when CF bit (in CCON register) is set.
1: Enables an interrupt when CF bit (in CCON register) is set.
The CCON register shown below contains the run control bit for the PCA and the flags for the PCA timer and each
module. To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this bit. The
CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the
CMOD register is set. The CF bit can only be cleared by software. CCF0 is the interrupt flags for module 0, and it set
by hardware when either a match or a capture occurs. These flags also can only be cleared by software. The PCA
interrupt system is shown Figure 15–3.
MEGAWIN
MG74PG1A08 Data Sheet
67
CCON: PCA Counter Control Register
SFR Attribute = Normal Read/Write
SFR Address = 0xD8
7
6
5
CF
CR
-R/W
R/W
W
RESET = 00xx-xxx0
4
3
---
2
--
1
--
0
CCF0
W
W
W
R/W
W
Bit 7: CF, PCA Counter Overflow flag.
0: Only be cleared by software.
1: Set by hardware when the counter rolls over. CF flag can generate an interrupt if bit ECF in CMOD is set. CF may
be set by either hardware or software.
Bit 6: CR, PCA Counter Run control bit.
0: Must be cleared by software to turn the PCA counter off.
1: Set by software to turn the PCA counter on.
Bit 5~1: Reserved. Software must write “0” on these bits when CCON is written.
Bit 0: CCF0, PCA Module 0 interrupt flag.
0: Must be cleared by software.
1: Set by hardware when a match or capture occurs.
Figure 15–3. PCA Interrupt System
ECF
CF
CR
--
--
--
--
--
CCF0
CCON
(CMOD.0)
PCA Timer/Counter
XPIE1.EPCA IE.EXPIE1
IE.EA
To Interrupt
Priority Processing
Module 0
ECCF0
(CCAPM0.0)
68
MG74PG1A08 Data Sheet
MEGAWIN
CL: PCA Counter Low byte Register
SFR Attribute = Normal Read/Write
SFR Address = 0xE9
7
6
5
CL.7
CL.6
CL.5
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
CL.4
CL.3
CL.2
R/W
R/W
R/W
CH: PCA Counter High byte Register
SFR Attribute = Normal Read/Write
SFR Address = 0xF9
RESET = 0000-0000
7
6
5
4
3
2
CH.7
CH.6
CH.5
CH.4
CH.3
CH.2
R/W
R/W
R/W
R/W
R/W
R/W
CLRL: PCA Counter Low byte Reload Register
SFR Attribute = Normal Read/Write
SFR Address = 0xCE
RESET = 0000-0000
7
6
5
4
3
2
CLRL.7
CLRL.6
CLRL.5
CLRL.4
CLRL.3
CLRL.2
R/W
R/W
R/W
R/W
R/W
R/W
CHRL: PCA Counter High byte Reload Register
SFR Attribute = Normal Read/Write
SFR Address = 0xCF
RESET = 0000-0000
7
6
5
4
3
2
CHRL.7
CHRL.6
CHRL.5
CHRL.4
CHRL.3
CHRL.2
R/W
MEGAWIN
R/W
R/W
R/W
R/W
R/W
MG74PG1A08 Data Sheet
1
CL.1
0
CL.0
R/W
R/W
1
CH.1
0
CH.0
R/W
R/W
1
CLRL.1
0
CLRL.0
R/W
R/W
1
CHRL.1
0
CHRL.0
R/W
R/W
69
15.3. Compare/Capture Modules
The compare/capture module has a mode register called CCAPM0 to select which function it will perform. Note the
ECCF0 bit which enables an interrupt to occur when a module's interrupt flag is set.
CCAPM0: PCA Module 0 Compare/Capture Register
SFR Attribute = Normal Read/Write
SFR Address = 0xDA
RESET = 0000-0000
7
6
5
4
3
P0INV
ECOM0
CAPP0
CAPN0
MAT0
R/W
R/W
R/W
R/W
R/W
2
TOG0
1
PWM0
0
ECCF0
R/W
R/W
R/W
Bit 7: Invert PWM output on CEX0.
0: Non-inverted PWM output.
1: Inverted PWM output.
Bit 6: ECOM0, Enable Comparator
0: Disable the digital comparator function.
1: Enables the digital comparator function.
Bit 5: CAPP0, Capture Positive enabled.
0: Disable the PCA capture function on CEX0 positive edge detected.
1: Enable the PCA capture function on CEX0 positive edge detected.
Bit 4: CAPN0, Capture Negative enabled.
0: Disable the PCA capture function on CEX0 positive edge detected.
1: Enable the PCA capture function on CEX0 negative edge detected.
Bit 3: MAT0, Match control.
0: Disable the digital comparator match event to set CCF0.
1: A match of the PCA counter with this module’s compare/capture register causes the CCF0 bit in CCON to be set.
If this bit is set with PWM0, it will select the module to 16-bit PWM mode.
Bit 2: TOG0, Toggle control.
0: Disable the digital comparator match event to toggle CEX0.
1: A match of the PCA counter with this module’s compare/capture register causes the CEX0 pin to toggle. If this bit
is set with PWM0, it will select the module to double channel 8-bit PWM mode.
Bit 1: PWM0, PWM control.
0: Disable the PWM mode in PCA module.
1: Enable the PWM function and cause CEX0 pin to be used as a pulse width modulated output.
Bit 0: ECCF0, Enable CCF0 interrupt.
0: Disable compare/capture flag CCF0 in the CCON register to generate an interrupt.
1: Enable compare/capture flag CCF0 in the CCON register to generate an interrupt.
Note: The bits CAPN0 (CCAPM0.4) and CAPP0 (CCAPM0.5) determine the edge on which a capture input will be
active. If both bits are set, both edges will be enabled and a capture will occur for either transition.
The module also has a pair of 8-bit compare/capture registers (CCAP0H, CCAP0L) associated with it. These
registers are used to store the time when a capture event occurred or when a compare event should occur.
70
MG74PG1A08 Data Sheet
MEGAWIN
15.4. Operation Modes of the PCA
Table 15–1 shows the CCAPM0 register settings for the various PCA functions.
Table 15–1. PCA Module 0 Modes
ECOM0 CAPP0 CAPN0 MAT0
TOG0 PWM0 ECCF0
Module Function
0
0
0
0
0
0
0
No operation
0
1
0
0
0
0
X
16-bit capture by a positive-edge trigger on CEX0
0
0
1
0
0
0
X
16-bit capture by a negative-edge trigger on CEX0
0
1
1
0
0
0
X
16-bit capture by a transition on CEX0
1
0
0
1
0
0
X
16-bit Software Timer
1
0
0
1
1
0
X
16-bit High Speed Output
1
0
0
0
0
1
X
8-bit Pulse Width Modulator (8-bit PWM)
1
0
0
1
0
1
X
16-bit PWM, un-buffered
1
0
0
0
1
1
X
Double Channel 8-bit PWM, un-buffered
15.4.1. Capture Mode
To use one of the PCA modules in the capture mode, either one or both of the bits CAPN0 and CAPP0 for that
module must be set. The external CEX0 input for the module is sampled for a transition. When a valid transition
occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module’s capture
registers (CCAP0L and CCAP0H). If the CCF0 and the ECCF0 bits for the module are both set, an interrupt will be
generated.
Figure 15–4. PCA Capture Mode (n=0)
CR
CF
--
--
--
CCF0
--
--
CCON
PCA Interrupt
(To CCFn)
CCAPnH
CCAPnL
Capture
CEXn
PCA Timer/Counter
CH
CL
overflow
reload
CCAPMn
n= 0
PnINV
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
0
0
1/0
1/0
0
0
0
0/1
CAPPn or CAPNn =1
MEGAWIN
MG74PG1A08 Data Sheet
CHRL
CLRL
71
15.4.2. 16-bit Software Timer Mode
The PCA modules can be used as software timers by setting both the ECOM0 and MAT0 bits in the module’s
CCAPM0 register. The PCA timer will be compared to the module’s capture registers, and when a match occurs an
interrupt will occur if the CCF0 and the ECCF0 bits for the module are both set.
Figure 15–5. PCA Software Timer Mode (n=0)
Write to
CCAPnL
CF
CR
--
CCAPnH
0
--
--
--
CCF0
CCON
Reset
Write to
CCAPnH
1
--
Enable
CCAPnL
(To CCFn)
Match
16-Bit Comparator
PCA Interrupt
PCA Timer/Counter
CH
CL
overflow
reload
CHRL
72
CLRL
PnINV
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
0
1
0
0
1
0
0
0/1
MG74PG1A08 Data Sheet
CCAPMn, n= 0
MEGAWIN
15.4.3. High Speed Output Mode
In this mode the CEX0 output associated with the PCA module will toggle each time a match occurs between the
PCA counter and the module’s capture registers. To activate this mode, the TOG0, MAT0 and ECOM0 bits in the
module’s CCAPM0 register must be set.
Figure 15–6. PCA High Speed Output Mode (n=0)
Write to
CCAPnL
CF
CR
--
Write to
CCAPnH
0
--
CCF0
--
--
CCAPnL
CCAPnH
1
--
CCON
Reset
Enable
(To CCFn)
Match
16-Bit Comparator
PCA Interrupt
Toggle
PCA Timer/Counter
CH
CL
CEXn
overflow
reload
CLRL
CHRL
MEGAWIN
PnINV
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
0
1
0
0
1
1
0
0/1
MG74PG1A08 Data Sheet
CCAPMn, n= 0
73
15.4.4. 8-bit PWM Mode (Buffered 8-bit PWM)
The PCA module can be used as 8-bit buffered PWM output. The frequency of the PWM output depends on the
clock source for the PCA timer and the PWM resolution setting. Software may modify the value of CHRL and CLRL
to decrease the PWM resolution, such as 7-bit PWM. To activate this mode, the PWM0 and ECOM0 bits in the
module’s CCAPM0 register must be set.
In this PWM mode, the duty cycle of the module is determined by the module’s capture register CCAP0L. When the
8-bit value of { CL } is less than the 8-bit value of { CCAP0L } the output will be low, and if equal to or greater than the
output will be high.
When CL overflows from 0xFF to 0x00, { CCAP0L } is reloaded with the value of { CCAP0H }. This allows updating
the PWM without glitches. The PWM0 and ECOM0 bits in the module’s CCAPM0 register must be set to enable the
8-bit PWM mode.
Using the 8-bit comparison, the duty cycle of the output can be improved to really start from 1/256, and up to 100%.
The formula for the duty cycle is:
Duty Cycle = 1 – { CCAP0H } / 256.
For examples,
a. If CCAP0H= 0x00, the duty cycle is 100%.
b. If CCAP0H= 0x40, the duty cycle is 75%.
c. If CCAP0H= 0xC0, the duty cycle is 25%.
d. If CCAP0H= 0xFF, the duty cycle is 1/256.
Software can program the value of CHRL and CLRL, reload registers of CH and CL, to modify the PWM resolution
less than 256. Please refer Figure 15–7 to find the PWM structure.
Figure 15–7. PCA 8-bit PWM Mode (n=0)
8 Bits
CCAPnH
Port I/O
8 Bits
CCAPnL
8-Bit Comparator
Q
Match
S
R
Enable
PCA Timer/Counter
CH
CL
Q
PWMnH
0
PWMnL
1
0
1
CEXn Output
(PWMn)
Q
overflow
PnINV
PWMn
reload
CHRL
74
CLRL
PnINV
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
0/1
1
0
0
0
0
1
0
CCAPMn, n= 0
MG74PG1A08 Data Sheet
MEGAWIN
15.4.5. 16-bit PWM Mode (Un-Buffered)
The PCA module can be used as 16-bit un-buffered PWM output. The frequency of the PWM output depends on the
clock source for the PCA timer and the PWM resolution setting. Software may modify the value of CHRL and CLRL
to decrease the PWM resolution, such as 10-bit PWM. To activate this mode, the MAT0, PWM0 and ECOM0 bits in
the module’s CCAPM0 register must be set.
In this PWM mode, the duty cycle of the module is determined by the module’s capture register CCAP0H and
CCAP0L. When the 16-bit value of { CH, CL] } is less than the 16-bit value of { CCAP0H, CCAP0L } the output will be
low, and if equal to or greater than the output will be high.
Using the 16-bit comparison, the duty cycle of the output can be improved to really start from 1/65536, and up to
100%. The formula for the duty cycle is:
Duty Cycle = 1 – { CCAP0H, CCAP0L } / 65536.
For examples,
a. If { CCAP0H, CCAP0L }= 0x0000, the duty cycle is 100%.
b. If { CCAP0H, CCAP0L }=0x4000, the duty cycle is 75%.
c. If { CCAP0H, CCAP0L }=0xC000, the duty cycle is 25%.
d. If { CCAP0H, CCAP0L }=0xFFFF, the duty cycle is 1/65536.
Software can program the value of CHRL and CLRL, reload registers of CH and CL, to modify the PWM resolution
less than 65536. Please refer Figure 15–8 to find the PWM structure.
Figure 15–8. PCA 16-bit PWM Mode (n=0)
Port I/O
16 Bits
CCAPnL
CCAPnH
Q
Match
16-Bit Comparator
S
Q
PWMnH
PWMnL
R
PCA Timer/Counter
Enable
0
1
0
1
CEXn Output
(PWMn)
Q
16 Bits
CH
CL
overflow
PnINV
PWMn
reload
CHRL
CLRL
PnINV
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
0/1
1
0
0
1
0
1
0
MEGAWIN
CCAPMn, n= 0
MG74PG1A08 Data Sheet
75
15.4.6. Double Channel PWM Mode (Un-Buffered 8-bit PWM)
The PCA module can be used as double channel un-buffered 8-bit PWM output, PWM0 and PWM0S. The frequency
of the PWM output depends on the clock source for the PCA timer and the PWM resolution setting. Software may
modify the value of CHRL and CLRL to decrease the PWM resolution, such as 8-bit PWM. To activate this mode, the
TOG0, PWM0 and ECOM0 bits in the module’s CCAPM0 register must be set.
In this PWM mode, there are two 8-bit comparators to execute the PWM outputs. The primary PWM output channel,
PWM0, is the comparison result of CL and CCAP0L. The secondary PWM output channel, PWM0S, is the
comparison result of CL and CCAP0H. Both of the PWM generators are similar to 8-bit buffered PWM mode except
the un-buffered PWM structure. Please refer Figure 15–9 to find the PWM structure.
Using the 8-bit comparison, the duty cycle of the output can be improved to really start from 1/256, and up to 100%.
The formula for the duty cycle is:
PWN0 Duty Cycle = 1 – { [CCAP0L] } / 256.
PWN0S Duty Cycle = 1 – { [CCAP0H] } / 256.
Figure 15–9. PCA Double Channel PWM Mode (n=0)
Port I/O
Q
8 Bits
CCAPnH
Match
S
Q
R
PWMnH
0
PWMnL
1
0
PWM0S Output
1
Q
8-Bit Comparator 1
CAPNn
CAPPn
8 Bits
CCAPnL
Port I/O
Q
8-Bit Comparator 0
Match
S
Enable
Q
PCA Timer/Counter
CH
CL
R
overflow
PWMnH
0
PWMnL
1
0
1
CEXn Output
(PWM0)
Q
PnINV
reload
PWMn
CLRL
CHRL
76
PnINV
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
0/1
1
0/1
0/1
0
1
1
0
CCAPMn, n= 0
MG74PG1A08 Data Sheet
MEGAWIN
16. Serial Port 0 (UART0)
The serial port 0 of MG74PG1A08 support full-duplex transmission, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously
received byte has been read from the register. However, if the first byte still hasn’t been read by the time reception of
the second byte is complete, one of the bytes will be lost. The serial port 0 receive and transmit registers are both
accessed at special function register S0BUF. Writing to S0BUF loads the transmit register, and reading from S0BUF
accesses a physically separate receive register.
The serial port 0 can operate in 4 modes: Mode 0 provides synchronous communication while Modes 1, 2, and 3
provide asynchronous communication. The asynchronous communication operates as a full-duplex Universal
Asynchronous Receiver and Transmitter (UART), which can transmit and receive simultaneously and at different
baud rates.
Mode 0: 8 data bits (LSB first) are transmitted or received through RXD0 (P3.0). TXD0 (P3.1) always outputs the
shift clock. The baud rate can be selected to 1/12 or 1/4 the system clock frequency by URM0X3 setting in AUXR2
register. In MG74PG1A08, the clock polarity of serial port Mode 0 can be selected by software. It is decided by P3.1
state before serial data shift in or shift out. Figure 16–4 and Figure 16–5 show the clock polarity waveform in Mode 0.
Mode 1: 10 bits are transmitted through TXD0 or received through RXD0. The frame data includes a start bit (0), 8
data bits (LSB first), and a stop bit (1), as shown in Figure 16–1. On receive, the stop bit would be loaded into RB80
in S0CON register. The baud rate is variable.
Figure 16–1. Mode 1 Data Frame
Mode 1
8-bit data
Start
D0
D1
D2
D3
D4
D7
D6
D5
Stop
Mode 2: 11 bits are transmitted through TXD0 or received through RXD0. The frame data includes a start bit (0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (1), as shown in Figure 16–2. On Transmit, the 9th
data bit comes from TB80 in S0CON register can be assigned the value of 0 or 1. On receive, the 9th data bit would
be loaded into RB80 in S0CON register, while the stop bit is ignored. The baud rate can be configured to 1/32 or
1/64 the system clock frequency.
Figure 16–2. Mode 2, 3 Data Frame
Mode 2, 3
9-bit data
Start
D0
D1
D2
D3
D4
D5
D6
D7
D8
Stop
Mode 3: Mode 3 is the same as Mode 2 except the baud rate is variable.
In all four modes, transmission is initiated by any instruction that uses S0BUF as a destination register. In Mode 0,
reception is initiated by the condition RI0=0 and REN0=1. In the other modes, reception is initiated by the incoming
start bit with 1-to-0 transition if REN0=1.
In addition to the standard operation, the UART0 can perform framing error detection by looking for missing stop bits,
and automatic address recognition.
MEGAWIN
MG74PG1A08 Data Sheet
77
16.1. Serial Port 0 Mode 0
Serial data enters and exits through RXD0. TXD0 outputs the shift clock. 8 bits are transmitted/received: 8 data bits
(LSB first). The shift clock source can be selected to 1/12 or 1/4 the system clock frequency by URM0X3 setting in
AUXR2 register. Figure 16–3 shows a simplified functional diagram of the serial port 0 in Mode 0.
Transmission is initiated by any instruction that uses S0BUF as a destination register. The “write to S0BUF” signal
triggers the UART0 engine to start the transmission. The data in the S0BUF would be shifted into the RXD0 (P3.0)
pin by each raising edge shift clock on the TXD0 (P3.1) pin. After eight raising edge of shift clocks passing, TI0
would be asserted by hardware to indicate the end of transmission. Figure 16–4 shows the transmission waveform
in Mode 0.
Reception is initiated by the condition REN0=1 and RI0=0. At the next instruction cycle, the Serial Port 0 Controller
writes the bits 11111110 to the receive shift register, and in the next clock phase activates Receive.
Receive enables Shift Clock which directly comes from RX Clock to the alternate output function of P3.1 pin. When
Receive is active, the contents on the RXD0 (P3.0) pin would be sampled and shifted into shift register by falling
edge of shift clock. After eight falling edge of shift clock, RI0 would be asserted by hardware to indicate the end of
reception. Figure 16–5 shows the reception waveform in Mode 0. The clock polarity can be selected by software
setting on P3.1 data latch before serial transfer shifted. If P3.1 is set to logic high, the clock polarity is same as
standard 8051. If P3.1 data latch is cleared to logic low, the clock polarity is inverted to standard 8051 UART Mode
0.
Figure 16–3. Serial Port 0 Mode 0
SYSCLK
80C51 Internal BUS
12
“0”
4
Write
S0BUF
“1”
URM0X3
RXD0 Alternated
for Input/output
Function
TXBUF
TX Clock
RX Clock
RXBUF
UART engine
REN0
TXD0 Alternated
for output
Function
Shift-clock
RXSTART
RI0
Serial Port 0 Interrupt
RI0
TI0
BTI
System Flag Interrupt
UTIE
Read
S0BUF
ESF
80C51 Internal BUS
78
MG74PG1A08 Data Sheet
MEGAWIN
Figure 16–4. Mode 0 Transmission Waveform
Write to
S0BUF
P3.1/TXD0
Software set/clear P3.1 to initial clock polarity
P3.1/TXD0
P3.0/RXD0
D0
D1
D2
D3
D4
D5
D6
D7
TI0
RI0
Figure 16–5. Mode 0 Reception Waveform
Write to
S0CON
Set REN0, Clear RI0
P3.1/TXD0
Software set/clear P3.1 to initial clock polarity
P3.1/TXD0
P3.0/RXD0
D0
D1
D2
D3
D4
D5
D6
D7
TI0
RI0
MEGAWIN
MG74PG1A08 Data Sheet
79
16.2. Serial Port 0 Mode 1
10 bits are transmitted through TXD0, or received through RXD0: a start bit (0), 8 data bits (LSB first), and a stop bit
(1). On receive, the stop bit goes into RB80 in S0CON. The baud rate is determined by the Timer 1 overflow rate.
Figure 16–1 shows the data frame in Mode 1 and Figure 16–6 shows a simplified functional diagram of the serial
port in Mode 1.
Transmission is initiated by any instruction that uses S0BUF as a destination register. The “write to S0BUF” signal
requests the UART0 engine to start the transmission. After receiving a transmission request, the UART0 engine
would start the transmission at the raising edge of TX Clock. The data in the S0BUF would be serial output on the
TXD0 pin with the data frame as shown in Figure 16–1 and data width depend on TX Clock. After the end of 8th data
transmission, TI0 would be asserted by hardware to indicate the end of data transmission.
Reception is initiated when Serial Port 0 Controller detected 1-to-0 transition at RXD0 sampled by RCK. The data on
the RXD0 pin would be sampled by Bit Detector in Serial Port 0 Controller. After the end of STOP-bit reception, RI0
would be asserted by hardware to indicate the end of data reception and load STOP-bit into RB80 in S0CON
register.
Figure 16–6. Serial Port 0 Mode 1, 2, 3
Mode 2
clock source
SYSCLK/2
Mode 1, 3
clock source
Timer 1
Overflow
80C51 Internal BUS
Write
S0BUF
2
“0”
2
“1”
“0”
SM00
“1”
SM10
SMOD1
TXBUF
TxD0
RXBUF
RxD0
TB80
RI0
1
16
TX Clock
Serial Port 0
Interrupt
TI0
UART engine
0
BTI
System Flag
Interrupt
SM10
UTIE
1
RCK
16
STOP-Bit
RX Clock
ESF
0
RB80
1
0
9th-Bit
SM10
SM00
Read
S0BUF
80C51 Internal BUS
80
MG74PG1A08 Data Sheet
MEGAWIN
16.3. Serial Port 0 Mode 2 and Mode 3
11 bits are transmitted through TXD0, or received through RXD0: a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB80) can be assigned the value of 0 or
1. On receive, the 9th data bit goes into RB80 in S0CON. The baud rate is programmable to select one of 1/16, 1/32
or 1/64 the system clock frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1.
Figure 16–2 shows the data frame in Mode 2 and Mode 3. Figure 16–6 shows a functional diagram of the serial port
in Mode 2 and Mode 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode
1 only in the 9th bit of the transmit shift register.
The “write to S0BUF” signal requests the Serial Port 0 Controller to load TB80 into the 9th bit position of the transmit
shit register and starts the transmission. After receiving a transmission request, the UART0 engine would start the
transmission at the raising edge of TX Clock. The data in the S0BUF would be serial output on the TXD0 pin with the
data frame as shown in Figure 16–2 and data width depend on TX Clock. After the end of 9th data transmission, TI0
would be asserted by hardware to indicate the end of data transmission.
Reception is initiated when the UART0 engine detected 1-to-0 transition at RXD0 sampled by RCK. The data on the
RXD0 pin would be sampled by Bit Detector in UART0 engine. After the end of 9th data bit reception, RI0 would be
asserted by hardware to indicate the end of data reception and load the 9th data bit into RB80 in S0CON register.
In all four modes, transmission is initiated by any instruction that use S0BUF as a destination register. Reception is
initiated in mode 0 by the condition RI0 = 0 and REN0 = 1. Reception is initiated in the other modes by the incoming
start bit with 1-to-0 transition if REN0=1.
16.4. Frame Error Detection
When used for framing error detection, the UART0 looks for missing stop bits in the communication. A missing stop
bit will set the FE bit in the S0CON register. The FE bit shares the S0CON.7 bit with SM00 and the function of
S0CON.7 is determined by SMOD0 bit (PCON0.6). If SMOD0 is set then S0CON.7 functions as FE. S0CON.7
functions as SM00 when SMOD0 is cleared. When S0CON.7 functions as FE, it can only be cleared by firmware.
Refer to Figure 16–7.
Figure 16–7. UART0 Frame Error Detection
9-bit data
Start
D0
D1
D2
D3
D4
D5
D6
D7
D8
Stop
SET FE bit if STOP=0
SM00 to UART mode control
PCON0.SMOD0
S0CON
MEGAWIN
SM00/
FE
SM10
SM20
REN0
TB80
RB80
TI0
MG74PG1A08 Data Sheet
RI0
81
16.5. Baud Rate Setting
Bits T1X12 and URM0X3 in AUXR2 register provide a new option for the baud rate setting, as listed below.
16.5.1. Baud Rate in Mode 0
Figure 16–8. Mode 0 baud rate equation
Mode 0 Baud Rate =
FSYSCLK
n
; n=12, if URM0X3=0
; n=4, if URM0X3=1
Note:
If URM0X3=0, the baud rate formula is as same as standard 8051.
Table 16–1. Serial Port Mode 0 baud rate example
SYSCLK URM0X3
Mode 0 Baud Rate
12MHz
0
1M bps
12MHz
1
3M bps
24MHz
0
2M bps
24MHz
1
6M bps
16.5.2. Baud Rate in Mode 2
Figure 16–9. Mode 2 baud rate equation
Mode 2 Baud Rate =
2SMOD1 X 2(SMOD2 X 2)
64
X FSYSCLK
Note:
If SMOD2=0, the baud rate formula is as same as standard 8051. If SMOD2=1, there is an enhanced function
for baud rate setting. Table 16–2 defines the Baud Rate setting with SMOD2 factor in Mode 2 baud rate
generator.
Table 16–2. Serial Port Mode 2 baud rate example
SYSCLK
SMOD2 SMOD1
Mode 2 Baud Rate
12MHz
0
0
187.5K bps
12MHz
0
1
375K bps
12MHz
1
0
750K bps
12MHz
1
1
--
82
Note
Default Baud Rate, standard
Double Baud Rate, standard
Double Baud Rate X2, enhanced
Reserved
MG74PG1A08 Data Sheet
MEGAWIN
16.5.3. Baud Rate in Mode 1 & 3
Using Timer 1 as the Baud Rate Generator
Figure 16–10. Mode 1/3 baud rate equation
2SMOD1 X 2(SMOD2 X 2)
Mode 1, 3 Baud Rate =
or =
FSYSCLK
X
32
2SMOD1 X 2(SMOD2 X 2)
32
12 x (256 – TH1)
FSYSCLK
X
1 x (256 – TH1)
; T1X12=0
; T1X12=1
Note:
If SMOD2=0, T1X12=0, the baud rate formula is as same as standard 8051. If SMOD2=1, there is an enhanced
function for baud rate setting. Table 16–3 defines the Baud Rate setting with SMOD2 factor in Timer 1 baud rate
generator.
Table 16–3. SMOD2 application criteria in Mode 1 & Mode 3 using Timer 1
SMOD2
SMOD1
0
0
1
1
0
1
0
1
Baud Rate
Note
Default Baud Rate
Double Baud Rate
Double Baud Rate X2
--
Standard function
Standard function
Enhanced function
Reserved.
Recommended Max.
Receive Error (%)
± 3%
± 3%
± 2%
--
Table 16–4 ~ Table 16–7 list various commonly used baud rates and how they can be obtained from Timer 1 in its
8-Bit Auto-Reload Mode.
Table 16–4. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=12.0MHz and SMOD2 = 0
TH1, the Reload Value
T1X12=0
Baud Rate
1200
2400
4800
9600
14400
19200
28800
38400
57600
115200
MEGAWIN
T1X12=1
SMOD1=0
SMOD1=1
Error
SMOD1=0
SMOD1=1
Error
230
243
---------
204
230
243
--------
0.16%
0.16%
0.16%
--------
-100
178
217
230
-243
246
---
--100
178
204
217
230
236
243
--
-0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
2.34%
0.16%
--
MG74PG1A08 Data Sheet
83
Table 16–5. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=12.0MHz and SMOD2 = 1
TH1, the Reload Value
T1X12=0
Baud Rate
115200
230400
T1X12=1
SMOD1=0
SMOD1=1
Error
SMOD1=0
SMOD1=1
Error
---
---
---
243
--
---
0.16%
--
Table 16–6. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=24.0MHz and SMOD2 = 0
TH1, the Reload Value
T1X12=0
Baud Rate
1200
2400
4800
9600
14400
19200
28800
38400
57600
115200
T1X12=1
SMOD1=0
SMOD1=1
Error
SMOD1=0
SMOD1=1
Error
204
230
243
--------
152
204
230
243
-------
0.16%
0.16%
0.16%
0.16%
-------
--100
178
204
217
230
-243
--
---100
152
178
204
217
230
243
--0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
Table 16–7. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=24.0MHz and SMOD2 = 1
TH1, the Reload Value
T1X12=0
Baud Rate
230400
460800
84
T1X12=1
SMOD1=0
SMOD1=1
Error
SMOD1=0
SMOD1=1
Error
---
---
---
243
--
---
0.16%
--
MG74PG1A08 Data Sheet
MEGAWIN
16.6. Serial Port 0 Mode 4 (SPI Master)
The Serial Port 0 of MG74PG1A08 is embedded an additional Mode 4 to support SPI master engine. The Mode 4 is
selected by SM30, SM00 and SM10. Table 16–8 shows the serial port 0 mode definition in MG74PG1A08.
Table 16–8. Serial Port 0 Mode Selection
SM30
SM00
SM10
Mode
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Description
shift register
8-bit UART
9-bit UART
9-bit UART
SPI Master
Reserved
SPI Slave
Reserved
Baud Rate
SYSCLK/12 or SYSCLK/4
variable
SYSCLK/64, /32
variable
SYSCLK/12 or SYSCLK/4
Reserved
Up to SYSCLK/8
Reserved
URM0X3 also controls the SPI transfer speed. If URM0X3 = 0, the SPI clock frequency is SYSCLK/12. If URM0X3 =
1, the SPI clock frequency is SYSCLK/4.
The SPI master in MG74PG1A08 uses the TXD0 as SPICLK, RXD0 as MOSI, and SOMI as MISO. nSS is selected
by MCU software on other port pin. Figure 16–11 shows the SPI connection. It also can support the configuration for
multiple slaves communication in Figure 16–12.
Figure 16–11. Serial Port 0 Mode 4, Single Master and Single Slave configuration
MCU Serial Port 0
Mode 4
(Master)
TXD0
SPICLK
RXD0
MOSI
SOMI
MISO
Port Pin
SPI
Slave
nSS
Figure 16–12. Serial Port 0 Mode 4, Single Master and Multiple Slaves configuration
MCU Serial Port 0
TXD0
SPICLK
RXD0
MOSI
SOMI
MISO
Port Pin 1
Slave #1
nSS
Mode 4
(Master)
SPICLK
MOSI
MISO
Port Pin 2
MEGAWIN
Slave #2
nSS
MG74PG1A08 Data Sheet
85
The SPI master satisfies the transfer with the full function SPI module of Megawin MG82/84 series MCU with CPOL,
CPHA and DORD selection. For CPOL and CPHA condition, MG74PG1A08 uses an easy way by initialize SPI clock
(TXD0/P3.1) polarity to fit them. Table 16–9 shows the serial port 0 Mode 4 mapping with the four SPI operating
mode.
Table 16–9. SPI mode mapping with Serial Port 0 Mode 4 configuration
SPI Mode CPOL CPHA Configuration in MG74PG1A08
0
0
0
Clear P3.1 to “0”
1
0
1
Clear P3.1 to “0”
2
1
0
Set P3.1 to “0”
3
1
1
Set P3.1 to “0”
For bit order control (DORD) on SPI serial transfer, MG74PG1A08 provides a SFR, BOREV, to reverse the bit order
by software program. After MCU writing a MSB first data format to BOREV, MCU will get the LSB first data by
reading BOREV back. The SPI master engine in serial port 0 Mode 4 is the LSB first transferred which is same as
serial port 0 Mode 0. To support SPI MSB first shift, MCU must use the BOREV write/read operation to reverse the
data bit order for SPI IN/OUT transmission. Figure 16–13 shows the BOREV configuration.
Figure 16–13. SFR BOREV read/write configuration
MCU Write
BOREV
D7
D6
D5
D4
D3
D2
D1
D0
D0
D1
D2
D3
D4
D5
D6
D7
MCU Read
Transmission is initiated by any instruction that uses S0BUF as a destination register. The “write to S0BUF” signal
triggers the UART0 engine to start the transmission. The data in the S0BUF would be shifted into the RXD0 pin as
MOSI serial data. The SPI shift clock is built on the TXD0 pin for SPICLK output. After eight raising edge of shift
clocks passing, TI0 would be asserted by hardware to indicate the end of transmission. And the contents on the
SOMI pin would be sampled and shifted into shift register. Then, “read S0BUF” can get the SPI shift-in data. Figure
16–14 shows the transmission waveform in Mode 0. RI0 will not be asserted in Mode 4.
Figure 16–14. Serial Port 0 Mode 4 transmission waveform (n=0)
Write to SnBUF
TXDn
(SPICLK)
Software set/clear TXDn assigned port pin to initial clock polarity
RXDn
(MOSI)
D0
D1
D2
D3
D4
D5
D6
D7
SnMI
(MISO)
D0
D1
D2
D3
D4
D5
D6
D7
TIn
RIn
86
MG74PG1A08 Data Sheet
MEGAWIN
16.7. Serial Port 0 Mode 6 (SPI Slave)
The serial port 0 mode 6 in MG74PG1A08 supports SPI slave mode. The Mode 6 is selected by SM30, SM00 and
SM10. Table 16–10 shows the serial port 0 mode definition in MG74PG1A08.
Table 16–10. Serial Port 0 Mode Selection
SM30
SM00
SM10
Mode
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Description
shift register
8-bit UART
9-bit UART
9-bit UART
SPI Master
Reserved
SPI Slave
Reserved
Baud Rate
SYSCLK/12 or SYSCLK/4
variable
SYSCLK/64, /32
variable
SYSCLK/12 or SYSCLK/4
Reserved
Up to SYSCLK/8
Reserved
The SPI slave in MG74PG1A08 uses the TXD0 as SPICLK, RXD0 as MOSI, and a dedicated MISO and nSS.
Figure 16–15 shows the SPI connection for multiple slave MCU communication.
The SPI slave engine of serial port 0 mode 6 serves the maximum SPI clock rate up to SYSCLK/8. If SYSCLK =
12MHz, MG74PG1A08 can receive the maximum frequency of SPICLK is 1.5MHz. This mode also supports the
CPHA and SSIG options and the control bits are located on SADEN.1 and SADEN.0. But, there is no CPOL option
in this chip. MG74PG1A08 builds an automatic detection scheme on SPICLK clock polarity in the SPI slave engine.
When CPHA is 0, SSIG must be 0 and nSS pin must be negated and reasserted between each successive serial
byte transfer. Note the S0BUF register cannot be written while nSS pin is active (low), and the operation is
undefined if CPHA is 0 and SSIG is 1.
When CPHA is 1, SSIG may be 0 or 1. If SSIG=0, the nSS pin may remain active low between successive transfers
(can be tied low at all times). This format is sometimes preferred for use in systems having a single fixed master and
a single slave configuration.
Figure 16–15. Serial Port 0 Mode 6, Single Master and Multiple Slaves configuration
MCU0 Serial Port
SPICLK
MOSI
SPICLK (TXD0)
MOSI (RXD0)
MISO
MISO
nSS0
nSS
SPI
Master
Mode 6
(Slave)
MCU1 Serial Port
SPICLK (TXD0)
MOSI (RXD0)
MISO
nSS1
MEGAWIN
Mode 6
(Slave)
nSS
MG74PG1A08 Data Sheet
87
16.8. Serial Port 0 Register
All the four operation modes of the serial port 0 are the same as those of the standard 8051 except the baud rate
setting. Two registers, PCON0 and AUXR2, are related to the baud rate setting:
S0CON: Serial port 0 Control Register
SFR Attribute = Normal Read/Write
SFR Address = 0x98
RESET = 0000-0000
7
6
5
4
3
2
SM00/FE
SM10
SM20
REN0
TB80
RB80
R/W
R/W
R/W
R/W
R/W
R/W
1
TI0
0
RI0
R/W
R/W
Bit 7: FE, Framing Error bit. The SMOD0 bit must be set to enable access to the FE bit.
0: The FE bit is not cleared by valid frames but should be cleared by software.
1: This bit is set by the receiver when an invalid stop bit is detected.
Bit 7: Serial port 0 mode bit 0, (SMOD0 must = 0 to access bit SM00)
Bit 6: Serial port 0 mode bit 1.
SM30
0
0
0
0
1
1
1
1
SM00
0
0
1
1
0
0
1
1
SM10
0
1
0
1
0
1
0
1
Mode
0
1
2
3
4
5
6
7
Description
shift register
8-bit UART
9-bit UART
9-bit UART
SPI Master
Reserved
SPI Slave
Reserved
Baud Rate
SYSCLK/12 or SYSCLK/4
variable
SYSCLK/64, /32
variable
SYSCLK/12 or SYSCLK/4
Reserved
Up to SYSCLK/8
Reserved
Bit 5: Serial port 0 mode bit 2.
0: Disable SM20 function.
1: Enable the automatic address recognition feature in Modes 2 and 3. If SM20=1, RI0 will not be set unless the
received 9th data bit is 1, indicating an address, and the received byte is a Given or Broadcast address. In mode1,
if SM20=1 then RI0 will not be set unless a valid stop Bit was received, and the received byte is a Given or
Broadcast address. In Mode 0, SM20 should be 0.
Bit 4: REN0, Enable serial 0 reception.
0: Clear by software to disable reception.
1: Set by software to enable reception.
Bit 3: TB80, The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
th
Bit 2: RB80, In Modes 2 and 3, the 9 data bit that was received. In Mode 1, if SM20 = 0, RB80 is the stop bit that
was received. In Mode 0, RB80 is not used.
Bit 1: TI0. Transmit interrupt flag.
0: Must be cleared by software.
th
1: Set by hardware at the end of the 8 bit time in Mode 0, or at the beginning of the stop bit in the other modes, in
any serial transmission. This bit is also set in mode 4 (SPI master) and mode 6 (SPI slave) after a SPI transfer
finished.
Bit 0: RI0. Receive interrupt flag.
0: Must be cleared by software.
th
1: Set by hardware at the end of the 8 bit time in Mode 0, or halfway through the stop bit time in the other modes, in
any serial reception (except see SM20).
88
MG74PG1A08 Data Sheet
MEGAWIN
S0BUF: Serial port 0 Buffer Register
SFR Attribute = Normal Read/Write
SFR Address = 0x99
RESET = XXXX-XXXX
7
6
5
4
3
2
S0BUF.7
S0BUF.6
S0BUF.5
S0BUF.4
S0BUF.3
S0BUF.2
R/W
R/W
R/W
R/W
R/W
1
S0BUF.1
0
S0BUF.0
R/W
R/W
R/W
Bit 7~0: It is used as the buffer register in transmission and reception.
PCON0: Power Control Register 0
SFR Attribute = Normal Read/Write or Protected Write
SFR Address = 0x87
POR = 0001-0000, RESET = 0000-0000
7
6
5
4
3
2
1
SMOD1
SMOD0
GF
POF
GF1
GF0
PD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
IDL
R/W
Bit 7: SMOD1, double Baud rate control bit.
0: Disable double Baud rate of the UART0.
1: Enable double Baud rate of the UART0 in mode 1, 2, or 3.
Bit 6: SMOD0, Frame Error select.
0: S0CON.7 is SM00 function.
1: S0CON.7 is FE function. Note that FE will be set after a frame error regardless of the state of SMOD0.
AUXR2: Auxiliary Register 2
SFR Attribute = Normal Read/Write
SFR Address = 0xA3
7
6
5
UTIE/
BTI/
URM0X3/
CPHA
SSIG
SMOD2
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
1
0
SM30
T1X12
T0X12
T1CKOE
T0CKOE
R/W
R/W
R/W
R/W
R/W
Bit 7: UART0 TI0 Enabled in system flag interrupt.
0: Disable the interrupt vector sharing for TI0 in system flag interrupt.
1: Set TI0 flag will share the interrupt vector with system flag interrupt.
In mode 6, SPI slave mode:
Bit 7: CPHA function in serial port 0 mode 6, SPI clock phase select
0: Data is driven when /SS pin is low (SSIG=0) and changes on the trailing edge of SPICLK. Data is sampled on the
leading edge of SPICLK.
1: Data is driven on the leading edge of SPICLK, and is sampled on the trailing edge.
(Note: If SSIG=1, CPHA must not be 1, otherwise the operation is not defined.)
Bit 6: BTI, Block TI0 in Serial Port 0 Interrupt.
0: Retain the TI0 to be a source of Serial Port 0 Interrupt.
1: Block TI0 to be a source of Serial Port 0 Interrupt.
In mode 6, SPI slave mode:
Bit 6: SSIG function in serial port 0 mode 6.
0: SPI slave engine is enabled by nSS input.
1: SPI slave ignores the nSS input and the engine is controlled by REN0 (S0CON.4). If REN0 = 0, SPI slave is
pending. If REN0 = 1, SPI slave is active and shift data on SPICLK edge transition.
Bit 5: URM0X3, Serial Port 0 mode 0 and mode 4 baud rate selector.
0: Clear to select SYSCLK/12 as the baud rate for UART0 Mode 0 and Mode 4.
1: Set to select SYSCLK/4 as the baud rate for UART0 Mode 0 and Mode 4.
MEGAWIN
MG74PG1A08 Data Sheet
89
In mode 1, 2, 3 UART0 mode:
Bit 5: SMOD2, extra double baud rate selector.
0: Disable extra double baud rate for UART0.
1: Enable extra double baud rate for UART0.
Bit 4: SM30, Serial Port 0 Mode control bit 3.
0: Disable Serial Port 0 Mode 4 & 6.
1: Enable SM30 to control Serial Port 0 Mode 4 & 6, SPI Master & Slave.
Bit 3: T1X12, Timer 1 clock source selector while C/T=0.
0: Clear to select SYSCLK/12.
1: Set to select SYSCLK as the clock source.
BOREV: Bit Order Reversed Register
SFR Attribute = Normal Read/Write
SFR Address = 0x96
RESET = 0000-0000
7
6
5
4
3
2
BOREV.7 BOREV.6 BOREV.5 BOREV.4 BOREV.3 BOREV.2
1
BOREV.1
0
BOREV.0
W
W
W
W
W
W
W
W
BOREV.0
BOREV.1
BOREV.2
BOREV.3
BOREV.4
BOREV.5
BOREV.6
BOREV.7
R
R
R
R
R
R
R
R
This register serves data read as a Bit-Order Reversed function with data written into. Because the serial port 0
engine is always LSB first on transmit/receive. This SFR is used by software to transfer bit order for different SPI
format. If the SPI transfer is MSB first, software must write transmitted data to BOREV and read back to get the
reversed bit order data. Then software writes the read back data to S0BUF to perform the SPI MSB first transmitting.
90
MG74PG1A08 Data Sheet
MEGAWIN
17. Keypad Interrupt (KBI)
The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when enabled port pin
is a low level occurred. This function can be used keypad recognition. Figure 17–1 shows the structure of the
keypad interrupt function.
There are two bit registers used for one port on this function. One bit enables the low nibble port pins for keypad
interrupt (KBI) function. Another one enables the high nibble port pins. And the port pin operating mode must be
configured to open-drain mode, open-drain mode with pull-up or quasi-bidirectional mode and the associated port
pin latch is set to “1”. If port pin is configured to push-pull output mode, analog-input-only or output low in open-drain
and quasi mode, the KBI on the port pin will be inhibited. Any recognized KBI event will cause the hardware to set
the interrupt flag KBIF and generate an interrupt if it has been enabled. Not necessary to enable the KBI interrupt,
enabled KBI port pin can wakeup CPU from idle mode (low level) and power-down mode (low level).
17.1. Keypad Interrupt Structure
Figure 17–1. Keypad interrupt structure
ESF
P3.7 input
P3.7 KBI input
(XPIE1.0)
KBI Interrupt
KBIFIE
(SFIE.3)
P3HKBI
P3.6 input
P3.6 KBI input
KBIF
PCON1.3
EXPIE1
(IE.5)
P3HKBI
P1.0 input
P1.0 KBI input
P1LKBI
MEGAWIN
MG74PG1A08 Data Sheet
91
17.2. Keypad Interrupt Register
KBIEN0: KBI Enable Control Register 0
SFR Attribute = Normal Read/Write
SFR Address = 0xD6
RESET = 00xx-00xx
7
6
5
4
3
2
P3HKBI
P3LKBI
--P1HKBI
P1LKBI
R/W
R/W
W
W
R/W
R/W
1
--
0
--
W
W
Bit 7: P3HKBI, Keypad Input function enable for P3.7 and P3.6.
0: Disable P3.7 and P3.6 KBI function.
1: Enable P3.7 and P3.6 KBI function.
Bit 6: P3LKBI, Keypad Input function enable for P3.2 ~ P3.0.
0: Disable P3.2 ~ P3.0 KBI function.
1: Enable P3.2 ~ P3.0 KBI function.
Bit 5~4: Reserved. Software must write “0” on these bits when KBIEN0 is written.
Bit 3: P1HKBI, Keypad Input function enable for P1.7 ~ P1.4.
0: Disable P1.7 ~ P1.4 KBI function.
1: Enable P1.7 ~ P1.4 KBI function.
Bit 2: P1LKBI, Keypad Input function enable for P1.3 ~ P1.0.
0: Disable P1.3 ~ P1.0 KBI function.
1: Enable P1.3 ~ P1.0 KBI function.
Bit 1~0: Reserved. Software must write “0” on these bits when KBIEN0 is written.
PCON1: Power Control Register 1
SFR Attribute = Normal Read/Write or Protected Write
SFR Address = 0x97
POR = 00xx-0000
7
6
5
4
3
KBIF
SWRF
EXRF
--R/W
R/W
W
W
R/W
2
BOF1
1
BOF0
0
WDTF
R/W
R/W
R/W
Bit 3: KBIF, Keypad Interrupt Flag.
0: This bit must be cleared by software writing “1” on it. Software writing “:0” is no operation.
1: This bit is only set by low level on enabled KBI port pin. Writing “1” on this bit will clear KBIF.
92
MG74PG1A08 Data Sheet
MEGAWIN
18. Serial Interface Detection (SID/STWI)
The serial interface detection module is always monitoring the “Start” and “Stop” condition on two-wire-interface.
STWI_SCL is the serial clock signal and STWI_SDA is the serial data signal. If any matched condition is detected,
hardware set the flag on STAF and STOF. Software can poll these two flags or set SIDFIE (SFIE.7) to share the
interrupt vector on System Flag. And STWI_SCL is located on nINT1 which helps MCU to strobe the serial data by
nINT1 interrupt. Software can use these resources to implement a variable TWI slave device.
18.1. Serial Interface Detection Structure
Figure 18–1 shows the configuration of STAF and STOF detection, interrupt architecture and event detecting
waveform.
Figure 18–1. Serial Interface Detection structure
ESF
(XPIE1.0)
AUXR1.3
STAF
Transition
Detection
STWI_SDA
input
SIDF Interrupt
SIDFIE
(SFIE.7)
SIDF
STOF
EXPIE1
(IE.5)
AUXR1.2
SYSCLK
STWI_SCL(nINT1)
input
enable
STWI_SDA
STWI_SCL
Set STAF
MEGAWIN
MG74PG1A08 Data Sheet
Set STOF
93
18.2. Serial Interface Detection Register
AUXR1: Auxiliary Control Register 1
SFR Attribute = Normal Read/Write
SFR Address = 0xA2
7
6
5
INT1IS1
INT1IS0
INT0IS0
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
STAF
STOF
GF
1
GF
0
GF
R/W
R/W
R/W
1
BOF0IE
0
WDTFIE
R/W
R/W
R/W
R/W
Bit 3: STAF, Start Flag detection of TWI.
0: Clear by firmware by writing “0” on it.
1: Set by hardware to indicate the START condition occurred on TWI bus.
Bit 2: STOF, Stop Flag detection of TWI.
0: Clear by firmware by writing “0” on it.
1: Set by hardware to indicate the START condition occurred on TWI bus.
SFIE: System Flag Interrupt Enable Register
SFR Attribute = Normal Read/Write
SFR Address = 0x8E
RESET = 0xxx-0000
7
6
5
4
3
2
SIDFIE
---KBIFIE
BOF1IE
R/W
W
W
W
R/W
R/W
Bit 7: SIDFIE, Serial Interface Detection Flag Interrupt Enabled.
0: Disable SIDF (STAF or STOF) interrupt.
1: Enable SIDF (STAF or STOF) interrupt.
94
MG74PG1A08 Data Sheet
MEGAWIN
19. Universal Serial Bus (USB)
MG74PG1A08 implements a USB full-speed function which is fully compliable with USB specification 2.0 and 1.1 to
support various USB applications. The USB block contains a on-chip 3.3V regulator, a USB transceiver which
transmits and receives differential USB signal, a 32 bytes FIFO which is a temporary store data unit, and a USB
Core to perform NRZI encoding and decoding, bit stuffing, CRC generation and checking, serial-parallel data
transforming, data flow between 32 bytes FIFO and CPU, USB special function register and setting, and
communication with CPU by accessing USBADR/USBDAT in CPU SFRs directly.
Before using MG74PG1A08 USB function, we assume that user has a comprehensive understanding on USB
protocol and application. So, the following descriptions in this chapter would not focus on the detail of USB
specification. If user is interesting in USB specification, user can download the latest version of USB specification
document from the USB official website http://www.usb.org/home.
Megawin Inc. also offer a development kit which contain sample code, C language library and application note on
the website http://www.megawin.com.tw/ to help user to implement design more quickly and easily.
Note:
MG74PG1A08 can’t be used as a USB HOST device or USB OTG device.
19.1. Features

Compliant with USB specification v1.1/v2.0.

Supports USB full speed 12M bps serial data transmission

Supports USB suspend/resume and remote wake-up

32 bytes FIFO for USB endpoint-shared buffer

8 bytes FIFO for EP0 Control In/Out buffer

8 bytes FIFO for EP1 Interrupt/Bulk IN buffer

16 bytes FIFO for EP2 Interrupt/Bulk IN/OUT buffer (default is IN)
19.2. Block Diagram
Figure 19–1. USB Block Diagram
Serial Interface Engine (SIE)
DP
DM
USB
Transceiver
Data
Transfer
Control
USB
SFRs
8051 Direct Addressing SFR
@USBADD &
@USBDAT
8051
Core
32B FIFO
MEGAWIN
MG74PG1A08 Data Sheet
95
19.3. FIFO Management
There are 32 bytes FIFO for temporary USB data store unit accessed by USB core and a total of 3 endpoints are
available in MG74PG1A08 as shown in Figure 19–2 Endpoint 0 supports a bi-direction control transfer. Endpoint 1/2
supports Interrupt/Bulk IN transaction. The maximum data packet size can be up to 8 bytes for endpoint 0 Control
function, 8 bytes for endpoint 1 IN function, 16 bytes for endpoint 2 IN/OUT function.
Figure 19–2. USB Endpoint 0/1/2 FIFO
Endp 0
8 Byte
INT
BULK
Endp 1 IN
8 Byte
INT
BULK
Endp 2 IN/OUT
16 Byte
Control
Total 32B FIFO
for 3 endpoints
19.4. Access USB 32 bytes FIFO
If ENUSB is set to enable USB function, a 32 bytes FIFO would be a dedicated buffer for USB application. But in
most application case, it is not necessary and wasted that all 32 bytes FIFO would reserve for USB buffer, the
unused USB buffer can provide MCU additional data RAM which is access through USB re-directed mechanism.
Figure 19–4 shows the USB FIFO access mechanism to share the USB FIFO for MCU application.
Access USB buffer through USB SFR re-direct flow:
Write data into USB buffer
1. Write EPINDEX=7
2. Write RXCNT (directly mapping RXCNT[5:0]} to 32B buffer Address space)
3. Write data into TXDAT
4. Repeat to step 2 (step 2 & 3 can be skipped, if the next buffer address is increased)
Read data from USB buffer
1. Write EPINDEX=7
2. Write RXCNT (directly mapping {RXCNT[5:0]} to 32B buffer Address space)
3. Read data from RXDAT
4. Repeat to step 2 (step 2 & 3 can be skipped, if the next buffer address is increased)
Figure 19–3. USB FIFO access mechanism
Memory w/ FIFO
Mechanism
USB Buffer
32 Bytes
0x000h
MCU Write
TXDAT
0x007h
0x008h
EPINDEX=7
TXCNT[1:0]
RXCNT[5:0]
MCU Read
ADD[5:0]
0x00Fh
0x010h
RXDAT
0x01Fh
96
Endpoint 0
8 Bytes
Endpoint 1 IN
8 Bytes
Endpoint 2
IN/OUT
USB FIFO
Mechanism
EPINDEX=0
RXDAT
MCU Read
TXDAT
MCU Write
EPINDEX=1
EPINDEX=2
16 Bytes
MG74PG1A08 Data Sheet
MEGAWIN
19.5. USB Initial
To activate the USB operation, the user should enable Clock Multiplier (CKM) unit by setting ENCKM bit, wait 100us
for CKM ready to work, and then enable USB function by setting ENUSB bit. Clearing bit ‘ENUSB’ will deactivate the
USB operation and let the USB function enter its power-down mode. These relevant control bits are contained in the
CKCON0 register, as follows.
DCON0: Device Control 0
SFR Attribute = Normal Read and Protected Write
SFR Address = 0xBC
RESET = x100-0110
7
6
5
4
3
2
USBR
WCKS
ENUSB
ENCKM
CKMIS1
CKMIS0
R/W
R/W
R/W
R/W
R/W
R/W
1
RSTIO
0
SWRST
R/W
R/W
Bit 6: USBR, Software trigger to reset USB function
0: Software end the reset of USB function.
1: Software start the reset of USB function.
Bit 5: ENUSB, Enable USB clock and whole USB function.
0: Disable USB clock and USB function.
1: Enable USB clock and USB function.
Bit 4: ENCKM, Enable clock multiplier (X8)
0: Disable the X8 clock multiplier.
1: Enable the X8 clock multiplier.
Bit 3~2: CKMIS1 ~ CKMIS0, Multiplier Input Clock Selection.
CKMIS[1:0]
Multiplier Input Clock Selection
0 0
6MHz input
0 1
12MHz input
1 0
24MHz input
1 1
36MHz input
Note:
Before using USB function, the setting of CKM must be correct to provide proper clock for USB
communication. Please refer Section “8 System Clock” to get the information about the setting of CKM.
MEGAWIN
MG74PG1A08 Data Sheet
97
19.6. Access USB SFR
Table 19–1 Table 19–1shows the USB SFR and their indirect address from C0H~FFH. USB SFR can be indirectly
accessed according to a 6-bit address hold in USBADR. Read/Write USBDAT will target the register indicated by
USBADR.
USB Write SFR procedure
1. Wait for UBSY==0
2. Write USB SFR address into USBADR
3. Write data into USBDAT
4. Repeat to step1 to write next data(step 2 can be skipped, when writing to the same USB SFR address)
USB Read SFR procedure
1. Wait for UBSY==0
2. Write USB SFR address into USBADR
3. Read data from USBDAT
4. Repeat to step 1 to read next data(step 2 can be skipped, when reading from the same USB SFR address)
Table 3–1
USBADR: USB indirect Address Register
SFR Page
= 0~F
SFR Address = 0xAB
POR+RESET = 0x00-0000
7
6
5
4
3
2
UBSY
-USFRA5
USFRA4
USFRA3
USFRA2
R
R/W
R/W
R/W
R/W
R/W
1
USFRA1
0
USFRA0
R/W
R/W
1
UDAT1
0
UDAT0
R/W
R/W
Bit 7: UBSY, USB core BUSY flag.
0: The data access request in USB core is finished.
1: USB core is BUSY on accessing software read/write request.
Bit 5~0: USFRA[5:0], USB SFR indirect address.
USBDAT: USB Data Register
SFR Page
= 0~F
SFR Address = 0xAA
7
6
5
UDAT7
UDAT6
UDAT5
R/W
R/W
R/W
POR+RESET = xxxx-xxxx
4
3
2
UDAT4
UDAT3
UDAT2
R/W
R/W
R/W
Bit 7~0: UDAT[7:0], USB SFR Data.
98
MG74PG1A08 Data Sheet
MEGAWIN
19.7. USB Interrupt
Figure 19–5 shows the USB interrupt structure and there are 11 interrupt flags which are located in USB SFRs
shown in Section “19.9.1 USB Function SFR Bit Assignment”. The USB interrupt is generated on the combination of
USB event flags and USB endpoint flags contained in USB SFRs. The USB event flags include USB reset flag
(URST), USB resume flag (URSM), USB suspend flag (USUS) and USB reset wakeup flag (URSTWKP) can
indicate that the upstream host has sent the USB reset, resume or suspend event on USB bus to device. The USB
endpoint flags, as UTXDx and URXDx (x=0~2), show the USB data transmission or reception of respective endpoint
had been done by USB transceiver. The associated interrupt enable bits are located in UIE, UIE1 and IEN registers.
Figure 19–4. USB Interrupt Diagram
UPCON
URST
EFSR
(IEN.2)
URSM
USUS
URSTWKP
UIE
SOFIF
UTXD2/
URXD2
SOFIE
UTXIE2
EF
(IEN.1)
USB interrupt to MCU
UTXD1
UTXIE1
URXD0
URXIE0
UTXD0
UIFLG
UTXIE0
UIE1
RXNAK
TXNAK
MEGAWIN
RXNAKE
UIFLG1
EF
(IEN.1)
TXNAKE
MG74PG1A08 Data Sheet
99
19.8. USB Special Function Registers
All USB SFRs would be reset by the reset sources as listed in Section “10 System Reset” (SYSRST) and the most of
USB SFRs would be reset when device receives the USB reset event (USBRST) except DCON0, DCON1, IEN,
SIOCTL registers and CONEN bit in UPCON register.
19.9. USB Function SFR Mapping
Table 19–1. USB Function SFR Mapping
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
xxF8H
--
--
--
--
--
--
--
--
xxFFH
xxF0H
--
EPINDEX
TXSTAT
TXDAT
TXCON
--
TXCNT
--
xxF7H
xxE8H
--
--
--
--
--
--
--
--
xxEFH
xxE0H
--
EPCON
RXSTAT
RXDAT
RXCON
--
RXCNT
--
xxE7H
xxD8H
UADDR
IEN
UIE
UIFLG
UIE1
UIFLG1
xxD0H
--
--
--
--
--
--
--
--
xxD7H
xxC8H
--
UPCON
--
--
--
--
--
--
xxCFH
xxC0H
UDCON0
UDCON1
SIOCTL
--
--
--
--
--
xxC7H
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
100
MG74PG1A08 Data Sheet
xxDFH
MEGAWIN
19.9.1. USB Function SFR Bit Assignment
Table 19–2. USB Function SFR Bit Assignment
SYMBOL
DESCRIPTION
ADDR
BIT SYMBOL
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
RESET
VALUE
FRST
--
--
--
--
0x00xxxxB
--
xx00000xB
UDCON0
USB Device Control
Register 0
C0H
EP2DIR
--
SCWKP
UDCON1
USB Device Control
Register 1
C1H
--
--
SETNO STLDEN NAKEP1 NAKEP0 RPDEN
UADDR
USB Address
Register
D8H
--
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
x0000000B
UPCON
USB Power
Control Register
C9H
CONEN
--
URWU
--
URSTWK
P
URST
URSM
USUS
0x0x0000B
IEN
Interrupt Enable
Register
D9H
--
--
--
--
--
EFSR
EF
--
xxxxx00xB
UIE
USB Interrupt
Enable Register
DAH
SOFIE
--
--
UTXIE2/
URXIE2
--
UTXIE1
URXIE0
UTXIE0
0xx0x000B
USB Interrupt
Flag Register
DBH
SOFIF
--
--
UTXD2/
URXD2
--
UTXD1
URXD0
UTXD0
0xx0x000B
USB Interrupt
Enable Register 1
DCH
--
--
--
--
--
--
00xxxxx0B
UIFLG1
USB Interrupt
Flag Register 1
DDH
RXNAK
TXNAK
--
--
--
--
--
--
00xxxxx0B
EPINDEX
Endpoint
Index Register
F1H
--
--
--
--
--
EPINX2
EPINX1
EPINX0
xxxxx000B
EPCON
Endpoint
Control Register
E1H
RXSTL
TXSTL
--
--
--
RXEPEN
--
TXEPEN
00x0x101B
RXSTAT
Endpoint Receive
Status Register
E2H
RXSEQ
RXSOV
W
--
--
--
000000xxB
RXDAT
FIFO Receive
Data Register
E3H
RXD7
RXD6
RXD5
RXD4
RXD3
RXD2
RXD1
RXD0
xxxxxxxxB
RXCON
FIFO Receive
Control Register
E4H
RXCLR
--
--
RXFFRC
--
--
--
--
0xx0xxxxB
RXCNT
FIFO Receive
Byte Count Register
E6H
RXBC7
RXBC6
RXBC5
RXBC4
RXBC3
RXBC2
RXBC1
RXBC0
00000000B
TXSTAT
Endpoint Transmit
Status Register
F2H
TXSEQ
--
--
--
TXSOVW
--
--
--
0xxx0xxxB
TXDAT
FIFO Transmit
Data Register
F3H
TXD7
TXD6
TXD5
TXD4
TXD3
TXD2
TXD1
TXD0
xxxxxxxxB
TXCON
FIFO Transmit
Control Register
F4H
TXCLR
--
--
TXFFRC
--
--
--
--
0xx0xxxxB
TXCNT
FIFO Transmit
Byte Count Register
F6H
TXBC7
TXBC6
TXBC5
TXBC4
TXBC3
TXBC2
TXBC1
TXBC0
xxxxxxxxB
SIOCTL
Serial I/O Control
Register
C2H
DPI
DMI
--
--
--
--
--
--
xxxxxxxxB
UIFLG
UIE1
MEGAWIN
RXNAKE TXNAKE
RXSETU
STOVW EDOVW
P
MG74PG1A08 Data Sheet
101
UDCON0: USB Device Control Register 0
SFR Address = 0xC0H
SYSRST= 0000-0000
7
6
5
4
3
--EP2DIR
SCWKP
FRST
R/W
W
R/W
R/W
W
2
1
0
--
--
--
W
W
W
Bit 7: EP2DIR-- Endpoint 2 Direction select
0: Endpoint 2 will be configured for IN function.
1: Endpoint 2 will be configured for OUT function.
Bit 6: Reserved. Software must write “0” on this bit when UDCON0 is written.
Bit 5: SCWKP, Software Control Remote-wakeup.
0: Remote-wakeup length will be decided by hardware setting.
1: Remote-wakeup length will be decided by URWU value.
Bit 4: FRST-- Function interface Reset Flag of USB device.
Set by hardware when the MG74PG1A08 detects the USB device interface in USB reset duration. If this bit is set,
the chip will not generate an interrupt to uC. It would be cleared by firmware writing '1' to it.
Bit 3~0: Reserved. Software must write “0” on this bit when UDCON0 is written.
UDCON1: USB Device Control Register 1
SFR Address = 0xC1H
SYSRST= 0000-000X
7
6
5
4
3
2
--SETNO
STLDEN
NAKEP1
NAKEP0
W
W
R/W
R/W
R/W
1
RPDEN
--
R/W
W
R/W
0
Bit 7~6: Reserved. Software must write “0” on this bit when UDCON1 is written.
Bit 5: SETNO-- Set No-response in EP0 IN/OUT transaction.
0: Device will send ACK/NAK/STALL packet in IN/OUT transaction.
1: Device will be just only response ACK packet with SETUP transaction but no response with EP0 IN/OUT
transaction.
Note:
This bit will be clear by HW when Device receive an SETUP token.
Bit 4: STLDEN-- STALL Done enable.
0: Disable IN/OUT STALL transaction flag setting.
1: IN/OUT STALL transaction will set TXD0/RXD0 in FIFLG.
Bit 3~2: NAKEP[1:0]-- Endpoint NAK done select.
00: RXNAK and TXNAK dedicated for endpoint 0
01:TXNAK dedicated for endpoint 1
10:TXNAK dedicated for endpoint 2
11: Reserved.
Bit 1: RPDEN, two individual pull-down Resistor enabled on DP and DM.
0: Disable the pull-down resistors on DP and DM.
1: Enable the pull-down resistors on DP and DM. The resistance is about 500K Ohm.
Bit 0: Reserved. Software must write “0” on this bit when UDCON1 is written.
102
MG74PG1A08 Data Sheet
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UADDR: USB Function Address Register
SFR Address = 0xD8H
SYSRST/USBRST= X000-0000
7
6
5
4
3
2
1
-UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
W
R/W
R/W
R/W
R/W
R/W
R/W
0
UADD0
R/W
Bit 7: Reserved. Software must write “0” on this bit when UADDR is written.
Bit 6~0: UADD[6:0]-- USB Function Address.
This register holds the address for the USB function. During bus enumeration, it is written with a unique value
assigned by the host.
UPCON: USB Power Control Register
SFR Address = 0xC9H
7
6
5
CONEN
-URWU
R/W
W
R/W
SYSRST/USBRST= 0X0X-X000
4
3
2
1
-URSTWKP
URST
URSM
W
R/W
R/W
R/W
0
USUS
R/W
Bit 7: CONEN-- USB Connect Enable.
Default is cleared to '0' after reset. FW should set '1' to enable connection to upper host/hub.
Bit 6: Reserved. Software must write “0” on this bit when UPCON is written.
Bit 5: URWU-- USB Remote Wake-Up Trigger.
0: If SCWKP=0, this bit will be cleared by hardware when remote-wakeup is completed. If SCWKP=1, this bit will be
cleared by firmware to stop device driving a remote wake-up on the USB bus. Don't set this bit unless the function
is suspended
1: This bit is set by the firmware to initiate a remote wake-up on the USB bus when CPU is wake-up by external
trigger.
Note:
Set by firmware to make driving resume signaling to the host. Don't set this bit unless the function is suspended
(USUS=1 and URSM=0).
SCWKP
0
1
Device resume length
The resume signal period which device drive is about 5~6T, T=1.172ms.
The resume signal period is which start by FW set URWU and end by FW clear URWU.
Bit 4: Reserved. Software must write “0” on this bit when UPCON is written.
Bit 3: URSTWKP—USB Reset wakeup Flag.
During suspend, set by hardware when the function detects the USB bus reset. If this bit is set, the chip will generate
an URSTWKP interrupt to uC. It would be cleared by firmware when serving the USB reset wakeup interrupt. This bit
is cleared when firmware writes '1' to it.
Bit 2: URST-- USB Reset Flag.
Set by hardware when the function detects the USB bus reset. If this bit is set, the chip will generate an USRT
interrupt to uC. It would be cleared by firmware when serving the USB reset interrupt. This bit is cleared when
firmware writes '1' to it.
Bit 1: URSM-- USB Resume Flag.
Set by hardware when the function detects the resume state on the USB bus. If this bit is set, the chip will generate
an interrupt to uC. It would be cleared by firmware when serving the function resume interrupt. This bit is cleared
when firmware writes '1' to it.
Bit 0: USUS-- USB Suspend Flag.
Set by hardware when the function detects the suspend state on the USB bus. If this bit is set, the chip will generate
an interrupt to uC. During the function suspend interrupt-service routine, firmware should clear this bit before enter
the suspend mode. This bit is cleared when firmware writes '1' to it.
MEGAWIN
MG74PG1A08 Data Sheet
103
IEN: Interrupt Enable Register
SFR Address = 0xD9H
7
6
5
---W
W
W
SYSRST= XXXX-X00X
4
3
2
--EFSR
1
EF
0
--
W
R/W
W
W
R/W
Bit 7~3: Reserved. Software must write “0” on these bits when IEN is written.
Bit 2: EFSR-- Enable USB Function’s Suspend/Resume interrupt.
If this bit is set, enables function’s interrupt of FPCON events. Function suspend/resume/remote-wakeup/USB-reset
interrupt enable bit. This bit doesn't be reset USB_RESET. Default is cleared.
Bit 1: EF-- Enable USB Function’s interrupt Flag.
If this bit is set, enables function’s interrupt of UIFLG. Transmit/receive done interrupt enable bit for USB function
endpoints. This bit doesn't be reset by USB_RESET. Default is cleared.
Bit 0: Reserved. Software must write “0” on this bit when IEN is written.
UIE: USB Interrupt Enable Register
SFR Address = 0xDAH
7
6
5
SOFIE
--
--
R/W
W
W
SYSRST/USBRST= 00X0-X000
4
3
2
1
UTXIE2/
-UTXIE1
URXIE0
URXIE2
R/W
W
R/W
R/W
0
UTXIE0
R/W
Bit 7: SOFIE-- Host SOF received Interrupt Enable.
If this bit is set, enables the Host SOF received interrupt. Default is cleared.
Bit 6~5: Reserved. Software must write “0” on this bit when UIE is written.
Bit 4: UTXIE2/URXIE2-- USB Function Transmit Interrupt Enable 2.
If this bit is set, enables the transmit and receive done interrupt for USB endpoint 2 (UTXD2/URXD2). Default is
cleared.
UTXIE2 - Enable UIFLG.UTXD2 Interrupt. (Default DCON.EP2DIR=0)
URXIE2 - Enable UIFLG.URXD2 Interrupt. (DCON.EP2DIR=1)
Bit 3: Reserved. Software must write “0” on this bit when UIE is written.
Bit 2: UTXIE1-- USB Function Transmit Interrupt Enable 1.
If this bit is set, enables the transmit done interrupt for USB endpoint 1 (UTXD1). Default is cleared.
Bit 1: URXIE0-- USB Function Receive Interrupt Enable 0.
If this bit is set, enables the receive done interrupt for USB endpoint 0 (URXD0). Default is cleared.
Bit 0: UTXIE0-- USB Function Transmit Interrupt Enable 0.
If this bit is set, enables the transmit done interrupt for USB endpoint 0 (UTXD0). Default is cleared.
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MG74PG1A08 Data Sheet
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UIFLG: USB Interrupt Flag Register
SFR Address = 0xDBH
7
6
5
SOFIF
--
--
R/W
W
W
SYSRST/USBRST= 00X0-X000
4
3
2
1
UTXD2/
-UTXD1
URXD0
URXD2
R/W
W
R/W
R/W
0
UTXD0
R/W
Bit 7: SOFIF-- Host SOF received Interrupt Flag.
This bit is set by hardware when detected a host SOF. UC can read/write-clear on this bit. This bit is cleared when
firmware writes '1' to it.
Bit 6~5: Reserved. Software must write “0” on this bit when UIFLG is written.
Bit 4: UTXD2/URXD2-- USB Transmit and Receive Done Flag for endpoint 2.
This bit is set by hardware when detected a transmit and receive done on endpoint 2. UC can read/write-clear on
this bit. This bit is cleared when firmware writes '1' to it.
UTXD2 -- Endpoint 2 Transmit done flag. (Default DCON.EP2DIR=0)
URXD2 -- Endpoint 2 Receive done flag. (DCON.EP2DIR=1)
Bit 3: Reserved. Software must write “0” on this bit when UIFLG is written.
Bit 2: UTXD1-- USB Transmit Done Flag for endpoint 1.
This bit is set by hardware when detected a transmit done on endpoint 1. UC can read/write-clear on this bit. This bit
is cleared when firmware writes '1' to it.
Bit 1: URXD0-- USB Receive Done Flag for endpoint 0.
This bit is set by hardware when detected a receive done on endpoint 0. UC can read/write-clear on this bit. This bit
is cleared when firmware writes '1' to it.
Bit 0: UTXD0-- USB Transmit Done Flag for endpoint 0.
This bit is set by hardware when detected a transmit done on endpoint 0. UC can read/write-clear on this bit. This bit
is cleared when firmware writes '1' to it.
UIE1: USB Interrupt Enable Register 1
SFR Address = 0xDCH
7
6
5
RXNAKE
TXNAKE
-R/W
R/W
W
SYSRST/USBRST= 00XX-XXX0
4
3
2
----
1
--
0
--
W
W
W
W
W
Bit 7: RXNAKE-- Enable RX NAK interrupt on NAKEP[1:0] indexed.
If this bit is set, enables the RXNAK interrupt for NAKEP[1:0] indexed endpoint. Default is cleared.
Bit 6: TXNAKE-- Enable TX NAK interrupt on NAKEP[1:0] indexed.
If this bit is set, enables the TXNAK interrupt for NAKEP[1:0] indexed endpoint. Default is cleared.
Bit 5~0: Reserved. Software must write “0” on this bit when UIE1 is written.
MEGAWIN
MG74PG1A08 Data Sheet
105
UIFLG1: USB Interrupt Flag Register 1
SFR Address = 0xDDH
SYSRST/USBRST= 00XX-XXX0
7
6
5
4
3
2
RXNAK
TXNAK
----R/W
R/W
W
W
W
W
1
--
0
--
W
W
Bit 7: RXNAK-- RX NAK Flag on NAKEP[1:0] indexed.
This bit is set by hardware when detected a receive done on the NAK packet for OUT transaction of the NAKEP[1:0]
indexed endpoint. This bit is clear when firmware write “1” to it.
Bit 6: TXNAK-- TX NAK Flag on NAKEP[1:0] indexed.
This bit is set by hardware when detected a transmit done on the NAK packet for IN transaction of the NAKEP[1:0]
indexed endpoint. This bit is clear when firmware write “1” to it.
Bit 5~0: Reserved. Software must write “0” on this bit when UIFLG1 is written.
EPINDEX: Endpoint Index Register
SFR Address = 0xF1H
7
6
5
---W
W
W
SYSRST/USBRST= XXXX-X000
4
3
2
1
--EPINX2
EPINX1
W
W
R/W
R/W
0
EPINX0
R/W
Bit 7~3: Reserved. Software must write “0” on these bits when EPINDEX is written.
Bit 2~0: EPINX[2:0]-- Endpoint Index Bits [2:0]
3’b000: USB Function Endpoint 0.
3’b001: USB Function Endpoint 1.
3’b010: USB Function Endpoint 2.
3’b011~110: Reserved.
3’b111: uC access 32 byte buffer enable.
EPCON: Endpoint Control Register (endpoint-indexed)
SFR Address = 0xE1H
SYSRST/USBRST= 00X0-X101
7
6
5
4
3
2
RXSTL
TXSTL
---RXEPEN
R/W
R/W
W
W
W
R/W
1
--
0
TXEPEN
W
R/W
Bit 7: RXSTL-- Receive Endpoint Stall.
Set this bit to stall the receive endpoint.
Note:
Clear this bit only when the host has intervened through commands sent down endpoint 0. When this bit is set and
RXSETUP is clear, the receive endpoint will respond with a STALL handshake to a valid OUT token. When this bit is
set and RXSETUP is set, the receive endpoint will NAK. This bit does not affect the reception of SETUP tokens by a
control endpoint.
Bit 6: TXSTL-- Transmit Endpoint Stall.
Set this bit to stall the transmit endpoint.
Note:
Clear this bit only when the host has intervened through commands sent down endpoint 0. When this bit is set and
RXSETUP is clear, the transmit endpoint will respond with a STALL handshake to a valid IN token. When this bit is
set and RXSETUP is set, the transmit endpoint will NAK.
Bit 5~3: Reserved. Software must write “0” on this bit when EPCON is written.
106
MG74PG1A08 Data Sheet
MEGAWIN
Bit 2: RXEPEN-- Receive Endpoint Enable.
Set this bit to enable the receive endpoint. When disabled, the endpoint does not respond to a valid OUT or SETUP
token. This bit in endpoint 0 is enabled after reset. This bit has the highest priority than RXSTL.
Bit 1: Reserved. Software must write “0” on this bit when EPCON is written.
Bit 0: TXEPEN-- Transmit Endpoint Enable.
Set this bit to enable the transmit endpoint. When disabled, the endpoint does not respond to a valid IN token. This
bit in endpoint 0 is enabled after reset. This bit has the highest priority than TXSTL.
RXSTAT: Endpoint Receive Status Register (endpoint-indexed)
SFR Address = 0xE2H
SYSRST/USBRST= 0000-00XX
7
6
5
4
3
2
RXSEQ
RXSETUP STOVW
EDOVW RXSOVW
-R/W
R/W
R/W
R/W
R/W
W
1
--
0
--
W
W
Bit 7: RXSEQ-- Receive Endpoint Sequence Bit (read, conditional write).
The bit will be toggled on completion of an ACK handshake in response to an OUT token. This bit can be written by
firmware if the RXOVW bit is set when written along with the new RXSEQ value.
Bit 6: RXSETUP-- Received Setup Transaction.
This bit is set by hardware when a valid SETUP transaction has been received. Clear this bit upon detection of a
SETUP transaction or the firmware is ready to handle the data/status stage of control transfer.
Bit 5: STOVW-- Start Overwrite Flag (read-only).
Set by hardware upon receipt of a SETUP token for the control endpoint to indicate that the receive FIFO is being
overwritten with new SETUP data. This bit is used only for control endpoints.
Bit 4: EDOVW-- End Overwrite Flag.
This flag is set by hardware during the handshake phase of a SETUP transaction. This bit is cleared by firmware to
read the FIFO data. This bit is only used for control endpoints.
Bit 3: RXSOVW-- Receive Data Sequence Overwrite Bit.
Write '1' to this bit to allow the value of the RXSEQ bit to be overwritten. Writing a '0' to this bit has no effect on
RXSEQ. This bit always returns '0' when read.
Bit 2~0: Reserved. Software must write “0” on these bits when RXSTAT is written.
RXDAT: Receive FIFO Data Register (endpoint-indexed)
SFR Address = 0xE3H
SYSRST/USBRST= XXXX-XXXX
7
6
5
4
3
2
1
RXD7
RXD6
RXD5
RXD4
RXD3
RXD2
RXD1
R
R
R
R
R
R
R
0
RXD0
R
Bit 7~0: RXD[7:0]-- Receive FIFO Data.
Receive FIFO data specified by EPINDEX is stored and read from this register.
MEGAWIN
MG74PG1A08 Data Sheet
107
RXCON: Receive FIFO Control Register (endpoint-indexed)
SFR Address = 0xE4H
SYSRST/USBRST= 0XX0-XXXX
7
6
5
4
3
2
RXCLR
--RXFFRC
--W
W
W
W
W
W
1
--
0
--
W
W
Bit 7: RXCLR-- Receive FIFO Clear.
Set this bit to flush the entire receive FIFO. All FIFO statuses are reverted to their reset states. Hardware clears this
bit when the flush operation is completed.
Bit 6~5: Reserved. Software must write “0” on these bits when RXCON is written.
Bit 4: RXFFRC-- Receive FIFO Read Complete.
Set this bit to release the receive FIFO when data set read is complete. Hardware clears this bit after the FIFO
release operation has been finished.
Bit 3~0: Reserved. Software must write “0” on these bits when RXCON is written.
RXCNT: Receive FIFO Byte Count Register (endpoint-indexed)
SFR Address = 0xE6H
SYSRST/USBRST= 0000-0000
7
6
5
4
3
2
RXBC7
RXBC6
RXBC5
RXBC4
RXBC3
RXBC2
R
R
R
R
R
R
1
RXBC1
0
RXBC0
R
R
Bit 7~0: RXBC[7:0]-- Receive Byte Count.
For endpoint 0~2, This register is used to store the byte count for the data packet received in the receive FIFO
specified by EPINDEX. If EPINDEX =3’b111, this register is designed to be a low byte address for read/write 32B
SRAM function.
TXSTAT: Endpoint Transmit Status Register (endpoint-indexed)
SFR Address = 0xF2H
SYSRST/USBRST= 0XXX-0XXX
7
6
5
4
3
2
TXSEQ
---TXSOVW
-R/W
W
W
W
R/W
W
1
--
0
--
W
W
Bit 7: TXSEQ-- Transmit Endpoint Sequence Bit (read, conditional write).
The bit will be transmitted in the next PID and toggled on a valid ACK handshake of an IN transaction. This bit can
be written by firmware if the TXOVW bit is set when written along with the new TXSEQ value.
Bit 6~4: Reserved. Software must write “0” on these bits when TXSTAT is written.
Bit 3: TXSOVW-- Transmit Data Sequence Overwrite Bit.
Write '1' to this bit to allow the value of the TXSEQ bit to be overwritten. Writing a '0' to this bit has no effect on
TXSEQ. This bit always returns '0' when read.
Bit 2~0: Reserved. Software must write “0” on these bits when TXSTAT is written.
TXDAT: Transmit FIFO Data Register (endpoint-indexed)
SFR Address = 0xF3H
SYSRST/USBRST= XXXX-XXXX
7
6
5
4
3
2
1
TXD7
TXD6
TXD5
TXD4
TXD3
TXD2
TXD1
W
W
W
W
W
W
W
0
TXD0
W
Bit 7~0: TXD[7:0]-- Transmit FIFO Data.
Data to be transmitted in the FIFO specified by EPINDEX is written to this register.
108
MG74PG1A08 Data Sheet
MEGAWIN
TXCON: Transmit FIFO Control Register (endpoint-indexed)
SFR Address = 0xF4H
SYSRST/USBRST= 0XXX-0XXX
7
6
5
4
3
2
TXCLR
--TXFFRC
--W
W
W
W
W
W
1
--
0
--
W
W
Bit 7: TXCLR-- Transmit FIFO Clear.
Set this bit to flush the entire transmit FIFO. All FIFO statuses are reverted to their reset states. Hardware clears this
bit when the flush operation is completed.
Bit 6~5: Reserved. Software must write “0” on these bits when TXCON is written.
Bit 4: TXFFRC-- Transmit FIFO Write Complete.
Set this bit to release the transmit FIFO when data set write is complete. Hardware clears this bit after the FIFO
release operation has been finished. Firmware should write this bit only after firmware finished writing TXCNT
register.
Bit 2~0: Reserved. Software must write “0” on these bits when TXCON is written.
TXCNT: Transmit FIFO Byte Count Register (endpoint-indexed)
SFR Address = 0xF6H
SYSRST/USBRST= XXXX-XXXX
7
6
5
4
3
2
1
TXBC7
TXBC6
TXBC5
TXBC4
TXBC3
TXBC2
TXBC1
W
W
W
W
W
W
W
0
TXBC0
W
Bit 7~0: TXBC[7:0]-- Transmit Byte Count.
For endpoint 0~2, this register is used to stored the byte count for the data packet in the transmit FIFO specified by
EPINDEX. If EPINDEX = 3’b111, this register is designed to be a high byte address for read/write 32B SRAM
function.
SIOCTL: Serial I/O Control Register High
SFR Address = 0x2FH
SYSRST = XXXX-XXXX
7
6
5
4
3
2
DPI
DMI
----R
R
R
R
R
R
1
--
0
--
R
R
Bit 7: DPI-- USB DP port state, read only
Read the port status on USB DP.
Bit 6: DMI-- USB DM port state, read only
Read the port status on USB DM.
Bit 5~0: Reserved. Read only.
MEGAWIN
MG74PG1A08 Data Sheet
109
20. Protected-Write SFR Access
MG74PG1A08 builds a special SFR with Protected-Write function to store the control registers for MCU operation.
These SFRs can be read by the normal SFR operation. In Write operation, SCMD must set to “8C” and then
followed the target SFR write.
Following descriptions are the SFR function definition with Protected-Write Key for “8C” on SCMD.
BIT ADDRESS AND SYMBOL
RESET
SYMBOL DESCRIPTION ADDR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0 VALUE
PCON2
CKCON2
DCON0
SPCON0
Power Control 2
Clock Control 2
Device Control 0
SFR Page Control 0
BAH AWBOD1 EBOD1
--BO1RE BO0RE
-BBH
---IHRCOE MCKS1 MCKS0 OSCS1
BCH WCKS USBR ENUSB ENCKM CKMIS1 CKMIS0 RSTIO
BDH
---WRCTL
-CKCTL0 PWCTL1
SPCON0: SFR Page Control 0
SFR Attribute = Normal Read and Protected Write
SFR Address = 0xBD
POR+LVR = xxx0-0000
7
6
5
4
3
2
---WRCTL
-CKCTL0
W
W
W
R/W
W
RMLS
OSCS0
SWRST
PWCTL0
01000000
xxx10000
00000110
0xx00000
1
PWCTL1
0
PWCTL0
R/W
R/W
R/W
Bit 7~5: Reserved. Software must write “0” on these bits when SPCON0 is written.
Bit 4: WRCTL. WDTCR SFR access Control.
If WRCTL is set, it will enable the protected-write function on WDTCR SFR modified with the protected key = 0x8C.
Read WDTCR still keeps the normal SFR read function.
Bit 3: Reserved. Software must write “0” on these bits when SPCON0 is written.
Bit 2: CKCTL0. CKCON0 SFR access Control.
If CKCTL0 is set, it will enable the protected-write function on CKCON0 SFR modified with the protected key = 0x8C.
Read CKCON0 still keeps the normal SFR read function.
Bit 1: PWCTL1. PCON1 SFR access Control.
If PWCTL1 is set, it will enable the write-protected function on PCON1 SFR modified with the protected key = 0x8C.
Read PCON1 still keeps the normal SFR read function.
Bit 0: PWCTL0. PCON0 SFR access Control.
If PWCTL0 is set, it will enable the write-protected function on PCON0 SFR modified with the protected key = 0x8C.
PCON0 still keeps the general SFR read function.
110
MG74PG1A08 Data Sheet
MEGAWIN
21. Hardware Option
The MCU’s Hardware Option defines the device behavior which cannot be programmed or controlled by software.
The hardware options can only be programmed by a Universal Programmer, the “Megawin 8051 Writer U3” or the
“Megawin 8051 ICE Adapter” (The ICE adapter also supports ICP programming function.). After whole-chip erased,
all the hardware options are left in “disabled” state. The MG74PG1A08 has the following Hardware Options:
LOCK:
: Enabled. Code dumped on a universal Writer or Programmer is locked to 0x00 for security.
: Disabled. Not locked.
OSCS1O: MCU OSC type selection bit from power-on.
: Enabled. MCU clock source select IHRCO.
: Disabled. MCU clock source select ILRCO.
RMLSO:
: Enabled. POR level on 1.95V
: Disabled. POR level on 2.3V
WDSFWP:
: Enabled. The WDT SFRs, WREN, NSW, ENW, WIDL, PS2, PS1 and PS0 in WDTCR, will be write-protected.
: Disabled. The WDT SFRs, WREN, NSW, ENW, WIDL, PS2, PS1 and PS0 in WDTCR, are free for writing of
software.
NSWDT: Non-Stopped WDT
: Enabled. Set WDTCR.NSW to enable the WDT running in power down mode (watch mode).
: Disabled. Clear WDTCR.NSW to disable the WDT running in power down mode (disable Watch mode).
HWENW: Hardware loaded for “ENW” of WDTCR.
: Enabled. Enable WDT and load the content of WRENO, NSWDT, HWWIDL and HWPS2~0 to WDTCR after
power-on.
: Disabled. WDT is not enabled automatically after power-on.
WRENO: WDT Reset Enable Option
: Enabled. Set WDTCR.WREN to enable a system reset function by WDTF.
: Disabled. Clear WDTCR.WREN to disable the system reset function by WDTF.
HWWIDL, HWPS2, HWPS1, HWPS0:
When HWENW is enabled, the content on these four fused bits will be loaded to WDTCR SFR after power-on.
P17EN:
: Enabled. RSTIO (DCON0.1) will be cleared and P1.7 function behaves on nRST pin.
: Disabled. RSTIO (DCON0.1) will be set and reserve nRST pin function.
FPUT: Fast Power-Up Timer enable.
: Enabled. Enable fast power-up timer less than 16ms.
: Disabled. Keep default power-up timer. It is about more than 16ms.
MEGAWIN
MG74PG1A08 Data Sheet
111
22. Application Notes
22.1. Power Supply Circuit
To have the MG74PG1A08 work with power supply varying from 2.3V to 5.5V adding some external decoupling and
bypass capacitors is necessary, as shown in Figure 22–1. There caps have to be close to the chip power and ground.
MG74PG1A08 work with battery power supply varying from 2.0V to 3.6V, as shown in Figure 22–2.
Figure 22–1. Power Supplied Circuit
Power Supply
MCU
VDD
0.1uF
10uF
V33
1uF
VSS
Figure 22–2. Battery Power Supplied Circuit
Power Supply
MCU
VDD
0.1uF
10uF
V33
VSS
112
MG74PG1A08 Data Sheet
MEGAWIN
22.2. Reset Circuit
Normally, the power-on reset can be successfully generated during power-up. However, to further ensure the MCU
a reliable reset during power-up, the external reset is necessary (RSTIO must set to 1). Figure 22–3 shows the
external reset circuit, which consists of a capacitor CEXT connected to VSS (ground).
In general, the nRST pin has an internal pull-high resistor (RRST). This internal MOS resistor to VDD permits a
power-up reset using only an external capacitor CEXT to VSS.
See Section “23.2 DC Characteristics” for RRST value.
Figure 22–3. Reset Circuit
Power Supply
MCU
VDD
RRST
nRST
0.1uF
CEXT
VSS
MEGAWIN
MG74PG1A08 Data Sheet
113
22.3. With USB application Circuit
Figure 22–4. USB Application Circuit
VDD
20 ohm
D1
20 ohm
D+
2
GND
3
4
5
6
10uF
0.1uF
7
8
P1.7
VSS
P3.6
P3.7
VDD
V33
P3.0
P3.1
SOP16
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P3.2
16
15
14
13
12
11
10
9
1uF
114
MG74PG1A08 Data Sheet
MEGAWIN
22.4. ICP Interface Circuit
MG74PG1A08 devices include an on-chip Megawin proprietary programming interface to allow
In-Chip-Programming (ICP) with the production part installed in the end application. The ICP interface uses a clock
signal (ICP_SCL) and a bi-directional data signal (ICP_SDA) to perform the device programming from a host
instruction.
The ICP interface allows the ICP_SCL/ICP_SDA pins to be shared with user functions so that In-Chip Programming
function could be performed. This is practicable because ICP communication is performed when the device is in the
start-up state (in power-on period less than 8ms), where the on-chip peripherals and user software are stalled. In
this state, the ICP interface can safely ‘borrow’ the ICP_SCL (P1.1) and ICP_SDA (P1.0) pins. The typical
configuration is shown in Figure 22–5.
It is strongly recommended to build the ICP interface circuit on target system. It will reserve the whole
capability for software programming and device options configured.
Attention:
P1.2 (VPP) pin will have 7.5V high voltage form U3 programmer within OTP programming period. It may
damage other components which connect to pin P1.2 (VPP).
The pins of ICP interface not allow any additional capacitance.
Figure 22–5. ICP Interface Circuit
Target System
MCU
2KΩ
Input 1
P1.2
Output 1
VDD
2KΩ
Input 2
ICP_SCL
Output 2
ICP_SDA
2KΩ
Input 3
ICP_CMD
Output 3
VSS
U3 Programmer
MEGAWIN
MG74PG1A08 Data Sheet
115
23. Electrical Characteristics
23.1. Absolute Maximum Rating
Parameter
Rating
Unit
Ambient temperature under bias
-40 ~ +85
°C
Storage temperature
-65 ~ + 150
°C
Voltage on any Port I/O Pin or nRST with respect to VSS
-0.5 ~ VDD + 0.5
V
Voltage on VDD with respect to VSS
-0.5 ~ +6.0
V
Maximum total current through VDD and VSS
200
mA
Maximum output current sunk by any Port pin
40
mA
*Note: stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
116
MG74PG1A08 Data Sheet
MEGAWIN
23.2. DC Characteristics
VDD = 5.0V±10%, VSS = 0V, TA = 25°C and execute NOP for each machine cycle, unless otherwise specified
Limits
Unit
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Input/Output Characteristics
Except P1.7, P3.6,
VIH1 Input High voltage (All I/O Ports)
0.6
VDD
P3.7
Input High voltage (P1.7,P3.6,
VIH2
0.75
VDD
P3.7)
Except P1.7, P3.6,
VIL1 Input Low voltage (All I/O Ports)
0.15
VDD
P3.7
Input Low voltage (P1.7,P3.6,
VIL2
0.2
VDD
P3.7)
Input High Leakage current (All I/O
IIH
VPIN = VDD
0
10
uA
Ports)
Logic 0 input current (P3 in
IIL1 quasi-mode or other Input port with VPIN = 0.4V
20
50
uA
on-chip pull-up resistor)
Logic 0 input current (All Input only
IIL2
VPIN = 0.4V
0
10
uA
or open-drain Ports)
Logic 1 to 0 input transition current
IH2L (P3 in quasi-mode or other Input
VPIN =VH2L
330
500
uA
port with on-chip pull-up resistor)
Output High current (All push-pull
IOH
VOH =2.4V
30
mA
output ports)
IOL Output Low current (All I/O Ports) VOL =0.4V
20
mA
RRST Internal reset pull-up resistance
VP17=0V
30
Kohm
Weak pull-high resistor (All I/O
Rph1
VPIN=2V
10
Kohm
Ports)
Very weak pull-high resistor (All I/O
Rph2
VPIN=0V
260
Kohm
Ports)
Power Consumption
SYSCLK = 6MHz @
IOP1 Normal mode operating current
2.7
mA
IHRCO
SYSCLK = 12MHz @
IOP2 Normal mode operating current
4
mA
IHRCO
SYSCLK = 24MHz @
IOP3 Normal mode operating current
4.5
mA
IHRCO with PLL
SYSCLK = 12MHz @
IOP4 Normal mode operating current
5.3
mA
IHRCO with USB+PLL
SYSCLK = 12MHz/8 @
IOPS1 Slow mode operating current
1.9
mA
IHRCO
SYSCLK = 12MHz @
IIDLE1 Idle mode operating current
2
mA
IHRCO
SYSCLK = 64KHz @
IIDLE2 Idle mode operating current
0.6
mA
ILRCO
SYSCLK = 64KHz @
ISUB1 Sub-clock mode operating current
0.6
mA
ILRCO
SYSCLK = 64KHz/8 @
ISUB2 Sub-clock mode operating current
0.6
mA
ILRCO
WDT = 64KHz @
IWAT Watch mode operating current
4
uA
ILRCO in PD mode
BOD1 enabled in PD
IMON1 Monitor Mode operating current
45
uA
mode
IPD1 Power down mode current
2
3
uA
POR/BOD0/BOD1 Characteristics
(1)
(1)
VPORL POR detection level for 1.95V
TA = -40°C to +85°C
1.85
2.0
2.15
V
(1)
(1)
VPORH POR detection level for 2.3V
TA = -40°C to +85°C
2.1
2.3
2.5
V
MEGAWIN
MG74PG1A08 Data Sheet
117
Symbol
VBOD0L
VBOD0H
VBOD1
IBOD1
Parameter
Test Condition
BOD0 detection level for 2.1V
BOD0 detection level for 2.6V
BOD1 detection level for 3.6V
BOD1 Power Consumption
TA = -40°C to +85°C
TA = -40°C to +85°C
TA = -40°C to +85°C
TA = +25°C, VDD=5.0V
Operating Condition
VPSR Power-on Slop Rate
TA = 25°C
VPOR1 Power-on Reset Valid Voltage
TA = -40°C to +85°C
VOP1 IHRCO Operating Speed 0–6MHz TA = 25°C
VOP2 IHRCO Operating Speed 0-12MHz TA = 25°C
VOP3 IHRCO Operating Speed 0-24MHz TA = 25°C
VOP4 CPU Operating Speed 0-3MHz
TA = 25°C
VOP5 CPU Operating Speed 0-6MHz
TA = 25°C
VOP6 CPU Operating Speed 0-12MHz
TA = 25°C
(1)
Data based on characterization results, not tested in production.
Min.
(1)
1.95
(1)
2.5
(1)
3.3
Limits
Typ.
Max.
(1)
2.1
2.25
(1)
2.6
2.7
(1)
3.6
3.9
40
0.05
0.1
5.5
5.5
5.5
5.5
5.5
5.5
2.0
2.4
2.7
2.0
2.4
2.7
Unit
V
V
V
uA
V/ms
V
V
V
V
V
V
V
23.3. USB Transceiver Electrical Characteristics
VDD = 4.0V ~ 5.5V, VSS = 0V, TA = 25°C, unless otherwise specified
Symbol
Parameter
VV33 3.3V regulator output voltage
IV33 Regulator Output drive current
RPU
Pull-Up Resistance
RPD
Pull-Down Resistance
RPU2 Pull-Up Resistance for PS/2 mode
Test Condition
TA = 25°C
TA = 25°C
On DP
min
3.0
Limits
typ
3.3
0.95
1.1
Unit
max
3.6
35
V
mA
1.3
Kohm
On DP & DM
500
Kohm
On DP & DM
7
Kohm
Transmitter
VOH
VOL
VCRS
ZDRVH
ZDRVL
TR
TF
Output High Voltage
Output Low Voltage
Output Cross Over point
Output Impedance on Driving High
Output Impedance on Driving Low
Output Rise Time
Output Fall Time
2.8
Receiver
VDI Differential Input Sensitivity
| DP – DM |
VCM Differential Input Common Mode Range
IL Input Leakage current
Pull-up Disabled
118
MG74PG1A08 Data Sheet
1.3
28
28
4
4
0.8
2.0
44
44
20
20
0.2
0.8
2.5
<1.0
V
V
V
Ohm
Ohm
ns
ns
V
V
uA
MEGAWIN
23.4. External Clock Characteristics
VDD = 2.7V ~ 5.5V, VSS = 0V, TA = -40°C to +85°C, unless otherwise specified
Oscillator
Symbol
Parameter
ECKI Mode
Unit
Min.
Max.
Frequency
1/tCLCL
0
12
MHz
(VDD = 2.0V ~ 5.5V)
tCLCL
Clock Period
80
ns
tCHCX
High Time
0.4T
0.6T
tCLCL
tCLCX
Low Time
0.4T
0.6T
tCLCL
tCLCH
Rise Time
5
ns
tCHCL
Fall Time
5
ns
Figure 23–1. External Clock Drive Waveform
tCHCL
tCLCH
tCHCX
VDD - 0.5V
0.7VDD
0.2VDD - 0.1
0.45V
tCLCX
tCLCL
23.5. IHRCO Characteristics
Parameter
Test Condition
Min.
2.0
Supply Voltage
IHRCO Frequency
TA = +25°C
TA = +25°C
-1.0
IHRCO Frequency Deviation
(1)
(factory calibrated)
TA = -40°C to +85°C
-4
IHRCO Start-up Time
TA = -40°C to +85°C
IHRCO Power Consumption
TA = +25°C, VDD=5.0V
(1)
Data based on characterization results, not tested in production.
Limits
Typ.
Unit
Max.
5.5
12
+1.0
(1)
+4
(1)
32
(1)
500
V
MHz
%
%
us
uA
23.6. ILRCO Characteristics
Parameter
Supply Voltage
ILRCO Frequency
Test Condition
Min.
2.0
TA = +25°C
(1)
TA = +25°C
-5
ILRCO Frequency Deviation
(1)
TA = -40°C to +85°C
-30
(1)
Data based on characterization results, not tested in production.
MEGAWIN
MG74PG1A08 Data Sheet
Limits
Typ.
Unit
Max.
5.5
64
(1)
+5
(1)
+30
V
KHz
%
%
119
23.7. CKM Characteristics
Parameter
Test Condition
Supply Voltage
TA = -40°C to +85°C
Clock Input Range
TA = -40°C to +85°C
CKM Start-up Time
TA = -40°C to +85°C
CKM Power Consumption
TA = +25°C, VDD=5.0V
(1)
Data guaranteed by design, not tested in production.
(2)
Data based on characterization results, not tested in production.
Min.
2.4
(1)
5
Limits
Typ.
6
10
650
Unit
Max.
5.5
(1)
6.5
20
V
MHz
us
uA
23.8. OTP Characteristics
Parameter
Supply Voltage
Program Voltage (VPP)
Access Time
Byte program time
Data Retention
Test Condition
TA = -40°C to +85°C
TA = -40°C to +85°C
TA = -40°C to +85°C
TA = -40°C to +85°C
TA = +85°C
Min.
3
7.25
Limits
Typ.
7.5
Unit
Max.
5
7.75
200
100
10
V
V
ns
us
year
23.9. Serial Port 0 Timing Characteristics
VDD = 5.0V±10%, VSS = 0V, TA = -40℃ to +85℃, unless otherwise specified
URM0X3 = 0
URM0X3 = 1
Symbol
Parameter
Min.
Max.
Min.
Max.
Serial
Port
0
Clock
Cycle
Time
tXLXL
12T
4T
Output Data Setup to Clock Rising Edge
tQVXH
10T-20
T-20
Output Data Hold after Clock Rising Edge
tXHQX
T-10
T-10
Input Data Hold after Clock Rising Edge
tXHDX
0
0
Clock Rising Edge to Input Data Valid
tXHDV
10T-20
4T-20
Unit
TSYSCLK
ns
ns
ns
ns
Figure 23–2. Shift Register Mode Timing Waveform (n=0)
120
MG74PG1A08 Data Sheet
MEGAWIN
24. Instruction Set
Table 24–1. Instruction Set
MNEMONIC
DESCRIPTION
BYTE
EXECUTION
Cycles
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
1
1
1
1
2
2
1
2
1
1
1
2
2
2
2
4
2
3
3
4
4
3
3
3
3
3
4
4
Not Support
Not Support
Not Support
Not Support
Not Support
Not Support
Not Support
Not Support
4
3
3
4
4
4
1
2
1
2
1
2
1
2
1
2
1
2
3
3
2
2
3
3
2
2
3
3
DATA TRASFER
MOV A,Rn
Move register to Acc
MOV A,direct
Move direct byte o Acc
MOV A,@Ri
Move indirect RAM to Acc
MOV A,#data
Move immediate data to Acc
MOV Rn,A
Move Acc to register
MOV Rn,direct
Move direct byte to register
MOV Rn,#data
Move immediate data to register
MOV direct,A
Move Acc to direct byte
MOV direct,Rn
Move register to direct byte
MOV direct,direct
Move direct byte to direct byte
MOV direct,@Ri
Move indirect RAM to direct byte
MOV direct,#data
Move immediate data to direct byte
MOV @Ri,A
Move Acc to indirect RAM
MOV @Ri,direct
Move direct byte to indirect RAM
MOV @Ri,#data
Move immediate data to indirect RAM
MOV DPTR,#data16
Load DPTR with a 16-bit constant
MOVC A,@A+DPTR
Move code byte relative to DPTR to Acc
MOVC A,@A+PC
Move code byte relative to PC to Acc
MOVX A,@Ri
Move on-chip auxiliary RAM(8-bit address) to Acc
MOVX A,@DPTR
Move on-chip auxiliary RAM(16-bit address) to Acc
MOVX @Ri,A
Move Acc to on-chip auxiliary RAM(8-bit address)
MOVX @DPTR,A
Move Acc to on-chip auxiliary RAM(16-bit address)
MOVX A,@Ri
Move external RAM(8-bit address) to Acc
MOVX A,@DPTR
Move external RAM(16-bit address) to Acc
MOVX @Ri,A
Move Acc to external RAM(8-bit address)
MOVX @DPTR,A
Move Acc to external RAM(16-bit address)
PUSH direct
Push direct byte onto Stack
POP direct
Pop direct byte from Stack
XCH A,Rn
Exchange register with Acc
XCH A,direct
Exchange direct byte with Acc
XCH A,@Ri
Exchange indirect RAM with Acc
XCHD A,@Ri
Exchange low-order digit indirect RAM with Acc
ARITHEMATIC OPERATIONS
ADD A,Rn
Add register to Acc
ADD A,direct
Add direct byte to Acc
ADD A,@Ri
Add indirect RAM to Acc
ADD A,#data
Add immediate data to Acc
ADDC A,Rn
Add register to Acc with Carry
ADDC A,direct
Add direct byte to Acc with Carry
ADDC A,@Ri
Add indirect RAM to Acc with Carry
ADDC A,#data
Add immediate data to Acc with Carry
SUBB A,Rn
Subtract register from Acc with borrow
SUBB A,direct
Subtract direct byte from Acc with borrow
SUBB A,@Ri
Subtract indirect RAM from Acc with borrow
MEGAWIN
MG74PG1A08 Data Sheet
121
SUBB A,#data
Subtract immediate data from Acc with borrow
INC A
Increment Acc
INC Rn
Increment register
INC direct
Increment direct byte
INC @Ri
Increment indirect RAM
DEC A
Decrement Acc
DEC Rn
Decrement register
DEC direct
Decrement direct byte
DEC @Ri
Decrement indirect RAM
INC DPTR
Increment DPTR
MUL AB
Multiply A and B
DIV AB
Divide A by B
DA A
Decimal Adjust Acc
2
1
1
2
1
1
1
2
1
1
1
1
1
2
2
3
4
4
2
3
4
4
1
4
5
4
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
2
3
3
2
4
4
2
3
3
2
4
4
2
3
3
2
4
4
1
2
1
1
1
1
1
1
2
1
2
1
2
2
2
2
2
1
4
1
4
1
4
3
3
3
3
LOGIC OPERATION
ANL A,Rn
AND register to Acc
ANL A,direct
AND direct byte to Acc
ANL A,@Ri
AND indirect RAM to Acc
ANL A,#data
AND immediate data to Acc
ANL direct,A
AND Acc to direct byte
ANL direct,#data
AND immediate data to direct byte
ORL A,Rn
OR register to Acc
ORL A,direct
OR direct byte to Acc
ORL A,@Ri
OR indirect RAM to Acc
ORL A,#data
OR immediate data to Acc
ORL direct,A
OR Acc to direct byte
ORL direct,#data
OR immediate data to direct byte
XRL A,Rn
Exclusive-OR register to Acc
XRL A,direct
Exclusive-OR direct byte to Acc
XRL A,@Ri
Exclusive-OR indirect RAM to Acc
XRL A,#data
Exclusive-OR immediate data to Acc
XRL direct,A
Exclusive-OR Acc to direct byte
XRL direct,#data
Exclusive-OR immediate data to direct byte
CLR A
Clear Acc
CPL A
Complement Acc
RL A
Rotate Acc Left
RLC A
Rotate Acc Left through the Carry
RR A
Rotate Acc Right
RRC A
Rotate Acc Right through the Carry
SWAP A
Swap nibbles within the Acc
BOOLEAN VARIABLE MANIPULATION
CLR C
Clear Carry
CLR bit
Clear direct bit
SETB C
Set Carry
SETB bit
Set direct bit
CPL C
Complement Carry
CPL bit
Complement direct bit
ANL C,bit
AND direct bit to Carry
ANL C,/bit
AND complement of direct bit to Carry
ORL C,bit
OR direct bit to Carry
ORL C,/bit
OR complement of direct bit to Carry
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MG74PG1A08 Data Sheet
MEGAWIN
MOV C,bit
Move direct bit to Carry
MOV bit,C
Move Carry to direct bit
2
2
3
4
2
2
3
3
3
3
3
4
4
5
2
3
1
1
2
3
2
1
2
2
3
3
3
3
2
3
1
6
6
4
4
3
4
3
3
3
3
5
4
4
5
4
5
1
BOOLEAN VARIABLE MANIPULATION
JC rel
Jump if Carry is set
JNC rel
Jump if Carry not set
JB bit,rel
Jump if direct bit is set
JNB bit,rel
Jump if direct bit not set
JBC bit,rel
Jump if direct bit is set and then clear bit
PROAGRAM BRACHING
ACALL addr11
Absolute subroutine call
LCALL addr16
Long subroutine call
RET
Return from subroutine
RETI
Return from interrupt subroutine
AJMP addr11
Absolute jump
LJMP addr16
Long jump
SJMP rel
Short jump
JMP @A+DPTR
Jump indirect relative to DPTR
JZ rel
Jump if Acc is zero
JNZ rel
Jump if Acc not zero
CJNE A,direct,rel
Compare direct byte to Acc and jump if not equal
CJNE A,#data,rel
Compare immediate data to Acc and jump if not equal
CJNE Rn,#data,rel
Compare immediate data to register and jump if not equal
CJNE @Ri,#data,rel
Compare immediate data to indirect RAM and jump if not equal
DJNZ Rn,rel
Decrement register and jump if not equal
DJNZ direct,rel
Decrement direct byte and jump if not equal
NOP
No Operation
MEGAWIN
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123
25. Package Dimension
25.1. SOP16
124
MG74PG1A08 Data Sheet
MEGAWIN
25.2. QFN16
MEGAWIN
MG74PG1A08 Data Sheet
125
26. Revision History
Table 26–1. Revision History
Rev
page
V0.22
V0.23
V0.24
V0.25
126
112
3,11,125
1.
1.
1.
1.
Descriptions
Preliminary version release.
Added QFN16 package type information.
Added battery power supply application.
Remove SOP10 package type.
MG74PG1A08 Data Sheet
Date
2016/02/01
2016/06/20
2016/08/24
2016/11/16
MEGAWIN
27. Disclaimers
Herein, Megawin stands for “Megawin Technology Co., Ltd.”
Life Support — This product is not designed for use in medical, life-saving or life-sustaining
applications, or systems where malfunction of this product can reasonably be expected to result in
personal injury. Customers using or selling this product for use in such applications do so at their own risk
and agree to fully indemnify Megawin for any damages resulting from such improper use or sale.
Right to Make Changes — Megawin reserves the right to make changes in the products - including
circuits, standard cells, and/or software - described or contained herein in order to improve design and/or
performance. When the product is in mass production, relevant changes will be communicated via an
Engineering Change Notification (ECN).
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