Anpec APW7063 Synchronous buck pwm and linear controller Datasheet

APW7063
Synchronous Buck PWM and Linear Controller
Features
•
General Description
The APW7063 integrates PWM and linear controller, as
well as the monitoring and protection functions into a
Provide Two Regulated Voltages
- Synchronous Rectified Buck PWM Controller
single package. The synchronous PWM controller which
drives dual N-channel MOSFETs, which provides one
- Linear Controller
•
Fast Transient Response
controlled power outputs with under-voltage and overcurrent protections. Linear controller drives an external
- 0~85% Duty Ratio
•
Excellent Output Voltage Regulation
N-channel MOSFET with under-voltage protection.
APW7063 provides excellent regulation for output load
- 0.8V Internal Reference
- ±1% Over Line Voltage and Temperature
•
•
•
variation. An internal 0.8V temperature-compensated reference voltage is designed to meet the various low out-
Over Current Protection
put voltage applications. APW7063 includes a 250kHz
free-running triangle-wave oscillator that is adjustable
- Sense Low-Side MOSFET’s RDS(ON)
Under Voltage Lockout
from 70kHz to 800kHz.
A power-on-reset (POR) circuit limits the VCC minimum
Small Converter Size
- 250kHz Free-Running Oscillator
opearting supply voltage to assure the controller working
well. Over current protection is achieved by monitoring
- Programmable From 70kHz to 800kHz
•
•
14-Lead SOIC Package
the voltage drop across the low side MOSFET, eliminating the need for a current sensing resistor and short cir-
Lead Free and Green Devices Available
(RoHS Compliant)
cuit condition is detected through the FB pin. The overcurrent protection triggers the soft-start function until the
fault events be removed, but Under-voltage protection will
shutdown IC directly.
Applications
•
•
•
•
•
Pull the COMP pin below 0.4V will shutdown the controller,
and both gate drive signals will be low.
Graphic Cards
Memory Power Supplies
Pin Configuration
DSL or Cable MODEMs
Set Top Boxes
Low-Voltage Distributed Power Supplies
RT
1
14
FBL
SS
2
13
DRIVE
VREG
3
12
VCC
FB
4
11
LGATE
COMP
5
10
PGND
GND
6
9
BOOT
PHASE
7
8
UGATE
SOP-14
(Top View)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
1
www.anpec.com.tw
APW7063
Ordering and Marking Information
Package Code
K : SOP-14
Operating Ambient Temperature Range
C : 0 to 70 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APW7063
Assembly Material
Handling Code
Temperature Range
Package Code
APW7063 K :
APW7063
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
Symbol
VCC
LGATE
(Note 1)
Rating
Unit
VCC to GND
Parameter
30
V
LGATE to GND
30
V
DRIVE
DRIVE to GND
30
V
UGATE
UGATE to GND
30
V
VBOOT
BOOT to GND
30
V
PHASE to GND
30
Operating Junction Temperature
TSTG
TSDR
Storage Temperature
Maximum Lead Soldering Temperature, 10 Seconds
V
0~150
o
-65 ~ 150
o
260
o
C
C
C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
θJA
Parameter
Junction to Ambient Resistance in Free Air
Typical Value
Unit
(Note 2)
o
160
SOP-14
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions
Symbol
VCC
VBOOT
Range
Parameter
Unit
Min.
Typ.
Max.
Supply Voltage
8
12
19
V
Boot Voltage
-
-
26
V
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
2
www.anpec.com.tw
APW7063
Electrical Characteristics
Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V, RT = OPEN and TA = 0 ~ 70oC. Typlcal values are
at TA = 25oC.
Symbol
Parameter
Test Conditions
APW7063
Unit
Min.
Typ.
Max.
-
3
-
mA
Rising VCC Threshold
7.0
7.2
7.4
V
Falling VCC Threshold
6.6
6.8
7.0
V
SUPPLY CURRENT
ICC
VCC Nominal Supply
UGATE and LGATE Open
POWER-ON-RESET
OSCILLATOR
Free Running Frequency
RT = OPEN, VCC = 12V
220
250
280
kHz
Total Variation
6kΩ < RT to GND < 200kΩ
-15
-
+15
%
Ramp Amplitude
RT = OPEN
-
1.7
-
VP-P
Reference Voltage
-
0.80
-
V
Reference Voltage Tolerance
-1
-
+1
%
DC Gain
-
75
-
dB
UGATE Duty Range
0
-
85
%
FB Input Current
-
-
0.1
µA
650
800
-
mA
-
4
8
Ω
550
700
-
mA
-
4
8
Ω
-
50
-
nS
-
0.8
-
V
REFERENCE
VREF
PWM EEEOR AMPLIFIER
GATE DRIVERS
IUGATE
Upper Gate Source
VBOOT = 12V, VUGATE = 6V
RUGATE
Upper Gate Sink
IUGATE = 0.3A
ILGATE
Lower Gate Source
VCC = 12V, VLGATE = 6V
RLGATE
Lower Gate Sink
ILGATE = 0.3A
TD
Dead Time
LINEAR REGULATOR
Reference Voltage
Regulation
-
2
-
%
8
10
12
mA
FB Under Voltage Level
-
50
-
%
FBL Under Voltage Level
-
50
-
%
OCSET Source Current
-
250
-
µA
Output Drive Current
VDRIVE = 4V
PROTECTION
VREG
VREG
Output Voltage Accuracy
VCC > 12V
5.5
6
6.5
V
IOUT
Output Current Capacity
VCC = 12V
-
20
-
mA
CSS = 0µF
-
2
-
mS
8
10
12
µA
-
0.4
-
V
-
50
-
mV
SOFT-START AND SHUTDOWN
TSS
Internal Soft-Start Interval
ISS
Soft-Start Charge Current
Shutdown Threshold
COMP Falling
Shutdown Hysteresis
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
3
www.anpec.com.tw
APW7063
Typical Operating Characteristics
Power Up
Power Down
VCC=VIN1=12V
VIN2=5V, CSS=0.1µF
VCC(10V/div)
VCC=VIN1=12V
VIN2=5V, CSS=0.1µF
VCC(10V/div)
SS(5V/div)
SS(5V/div)
VOUT1(2V/div)
VOUT1(2V/div)
VOUT2(2V/div)
VOUT2(2V/div)
Time (10ms/div)
Time (10ms/div)
Enable (COMP is left open)
Shutdown (COMP is pulled to GND)
VCC=VIN1=12V
VIN2=5V, CSS=0.1µF
VCC=VIN1=12V
VIN2=5V, CSS=0.1µF
VOUT2(2V/div)
VOUT2(2V/div)
VOUT1(2V/div)
VOUT1(2V/div)
COMP(1V/div)
COMP(1V/div)
SS(5V/div)
SS(5V/div)
Time (2ms/div)
Time (10ms/div)
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
4
www.anpec.com.tw
APW7063
Typical Operating Characteristics (Cont.)
UGATE Falling
UGATE Rising
VCC=2V, VIN=12V
VCC=2V, VIN=12V
LGATE(10V/div)
LGATE(10V/div)
PHASE(10V/div)
PHASE(10V/div)
UGATE(10V/div)
UGATE(10V/div)
Time (50ns/div)
Time (50ns/div)
Under Voltage Protection (PWM)
IL(10A/div)
Under Voltage Protection (Linear)
VCC=12,VIN=12V
VOUT=3.3V, L=2.2mH
SS(5V/div)
VCC=12V, VIN=5V
VOUT2=2.5V
SS(5V/div)
VOUT2(2V/div)
VOUT1 (2V/div)
UGATE (10V/div)
DRV(5V/div)
Time (5µs/div)
Time (5µs/div)
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
5
www.anpec.com.tw
APW7063
Typical Operating Characteristics (Cont.)
PWM Load Transient
Linear Load Transient
VCC=12V
VIN=12V
VOUT=3.3V
COUT=470mFx2
ESR=22.5mW
L=1.5mH
f=400kHz
VCC=12V
VIN=12V
VOUT=2.5V
COUT=470mF
VOUT2(100mV/div)
VOUT1(100mV/div)
IOUT2(1A/div)
IOUT1(5A/div)
Time (20µs/div)
Time (10µs/div)
UGATE Sink Current vs. UGATE Voltage
UGATE Source Current vs. UGATE Voltage
1.2
VBOOT=12V
VBOOT=12V
1.2
1
UGATE Sink Current (A)
UGATE Source Current (A)
1.4
1
0.8
0.6
0.4
0.2
0.8
0.6
0.4
0.2
0
0
0
2
4
6
8
10
0
12
4
6
8
10
12
UGATE Voltage (V)
UGATE Voltage (V)
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
2
6
www.anpec.com.tw
APW7063
Typical Operating Characteristics (Cont.)
LGATE Source Current vs. LGATE Voltage
LGATE Sink Current vs. LGATE Voltage
1.4
1.2
VCC=12V
VCC=12V
1
1
LGATE Sink Current (A)
LGATE Source Current (A)
1.2
0.8
0.6
0.4
0.2
0.8
0.6
0.4
0.2
0
0
0
2
4
6
8
10
12
0
LGATE Voltage (V)
2
4
6
8
10
12
LGATE Voltage (V)
Over Current Protection
VCC=12V,VIN=12V, VOUT=2.5V, ROCSET=1kW
RDS(ON)=16mW, L=2.2mH, IOUT=15A
Switching Frequence vs. RT Resistance
10000
IL(10A/div)
RT pull up to 12V
RT Resistance (kΩ)
1000
SS(5V/div)
UGATE(20V/div)
100
RT pull down to GND
10
1
VOUT1(2V/div)
10
Time (5µs/div)
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
100
1000
Switching Frequency (kHz)
7
www.anpec.com.tw
APW7063
Typical Operating Characteristics (Cont.)
Comp Source Current vs. Comp Voltage
Comp Sink Current vs. Comp Voltage
150
150
VCC=12V
VCC=12V
125
Source Current (µA)
Sink Current (µA)
125
100
75
50
25
100
75
50
25
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
1
1.5
Comp Voltage (V)
2
2.5
3
4
Drive Source Current vs. Drive Voltage
Drive Sink Current vs. Drive Voltage
40
10
VCC=12V
VCC=12V
8
30
Source Current (mA)
Sink Current (mA)
3.5
Comp Voltage (V)
6
4
2
20
10
0
0
0
2
4
6
8
10
0
12
Drive Voltage (V)
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
2
4
6
8
10
12
Drive Voltage (V)
8
www.anpec.com.tw
APW7063
Typical Operating Characteristics (Cont.)
VREG Voltage vs. Supply Voltage
VREG Voltage vs. Load Current
6
6.5
VCC=12V
VREG Voltage (V)
VREG Voltage (V)
5.5
5
4.5
6.25
6
5.75
4
5.5
0
2
4
6
8
10
12
14
16
18
0
5
Supply Voltage (V)
10
15
20
Load Current (mA)
Supply Current vs. Supply Voltage
Reference Voltage vs. Temperature
4
0.8
ICC
3
Reference Voltage (V)
Supply Current (mA)
3.5
2.5
2
ICC(SHDN)
1.5
1
0.798
0.796
0.794
0.792
0.5
0.79
0
0
2
4
6
8
10
-40
12
Supply Voltage (V)
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
-20
0
20
40
60
80
100 120
Temperature (°C)
9
www.anpec.com.tw
APW7063
Typical Application Circuit
1. Boot-Strap - Use Internal Regulator
12V
C1
1µF
5V
3V3
+ C3
470µF
6.3V
25mR
2
Q1
APM3055L
VINR1
R3
NC
NC
1
2
3
4
5
6
7
C7
0.1µF
1
R14
0R
3
+ C10
470µF
6.3V
25mR
C2
1µF
C11
4.7µF
R5
3.125kF
1%
R13
0R
U1
APW7063
RT
FBL
SS
DRIVE
VREG
VCC
FB
LGATE
COMP PGND
GND
BOOT
PHASEUGATE
C19
220pF
R7
1kF
1%
D1
1N4148
14
13
12
11
10
9
8
L1
1µH
R2
2R2
R4
0R
C12
0.1µF
4
R6
620R
C16
0.01µF
C17
56pF
C4
4.7µF
8
7
6
5
C8
1µF
4
R9
0R
1
2
3
12V
VIN
+C5
+ C9
470µF
470µF
16V
16V
25mR
25mR
+C6
470µF
16V
25mR
Q2
APM4220
8
7
6
5
Q3
APM4220
1
2
3
2.5V
L2
2.2µH
D2
SR24
2A/40V
R8
NC
R10
2.32kF
1%
+
+
C13
C14
1000µF 1000µF
6.3V
6.3V
30mR
30mR
C15
4.7µF
C18
NC
R11
20K
SHDN
R12
1.07kF
1%
2. Boot-Strap - Use External Power
12V
5V
D1
1N4148
C1
1µF
+ C2
470µF
6.3V
25mR 2
3V3
VIN R2
R3
Q1
APM3055L
1
C10
4.7µF
C4
0.1µF
R14
0R
1
2
3
4
5
6
7
R13
0R
3
+C9
470µF
6.3V
25mR
U1
NC
NC
R5
3.125kF
1%
R8
1kF
1%
C19
220pF
APW7063
RT
FBL
SS
DRIVE
VREG
VCC
FB
LGATE
COMP PGND
GND
BOOT
PHASEUGATE
14
13
12
11
10
9
8
C8
1µF
R4
0R
C11
0.1µF
C16
56pF
4
R6
820R
R9
0R
C15
0.01µF
R11
20K
SHDN
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
12V
L1
1µH
R1
2R2
4
8
7
6
5
Q2
APM4220
1
2
3
8
7
6
5
Q3
APM422
01
2
3
C3
4.7µF
VIN
+ C7
470µF
16V
25mR
+ C5
+ C6
470µF
470µF
16V
16V
25mR
25mR
L2
2.2µH
D2
SR24
2A/40V
2.5V
+
R7
100R
R10
2.32kF
1%
C12
1000µF
6.3V
30mR
+
C13
C14
1000µF 4.7µF
6.3V
30mR
C17
0.1µF
R12
1.07kF
1%
10
www.anpec.com.tw
APW7063
Block Diagram
SS
VCC
BOOT
vcc
Power-On
Reset
ISS
10µA
5.8V
Gate Control
UGATE
vcc
Soft Start
and
Fault Logic
GND
IOCSET
250µA
PHASE
VCC
50%VREF
:2
O.C.P
Comparator
U.V.P
Comparator
LGATE
PGND
50%VREF
Error Amp
PWM
Comparator
FBL
:2
VCC
VCC
DRIVE
VREF
Oscillator
Regulator
Triangle
Wave
FB
COMP
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
RT
VREF
VREG
11
www.anpec.com.tw
APW7063
Function Pin Description
RT (Pin 1)
VOLTAGE
VSOFT-START
This pin can adjust the switching frequency. Connect a
resistor from RT to VCC for decreasing the switching
frequency. Conversely, connect a resistor from RT to GND
for increasing the switching frequency (See Typical
VOUT2
Characteristics).
VOUT1
SS (Pin 2)
Connect a capacitor from this pin to GND to set the softstart interval of the converter. An internal 10µA current
source charges this capacitor to 5.2V. The SS voltage
clamps the reference voltage to the SS voltage, and Fig-
FB
t0
ure1 shows the soft-start interval. At t0, the internal source
current starts to charge the capacitor and the internal 0.8V
TIME
t3
An internal regulator will supply 6V for boost voltage, a
1µF capacitor to GND is recommended for stability. If the
the output2 is the same as the output1, but it starts from
the SS at 2.2V to 3.0V. The APW7063 also provides the
VREG voltage has variation by other interference, the IC
can not work normally. When the VCC<8V, don’t use the
internal Soft-Start which is fixed to 2ms (t0 to t1). If the
VREG for BOOST voltage.
external Soft-Start interval is slower than the internal SoftStart interval (CSS<0.025µF) or no external capacitor,
FB (Pin 4)
the Soft-Start will follow the internal Soft-Start.
FB pin is the inverting input of the error amplifier, and it
C SS
TSoft-Start = t1 - t0 =
× 0.8V
I SS
C SS
t3 = t2 +
× 0.8V
I SS
receives the feedback voltage from an external resistive
divider across the output (VOUT). The output voltage is determined by :


VOUT = 0.8V × 1 +
Where:
CSS = external Soft-Start capacitor
ROUT 

RGND 
where ROUT is the resistor connected from VOUT to FB,
ISS = Soft-Start current = 10µA
ISS
t2
VREG (Pin 3)
terval is completed. This method provides a rapid and
controlled output voltage rise. The way of the Soft-Start of
t2 =
t1
Figure 1. Soft-Start Interval
reference also starts to rise and follows the SS. Until the
internal reference reaches to 0.8V at t2, the soft-start in-
CSS
FBL
and RGND is the resistor connected from FB to GND.
× 2.2 V
When the FB voltage is under 50% Vref, it will cause the
under voltage protection and shutdown the device. Remove the condition and restart the VCC voltage or pull the
COMP from low to high once will enable the device again.
COMP (Pin 5)
This pin is the output of the error amplifier. Add an external resistor and capacitor network to provide the loop
compensation for the PW M converter (See Application Information).
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
12
www.anpec.com.tw
APW7063
Function Pin Description (Cont.)
COMP (Pin 5) (Cont.)
A 1µF decoupling capacitor to GND is recommended.
Pull this pin below 0.4V will shutdown the controller, forcing the UGATE and LGATE signals to be 0V. A soft-start
DRIVE (Pin 13)
Connect this pin to the gate of an external N-channel
cycle will be initiated upon the release of this pin.
MOSFET transistor. This pin provides the gate voltage for
the linear regulator pass transistor. It also provides a
GND (Pin 6)
means of compensating the linear controller for applications where the user needs to optimize the regulator tran-
Signal ground for the IC.
PHASE (Pin 7)
sient response.
A resistor (ROCSET) is connected between this pin and the
FBL (Pin 14)
drain of the low-side MOSFET will determine the over
current limit. An internal 250µA current source will flow
Connect this pin to the output of the linear regulator via a
proper sized resistor divider. The voltage at this pin is
through this resistor, creating a voltage drop. This voltage will be compared with the voltage across the low-
regulated to 0.8V and the output voltage is determined
using the following equation :
side MOSFET. The threshold of the over current limit is
therefore given by :
R OCSET =


VOUT = 0.8V ×  1 +
ILIMIT × R DS(ON)
250uA
ROUT 

RGND 
where ROUT is the resistor connected from VOUT to FBL,
An over current condition will cycle the soft-start function
until the over current condition is removed. Because of
and RGND is the resistor connected from FBL to GND.
the comparator delay time, the on time of the low-side
MOSFET must be longer than 800ns to have the over
This pin also monitores the under-voltage events. If the
linear regulator is not used, tie the FBL to VREG.
current protection work.
UGATE (Pin 8)
This pin provides gate drive for the high-side MOSFET.
BOOT (Pin 9)
This pin provides the supply voltage to the high side
MOSFET driver. For driving logic level N-channel MOSEFT,
a bootstrap circuit can be used to create a suitable driver’s
supply.
PGND (Pin 10)
Power ground for the gate diver. Connect the lower
MOSFET source to this pin.
LGATE (Pin 11)
This pin provides the gate drive signal for the low side
MOSFET.
VCC (Pin 12)
This pin provides a supply voltage for the device. When
VCC is above the rising threshold 4.2V, it turns on the
device is turned on. Conversely, when VCC is below the
falling threshold 3.9V, the device is turned off.
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
13
www.anpec.com.tw
APW7063
Application Information
Component Selection Guidelines
ripple current to be approximately 30% of the maximum
Output Capacitor Selection
output current.
Once the inductance value has been chosen, selecting
The selection of COUT is determined by the required effective series resistance (ESR) and voltage rating rather than
an inductor is capable of carrying the required peak current without going into saturation. In some types of
the actual capacitance requirement. Therefore, selecting
high performance low ESR capacitors is intended for
inductors, especially core that is make of ferrite, the ripple
current will increase abruptly when it saturates. This will
switching regulator applications. In some applications,
multiple capacitors have to be paralled to achieve the
result in a larger output ripple voltage.
Compensation
desired ESR value. If tantalum capacitors are used, make
sure they are surge tested by the manufactures. If in doubt,
The output LC filter of a step down converter introduces a
double pole, which contributes with –40dB/decade gain
consult the capacitors manufacturer.
slope and 180 degrees phase shift in the control loop. A
compensation network between COMP pin and ground
Input Capacitor Selection
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, select
should be added. The simplest loop compensation network is shown in Figure 5.
The output LC filter consists of the output inductor and
output capacitors. The transfer function of the LC filter is
the capacitor voltage rating to be at least 1.3 times higher
than the maximum input voltage. The maximum RMS
current rating requirement is approximately IOUT/2 where
IOUT is the load current. During power up, the input capaci-
given by:
tors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge tested
GAINLC =
by the manufactures. If in doubt, consult the capacitors
1+ s × ESR× COUT
s × L × COUT + s × ESR× COUT + 1
2
The poles and zero of this transfer function are:
manufacturer.
For high frequency decoupling, a ceramic capacitor between 0.1µF to 1µF can connect between VCC and ground
FLC =
pin.
FESR =
Inductor Selection
1
2 × π × L × COUT
1
2 × π × ESR × COUT
The inductance of the inductor is determined by the out-
The FLC is the double poles of the LC filter, and FESR is
put voltage requirement. The larger the inductance, the
lower the inductor’s current ripple. This will translate into
the zero introduced by the ESR of the output capacitor.
lower output ripple voltage. The ripple current and ripple
voltage can be approximated by:
IRIPPLE =
VIN - VOUT
Fs x L
x
PHASE
L
Output
V OUT
C OUT
VIN
ESR
where Fs is the switching frequency of the regulator.
∆VOUT = IRIPPLE x ESR
Figure 2. The Output LC Filter
A tradeoff exists between the inductor’s ripple current and
the regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current and vice
versa. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
14
www.anpec.com.tw
APW7063
Application Information (Cont.)
Compensation (Cont.)
The pole and zero of the compensation network are:
FP =
F LC
-40dB/dec
FZ
FESR
Gain
=
1
2 × π × R3 ×
1
C1× C2
C1 + C2
2 × π × R3 × C1
V OUT
-20dB/dec
E rror
A m plifier
R1
FB
-
Frequency
Figure 3. The LC Filter Gain & Frequency
R2
COMP
+
The PWM modulator is shown in Figure 4. The input is
the output of the error amplifier and the output is the PHASE
R3
V REF
C2
C1
node. The transfer function of the PWM modulator is given
by:
GAINPWM =
V IN
Figure 5. Compensation Network
∆ V OSC
The closed loop gain of the converter can be written as:
VIN
Driver
GAINLC x GAINPWM x
PWM
Comparator
R2
x GAINAMP
R1+ R2
Figure 6 shows the converter gain and the following guidelines will help to design the compensation network.
VOSC
1.Select the desired zero crossover frequency FO:
Output of
Error
Amplifier
(1/5 ~ 1/10) x FS >FO>FZ
Use the following equation to calculate R3:
PHASE
R3 =
Driver

= gm ×


1 
1 
 //

sC1  sC2 
R2
×
FO
gm
Calculate the C1 by the equation:
C1 =
1
2 × π × R1× 0.75 × FLC
3. Set the pole at the half the switching frequency:
FP = 0.5xFS

 × C2
R3 × C1 × C2 
C1 + C2
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
R1 + R2
FLC:
FZ = 0.75 x FLC
1


s +

R3 × C1 

s × s +
×
2.Place the zero FZ before the LC filter double poles
C1 introduce a zero and C2 introduces a pole to reduce
the switching noise. The transfer function of error ampli-

F LC
2
gm = 900µA/V
The compensation circuit is shown in Figure 5. R3 and
GAINAMP = gm× Zo = gm ×  R3 +
V IN
F ESR
×
Where:
Figure 4. The PWM Modulator
fier is given by:
∆ V OSC
15
www.anpec.com.tw
APW7063
Application Information (Cont.)
Linear Regulator Input/Output Capacitor Selection
Compensation (Cont.)
Calculate the C2 by the equation:
C2 =
The input capacitor is chosen based on its voltage rating.
Under load transient condition, the input capacitor will
C1
π × R3 × C1 × F S − 1
momentarily supply the required transient current. A 1µF
ceramic capacitor will be sufficient in most applications.
The output capacitor for the linear regulator is chosen to
minimize any droop during load transient condition. In
F Z=0.75FLC
20 ⋅log(gm⋅R3)
addition, the capacitor is chosen based on its voltage
rating.
F P=0.5FS
Compensation Gain
Linear Regulator MOSFET Selection
The maximum DRIVE voltage is determined by the VCC.
Since this pin drives an external N-channel MOSFET, the
Gain
FLC
20 ⋅ log
maximum output voltage of the linear regulator is dependent upon the VGS.
FO
VIN
? VOSC
F ESR
Converter
Gain
PWM &
Filter Gain
VOUT2MAX = VCC- VGS
Another criteria is its efficiency of heat removal. The power
dissipated by the MOSFET is given by:
Frequency
Figure 6. Converter Gain & Frequency
Pdiss = Iout * (VIN - VOUT2)
where Iout is the maximum load current
MOSFET Selection
Vout2 is the nominal output voltage
The selection of the N-channel power MOSFETs is determined by the RDS(ON), reverse transfer capacitance (CRSS),
and maximum output current requirement.The losses in
In some applications, heatsink may be required to help
maintain the junction temperature of the MOSFET below
its maximum rating.
the MOSFETs have two components: conduction loss and
transition loss. For the upper and lower MOSFET, the
Layout Consideration
losses are approximately given by the following equations:
In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In
2
PUPPER = Iout (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS
2
general, interconnecting impedances should be minimized by using short and wide printed circuit traces. Sig-
PLOWER = Iout (1+ TC)(RDS(ON))(1-D)
where IOUT is the load current
TC is the temperature dependency of RDS(ON)
nal and power grounds are to be kept separate and finally
combined using ground plane construction or single point
FS is the switching frequency
tsw is the switching interval
grounding. Figure 8 illustrates the layout, with bold lines
indicating high current paths. Components along the bold
D is the duty cycle
lines should be placed close together. Below is a checklist for your layout:
Note that both MOSFETs have conduction losses while
the upper MOSFET include an additional transition loss.
• Keep the switching nodes (UGATE, LGATE, and PHASE)
The switching internal, tsw, is the function of the reverse
transfer capacitance CRSS. Figure 7 illustrates the switch-
away from sensitive small signal nodes since these
nodes are fast moving signals. Therefore, keep traces
ing waveform internal of the MOSFET.
The (1+TC) term factors in the temperature dependency
to these nodes as short as possible.
• The ground return of CIN must return to the combine
COUT (-) terminal.
of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET.
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
16
www.anpec.com.tw
APW7063
Application Information (Cont.)
Layout Consideration (Cont.)
• Capacitor CBOOT should be connected as close to
the BOOT and PHASE pins as possible.
Voltage across
drain and source of MOSFET
VDS
t sw
Time
Figure 7. Switching waveform across MOSFET
VIN
C IN
APW7063
PGND
11
+
LGATE 12
U
9
1 UGATE
C OUT
Q1
Q2
PHASE 8
+
L1
L
O
A
D
VOUT
Figure 8. Recommended Layout Diagram
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
17
www.anpec.com.tw
APW7063
Package Information
SOP-14
D
E
E1
SEE VIEW A
h X 45
°
e
c
0.25
A
GAUGE PLANE
SEATING PLANE
A1
A2
b
L
VIEW A
S
Y
M
B
O
L
SOP-14
INCHES
MILLIMETERS
MIN.
MAX.
A
MIN.
MAX.
1.75
0.069
0.010
0.004
0.25
A1
0.10
A2
1.25
b
0.31
0.51
0.012
0.020
c
0.17
0.25
0.007
0.010
D
8.55
8.75
0.337
0.344
5.80
6.20
0.228
0.244
3.80
4.00
0.150
0.157
0.020
0.050
E
E1
e
0.049
1.27 BSC
0.050 BSC
h
0.25
0.50
0.010
L
0.40
1.27
0.016
0
0°
8°
0°
8°
Note: 1. Follow JEDEC MS-012 AB.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
18
www.anpec.com.tw
APW7063
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
SOP-14
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
16.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
16.0±0.30
1.75±0.10
7.50±0.10
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
9.00±0.20
2.10±0.20
4.0±0.10
8.0±0.10
(mm)
Devices Per Unit
Package Type
Unit
Quantity
SOP-14
Tape & Reel
2500
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
19
www.anpec.com.tw
APW7063
Taping Direction Information
SOP-14
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
20
www.anpec.com.tw
APW7063
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
21
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
www.anpec.com.tw
APW7063
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
22
www.anpec.com.tw