Data sheet acquired from Harris Semiconductor SCHS225 CD74AC04, CD74ACT04, CD74AC05, CD74ACT05 Hex Inverters September 1998 Features Description • CD74AC04, CD74ACT04 . . . . . . . . . . . . Active Outputs The CD74AC04, CD74ACT04, CD74AC05 and CD74ACT05 are hex inverters that utilize the Harris Advanced CMOS Logic technology. • CD74AC05, CD74ACT05 . . . . . . . . Open-Drain Outputs • Buffered Inputs Ordering Information • Typical Propagation Delay - 3.5ns at VCC = 5V, TA = 25oC, CL = 50pF [ /Title (CD74 AC04, CD74 ACT04 , CD74 AC05, CD74 ACT05 ) /Subject (Hex Inverters) /Autho r () /Keywords (Harris Semiconductor, Advan ced CMOS , Harris Semiconductor, Advan PART NUMBER TEMP. RANGE (oC) PKG. NO. PACKAGE • Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 CD74AC04E -55 to 125 14 Ld PDIP E14.3 CD74ACT04E -55 to 125 14 Ld PDIP E14.3 • SCR-Latchup-Resistant CMOS Process and Circuit Design CD74AC05E -55 to 125 14 Ld PDIP E14.3 CD74ACT05E -55 to 125 14 Ld PDIP E14.3 • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption CD74AC04M -55 to 125 14 Ld SOIC M14.15 CD74ACT04M -55 to 125 14 Ld SOIC M14.15 CD74AC05M -55 to 125 14 Ld SOIC M14.15 CD74ACT05M -55 to 125 14 Ld SOIC M14.15 • Balanced Propagation Delays • AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply NOTES: • ±24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50Ω Transmission Lines 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. Pinout Functional Diagram CD74AC04, CD74ACT04, CD74AC05, CD74ACT05 (PDIP, SOIC) TOP VIEW 1 2 3 4 5 6 9 8 11 10 1A 2A 1A 1 14 VCC 1Y 2 13 6A 2A 3 12 6Y 3A 1Y 2Y 3Y 4Y 4A 2Y 4 11 5A 3A 5 10 5Y 3Y 6 9 4A GND 7 5Y 5A 12 13 6Y 6A 8 4Y GND = 7 VCC = 14 TRUTH TABLE CD74AC/ACT04 CD74AC/ACT05 INPUT OUTPUT INPUT OUTPUT L H L Z H L H L Z = High Impedance CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a Trademark of Fairchild Semiconductor. Copyright © Harris Corporation 1998 1 File Number 1945.1 CD74AC04, CD74ACT04, CD74AC05, CD74ACT05 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA Thermal Resistance (Typical, Note 5) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 4) AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. For up to 4 outputs per device, add ±25mA for each additional output. 4. Unless otherwise specified, all voltages are referenced to ground. 5. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VIH - - 1.5 1.2 - 1.2 - 1.2 - V 3 2.1 - 2.1 - 2.1 - V AC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage (04) VIL VOH - VIH or VIL - -0.05 5.5 3.85 - 3.85 - 3.85 - V 1.5 - 0.3 - 0.3 - 0.3 V 3 - 0.9 - 0.9 - 0.9 V 5.5 - 1.65 - 1.65 - 1.65 V 1.5 1.4 - 1.4 - 1.4 - V -0.05 3 2.9 - 2.9 - 2.9 - V -0.05 4.5 4.4 - 4.4 - 4.4 - V -4 3 2.58 - 2.48 - 2.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 (Note 6, 7) 5.5 - - 3.85 - - - V -50 (Note 6, 7) 5.5 - - - - 3.85 - V 2 CD74AC04, CD74ACT04, CD74AC05, CD74ACT05 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 - 0.1 V 0.05 3 - 0.1 - 0.1 - 0.1 V 0.05 4.5 - 0.1 - 0.1 - 0.1 V 12 3 - 0.36 - 0.44 - 0.5 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 6, 7) 5.5 - - - 1.65 - - V 50 (Note 6, 7) 5.5 - - - - - 1.65 V II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 4 - 40 - 80 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - 0.8 - 0.8 - 0.8 V High Level Output Voltage (04) VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - 4.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V Input Leakage Current Quiescent Supply Current, SSI ACT TYPES Low Level Output Voltage Input Leakage Current Quiescent Supply Current, SSI Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load VOL VIH or VIL -75 5.5 - - 3.85 - - - V -50 5.5 - - - - 3.85 - V 0.05 4.5 - 0.1 - 0.1 - 0.1 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 6, 7) 5.5 - - - 1.65 - - V 50 (Note 6, 7) 5.5 - - - - - 1.65 V II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 4 - 40 - 80 µA ∆ICC VCC -2.1 - 4.5 to 5.5 - 2.4 - 2.8 - 3 mA NOTES: 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC. ACT Input Load Table INPUT UNIT LOAD nA 0.18 NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC. 3 CD74AC04, CD74ACT04, CD74AC05, CD74ACT05 Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) -40oC TO 85oC PARAMETER -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS tPLH, tPHL 1.5 - - 74 - - 81 ns 3.3 (Note 9) 2.3 - 8.3 2.3 - 9.1 ns 5 (Note 10) 1.7 - 5.9 1.6 - 6.5 ns 1.5 - - 74 - - 81 ns 3.3 2.3 - 8.3 2.3 - 9.1 ns 5 1.7 - 5.9 1.6 - 6.5 ns AC TYPES Propagation Delay, Input to Output (CD74AC/ACT04) Propagation Delay, High Z to Output Low (CD74AC/ACT05) Propagation Delay, Output Low to High Z (CD74AC/ACT05) tPZL tPLZ 1.5 - - 94 - - 103 ns 3.3 3 - 10.4 2.9 - 11.5 ns 5 2.2 - 7.5 2.1 - 8.2 ns CI - - - 10 - - 10 pF CPD (Note 11) - - 105 - - 105 - pF tPLH, tPHL 5 (Note 10) 2.4 - 8.5 2.3 - 9.3 ns Propagation Delay, Output Low to High Z tPLZ 5 2.8 - 9.8 2.7 - 10.8 ns Propagation Delay, High Z to Output Low (CD74AC/ACT05) tPZL 5 2.4 - 8.5 2.3 - 9.3 ns CI - - - 10 - - 10 pF CPD (Note 11) - - 105 - - 105 - pF Input Capacitance Power Dissipation Capacitance ACT TYPES Propagation Delay, Input to Output (CD74AC/ACT04) Input Capacitance Power Dissipation Capacitance NOTES: 8. Limits tested at 100%. 9. 3.3V Min at 3.6V, Max at 3V. 10. 5V Min at 5.5V, Max at 4.5V. 11. CPD is used to determine the dynamic power consumption per gate. AC: PD = VCC2 fi (CPD + CL) ACT: PD = VCC2 fi (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage. tr OUTPUT RL (NOTE) 500Ω tf 90% VS GND INPUT DUT OUTPUT LOAD CL 50pF OUTPUT NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ. Input Level VS tPHL CD74AC CD74ACT VCC 3V Input Switching Voltage, VS 0.5 VCC 1.5V Output Switching Voltage, VS 0.5 VCC 0.5 VCC tPLH FIGURE 2. WAVEFORMS FIGURE 1. PROPAGATION DELAY TIMES 4 CD74AC04, CD74ACT04, CD74AC05, CD74ACT05 INPUT LEVEL nA VS VS tPZL tPLZ VS nY 20% OUTPUT LOW OUTPUT OFF OUTPUT LOW 500Ω VCC nA 50pF 500Ω FIGURE 3. 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