LM193JAN www.ti.com SNOSAN2A – MAY 2005 – REVISED MARCH 2013 LM193JAN Low Power Low Offset Voltage Dual Comparators Check for Samples: LM193JAN FEATURES DESCRIPTION • The LM193 series consists of two independent precision voltage comparators with an offset voltage specification as low as 2.0 mV max for two comparators which were designed specifically to operate from a single power supply over a wide range of voltages. Operation from split power supplies is also possible and the low power supply current drain is independent of the magnitude of the power supply voltage. These comparators also have a unique characteristic in that the input common-mode voltage range includes ground, even though operated from a single power supply voltage. 1 2 • • • • • • • • Wide Supply – Voltage Range: 5.0VDC to 36VDC – Single or Dual Supplies: ±2.5VDC to ±18VDC Very Low Supply Current Drain (0.4 mA) — Independent of Supply Voltage Low Input Biasing Current: 25 nA typ Low Input Offset Current: ±3 nA typ Maximum Offset Voltage +5mV Max @ 25°C Input Common-Mode Voltage Range Includes Ground Differential Input Voltage Range Equal to the Power Supply Voltage Low Output Saturation Voltage,: 250 mV at 4 mA typ Output Voltage Compatible with TTL, DTL, ECL, MOS and CMOS Logic Systems ADVANTAGES • • • • • • High Precision Comparators Reduced VOS Drift Over Temperature Eliminates Need for Dual Supplies Allows Sensing Near Ground Compatible with all Forms of Logic Power Drain Suitable for Battery Operation Squarewave Oscillator Application areas include limit comparators, simple analog to digital converters; pulse, squarewave and time delay generators; wide range VCO; MOS clock timers; multivibrators and high voltage digital logic gates. The LM193 series was designed to directly interface with TTL and CMOS. When operated from both plus and minus power supplies, the LM193 series will directly interface with MOS logic where their low power drain is a distinct advantage over standard comparators. Non-Inverting Comparator with Hysteresis 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated LM193JAN SNOSAN2A – MAY 2005 – REVISED MARCH 2013 www.ti.com Schematic and Connection Diagrams Figure 1. TO-99 Figure 2. CDIP Package These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM193JAN LM193JAN www.ti.com SNOSAN2A – MAY 2005 – REVISED MARCH 2013 Absolute Maximum Ratings (1) Supply Voltage, V+ 36VDC or ±18VDC Differential Input Voltage (2) 36V Output Voltage 36V −0.3VDC to +36VDC Input Voltage Input Current (VIN< −0.3VDC) (3) 50 mA Power Dissipation (4) CDIP 400 mW @ TA = 125°C TO-99 330 mW @ TA = 125°C Maximum Junction Temperature (TJmax) 175°C Output Short-Circuit to Ground (5) Continuous −55°C ≤ TA ≤ +125°C Operating Temperature Range −65°C ≤ TA ≤ +150°C Storage Temperature Range TO-99 θJA Thermal Resistance θJC CDIP Metal Can (Still Air) 174°C/W Metal Can (500LF/Min Air flow) 99°C/W CERDIP (Still Air) 146°C/W CERDIP (500LF/Min Air flow) 85°C/W TO-99 44°C/W CDIP 33°C/W Lead Temperature(Soldering, 10 seconds) 260°C ESD Tolerance (6) 500V (1) (2) (3) (4) (5) (6) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3V (or 0.3V below the magnitude of the negative power supply, if used). This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than −0.3VDC. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output current is approximately 20 mA independent of the magnitude of V+. Human body model, 1.5KΩ in series with 100pF. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM193JAN 3 LM193JAN SNOSAN2A – MAY 2005 – REVISED MARCH 2013 www.ti.com Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup Description Temp°C 1 Static tests at 25 2 Static tests at 125 3 Static tests at -55 4 Dynamic tests at 25 5 Dynamic tests at 125 6 Dynamic tests at -55 7 Functional tests at 25 8A Functional tests at 125 8B Functional tests at -55 9 Switching tests at 25 10 Switching tests at 125 11 Switching tests at -55 12 Settling time at 25 13 Settling time at 125 14 Settling time at -55 LM193JAN Electrical Characteristics DC Parameters Symbol Parameter Conditions VIO Input Offset Voltage IIO ±IIB (1) 4 Input offset Current Input Bias Current Min Max Unit +VCC = 30V, -VCC = 0V, VO = 15V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 2V, -VCC = -28V, VO = -13V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 5V, -VCC = 0V, VO = 1.4V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 2V, -VCC = -3V, VO = -1.6V -5.0 5.0 mV 1 +VCC = 30V, -VCC = 0V, VO = 15V, RS = 20KΩ Notes Subgroups -7.0 7.0 mV 2, 3 See (1) -25 25 nA 1, 2 See (1) -75 75 nA 3 (1) 1, 2 +VCC = 2V, -VCC = -28V, VO = -13V, RS = 20KΩ See -25 25 nA See (1) -75 75 nA 3 +VCC = 5V, -VCC = 0V, VO = 1.4V, RS = 20KΩ See (1) -25 25 nA 1, 2 See (1) -75 75 nA 3 +VCC = 2V, -VCC = -3V, VO = -1.6V, RS = 20KΩ See (1) -25 25 nA 1, 2 See (1) -75 75 nA 3 +VCC = 30V, -VCC = 0V, VO = 15V, RS = 20KΩ See (1) -100 +0.1 nA 1, 2 See (1) -200 +0.1 nA 3 +VCC = 2V, -VCC = -28V, VO = -13V, RS = 20KΩ See (1) -100 +0.1 nA 1, 2 See (1) -200 +0.1 nA 3 (1) 1, 2 +VCC = 5V, -VCC = 0V, VO = 1.4V, RS = 20KΩ See -100 +0.1 nA See (1) -200 +0.1 nA 3 +VCC = 2V, -VCC = -3V, VO = -1.6V, RS = 20KΩ See (1) -100 +0.1 nA 1, 2 See (1) -200 +0.1 nA 3 S/S RS = 20KΩ, tested with RS = 100KΩ for better resolution Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM193JAN LM193JAN www.ti.com SNOSAN2A – MAY 2005 – REVISED MARCH 2013 LM193JAN Electrical Characteristics DC Parameters (continued) Symbol Parameter Conditions Notes CMRR Input Voltage Common Mode Rejection 2V ≤ +VCC ≤ 30V, -28V ≤ -VCC ≤ 0V, -13V ≤ VO ≤ 15V 2V ≤ +VCC ≤ 5V, -3V ≤ -VCC ≤ 0V, -1.6V ≤ VO ≤ 1.4V Min Max Unit Subgroups 76 dB 1, 2, 3 70 dB 1, 2, 3 1.0 µA 1, 2, 3 ICEX Output Leakage Current +VCC = 30V, -VCC = 0V, VO = +30V +IIL Input Leakage Current +VCC = 36V, -VCC = 0V, +VI = 34V, -VI = 0V -500 500 nA 1, 2, 3 -500 1, 2, 3 -IIL Input Leakage Current +VCC = 36V, -VCC = 0V, +VI = 0V, -VI = 34V 500 nA VOL Logical "0" Output Voltage +VCC = 4.5V, -VCC = 0V, IO = 4mA 0.4 V 1 0.7 V 2, 3 +VCC = 4.5V, -VCC = 0V, IO = 8mA 1.5 V 1 2.0 V 2, 3 +VCC = 5V, -VCC = 0V, VID = 15mV 2.0 mA 1, 2 3.0 mA 3 +VCC = 30V, -VCC = 0V, VID = 15mV 3.0 mA 1, 2 4.0 mA 3 ICC Power Supply Current ΔIO / ΔT ΔIIO / ΔT AVS (2) (3) Temperature Coefficient of Input Offset Voltage 25°C ≤ TA ≤ +125°C See -25 25 µV/°C 2 -55°C ≤ TA ≤ 25°C See (2) -25 25 µV/°C 3 Temperature Coefficient of Input Offset Current 25°C ≤ TA ≤ +125°C See (2) -300 300 pA/°C 2 -55°C ≤ TA ≤ 25°C See (2) -400 400 pA/°C 3 Open Loop Voltage Gain VLat (2) Voltage Latch (Logical "1" Input) +VCC = 15V, -VCC = 0V, RL = 15KΩ, 1V ≤ VO ≤ 11V See (3) 50 V/mV 4 See (3) 25 V/mV 5, 6 0.4 V 9 Max Unit Subgroups 7, 8B +VCC = 5V, -VCC = 0V, VI = 10V, IO = 4mA Calculated parameter for ΔVIO / ΔT and ΔIIO / ΔT. K in datalog is equivalent to V/mV. AC Parameters The following conditions apply, unless otherwise specified. +VCC = 5V, −VCC = 0V Symbol Parameter Conditions tRLH Response Time VI = 100mV, RL = 5.1KΩ, VOD = 5mV 5.0 µS 7.0 µS 8A VI = 100mV, RL = 5.1KΩ, VOD = 50mV 0.8 µS 7, 8B 1.2 µS 8A VI = 100mV, RL = 5.1KΩ, VOD = 5mV 2.5 µS 7, 8B 3.0 µS 8A VI = 100mV, RL = 5.1KΩ, VOD = 50mV 0.8 µS 7, 8B 1.0 µS 8A tRHL CS Response Time Channel Separation Notes Min +VCC = 20V, -VCC = -10V, A to B 80 dB 7 +VCC = 20V, -VCC = -10V, B to A 80 dB 7 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM193JAN 5 LM193JAN SNOSAN2A – MAY 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics Supply Current Input Current Figure 3. Figure 4. Output Saturation Voltage Response Time for Various Input Overdrives—Negative Transition Figure 5. Figure 6. Response Time for Various Input Overdrives—Positive Transition Figure 7. 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM193JAN LM193JAN www.ti.com SNOSAN2A – MAY 2005 – REVISED MARCH 2013 APPLICATION HINTS The LM193 series are high gain, wide bandwidth devices which, like most comparators, can easily oscillate if the output lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows up only during the output voltage transition intervals as the comparator change states. Power supply bypassing is not required to solve this problem. Standard PC board layout is helpful as it reduces stray input-output coupling. Reducing the input resistors to < 10 kΩ reduces the feedback signal levels and finally, adding even a small amount (1.0 to 10 mV) of positive feedback (hysteresis) causes such a rapid transition that oscillations due to stray feedback are not possible. Simply socketing the IC and attaching resistors to the pins will cause inputoutput oscillations during the small transition intervals unless hysteresis is used. If the input signal is a pulse waveform, with relatively fast rise and fall times, hysteresis is not required. All input pins of any unused comparators should be tied to the negative supply. The bias network of the LM193 series establishes a drain current which is independent of the magnitude of the power supply voltage over the range of from 2.0 VDC to 30 VDC. It is usually unnecessary to use a bypass capacitor across the power supply line. The differential input voltage may be larger than V+ without damaging the device (1). Protection should be provided to prevent the input voltages from going negative more than −0.3 VDC (at 25°C). An input clamp diode can be used as shown in the applications section. The output of the LM193 series is the uncommitted collector of a grounded-emitter NPN output transistor. Many collectors can be tied together to provide an output OR'ing function. An output pull-up resistor can be connected to any available power supply voltage within the permitted supply voltage range and there is no restriction on this voltage due to the magnitude of the voltage which is applied to the V+ terminal of the LM193 package. The output can also be used as a simple SPST switch to ground (when a pull-up resistor is not used). The amount of current which the output device can sink is limited by the drive available (which is independent of V+) and the β of this device. When the maximum current limit is reached (approximately 16mA), the output transistor will come out of saturation and the output voltage will rise very rapidly. The output saturation voltage is limited by the approximately 60Ω rSAT of the output transistor. The low offset voltage of the output transistor (1.0mV) allows the output to clamp essentially to ground level for small load currents. (1) Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3V (or 0.3V below the magnitude of the negative power supply, if used). Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM193JAN 7 LM193JAN SNOSAN2A – MAY 2005 – REVISED MARCH 2013 www.ti.com Typical Applications (V+=5.0 VDC) Basic Comparator Driving CMOS Driving TTL Squarewave Oscillator Pulse Generator Crystal Controlled Oscillator * For large ratios of R1/R2, D1 can be omitted. Figure 8. Two-Decade High Frequency VCO V* = +30 VDC +250 mVDC ≤ VC ≤ +50 VDC 700Hz ≤ fo ≤ 100kHz Basic Comparator 8 Non-Inverting Comparator with Hysteresis Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM193JAN LM193JAN www.ti.com SNOSAN2A – MAY 2005 – REVISED MARCH 2013 Inverting Comparator with Hysteresis Output Strobing AND Gate OR Gate Large Fan-in AND Gate Limit Comparator Comparing Input Voltages of Opposite Polarity ORing the Outputs Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM193JAN 9 LM193JAN SNOSAN2A – MAY 2005 – REVISED MARCH 2013 10 www.ti.com Zero Crossing Detector (Single Power Supply) One-Shot Multivibrator Bi-Stable Multivibrator One-Shot Multivibrator with Input Lock Out Zero Crossing Detector Comparator With a Negative Reference Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM193JAN LM193JAN www.ti.com SNOSAN2A – MAY 2005 – REVISED MARCH 2013 Figure 9. Time Delay Generator Split-Supply Applications (V+=+15 VDC and V−=−15 VDC) Figure 10. MOS Clock Driver Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM193JAN 11 LM193JAN SNOSAN2A – MAY 2005 – REVISED MARCH 2013 www.ti.com REVISION HISTORY SECTION Date Released Revision Section Originator Changes 05/09/05 A New Release. Corporate format L. Lytle 1 MDS datasheets converted into one Corp. datasheet format. DC Drift table was deleted due to no JANS product offerings. MJLM193-X Rev 1A1 MDS will be archived. 03/26/2013 A All Sections 12 Changed layout of National Data Sheet to TI format Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM193JAN PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) (3) Top-Side Markings (4) JL193BGA ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 JL193BGA JM38510/11202BGA Q ACO JM38510/11202BGA Q >T JM38510/11202BGA ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 JL193BGA JM38510/11202BGA Q ACO JM38510/11202BGA Q >T M38510/11202BGA ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 JL193BGA JM38510/11202BGA Q ACO JM38510/11202BGA Q >T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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