TI MSP430F2013IRSAR Mixed signal microcontroller Datasheet

MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
MIXED SIGNAL MICROCONTROLLER
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
Low Supply Voltage Range 1.8 V to 3.6 V
Ultra-Low Power Consumption
– Active Mode: 220 µA at 1 MHz, 2.2 V
– Standby Mode: 0.5 µA
– Off Mode (RAM Retention): 0.1 µA
Five Power-Saving Modes
Ultra-Fast Wake-Up From Standby Mode in
Less Than 1 µs
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
Basic Clock Module Configurations:
– Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies to ±1%
– Internal Very Low-Power Low-Frequency
Oscillator
– 32-kHz Crystal
– External Digital Clock Source
16-Bit Timer_A With Two Capture/Compare
Registers
On-Chip Comparator for Analog Signal
Compare Function or Slope A/D
(MSP430F20x1)
10-Bit 200-ksps A/D Converter With Internal
Reference, Sample-and-Hold, and Autoscan
(MSP430F20x2)
16-Bit Sigma-Delta A/D Converter With
Differential PGA Inputs and Internal Reference
(MSP430F20x3)
Universal Serial Interface (USI) Supporting SPI
and I2C (MSP430F20x2 and MSP430F20x3)
Brownout Detector
•
•
•
•
•
Serial Onboard Programming, No External
Programming Voltage Needed, Programmable
Code Protection by Security Fuse
On-Chip Emulation Logic With Spy-Bi-Wire
Interface
Family Members:
– MSP430F2001
– 1KB + 256B Flash Memory
– 128B RAM
– MSP430F2011
– 2KB + 256B Flash Memory
– 128B RAM
– MSP430F2002
– 1KB + 256B Flash Memory
– 128B RAM
– MSP430F2012
– 2KB + 256B Flash Memory
– 128B RAM
– MSP430F2003
– 1KB + 256B Flash Memory
– 128B RAM
– MSP430F2013
– 2KB + 256B Flash Memory
– 128B RAM
Available in 14-Pin Plastic Small-Outline Thin
Package (TSSOP), 14-Pin Plastic Dual Inline
Package (PDIP), and 16-Pin QFN
For Complete Module Descriptions, See the
MSP430x2xx Family User's Guide (SLAU144)
DESCRIPTION
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430F20xx series is an ultra-low-power mixed signal microcontroller with a built-in 16-bit timer and ten
I/O pins. In addition, the MSP430F20x1 has a versatile analog comparator. The MSP430F20x2 and
MSP430F20x3 have built-in communication capability using synchronous protocols (SPI or I2C) and a 10-bit A/D
converter (MSP430F20x2) or a 16-bit sigma-delta A/D converter (MSP430F20x3).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data for display or for transmission to a host system. Stand alone RF sensor front end is another
area of application.
Table 1. Available Options (1)
TA
(1)
(2)
2
PACKAGED DEVICES (2)
PLASTIC 14-PIN TSSOP (PW)
PLASTIC 14-PIN DIP (N)
PLASTIC 16-PIN QFN (RSA)
-40°C to 85°C
MSP430F2001IPW
MSP430F2011IPW
MSP430F2002IPW
MSP430F2012IPW
MSP430F2003IPW
MSP430F2013IPW
MSP430F2001IN
MSP430F2011IN
MSP430F2002IN
MSP430F2012IN
MSP430F2003IN
MSP430F2013IN
MSP430F2001IRSA
MSP430F2011IRSA
MSP430F2002IRSA
MSP430F2012IRSA
MSP430F2003IRSA
MSP430F2013IRSA
-40°C to 105°C
MSP430F2001TPW
MSP430F2011TPW
MSP430F2002TPW
MSP430F2012TPW
MSP430F2003TPW
MSP430F2013TPW
MSP430F2001TN
MSP430F2011TN
MSP430F2002TN
MSP430F2012TN
MSP430F2003TN
MSP430F2013TN
MSP430F2001TRSA
MSP430F2011TRSA
MSP430F2002TRSA
MSP430F2012TRSA
MSP430F2003TRSA
MSP430F2013TRSA
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Device Pinout, MSP430F20x1
See port schematics section for detailed I/O information.
PW or N PACKAGE
(TOP VIEW)
VCC
1
14
VSS
P1.0/TACLK/ACLK/CA0
2
13
XIN/P2.6/TA1
P1.1/TA0/CA1
3
12
XOUT/P2.7
P1.2/TA1/CA2
4
11
TEST/SBWTCK
P1.3/CAOUT/CA3
5
10
P1.4/SMCLK/CA4/TCK
P1.5/TA0/CA5/TMS
6
9
RST/NMI/SBWTDIO
P1.7/CAOUT/CA7/TDO/TDI
7
8
P1.6/TA1/CA6/TDI/TCLK
15 14
NC
VSS
NC
VCC
RSA PACKAGE
(TOP VIEW)
2
11
XOUT/P2.7
P1.2/TA1/CA2
3
10
TEST/SBWTCK
P1.3/CAOUT/CA3
4
9
Copyright © 2005–2011, Texas Instruments Incorporated
6
7
RST/NMI/SBWTDIO
P1.7/CAOUT/CA7/TDO/TDI
P1.4/SMCLK/CA4/TCK
P1.1/TA0/CA1
P1.6/TA1/CA6/TDI/TCLK
XIN/P2.6/TA1
1
P1.5/TA0/CA5/TMS
12
P1.0/TACLK/ACLK/CA0
3
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Device Pinout, MSP430F20x2
See port schematics section for detailed I/O information.
PW or N PACKAGE
(TOP VIEW)
VCC
1
14
VSS
P1.0/TACLK/ACLK/A0
2
13
XIN/P2.6/TA1
P1.1/TA0/A1
3
12
XOUT/P2.7
P1.2/TA1/A2
4
11
TEST/SBWTCK
P1.3/ADC10CLK/A3/VREF−/VeREF−
5
10
P1.4/SMCLK/A4/VREF+/VeREF+/TCK
P1.5/TA0/A5/SCLK/TMS
6
9
RST/NMI/SBWTDIO
P1.7/A7/SDI/SDA/TDO/TDI
7
8
P1.6/TA1/A6/SDO/SCL/TDI/TCLK
AVSS
DVSS
15 14
12
XIN/P2.6/TA1
2
11
XOUT/P2.7
P1.2/TA1/A2
3
10
TEST/SBWTCK
P1.3/ADC10CLK/A3/VREF−/VeREF−
4
9
6
7
RST/NMI/SBWTDIO
P1.7/A7/SDI/SDA/TDO/TDI
P1.1/TA0/A1
P1.6/TA1/A6/SDO/SCL/TDI/TCLK
1
P1.5/TA0/A5/SCLK/TMS
P1.0/TACLK/ACLK/A0
P1.4/SMCLK/A4/VREF+/VeREF+/TCK
4
AVCC
DVCC
RSA PACKAGE
(TOP VIEW)
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Device Pinout, MSP430F20x3
See port schematics section for detailed I/O information.
PW or N PACKAGE
(TOP VIEW)
VCC
1
14
VSS
P1.0/TACLK/ACLK/A0+
2
13
XIN/P2.6/TA1
P1.1/TA0/A0−/A4+
3
12
XOUT/P2.7
P1.2/TA1/A1+/A4−
4
11
TEST/SBWTCK
P1.3/VREF/A1−
5
10
P1.4/SMCLK/A2+/TCK
P1.5/TA0/A2−/SCLK/TMS
6
9
RST/NMI/SBWTDIO
P1.7/A3−/SDI/SDA/TDO/TDI
7
8
P1.6/TA1/A3+/SDO/SCL/TDI/TCLK
15 14
AVSS
DVSS
AVCC
DVCC
RSA PACKAGE
(TOP VIEW)
2
11
XOUT/P2.7
P1.2/TA1/A1+/A4−
3
10
TEST/SBWTCK
P1.3/VREF/A1−
4
9
Copyright © 2005–2011, Texas Instruments Incorporated
6
7
RST/NMI/SBWTDIO
P1.7/A3−/SDI/SDA/TDO/TDI
P1.4/SMCLK/A2+/TCK
P1.1/TA0/A0−/A4+
P1.6/TA1/A3+/SDO/SCL/TDI/TCLK
XIN/P2.6/TA1
1
P1.5/TA0/A2−/SCLK/TMS
12
P1.0/TACLK/ACLK/A0+
5
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Functional Block Diagram, MSP430F20x1
VCC
VSS
P1.x & JTAG
8
XIN
P2.x &
XIN/XOUT
2
XOUT
ACLK
Basic Clock
System+
SMCLK
MCLK
Flash
RAM
2kB
1kB
128B
128B
Comparator
_A+
8 channel
input mux
Port P1
Port P2
8 I/O
Interrupt
capability,
pull−up/down
resistors
2 I/O
Interrupt
capability,
pull−up/down
resistors
MAB
16MHz
CPU
incl. 16
Registers
MDB
Emulation
(2BP)
JTAG
Interface
Watchdog
WDT+
Brownout
Protection
15/16−Bit
Timer_A2
2 CC
Registers
Spy−Bi Wire
RST/NMI
NOTE: See port schematics section for detailed I/O information.
Functional Block Diagram, MSP430F20x2
VCC
VSS
P1.x & JTAG
8
XIN
P2.x &
XIN/XOUT
2
XOUT
Basic Clock
System+
ACLK
ADC10
SMCLK
MCLK
16MHz
CPU
incl. 16
Registers
Flash
RAM
2kB
1kB
128B
128B
10−bit
8 Channels
Autoscan
DTC
Port P1
Port P2
8 I/O
Interrupt
capability,
pull−up/down
resistors
2 I/O
Interrupt
capability,
pull−up/down
resistors
MAB
MDB
Emulation
(2BP)
JTAG
Interface
USI
Brownout
Protection
Watchdog
WDT+
15/16−Bit
Spy−Bi Wire
Timer_A2
2 CC
Registers
Universal
Serial
Interface
SPI, I2C
RST/NMI
NOTE: See port schematics section for detailed I/O information.
6
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Functional Block Diagram, MSP430F20x3
VCC
VSS
P1.x & JTAG
8
XIN
P2.x &
XIN/XOUT
2
XOUT
Basic Clock
System+
ACLK
SD16_A
SMCLK
MCLK
16MHz
CPU
incl. 16
Registers
Flash
RAM
2kB
1kB
128B
128B
16−bit
Sigma−
Delta A/D
Converter
Port P1
Port P2
8 I/O
Interrupt
capability,
pull−up/down
resistors
2 I/O
Interrupt
capability,
pull−up/down
resistors
MAB
MDB
Emulation
(2BP)
JTAG
Interface
USI
Brownout
Protection
Watchdog
WDT+
15/16−Bit
Spy−Bi Wire
Timer_A2
2 CC
Registers
Universal
Serial
Interface
SPI, I2C
RST/NMI
NOTE: See port schematics section for detailed I/O information.
Copyright © 2005–2011, Texas Instruments Incorporated
7
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Table 2. Terminal Functions, MSP430F20x1
TERMINAL
NAME
NO.
DESCRIPTION
I/O
PW, N
RSA
P1.0/TACLK/ACLK/CA0
2
1
I/O
General-purpose digital I/O pin
Timer_A, clock signal TACLK input
ACLK signal output
Comparator_A+, CA0 input
P1.1/TA0/CA1
3
2
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output
Comparator_A+, CA1 input
P1.2/TA1/CA2
4
3
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: Out1 output
Comparator_A+, CA2 input
P1.3/CAOUT/CA3
5
4
I/O
General-purpose digital I/O pin
Comparator_A+, output / CA3 input
P1.4/SMCLK/C4/TCK
6
5
I/O
General-purpose digital I/O pin
SMCLK signal output
Comparator_A+, CA4 input
JTAG test clock, input terminal for device programming and test
P1.5/TA0/CA5/TMS
7
6
I/O
General-purpose digital I/O pin
Timer_A, compare: Out0 output
Comparator_A+, CA5 input
JTAG test mode select, input terminal for device programming and test
P1.6/TA1/CA6/TDI/TCLK
8
7
I/O
General-purpose digital I/O pin
Timer_A, compare: Out1 output
Comparator_A+, CA6 input
JTAG test data input or test clock input during programming and test
P1.7/CAOUT/CA7/TDO/TDI (1)
9
8
I/O
General-purpose digital I/O pin
Comparator_A+, output / CA7 input
JTAG test data output terminal or test data input during programming and test
XIN/P2.6/TA1
13
12
I/O
Input terminal of crystal oscillator
General-purpose digital I/O pin
Timer_A, compare: Out1 output
XOUT/P2.7
12
11
I/O
Output terminal of crystal oscillator
General-purpose digital I/O pin (2)
RST/NMI/SBWTDIO
10
9
I
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/SBWTCK
11
10
I
Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
VCC
1
16
Supply voltage
VSS
14
14
Ground reference
NC
NA
13, 15
QFN Pad
NA
Pad
(1)
(2)
8
Not connected
NA
QFN package pad. Connection to VSS is recommended.
TDO or TDI is selected via JTAG instruction.
If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Table 3. Terminal Functions, MSP430F20x2
TERMINAL
NAME
NO.
DESCRIPTION
I/O
PW, N
RSA
P1.0/TACLK/ACLK/A0
2
1
I/O
General-purpose digital I/O pin
Timer_A, clock signal TACLK input
ACLK signal output
ADC10 analog input A0
P1.1/TA0/A1
3
2
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output
ADC10 analog input A1
P1.2/TA1/A2
4
3
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: Out1 output
ADC10 analog input A2
I/O
General-purpose digital I/O pin
ADC10 conversion clock output
ADC10 analog input A3
Input for negative external reference voltage/negative internal reference voltage
output
P1.3/ADC10CLK/A3/
VREF-/VeREF-
P1.4/SMCLK/A4/VREF+/
VeREF+/TCK
P1.5/TA0/A5/SCLK/TMS
5
6
7
4
5
General-purpose digital I/O pin
SMCLK signal output
ADC10 analog input A4
Input for positive external reference voltage/positive internal reference voltage
output
JTAG test clock, input terminal for device programming and test
I/O
6
I/O
General-purpose digital I/O pin
Timer_A, compare: Out0 output
ADC10 analog input A5
USI: external clock input in SPI or I2C mode; clock output in SPI mode
JTAG test mode select, input terminal for device programming and test
P1.6/TA1/A6/SDO/SCL/
TDI/TCLK
8
7
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1B input, compare: Out1 output
ADC10 analog input A6
USI: Data output in SPI mode; I2C clock in I2C mode
JTAG test data input or test clock input during programming and test
P1.7/A7/SDI/SDA/
TDO/TDI (1)
9
8
I/O
General-purpose digital I/O pin
ADC10 analog input A7
USI: Data input in SPI mode; I2C data in I2C mode
JTAG test data output terminal or test data input during programming and test
XIN/P2.6/TA1
13
12
I/O
Input terminal of crystal oscillator
General-purpose digital I/O pin
Timer_A, compare: Out1 output
XOUT/P2.7
12
11
I/O
Output terminal of crystal oscillator
General-purpose digital I/O pin (2)
RST/NMI/SBWTDIO
10
9
I
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/SBWTCK
11
10
I
Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
VCC
1
NA
Supply voltage
VSS
14
NA
Ground reference
DVCC
NA
16
Digital supply voltage
AVCC
NA
15
Analog supply voltage
DVSS
NA
14
Digital ground reference
AVSS
NA
13
QFN Pad
NA
Pad
(1)
(2)
Analog ground reference
NA
QFN package pad. Connection to VSS is recommended.
TDO or TDI is selected via JTAG instruction.
If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
Copyright © 2005–2011, Texas Instruments Incorporated
9
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Table 4. Terminal Functions, MSP430F20x3
TERMINAL
NAME
NO.
DESCRIPTION
I/O
PW, N
RSA
P1.0/TACLK/ACLK/A0+
2
1
I/O
General-purpose digital I/O pin
Timer_A, clock signal TACLK input
ACLK signal output
SD16_A positive analog input A0
P1.1/TA0/A0-/A4+
3
2
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output
SD16_A negative analog input A0
SD16_A positive analog input A4
P1.2/TA1/A1+/A4-
4
3
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: Out1 output
SD16_A positive analog input A1
SD16_A negative analog input A4
P1.3/VREF/A1-
5
4
I/O
General-purpose digital I/O pin
Input for an external reference voltage/internal reference voltage output (can be
used as mid-voltage)
SD16_A negative analog input A1
P1.4/SMCLK/A2+/TCK
6
5
I/O
General-purpose digital I/O pin
SMCLK signal output
SD16_A positive analog input A2
JTAG test clock, input terminal for device programming and test
I/O
General-purpose digital I/O pin
Timer_A, compare: Out0 output
SD16_A negative analog input A2
USI: external clock input in SPI or I2C mode; clock output in SPI mode
JTAG test mode select, input terminal for device programming and test
P1.5/TA0/A2-/SCLK/TMS
7
6
P1.6/TA1/A3+/SDO/SCL/
TDI/TCLK
8
7
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1B input, compare: Out1 output
SD16_A positive analog input A3
USI: Data output in SPI mode; I2C clock in I2C mode
JTAG test data input or test clock input during programming and test
P1.7/A3-/SDI/SDA/
TDO/TDI (1)
9
8
I/O
General-purpose digital I/O pin
SD16_A negative analog input A3
USI: Data input in SPI mode; I2C data in I2C mode
JTAG test data output terminal or test data input during programming and test
XIN/P2.6/TA1
13
12
I/O
Input terminal of crystal oscillator
General-purpose digital I/O pin
Timer_A, compare: Out1 output
XOUT/P2.7
12
11
I/O
Output terminal of crystal oscillator
General-purpose digital I/O pin (2)
RST/NMI/SBWTDIO
10
9
I
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/SBWTCK
11
10
I
Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
VCC
1
NA
Supply voltage
VSS
14
NA
Ground reference
DVCC
NA
16
Digital supply voltage
AVCC
NA
15
Analog supply voltage
DVSS
NA
14
Digital ground reference
AVSS
NA
13
QFN Pad
NA
Pad
(1)
(2)
10
Analog ground reference
NA
QFN package pad. Connection to VSS is recommended.
TDO or TDI is selected via JTAG instruction.
If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
Instruction Set
General-Purpose Register
R11
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 5 shows examples of the three types of
instruction formats; Table 6 shows the address
modes.
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
The CPU is integrated with 16 registers that provide
reduced
instruction
execution
time.
The
register-to-register operation execution time is one
cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
Table 5. Instruction Word Formats
INSTRUCTION FORMAT
EXAMPLE
OPERATION
Dual operands, source-destination
ADD R4,R5
R4 + R5 ---> R5
Single operands, destination only
CALL R8
PC -->(TOS), R8--> PC
Relative jump, un/conditional
JNE
Jump-on-equal bit = 0
Table 6. Address Mode Descriptions
ADDRESS MODE
D
(1)
SYNTAX
EXAMPLE
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 --> R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5)--> M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
M(EDE) --> M(TONI)
Absolute
✓
✓
MOV &MEM,&TCDAT
M(MEM) --> M(TCDAT)
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) --> M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) --> R11
R10 + 2--> R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 --> M(TONI)
(1)
S
(1)
OPERATION
S = source, D = destination
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Operating Modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake the device from any of the five low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active
– MCLK is disabled
• Low-power mode 1 (LPM1)
– CPU is disabled
– ACLK and SMCLK remain active. MCLK is disabled
– DCO's dc-generator is disabled if DCO not used in active mode
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and SMCLK are disabled
– DCO's dc-generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK and SMCLK are disabled
– DCO's dc-generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK and SMCLK are disabled
– DCO's dc-generator is disabled
– Crystal oscillator is stopped
12
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the
CPU goes into LPM4 immediately after power-up.
Table 7. Interrupt Sources
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog Timer+
Flash key violation
PC out-of-range (1)
PORIFG
RSTIFG
WDTIFG
KEYV
See (2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG (2) (3)
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
30
0FFFAh
29
0FFF8h
28
Comparator_A+ (MSP430F20x1)
CAIFG (4)
maskable
0FFF6h
27
Watchdog Timer+
WDTIFG
maskable
0FFF4h
26
maskable
0FFF2h
25
maskable
0FFF0h
24
0FFEEh
23
0FFECh
22
0FFEAh
21
Timer_A2
Timer_A2
ADC10 (MSP430F20x2)
TACCR0 CCIFG
(4)
TACCR1 CCIFG.TAIFG (2) (4)
ADC10IFG
(4)
maskable
SD16_A (MSP430F20x3)
SD16CCTL0 SD16OVIFG,
SD16CCTL0 SD16IFG (2) (4)
maskable
USI
(MSP430F20x2, MSP430F20x3)
USIIFG, USISTTIFG (2) (4)
maskable
0FFE8h
20
I/O Port P2 (two flags)
P2IFG.6 to P2IFG.7
(2) (4)
maskable
0FFE6h
19
I/O Port P1 (eight flags)
P1IFG.0 to P1IFG.7 (2) (4)
maskable
0FFE4h
18
0FFE2h
17
See
(1)
(2)
(3)
(4)
(5)
(5)
0FFE0h
16
0FFDEh to 0FFC0h
15 to 0, lowest
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
Multiple source flags
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Interrupt flags are located in the module.
The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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Special Function Registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 8. Interrupt Enable Register 1 and 2
Address
7
6
00h
WDTIE
OFIE
NMIIE
ACCVIE
Address
5
4
1
0
ACCVIE
NMIIE
3
2
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
6
5
4
3
2
1
0
01h
Table 9. Interrupt Flag Register 1 and 2
Address
7
6
5
02h
WDTIFG
OFIFG
PORIFG
RSTIFG
NMIIFG
Address
4
3
2
1
0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
Flag set on oscillator fault.
Power-On Reset interrupt flag. Set on VCC power-up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
Set via RST/NMI pin
7
6
5
4
3
2
1
0
03h
14
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MSP430F20x1
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Memory Organization
Table 10. Memory Organization
MSP430F200x
MSP430F201x
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
1KB Flash
0FFFFh-0FFC0h
0FFFFh-0FC00h
2KB Flash
0FFFFh-0FFC0h
0FFFFh-0F800h
Information memory
Size
Flash
256 Byte
010FFh - 01000h
256 Byte
010FFh - 01000h
Size
128 Byte
027Fh - 0200h
128 Byte
027Fh - 0200h
16-bit
8-bit
8-bit SFR
01FFh - 0100h
0FFh - 010h
0Fh - 00h
01FFh - 0100h
0FFh - 010h
0Fh - 00h
RAM
Peripherals
Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port, or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also
called information memory.
• Segment A contains calibration data. After reset segment A is protected against programming and erasing. It
can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is
required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using all
instructions. For complete module descriptions, refer to the MSP430F2xx Family User's Guide.
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally-controlled oscillator (DCO).
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic
clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
Table 11. DCO Calibration Data (Provided From Factory in Flash Information
Memory Segment A)
DCO FREQUENCY
1 MHz
8 MHz
12 MHz
16 MHz
CALIBRATION REGISTER
SIZE
ADDRESS
CALBC1_1MHZ
byte
010FFh
CALDCO_1MHZ
byte
010FEh
CALBC1_8MHZ
byte
010FDh
CALDCO_8MHZ
byte
010FCh
CALBC1_12MHZ
byte
010FBh
CALDCO_12MHZ
byte
010FAh
CALBC1_16MHZ
byte
010F9h
CALDCO_16MHZ
byte
010F8h
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
There is one 8-bit I/O port implemented—port P1—and two bits of I/O port P2:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup/pulldown resistor.
Watchdog Timer (WDT+)
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
16
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MSP430F20x1
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Timer_A2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 12. Timer_A2 Signal Connections (MSP430F20x1)
INPUT PIN NUMBER
PW, N
RSA
DEVICE INPUT
SIGNAL
2 - P1.0
1 - P1.0
TACLK
MODULE
INPUT NAME
TACLK
ACLK
ACLK
SMCLK
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN NUMBER
PW, N
RSA
2 - P1.0
1 - P1.0
TACLK
INCLK
3 - P1.1
2 - P1.1
TA0
CCI0A
3 - P1.1
2 - P1.1
ACLK (internal)
CCI0B
7 - P1.5
6 - P1.5
VSS
GND
4 - P1.2
3 - P1.2
8 - P1.6
7 - P1.6
13 - P2.6
12 - P2.6
4 - P1.2
3 - P1.2
VCC
VCC
TA1
CCI1A
CAOUT
(internal)
CCI1B
VSS
GND
VCC
VCC
CCR0
CCR1
TA0
TA1
Table 13. Timer_A2 Signal Connections (MSP430F20x2, MSP430F20x3)
PW, N
INPUT PIN NUMBER
RSA
DEVICE INPUT
SIGNAL
MODULE
INPUT NAME
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
2 - P1.0
1 - P1.0
TACLK
TACLK
Timer
NA
CCR0
TA0
ACLK
ACLK
SMCLK
SMCLK
TACLK
INCLK
2 - P1.0
1 - P1.0
3 - P1.1
2 - P1.1
TA0
CCI0A
7 - P1.5
6 - P1.5
ACLK (internal)
CCI0B
VSS
GND
VCC
VCC
TA1
RSA
3 - P1.1
2 - P1.1
7 - P1.5
6 - P1.5
4 - P1.2
3 - P1.2
4 - P1.2
3 - P1.2
TA1
CCI1A
8 - P1.6
7 - P1.6
TA1
CCI1B
8 - P1.6
7 - P1.6
VSS
GND
13 - P2.6
12 - P2.6
VCC
VCC
Copyright © 2005–2011, Texas Instruments Incorporated
CCR1
OUTPUT PIN NUMBER
PW, N
17
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Comparator_A+ (MSP430F20x1)
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
USI (MSP430F20x2 and MSP430F20x3)
The universal serial interface (USI) module is used for serial data communication and provides the basic
hardware for synchronous communication protocols like SPI and I2C.
ADC10 (MSP430F20x2)
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
SD16_A (MSP430F20x3)
The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit sigma-delta
core and reference generator. In addition to external analog inputs, internal VCC sense and temperature sensors
are also available.
18
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MSP430F20x1
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Peripheral File Map
Table 14. Peripherals With Word Access
ADC10
(MSP430F20x2)
ADC
ADC
ADC
ADC
control 0
control 1
memory
data transfer start address
ADC10CTL0
ADC10CTL1
ADC10MEM
ADC10SA
01B0h
01B2h
01B4h
01BCh
SD16_A
(MSP430F20x3)
General Control
Channel 0 Control
Interrupt vector word register
Channel 0 conversion memory
SD16CTL
SD16CCTL0
SD16IV
SD16MEM0
0100h
0102h
0110h
0112h
Timer_A
Capture/compare register
Capture/compare register
Timer_A register
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
TACCR1
TACCR0
TAR
TACCTL1
TACCTL0
TACTL
TAIV
0174h
0172h
0170h
0164h
0162h
0160h
012Eh
Flash Memory
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
Watchdog Timer+
Watchdog/timer control
WDTCTL
0120h
ADC10
(MSP430F20x2)
Analog enable
ADC data transfer control register 1
ADC data transfer control register 0
ADC10AE
ADC10DTC1
ADC10DTC0
04Ah
049h
048h
SD16_A
(MSP430F20x3)
Channel 0 Input Control
Analog Enable
SD16INCTL0
SD16AE
0B0h
0B7h
USI
(MSP430F20x2 and MSP430F20x3)
USI
USI
USI
USI
USI
USICTL0
USICTL1
USICKCTL
USICNT
USISR
078h
079h
07Ah
07Bh
07Ch
Comparator_A+
(MSP430F20x1)
Comparator_A+ port disable
Comparator_A+ control 2
Comparator_A+ control 1
CAPD
CACTL2
CACTL1
05Bh
05Ah
059h
Basic Clock System+
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
053h
058h
057h
056h
Port P2
Port P2 resistor enable
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
P2REN
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P1
Port P1 resistor enable
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
027h
026h
025h
024h
023h
022h
021h
020h
Special Function
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
IFG2
IFG1
IE2
IE1
003h
002h
001h
000h
Table 15. Peripherals With Byte Access
control 0
control 1
clock control
bit counter
shift register
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Absolute Maximum Ratings (1)
Voltage applied at VCC to VSS
-0.3 V to 4.1 V
Voltage applied to any pin (2)
-0.3 V to VCC + 0.3 V
±2 mA
Diode current at any device terminal
Storage temperature (3)
Tstg
Unprogrammed device
-55°C to 150°C
Programmed device
-40°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
(1)
(2)
(3)
Recommended Operating Conditions
MIN
VCC
Supply voltage
VSS
Supply voltage
TA
Operating free-air temperature
fSYSTE
(2)
MAX
During program execution
1.8
3.6
During flash program/erase
2.2
3.6
0
Processor frequency (maximum MCLK frequency) (1) (2)
M
(1)
NOM
UNIT
V
V
I version
-40
85
T version
-40
105
VCC = 1.8 V,
Duty cycle = 50% ± 10%
dc
6
VCC = 2.7 V,
Duty cycle = 50% ± 10%
dc
12
VCC ≥ 3.3 V,
Duty cycle = 50% ± 10%
dc
16
°C
MHz
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend :
System Frequency −MHz
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
6 MHz
1.8 V
2.2 V
2.7 V
3.3 V
3.6 V
Supply Voltage −V
Note:
Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 1. Safe Operating Area
20
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MSP430F20x2
MSP430F20x1
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
PARAMETER
IAM,1MHz
IAM,1MHz
IAM,4kHz
IAM,100kHz
(1)
(2)
TYP
MAX
2.2 V
220
270
Active mode (AM)
current (1 MHz)
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
3V
300
370
2.2 V
190
Active mode (AM)
current (1 MHz)
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
Program executes in RAM,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
3V
260
-40°C to 85°C
2.2 V
1.2
105°C
2.2 V
Active mode (AM)
current (4 kHz)
fMCLK = fSMCLK = fACLK = 32768 Hz/8
= 4096 Hz,
fDCO = 0 Hz,
Program executes in flash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1,
SCG1 = 0, OSCOFF = 0
-40°C to 85°C
3V
105°C
3V
fMCLK = fSMCLK = fDCO(0, 0) ≈ 100 kHz,
fACLK = 0 Hz,
Program executes in flash,
RSELx = 0, DCOx = 0,
CPUOFF = 0, SCG0 = 0,
SCG1 = 0, OSCOFF = 1
-40°C to 85°C
2.2 V
105°C
2.2 V
-40°C to 85°C
3V
105°C
3V
Active mode (AM)
current (100 kHz)
TEST CONDITIONS
TA
VCC
MIN
UNIT
µA
µA
3
6
1.6
4
µA
7
37
50
60
40
55
µA
65
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
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Typical Characteristics - Active Mode Supply Current (Into VCC)
ACTIVE MODE CURRENT
vs
VCC
(TA = 25°C)
ACTIVE MODE CURRENT
vs
DCO FREQUENCY
5.0
4.0
Active Mode Current − mA
Active Mode Current − mA
f DCO = 16 MHz
4.0
3.0
f DCO = 12 MHz
2.0
1.0
f DCO = 8 MHz
3.0
2.0
1.0
f DCO = 1 MHz
0.0
1.5
2.0
2.5
3.0
VCC − Supply Voltage − V
Figure 2.
22
3.5
4.0
0.0
0.0
4.0
8.0
12.0
16.0
f DCO − DCO Frequency − MHz
Figure 3.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
ILPM0,1MHz
ILPM0,100kHz
ILPM2
ILPM3,LFXT1
TEST CONDITIONS
TA
MAX
65
80
Low-power mode 0
(LPM0) current (3)
3V
85
100
2.2 V
37
48
Low-power mode 0
(LPM0) current (3)
fMCLK = 0 MHz,
fSMCLK = fDCO(0, 0) ≈ 100 kHz,
fACLK = 0 Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 1
3V
41
52
22
29
Low-power mode 2
(LPM2) current (4)
fMCLK = fSMCLK = 0 MHz, fDCO = 1
MHz,
fACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 1, OSCOFF = 0
Low-power mode 3
(LPM3) current (3)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32,768 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
-40°C to 85°C
105°C
Low-power mode 3
(LPM3) current (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator
(VLO),
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
Low-power mode 4
(LPM4) current (5)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 1
2.2 V
-40°C to 85°C
105°C
3V
32
0.7
0.7
1
1.4
2.3
2.2 V
3
6
-40°C
0.9
1.2
0.9
1.2
1.6
2.8
3V
105°C
3
7
-40°C
0.4
0.7
0.5
0.7
1
1.6
85°C
2.2 V
105°C
2
5
-40°C
0.5
0.9
0.6
0.9
1.3
1.8
25°C
3V
105°C
2.5
6
-40°C
0.1
0.5
0.1
0.5
0.8
1.5
2
4
25°C
85°C
2.2 V/3 V
105°C
µA
µA
1.2
105°C
25°C
µA
34
25°C
85°C
UNIT
31
25
-40°C
85°C
(1)
(2)
(3)
(4)
(5)
TYP
2.2 V
25°C
ILPM4
MIN
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
85°C
ILPM3,VLO
VCC
(2)
µA
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
Copyright © 2005–2011, Texas Instruments Incorporated
23
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
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Schmitt-Trigger Inputs (Ports P1 and P2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VIT+
TEST CONDITIONS
Positive-going input threshold voltage
VIT-
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ - VIT-)
RPull
Pullup/pulldown resistor
For pullup: VIN = VSS,
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
VCC
MIN
TYP
MAX
0.45 VCC
0.75 VCC
2.2 V
1.00
1.65
3V
1.35
2.25
0.25 VCC
0.55 VCC
2.2 V
0.55
1.20
3V
0.75
1.65
2.2 V
0.2
1.0
3V
0.3
1.0
20
35
50
5
UNIT
V
V
V
kΩ
pF
Inputs (Ports P1 and P2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(int)
(1)
External interrupt timing
TEST CONDITIONS
VCC
Port P1, P2: P1.x to P2.x, External trigger pulse
width to set interrupt flag (1)
MIN
2.2 V/3 V
TYP
MAX
20
UNIT
ns
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger signals
shorter than t(int).
Leakage Current (Ports P1 and P2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
24
High-impedance leakage current
TEST CONDITIONS
(1) (2)
VCC
2.2 V/3 V
MIN
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Outputs (Ports P1 and P2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = -1.5 mA
VOH
(1)
(2)
MAX
VCC - 0.25
VCC
VCC - 0.6
VCC
I(OHmax) = -1.5 mA (1)
3V
VCC - 0.25
VCC
I(OHmax) = -6 mA (2)
3V
VCC - 0.6
VCC
2.2 V
VSS
VSS + 0.25
2.2 V
VSS
VSS + 0.6
I(OLmax) = 1.5 mA (1)
3V
VSS
VSS + 0.25
I(OLmax) = 6 mA (2)
3V
VSS
VSS + 0.6
(2)
(1)
I(OLmax) = 6 mA (2)
Low-level output voltage
TYP
2.2 V
I(OLmax) = 1.5 mA
VOL
MIN
2.2 V
I(OHmax) = -6 mA
High-level output voltage
VCC
(1)
UNIT
V
V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±12 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency (Ports P1 and P2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fPx.y
Port output frequency
(with load)
P1.4/SMCLK, CL = 20 pF, RL = 1 kΩ (1)
fPort°CLK
Clock output frequency
P2.0/ACLK, P1.4/SMCLK, CL = 20 pF (2)
(1)
(2)
(2)
MIN
TYP
MAX
2.2 V
10
3V
12
2.2 V
12
3V
16
UNIT
MHz
MHz
A resistive divider with 2 × 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Copyright © 2005–2011, Texas Instruments Incorporated
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MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
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Typical Characteristics - Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
VCC = 2.2 V
P1.7
TA = 25°C
25.0
TA = 85°C
20.0
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
30.0
VCC = 3 V
P1.7
40.0
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
VOL − Low-Level Output Voltage − V
1.5
2.0
2.5
Figure 5.
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
3.0
3.5
0.0
VCC = 2.2 V
P1.7
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
1.0
Figure 4.
−5.0
−10.0
−15.0
TA = 85°C
−20.0
TA = 25°C
0.5
1.0
1.5
2.0
VOH − High-Level Output Voltage − V
Figure 6.
26
0.5
VOL − Low-Level Output Voltage − V
0.0
−25.0
0.0
TA = 25°C
2.5
VCC = 3 V
P1.7
−10.0
−20.0
−30.0
TA = 85°C
−40.0
TA = 25°C
−50.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH − High-Level Output Voltage − V
Figure 7.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
POR/Brownout Reset (BOR) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC(start)
See Figure 8
dVCC/dt ≤ 3 V/s
V(B_IT-)
See Figure 8 through Figure 10
dVCC/dt ≤ 3 V/s
Vhys(B_IT-)
See Figure 8
dVCC/dt ≤ 3 V/s
td(BOR)
See Figure 8
t(reset)
Pulse length needed at RST/NMI pin to
accepted reset internally
(1)
VCC
MIN
TYP
MAX
0.7 ×
V(B_IT-)
70
2.2 V/3 V
2
130
UNIT
V
1.71
V
210
mV
2000
µs
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) +
Vhys(B_IT-)is ≤ 1.8 V.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
Copyright © 2005–2011, Texas Instruments Incorporated
27
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Typical Characteristics - POR/Brownout Reset (BOR)
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
t pw − Pulse Width − µs
1 ns
t pw − Pulse Width − µs
Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
t pw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
0
0.001
t f = tr
1
t pw − Pulse Width − µs
1000
tf
tr
t pw − Pulse Width − µs
Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
28
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Main DCO Characteristics
•
•
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
faverage =
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1)
DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
Supply voltage
TEST CONDITIONS
VCC
MIN
TYP
MAX
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
RSELx = 15
3.0
3.6
UNIT
V
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
2.2 V/3 V
0.06
0.14
MHz
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
2.2 V/3 V
0.07
0.17
MHz
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
2.2 V/3 V
0.10
0.20
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
2.2 V/3 V
0.14
0.28
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
2.2 V/3 V
0.20
0.40
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
0.28
0.54
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
2.2 V/3 V
0.39
0.77
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
2.2 V/3 V
0.54
1.06
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
2.2 V/3 V
0.80
1.50
MHz
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
2.2 V/3 V
1.10
2.10
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
2.2 V/3 V
1.60
3.00
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
2.2 V/3 V
2.50
4.30
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
2.2 V/3 V
3.00
5.50
MHz
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
2.2 V/3 V
4.30
7.30
MHz
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
2.2 V/3 V
6.00
9.60
MHz
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
2.2 V/3 V
8.60
13.9
MHz
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
12.0
18.5
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
16.0
26.0
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
2.2 V/3 V
1.55
ratio
SDCO
Frequency step between tap
DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
2.2 V/3 V
1.05
1.08
1.12
Duty cycle
Measured at P1.4/SMCLK
2.2 V/3 V
40
50
60
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29
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MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
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Calibrated DCO Frequencies - Tolerance at Calibration
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Frequency tolerance at calibration
TA
VCC
MIN
TYP
MAX
UNIT
25°C
3V
-1
±0.2
+1
25°C
3V
0.990
1
1.010
MHz
%
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
25°C
3V
7.920
8
8.080
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
25°C
3V
11.88
12
12.12
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
25°C
3V
15.84
16
16.16
MHz
MAX
UNIT
Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fCAL(1MHz)
fCAL(8MHz)
fCAL(12MHz)
fCAL(16MHz)
30
TA
VCC
1-MHz tolerance over
temperature
0°C to 85°C
3V
-2.5
±0.5
+2.5
%
8-MHz tolerance over
temperature
0°C to 85°C
3V
-2.5
±1.0
+2.5
%
12-MHz tolerance over
temperature
0°C to 85°C
3V
-2.5
±1.0
+2.5
%
16-MHz tolerance over
temperature
0°C to 85°C
3V
-3
±2.0
+3
%
2.2 V
0.97
1
1.03
3V
0.975
1
1.025
3.6 V
0.97
1
1.03
2.2 V
7.76
8
8.4
3V
7.8
8
8.2
3.6 V
7.6
8
8.24
2.2 V
11.7
12
12.3
3V
11.7
12
12.3
3.6 V
11.7
12
12.3
3V
15.52
16
16.48
15
16
16.48
1-MHz calibration value
8-MHz calibration value
12-MHz calibration value
16-MHz calibration value
TEST CONDITIONS
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
0°C to 85°C
3.6 V
MIN
TYP
MHz
MHz
MHz
MHz
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
1-MHz tolerance over VCC
25°C
8-MHz tolerance over VCC
25°C
12-MHz tolerance over VCC
16-MHz tolerance over VCC
UNIT
1.8 V to 3.6 V
-3
±2
+3
%
1.8 V to 3.6 V
-3
±2
+3
%
25°C
2.2 V to 3.6 V
-3
±2
+3
%
25°C
3 V to 3.6 V
-6
±2
+3
%
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
25°C
1.8 V to 3.6 V
0.97
1
1.03
MHz
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
25°C
1.8 V to 3.6 V
7.76
8
8.24
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
25°C
2.2 V to 3.6 V
11.64
12
12.36
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
25°C
3 V to 3.6 V
15
16
16.48
MHz
MIN
TYP
MAX
UNIT
Calibrated DCO Frequencies - Overall Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
1-MHz tolerance
overall
I: -40°C to 85°C
T: -40°C to 105°C
1.8 V to 3.6 V
-5
±2
+5
%
8-MHz tolerance
overall
I: -40°C to 85°C
T: -40°C to 105°C
1.8 V to 3.6 V
-5
±2
+5
%
12-MHz
tolerance overall
I: -40°C to 85°C
T: -40°C to 105°C
2.2 V to 3.6 V
-5
±2
+5
%
16-MHz
tolerance overall
I: -40°C to 85°C
T: -40°C to 105°C
3 V to 3.6 V
-6
±3
+6
%
fCAL(1MHz)
BCSCTL1 = CALBC1_1MHZ,
1-MHz
DCOCTL = CALDCO_1MHZ,
calibration value
Gating time: 5 ms
I: -40°C to 85°C
T: -40°C to 105°C
1.8 V to 3.6 V
0.95
1
1.05
MHz
fCAL(8MHz)
BCSCTL1 = CALBC1_8MHZ,
8-MHz
DCOCTL = CALDCO_8MHZ,
calibration value
Gating time: 5 ms
I: -40°C to 85°C
T: -40°C to 105°C
1.8 V to 3.6 V
7.6
8
8.4
MHz
fCAL(12MHz)
BCSCTL1 = CALBC1_12MHZ,
12-MHz
DCOCTL = CALDCO_12MHZ,
calibration value
Gating time: 5 ms
I: -40°C to 85°C
T: -40°C to 105°C
2.2 V to 3.6 V
11.4
12
12.6
MHz
fCAL(16MHz)
BCSCTL1 = CALBC1_16MHZ,
16-MHz
DCOCTL = CALDCO_16MHZ,
calibration value
Gating time: 2 ms
I: -40°C to 85°C
T: -40°C to 105°C
3 V to 3.6 V
15
16
17
MHz
Copyright © 2005–2011, Texas Instruments Incorporated
31
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Typical Characteristics - Calibrated 1-MHz DCO Frequency
CALIBRATED 1-MHz FREQUENCY
vs
TEMPERATURE
CALIBRATED 1-MHz FREQUENCY
vs
SUPPLY VOLTAGE
1.03
1.03
1.02
1.02
Frequency − MHz
1.00
VCC = 2.2 V
VCC = 3.0 V
0.99
Frequency − MHz
VCC = 1.8 V
1.01
1.01
TA = 105 °C
TA = 85 °C
1.00
TA = 25 °C
0.99
TA = −40 °C
VCC = 3.6 V
0.98
0.98
0.97
−50.0
−25.0
0.0
25.0
50.0
TA − Temperature − °C
Figure 11.
32
75.0
100.0
0.97
1.5
2.0
2.5
3.0
3.5
4.0
VCC − Supply Voltage − V
Figure 12.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Wake-Up From Lower-Power Modes (LPM3/4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ
tDCO,LPM3/4
2.2 V/3 V
(1)
(2)
1.5
µs
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ
1
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ
tCPU,LPM3/4
UNIT
2
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ
DCO clock wake-up time
from LPM3/4 (1)
MAX
3V
CPU wake-up time from
LPM3/4 (2)
1
1 / fMCLK +
tClock,LPM3/4
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4
DCO WAKE-UP TIME FROM LPM3
vs
DCO FREQUENCY
DCO Wake Time − us
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 13.
Copyright © 2005–2011, Texas Instruments Incorporated
33
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF,logic
LFXT1 oscillator logic level
square wave input frequency, XTS = 0, LFXT1Sx = 3
LF mode
OALF
Oscillation allowance for
LF crystals
CL,eff
fFault,LF
(1)
(2)
(3)
(4)
Integrated effective load
capacitance, LF mode (2)
XTS = 0, LFXT1Sx = 0 or 1
VCC
MIN
TYP
1.8 V to 3.6 V
1.8 V to 3.6 V
MAX
32768
10000
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
200
UNIT
Hz
50000
Hz
kΩ
XTS = 0, XCAPx = 0
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Duty cycle, LF mode
XTS = 0, Measured at P1.0/ACLK,
fLFXT1,LF = 32768 Hz
2.2 V/3 V
30
Oscillator fault frequency,
LF mode (3)
XTS = 0, LFXT1Sx = 3 (4)
2.2 V/3 V
10
50
pF
70
%
10000
Hz
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TA
-40°C to 85°C
fVLO
VLO frequency
dfVLO/dT
VLO frequency temperature drift (1)
dfVLO/dVCC
(1)
(2)
105°C
VLO frequency supply voltage drift
(2)
VCC
MIN
TYP
MAX
4
12
20
2.2 V/3 V
I: -40°C to 85°C
T: -40°C to 105°C
2.2 V/3 V
25°C
1.8 V to 3.6 V
22
UNIT
kHz
0.5
%/°C
4
%/V
Calculated using the box method:
I: (MAX(-40 to 85°C) - MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C - (-40°C))
T: (MAX(-40 to 105°C) - MIN(-40 to 105°C)) / MIN(-40 to 105°C) / (105°C - (-40°C))
Calculated using the box method: (MAX(1.8 to 3.6 V) - MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V - 1.8 V)
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A clock frequency
Internal: SMCLK, ACLK
External: TACLK, INCLK
Duty cycle = 50% ± 10%
tTA,cap
Timer_A capture timing
TA0, TA1
34
VCC
MIN
TYP
MAX
2.2 V
10
3V
16
2.2 V/3 V
20
UNIT
MHz
ns
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
USI, Universal Serial Interface (MSP430F20x2, MSP430F20x3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fUSI
TEST CONDITIONS
External: SCLK,
Duty cycle = 50% ±10%,
SPI slave mode
USI clock frequency
USI module in I2C mode,
I(OLmax) = 1.5 mA
VOL,I2C Low-level output voltage on SDA and SCL
VCC
MIN
TYP
MAX
2.2 V
10
3V
16
2.2 V/3 V
VSS
UNIT
MHz
VSS + 0.4
V
Typical Characteristics, USI Low-Level Output Voltage on SDA and SCL
(MSP430F20x2, MSP430F20x3)
USI LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
USI LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
5.0
5.0
TA = 25°C
4.0
3.0
TA = 85°C
2.0
1.0
0.0
0.0
0.2
TA = 25°C
VCC = 3 V
0.4
0.6
0.8
VOL − Low-Level Output Voltage − V
Figure 14.
Copyright © 2005–2011, Texas Instruments Incorporated
1.0
I OL − Low-Level Output Current − mA
I OL − Low-Level Output Current − mA
VCC = 2.2 V
4.0
TA = 85°C
3.0
2.0
1.0
0.0
0.0
0.2
0.4
0.6
0.8
1.0
VOL − Low-Level Output V oltage − V
Figure 15.
35
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Comparator_A+ (MSP430F20x1) (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(DD)
CAON = 1, CARSEL = 0, CAREF = 0
I(Refladder/RefDiode)
CAON = 1, CARSEL = 0, CAREF = 1/2/3,
No load at P1.0/CA0 and P1.1/CA1
VCC
MIN
TYP
MAX
2.2 V
25
40
3V
45
60
2.2 V
30
50
3V
45
71
UNIT
μA
μA
VIC
Common-mode input voltage
range
CAON = 1
2.2 V/3 V
0
V(Ref025)
Voltage at 0.25 VCC node /
VCC
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at P1.0/CA0 and P1.1/CA1
2.2 V/3 V
0.23
0.24
0.25
V(Ref050)
Voltage at 0.5 VCC node /
VCC
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at P1.0/CA0 and P1.1/CA1
2.2 V/3 V
0.47
0.48
0.5
390
480
540
See Figure 20 and Figure 21
PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at P1.0/CA0 and P1.1/CA1,
TA = 85°C
2.2 V
V(RefVT)
3V
400
490
550
Vp - VS
Offset voltage (2)
2.2 V/3 V
-30
30
mV
Vhys
Input hysteresis
2.2 V/3 V
0
0.7
1.4
mV
TA = 25°C, Overdrive 10 mV,
Without filter: CAF = 0 (3)
(see Figure 16 and Figure 17)
2.2 V
80
165
300
3V
70
120
240
TA = 25°C, Overdrive 10 mV,
With filter: CAF = 1 (3)
(see Figure 16 and Figure 17)
2.2 V
1.4
1.9
2.8
3V
0.9
1.5
2.2
t(response)
(1)
(2)
(3)
36
Response time
(low-high and high-low)
CAON = 1
VCC - 1
V
mV
ns
μs
The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.y) specification.
The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The
two successive measurements are then summed together.
Response time measured at P1.3/CAOUT
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
0V
VCC
0
1
CAF
CAON
Low Pass Filter
+
_
V+
V−
0
0
1
1
To Internal
Modules
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 µs
Figure 16. Block Diagram of Comparator_A+ Module
VCAOUT
Overdrive
V−
400 mV
t (response)
V+
Figure 17. Overdrive Definition
Figure 18. Comparator_A+ Short Resistance Test Condition
CASHORT
CA0
CA1
1
VIN
+
−
Comparator_A+
CASHORT = 1
IOUT = 10µA
Figure 19. Comparator_A+ Short Resistance Test Condition
Copyright © 2005–2011, Texas Instruments Incorporated
37
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Typical Characteristics, Comparator_A+ (MSP430x20x1)
V(RefVT)
vs
TEMPERATURE
(VCC = 3 V)
V(RefVT)
vs
TEMPERATURE
(VCC = 2.2 V)
650
650
VCC = 2.2 V
600
V(REFVT) − Reference Volts −mV
V(REFVT) − Reference Volts −mV
VCC = 3 V
Typical
550
500
450
400
−45
−25
−5
15
35
55
75
95
600
Typical
550
500
450
400
−45
115
−25
TA − Free-Air Temperature − °C
−5
15
35
55
75
95
115
TA − Free-Air Temperature − °C
Figure 20.
Figure 21.
SHORT RESISTANCE
vs
VIN/VCC
Short Resistance − kOhms
100.00
VCC = 1.8V
VCC = 2.2V
10.00
VCC = 3.0V
VCC = 3.6V
1.00
0.0
0.2
0.4
0.6
0.8
1.0
VIN/VCC − Normalized Input Voltage − V/V
Figure 22.
38
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
10-Bit ADC, Power Supply and Input Range Conditions (MSP430F20x2) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
Analog supply voltage
range
VSS = 0 V
VAx
Analog input voltage
range (2)
All Ax terminals,
Analog inputs selected in
ADC10AE register
IADC10
ADC10 supply current (3)
fADC10CLK = 5 MHz,
ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1,
ADC10SHT1 = 0, ADC10DIV = 0
IREF+
Reference supply
current, reference buffer
disabled (4)
fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
TA
I: -40°C to 85°C
T: -40°C to 105°C
VCC
TYP
MAX
UNIT
2.2
3.6
V
0
VCC
V
2.2 V
0.52
1.05
3V
0.6
1.2
2.2 V/3 V
0.25
0.4
I: -40°C to 85°C
T: -40°C to 105°C
mA
mA
3V
0.25
0.4
1.1
1.4
Reference buffer supply
IREFB,0 current with
ADC10SR = 0 (4)
fADC10CLK = 5 MHz
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
-40°C to 85°C
2.2 V/3 V
105°C
2.2 V/3 V
Reference buffer supply
IREFB,1 current with
ADC10SR = 1 (4)
fADC10CLK = 5 MHz,
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
-40°C to 85°C
2.2 V/3 V
105°C
2.2 V/3 V
CI
Input capacitance
Only one terminal Ax selected at
a time
I: -40°C to 85°C
T: -40°C to 105°C
RI
Input MUX ON
resistance
0 V ≤ VAx ≤ VCC
I: -40°C to 85°C
T: -40°C to 105°C
(1)
(2)
(3)
(4)
MIN
2.2 V/3 V
1.8
0.5
mA
0.7
0.8
mA
27
pF
2000
Ω
The leakage current is defined in the leakage current table with Px.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
Copyright © 2005–2011, Texas Instruments Incorporated
39
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
10-Bit ADC, Built-In Voltage Reference (MSP430F20x2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC,REF+
Positive built-in
reference analog
supply voltage range
VREF+
Positive built-in
reference voltage
ILD,VREF+
Maximum VREF+ load
current
VREF+ load regulation
TEST CONDITIONS
VCC
MIN
IVREF+ ≤ 1 mA, REF2_5V = 0
2.2
IVREF+ ≤ 0.5 mA, REF2_5V = 1
2.8
IVREF+ ≤ 1 mA, REF2_5V = 1
2.9
TYP
MAX
V
IVREF+ ≤ IVREF+max, REF2_5V = 0
2.2 V/3 V
1.41
1.5
1.59
IVREF+ ≤ IVREF+max, REF2_5V = 1
3V
2.35
2.5
2.65
2.2 V
UNIT
V
±0.5
3V
±1
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 0.75 V,
REF2_5V = 0
2.2 V/3 V
±2
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 1.25 V,
REF2_5V = 1
3V
mA
LSB
±2
VREF+ load regulation
response time
IVREF+ = 100 µA to 900 µA,
VAx ≈ 0.5 x VREF+,
Error of conversion result
≤1 LSB
CVREF+
Maximum capacitance
at pin VREF+ (1)
IVREF+ ≤ ±1 mA,
REFON = 1, REFOUT = 1
2.2 V/3 V
100
pF
TCREF+
Temperature
coefficient
IVREF+ = constant with
0 mA ≤ IVREF+ ≤ 1 mA
2.2 V/3 V
±100
ppm/°C
tREFON
Settling time of internal IVREF+ = 0.5 mA, REF2_5V = 0,
reference voltage (2)
REFON = 0 to 1
tREFBURST
(1)
(2)
40
Settling time of
reference buffer (2)
ADC10SR = 0
ADC10SR = 1
IVREF+ = 0.5 mA,
REF2_5V = 0,
REFON = 1,
REFBURST = 1
ADC10SR = 0
IVREF+ = 0.5 mA,
REF2_5V = 1,
REFON = 1,
REFBURST = 1
ADC10SR = 0
ADC10SR = 1
ADC10SR = 1
400
3V
3.6 V
ns
2000
30
µs
1
2.2 V
2.5
2
3V
µs
4.5
The capacitance applied to the internal buffer operational amplifier, if switched to terminal P1.4/SMCLK/A4/VREF+/VeREF+/TCK
(REFOUT = 1), must be limited; otherwise, the reference buffer may become unstable.
The condition is that the error in a conversion started after tREFON or tRefBuf is less than ±0.5 LSB.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
10-Bit ADC, External Reference (MSP430F20x2) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VeREF+
TEST CONDITIONS
Positive external reference input
voltage range (2)
MIN
MAX
VeREF+ > VeREF-,
SREF1 = 1, SREF0 = 0
1.4
VCC
VeREF- ≤ VeREF+ ≤ VCC - 0.15 V,
SREF1 = 1, SREF0 = 1 (3)
1.4
3
0
1.2
V
1.4
VCC
V
VeREF-
Negative external reference input
voltage range (4)
VeREF+ > VeREF-
ΔVeREF
Differential external reference
input voltage range
ΔVeREF = VeREF+ - VeREF-
VeREF+ > VeREF- (5)
IVeREF+
IVeREF(1)
(2)
(3)
(4)
(5)
Static input current into VeREF+
Static input current into VeREF-
VCC
UNIT
V
0 V ≤ VeREF+ ≤ VCC,
SREF1 = 1, SREF0 = 0
±1
µA
2.2 V/3 V
0 V ≤ VeREF+ ≤ VCC - 0.15 V ≤ 3 V,
SREF1 = 1, SREF0 = 1 (3)
0
0 V ≤ VeREF- ≤ VCC
±1
2.2 V/3 V
µA
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
Under this condition, the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
10-Bit ADC, Timing Parameters (MSP430F20x2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADC10SR = 0
fADC10CLK
ADC10 input clock
frequency
For specified performance of
ADC10 linearity parameters
fADC10OSC
ADC10 built-in
oscillator frequency
ADC10DIVx = 0, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
tCONVERT
Conversion time
tADC10ON
Turn on settling time
of the ADC (1)
(1)
ADC10SR = 1
fADC10CLK from ACLK, MCLK or SMCLK,
ADC10SSELx ≠ 0
VCC
MIN
TYP
MAX
0.45
6.3
0.45
1.5
2.2 V/3 V
3.7
6.3
2.2 V/3 V
2.06
3.51
2.2 V/3 V
UNIT
MHz
MHz
µs
13 ×
ADC10DIVx ×
1/fADC10CLK
100
ns
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Copyright © 2005–2011, Texas Instruments Incorporated
41
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
10-Bit ADC, Linearity Parameters (MSP430F20x2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
EI
Integral linearity error
2.2 V/3 V
±1
LSB
ED
Differential linearity error
2.2 V/3 V
±1
LSB
EO
Offset error
2.2 V/3 V
±1
LSB
EG
Gain error
2.2 V/3 V
±1.1
±2
LSB
ET
Total unadjusted error
2.2 V/3 V
±2
±5
LSB
TYP
MAX
UNIT
2.2 V
40
120
3V
60
160
Source impedance RS < 100 Ω
10-Bit ADC, Temperature Sensor and Built-In VMID (MSP430F20x2) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ISENSOR
TEST CONDITIONS
Temperature sensor supply
current (1)
REFON = 0, INCHx = 0Ah,
TA = 25°C
ADC10ON = 1, INCHx = 0Ah (2)
TCSENSOR
VOffset,Sensor
VCC
Sensor offset voltage
ADC10ON = 1, INCHx = 0Ah
2.2 V/3 V
(2)
VSENSOR
Sensor output voltage
Temperature sensor voltage at
TA = 85°C
Temperature sensor voltage at
TA = 25°C
3.44
3.55
-100
Temperature sensor voltage at
TA = 105°C (T version only)
(3)
MIN
3.66 mV/°C
100
1265
1365
1465
1195
1295
1395
985
1085
1185
895
995
1095
2.2 V/3 V
Temperature sensor voltage at
TA = 0°C
Sample time required if
channel 10 is selected (4)
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
Current into divider at
channel 11 (4)
ADC10ON = 1, INCHx = 0Bh
VMID
VCC divider at channel 11
ADC10ON = 1, INCHx = 0Bh,
VMID ≈ 0.5 × VCC
2.2 V
1.06
1.1
1.14
3V
1.46
1.5
1.54
tVMID(sample)
Sample time required if
channel 11 is selected (5)
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V
1400
3V
1220
(1)
(2)
(3)
(4)
(5)
42
mV
mV
tSENSOR(sample)
2.2 V/3 V
µA
µs
30
2.2 V
N/A
3V
N/A
µA
V
ns
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high).When REFON = 1, ISENSOR is included in IREF+.When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
Results based on characterization and/or production test, not TCSensor or VOffset,sensor.
No additional current is needed. The VMID is used during sampling.
The on time, tVMID(on), is included in the sampling time, tVMID(sample); no additional on time is needed.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
SD16_A, Power Supply and Recommended Operating Conditions (MSP430F20x3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
AVCC
Analog supply voltage
range
TEST CONDITIONS
TA
SD16LP = 0,
fSD16 = 1 MHz,
SD16OSR = 256
Analog supply current
including internal
reference
SD16 input clock
frequency
TYP
2.5
730
105°C
GAIN: 4,8,16
-40°C to 85°C
810
105°C
V
1050
1150
1300
105°C
1160
3V
1700
1850
-40°C to 85°C
720
105°C
µA
1030
1160
-40°C to 85°C
GAIN: 32
UNIT
1170
-40°C to 85°C
GAIN: 1
MAX
3.6
-40°C to 85°C
GAIN: 32
SD16LP = 1,
fSD16 = 0.5 MHz,
SD16OSR = 256
fSD16
MIN
AVCC = DVCC = VCC,
AVSS = DVSS = VSS = 0 V
GAIN: 1,2
ISD16
VCC
810
105°C
1150
1300
SD16LP = 0
(Low power mode disabled)
0.03
1
0.03
0.5
1.1
3V
SD16LP = 1
(Low power mode enabled)
MHz
SD16_A, Input Range (MSP430F20x3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VID,FSR
VID
Differential full scale input voltage
range (1)
TEST CONDITIONS
VCC
Bipolar mode, SD16UNI = 0
Unipolar mode, SD16UNI = 1
MIN
TYP
-(VREF/2)/
GAIN
+(VREF/2)/
GAIN
0
+(VREF/2)/
GAIN
SD16GAINx = 1
±500
SD16GAINx = 2
±250
SD16GAINx = 4
±125
Differential input voltage range for
SD16REFON = 1
specified performance (1)
SD16GAINx = 8
±31
SD16GAINx = 32
±15
UNIT
mV
mV
±62
SD16GAINx = 16
SD16GAINx = 1
MAX
200
ZI
Input impedance
(one input pin to AVSS)
fSD16 = 1 MHz
ZID
Differential input impedance
(IN+ to IN-)
fSD16 = 1 MHz
VI
Absolute input voltage range
AVSS - 0.1
AVCC
V
VIC
Common-mode input voltage
range
AVSS - 0.1
AVCC
V
(1)
SD16GAINx = 32
SD16GAINx = 1
SD16GAINx = 32
3V
3V
kΩ
75
300
400
100
150
kΩ
The analog input range depends on the reference voltage applied to VREF. If VREF is sourced externally, the full-scale range is defined
by VFSR+ = +(VREF/2)/GAIN and VFSR- = -(VREF/2)/GAIN. The analog input range should not exceed 80% of VFSR+ or VFSR-.
Copyright © 2005–2011, Texas Instruments Incorporated
43
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
SD16_A, SINAD Performance (fSD16 = 1 MHz, SD16OSRx = 1024, SD16REFON = 1)
(MSP430F20x3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
SINAD1024
Signal-to-noise + distortion ratio
(OSR = 1024)
TEST CONDITIONS
VCC
PW, N
RSA
MIN
TYP
MIN
TYP
SD16GAINx = 1,
Signal amplitude: VIN = 500 mV,
Signal frequency: fIN = 100 Hz
84
85
86
87
SD16GAINx = 2,
Signal amplitude: VIN = 250 mV,
Signal frequency: fIN = 100 Hz
82
83
82
83
SD16GAINx = 4,
Signal amplitude: VIN = 125 mV,
Signal frequency: fIN = 100 Hz
78
79
78
79
SD16GAINx = 8,
Signal amplitude: VIN = 62 mV,
Signal frequency: fIN = 100 Hz
3V
UNIT
dB
73
74
73
74
SD16GAINx = 16,
Signal amplitude: VIN = 31 mV,
Signal frequency: fIN = 100 Hz
68
69
68
69
SD16GAINx = 32,
Signal amplitude: VIN = 15 mV,
Signal frequency: fIN = 100 Hz
62
63
62
63
SD16_A, SINAD Performance (fSD16 = 1 MHz, SD16OSRx = 256, SD16REFON = 1) (MSP430F20x3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
SINAD256
44
Signal-to-noise + distortion ratio
(OSR = 256)
TEST CONDITIONS
VCC
PW, N
RSA
MIN
TYP
MIN
TYP
SD16GAINx = 1,
Signal amplitude: VIN = 500 mV,
Signal frequency: fIN = 100 Hz
80
81
82
83
SD16GAINx = 2,
Signal amplitude: VIN = 250 mV,
Signal frequency: fIN = 100 Hz
74
75
76
77
SD16GAINx = 4,
Signal amplitude: VIN = 125 mV,
Signal frequency: fIN = 100 Hz
69
70
71
72
SD16GAINx = 8,
Signal amplitude: VIN = 62 mV,
Signal frequency: fIN = 100 Hz
3V
UNIT
dB
63
64
67
68
SD16GAINx = 16,
Signal amplitude: VIN = 31 mV,
Signal frequency: fIN = 100 Hz
58
59
63
64
SD16GAINx = 32,
Signal amplitude: VIN = 15 mV,
Signal frequency: fIN = 100 Hz
52
53
57
58
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Typical Characteristics, SD16_A SINAD Performance Over OSR (MSP430F20x3)
SINAD PERFORMANCE
vs
OSR
(fSD16 = 1 MHz, SD16REFON = 1,SD16GAINx = 1)
90.0
85.0
SINAD − dB
80.0
75.0
70.0
65.0
RSA
PW, or N
60.0
55.0
10.00
100.00
1000.00
OSR
Figure 23.
SD16_A, Performance (fSD16 = 1 MHz, SD16OSRx = 256, SD16REFON = 1) (MSP430F20x3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
G
Nominal gain
MIN
TYP
MAX
SD16GAINx = 1
TEST CONDITIONS
0.97
1.00
1.02
SD16GAINx = 2
1.90
1.96
2.02
3.76
3.86
3.96
7.36
7.62
7.84
14.56
15.04
15.52
27.20
28.35
29.76
SD16GAINx = 4
SD16GAINx = 8
VCC
3V
SD16GAINx = 16
SD16GAINx = 32
ΔG/ΔT
Gain temperature drift
EOS
Offset error
ΔEOS/ΔT
Offset error temperature
coefficient
CMRR
Common-mode rejection
ratio
SD16GAINx = 1 (1)
SD16GAINx = 1
SD16GAINx = 32
SD16GAINx = 1
SD16GAINx = 32
SD16GAINx = 1,
Common-mode input signal:
VID = 500 mV, fIN = 50 Hz, 100 Hz
SD16GAINx = 32,
Common-mode input signal:
VID = 16 mV, fIN = 50 Hz, 100 Hz
3V
15
3V
ppm/°C
±0.2
3V
UNIT
±1.5
±4
±20
±20
±100
%FSR
ppm
FSR/°C
>90
3V
dB
>75
DC PSR
DC power supply rejection
SD16GAINx = 1, VIN = 500 mV,
VCC = 2.5 V to 3.6 V (2)
2.5 V to 3.6 V
0.35
%/V
AC PSRR
AC power supply rejection
ratio
SD16GAINx = 1,
VCC = 3 V ± 100 mV, fIN = 50 Hz
3V
>80
dB
(1)
(2)
Calculated using the box method: (MAX(-40°C to 85°C) - MIN(-40°C to 85°C)) / MIN(-40°C to 85°C) / (85°C - (-40°C))
Calculated using the ADC output code and the box method:
(MAX-code(2.5 V to 3.6 V) - MIN-code(2.5 V to 3.6 V)) / MIN-code(2.5 V to 3.6 V) / (3.6 V - 2.5 V)
Copyright © 2005–2011, Texas Instruments Incorporated
45
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
SD16_A, Built-In Voltage Reference (MSP430F20x3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
UNIT
3V
1.14
1.20
1.26
V
190
280
VREF
Internal reference voltage
SD16REFON = 1,
SD16VMIDON = 0
IREF
Reference supply current
SD16REFON = 1,
SD16VMIDON = 0
TC
Temperature coefficient
SD16REFON = 1,
SD16VMIDON = 0
CREF
VREF load capacitance
SD16REFON = 1,
SD16VMIDON = 0 (1)
ILOAD
VREF(I) maximum load current
SD16REFON = 1,
SD16VMIDON = 0
3V
tON
Turn-on time
SD16REFON = 0 → 1,
SD16VMIDON = 0,
CREF = 100 nF
3V
DC PSR
DC power supply rejection
ΔVREF/ΔVCC
SD16REFON = 1,
SD16VMIDON = 0,
VCC = 2.5 V to 3.6 V
(1)
-40°C to 85°C
3V
105°C
3V
295
3V
18
50 ppm/°C
100
nF
±200
5
2.5 V to 3.6 V
µA
nA
ms
µV/V
100
There is no capacitance required on VREF. However, a capacitance of at least 100 nF is recommended to reduce any reference voltage
noise.
SD16_A, Reference Output Buffer (MSP430F20x3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
VREF,BUF
Reference buffer output voltage
SD16REFON = 1,
SD16VMIDON = 1
IREF,BUF
Reference supply + reference
output buffer quiescent current
SD16REFON = 1,
SD16VMIDON = 1
CREF(O)
Required load capacitance on
VREF
SD16REFON = 1,
SD16VMIDON = 1
ILOAD,Max
Maximum load current on VREF
SD16REFON = 1,
SD16VMIDON = 1
3V
Maximum voltage variation vs
load current
|ILOAD| = 0 to 1 mA
3V
Turn on time
SD16REFON = 0 → 1,
SD16VMIDON = 1,
CREF = 470 nF
3V
tON
MIN
3V
-40°C to 85°C
105°C
TYP
MAX
1.2
385
3V
UNIT
V
600
660
470
µA
nF
-15
±1
mA
+15
mV
µs
100
SD16_A, External Reference Input (MSP430F20x3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC
MIN
TYP
MAX
VREF(I) Input voltage range
PARAMETER
SD16REFON = 0
3V
1
1.25
1.5
V
IREF(I)
SD16REFON = 0
3V
50
nA
46
Input current
TEST CONDITIONS
UNIT
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
SD16_A, Temperature Sensor (1) (MSP430F20x3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
1.32
1.46 mV/°C
TCSensor
Sensor temperature coefficient
1.18
VOffset,Sensor
Sensor offset voltage
-100
Temperature sensor voltage at
TA = 85°C
VSensor
Temperature sensor voltage at
TA = 25°C
Sensor output voltage (2)
3V
Temperature sensor voltage at
TA = 0°C
(1)
(2)
UNIT
100
435
475
515
355
395
435
320
360
400
mV
mV
Values are not based on calculations using TCSensor or VOffset,sensor but on measurements.
The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
VCC(PGM/ERASE)
Program and erase supply voltage
2.2
fFTG
Flash timing generator frequency
IPGM
Supply current from VCC during program
2.2 V/3.6 V
1
IERASE
Supply current from VCC during erase
2.2 V/3.6 V
1
tCPT
Cumulative program time (1)
2.2 V/3.6 V
tCMErase
Cumulative mass erase time
2.2 V/3.6 V
257
tRetention
Data retention duration
TJ = 25°C
UNIT
3.6
V
476
kHz
5
mA
7
mA
10
ms
20
104
Program/erase endurance
MAX
ms
105
cycles
100
years
Word or byte program time
(2)
30
tFTG
0
Block program time for first byte or word
(2)
25
tFTG
tBlock,
1-63
Block program time for each additional byte or
word
(2)
18
tFTG
tBlock,
End
Block program end-sequence wait time
(2)
6
tFTG
tMass Erase
Mass erase time
(2)
10593
tFTG
tSeg Erase
Segment erase time
(2)
4819
tFTG
tWord
tBlock,
(1)
(2)
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
RAM retention supply voltage
TEST CONDITIONS
(1)
CPU halted
MIN
1.6
MAX
UNIT
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
Copyright © 2005–2011, Texas Instruments Incorporated
47
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V/3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V/3 V
0.025
15
µs
tSBW,En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge (1))
2.2 V/3 V
1
µs
tSBW,Ret
Spy-Bi-Wire return to normal operation time
2.2 V/3 V
15
100
µs
fTCK
TCK input frequency (2)
2.2 V
0
5
MHz
3V
0
10
MHz
RInternal
Internal pulldown resistance on TEST
2.2 V/3 V
25
90
kΩ
(1)
(2)
60
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
(1)
48
TEST CONDITIONS
TA = 25°C
MIN
MAX
2.5
6
UNIT
V
7
V
100
mA
1
ms
Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
APPLICATION INFORMATION, MSP430F20X1
Port P1 (P1.0 to P1.3) Pin Schematics, MSP430F20x1
Pad Logic
To Comparator_A+
From Comparator_A+
CAPD.x
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
DVCC
P1.0/TACLK/ACLK/CA0
P1.1/TA0/CA1
P1.2/TA1/CA2
P1.3/CAOUT/CA3
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
Set
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge
Select
Table 16. Control Signal " From Comparator_A+"
PIN NAME
FUNCTION
SIGNAL "From Comparator_A+" = 1 (1)
P2CA4
P2CA0
P2CA3
P2CA2
P2CA1
P1.0/TACLK/ACLK/CA0
CA0
0
1
N/A
N/A
N/A
P1.1/TA0/CA1
CA1
1
0
0
0
1
P1.2/TA1/CA2
CA2
1
1
0
1
0
P1.3/CAOUT/CA3
CA3
N/A
N/A
0
1
1
(1)
OR
N/A = Not available or not applicable
Copyright © 2005–2011, Texas Instruments Incorporated
49
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Table 17. Port P1 (P1.0 to P1.3) Pin Functions, MSP430F20x1
PIN NAME (P1.x)
x
FUNCTION
P1.0
P1.0/TACLK/ACLK/CA0
0
1
0
0
1
0
ACLK
1
1
0
CA0 (3)
X
X
1
0/1
0
0
Timer_A2.CCI0A
input/output
0
1
0
Timer_A2.TA0
1
1
0
(3)
P1.2 (2) input/output
2
Timer_A2.CCI1A
(1)
(2)
(3)
50
3
X
X
1
0/1
0
0
0
1
0
Timer_A2.TA1
1
1
0
CA2 (3)
X
X
1
0/1
0
0
0
1
0
P1.3 (2) input/output
P1.3/CAOUT/CA3
CAPD.x
0
CA1
P1.2/TA1/CA2
P1SEL.x
0/1
(2)
input/output
P1DIR.x
Timer_A2.TACLK/INCLK
P1.1
P1.1/TA0/CA1
(2)
CONTROL BITS / SIGNALS (1)
N/A
CAOUT
1
1
0
CA3 (3)
X
X
1
X = Don't care
Default after reset (PUC/POR)
Setting the CAPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for
that pin, regardless of the state of the associated CAPD.x bit.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P1 (P1.4 to P1.6) Pin Schematics, MSP430F20x1
Pad Logic
To Comparator_A+
From Comparator_A+
CAPD.x
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
DVCC
P1.4/SMCLK/CA4/TCK
P1.5/TA0/CA5/TMS
P1.6/TA1/CA6/TDI
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
Set
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge
Select
To JTAG
From JTAG
Table 18. Control Signal " From Comparator_A+"
PIN NAME
FUNCTION
SIGNAL "From Comparator_A+" = 1
P2CA3
P2CA2
P2CA1
P1.4/SMCLK/CA4/TCK
CA4
1
0
0
P1.5/TA0/CA5/TMS
CA5
1
0
1
P1.6/TA1/CA6/TDI
CA6
1
1
0
Copyright © 2005–2011, Texas Instruments Incorporated
51
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P1 (P1.7) Pin Schematics, MSP430F20x1
Pad Logic
To Comparator_A+
From Comparator_A+
CAPD.7
P1REN.7
P1DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.7
DVSS
P1.7/CAOUT/CA7/TDO/TDI
Bus
Keeper
P1SEL.7
EN
P1IN.7
EN
Module X IN
D
P1IE.7
P1IRQ.7
EN
Q
P1IFG.7
P1SEL.7
P1IES.7
Set
Interrupt
Edge
Select
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
Table 19. Control Signal " From Comparator_A+"
PIN NAME
P1.7/CAOUT/CA7/TDO/TDI
52
FUNCTION
CA7
SIGNAL "From Comparator_A+" = 1
P2CA3
P2CA2
P2CA1
1
1
1
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Table 20. Port P1 (P1.4 to P1.7) Pin Functions, MSP430F20x1
PIN NAME (P1.x)
FUNCTION (1)
x
P1.4
P1.4/SMCLK/CA4/TCK
4
(3)
6
0
0
1
0
0
SMCLK
1
1
0
0
CA4 (4)
X
X
1
0
(5)
(5)
(6)
X
1
0
0
0
0
1
0
0
1
1
0
0
X
X
1
0
TMS (5)
X
X
X
1
(3)
0/1
0
0
0
N/A
input/output
0
1
0
0
Timer_A2.TA1
1
1
0
0
CA6 (4)
X
X
1
0
(5)
N/A
(1)
(2)
(3)
(4)
X
CA5 (4)
P1.7 (3) input/output
7
X
0/1
Timer_A2.TA0
TDI
P1.7/CAOUT/CA7/TDO/TDI
JTAG Mode
0
P1.6
P1.6/TA1/CA6/TDI
CAPD.x
0
N/A
5
P1SEL.x
0/1
P1.5 (3) input/output
P1.5/TA0/CA5/TMS
P1DIR.x
N/A
TCK
input/output
CONTROL BITS / SIGNALS (2)
X
X
X
1
0/1
0
0
0
0
1
0
0
CAOUT
1
1
0
0
CA7 (4)
X
X
1
0
TDO/TDI (5) (6)
X
X
X
1
N/A = Not available or not applicable
X = Don't care
Default after reset (PUC/POR)
Setting the CAPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for
that pin, regardless of the state of the associated CAPD.x bit.
In JTAG mode the internal pullup/down resistors are disabled.
Function controlled by JTAG
Copyright © 2005–2011, Texas Instruments Incorporated
53
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P2 (P2.6) Pin Schematics, MSP430F20x1
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT
LFXT1 off
0
LFXT1CLK
1
P2SEL.7
Pad Logic
P2REN.6
P2DIR.6
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.6
DVSS
P2.6/XIN/TA1
Bus
Keeper
P2SEL.6
EN
P2IN.6
EN
Module X IN
D
P2IE.6
P2IRQ.6
EN
Q
P2IFG.6
P2SEL.6
P2IES.6
Set
Interrupt
Edge
Select
Table 21. Port P2 (P2.6) Pin Functions, MSP430F20x1
PIN NAME (P2.x)
x
CONTROL BITS / SIGNALS
FUNCTION
P2DIR.x
P2SEL.x
0/1
0
XIN (1) (2)
0
1
Timer_A2.TA1
1
1
P2.6 input/output
P2.6/XIN/TA1
(1)
(2)
54
6
Default after reset (PUC/POR)
XIN is used as digital clock input if the bits LFXT1Sx in register BCSCTL3 are set to 11.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P2 (P2.7) Pin Schematics, MSP430F20x1
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
LFXT1 off
0
LFXT1CLK
From P2.6/XIN
1
P2.6/XIN/TA1
Pad Logic
P2SEL.6
P2REN.7
P2DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.7
DVSS
P2.7/XOUT
Bus
Keeper
P2SEL.7
EN
P2IN.7
EN
Module X IN
D
P2IE.7
P2IRQ.7
EN
Q
Set
P2IFG.7
Interrupt
Edge
Select
P2SEL.7
P2IES.7
Table 22. Port P2 (P2.7) Pin Functions, MSP430F20x1
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL.x
0/1
0
DVSS
0
1
XOUT (1) (2)
1
1
P2.7 input/output
P2.7/XOUT
(1)
(2)
7
CONTROL BITS / SIGNALS
Default after reset (PUC/POR)
If the pin P2.7/XOUT is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this
pin after reset.
Copyright © 2005–2011, Texas Instruments Incorporated
55
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
APPLICATION INFORMATION, MSP430F20X2
Port P1 (P1.0 to P1.2) Pin Schematics, MSP430F20x2
Pad Logic
To ADC 10
INCHx = x
ADC10AE.x
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
DVCC
Bus
Keeper
P1SEL.x
P1.0/TACLK/ACLK/A0
P1.1/TA0/A1
P1.2/TA1/A2
EN
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
P1IFG.x
P1SEL.x
P1IES.x
56
EN
Q
Set
Interrupt
Edge
Select
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Table 23. Port P1 (P1.0 to P1.2) Pin Functions, MSP430F20x2
PIN NAME (P1.x)
x
FUNCTION
P1.0
P1.0/TACLK/ACLK/A0
0
1
(1)
(2)
(3)
(4)
INCHx
0
0
N/A
1
0
N/A
ACLK
1
1
0
N/A
A0 (4)
X
X
1
0
0/1
0
0
N/A
Timer_A2.CCI0A
input/output
0
1
0
N/A
Timer_A2.TA0
1
1
0
N/A
(4)
P1.2 (3) input/output
2
ADC10AE.x
0
A1
P1.2/TA1/A2
P1SEL.x
0/1
(3)
input/output
P1DIR.x
Timer_A2.TACLK/INCLK
P1.1
P1.1/TA0/A1
(3)
CONTROL BITS / SIGNALS (1) (2)
Timer_A2.CCI1A
X
X
1
1
0/1
0
0
N/A
0
1
0
N/A
Timer_A2.TA1
1
1
0
N/A
A2 (4)
X
X
1
2
X = Don't care
N/A = Not available or not applicable
Default after reset (PUC/POR)
Setting the ADC10AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Copyright © 2005–2011, Texas Instruments Incorporated
57
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P1 (P1.3) Pin Schematics, MSP430F20x2
SREF2
VSS
0
To ADC 10 VR−
Pad Logic
1
A3
INCHx = 3
ADC10AE.3
P1REN.3
P1DIR.3
0
P1OUT.3
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P1.3/ADC10CLK/
A3/VREF−/VeREF−
Bus
Keeper
P1SEL.3
EN
P1IN.3
EN
Module X IN
D
P1IE.3
P1IRQ.3
EN
Q
P1IFG.3
Set
Interrupt
Edge
Select
P1SEL.3
P1IES.3
Table 24. Port P1 (P1.3) Pin Functions, MSP430F20x2
PIN NAME (P1.x)
x
FUNCTION
P1SEL.x
ADC10AE.x
INCHx
0/1
0
0
N/A
N/A
0
1
0
N/A
ADC10CLK
1
1
0
N/A
A3 (4)
X
X
1
3
X
X
1
N/A
P1.3 (3) input/output
P1.3/ADC10CLK/A3/
VREF-/VeREF-
3
VREF-/VeREF-
(1)
(2)
(3)
(4)
(5)
58
CONTROL BITS / SIGNALS (1) (2)
P1DIR.x
(4) (5)
X = Don't care
N/A = Not available or not applicable
Default after reset (PUC/POR)
Setting the ADC10AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
An applied voltage is used as negative reference if bit SREF3 in register ADC10CTL0 is set.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P1 (P1.4) Pin Schematic, MSP430F20x2
Pad Logic
To /from ADC 10
positive reference
A4
INCHx = 4
ADC10AE.4
P1REN.4
P1DIR.4
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P1OUT.4
DVSS
DVCC
P1.4/SMCLK/A4/VREF+/VeREF+/TCK
Bus
Keeper
P1SEL.4
EN
EN
Module X IN
D
P1IE.4
P1IRQ.4
EN
Q
P1IFG.4
P1SEL.4
P1IES.4
Set
Interrupt
Edge
Select
To JTAG
From JTAG
Copyright © 2005–2011, Texas Instruments Incorporated
59
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P1 (P1.5) Pin Schematics, MSP430F20x2
Pad Logic
A5
INCHx = 5
ADC10AE.5
P1REN.5
P1SEL.5
USIPE5
P1DIR.5
0
USI Module Direction
1
P1OUT.5
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.5/TA0/SCLK/A5/TMS
Bus
Keeper
EN
P1IN.5
EN
Module X IN
D
P1IE.5
P1IRQ.5
EN
Q
P1IFG.5
P1SEL.5
P1IES.5
Set
Interrupt
Edge
Select
To JTAG
From JTAG
60
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P1 (P1.6) Pin Schematics, MSP430F20x2
Pad Logic
A6
INCHx = 6
ADC10AE.6
P1REN.6
P1SEL.6
USIPE6
P1DIR.6
0
USI Module Direction
1
P1OUT.6
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.6/TA1/SDO/SCL/A6/TDI
USI Module Output
(I2C Mode)
Bus
Keeper
EN
P1IN.6
EN
Module X IN
D
P1IE.6
P1IRQ.6
EN
Q
P1IFG.6
P1SEL.6
P1IES.6
Set
Interrupt
Edge
Select
To JTAG
From JTAG
Copyright © 2005–2011, Texas Instruments Incorporated
61
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P1 (P1.7) Pin Schematics, MSP430F20x2
Pad Logic
A7
INCHx = 7
ADC10AE.7
P1REN.7
P1SEL.7
USIPE7
P1DIR.7
0
USI Module Direction
1
P1OUT.7
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.7/SDI/SDA/A7/TDO/TDI
USI Module Output
(I2C Mode)
Bus
Keeper
EN
P1IN.7
EN
Module X IN
D
P1IE.7
P1IRQ.7
EN
Q
P1IFG.7
P1SEL.7
P1IES.7
Set
Interrupt
Edge
Select
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
62
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Table 25. Port P1 (P1.4 to P1.7) Pin Functions, MSP430F20x2
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
USIP.x
ADC10AE.x
INCHx
JTAG Mode
0/1
0
N/A
0
N/A
0
N/A
0
1
N/A
0
N/A
0
SMCLK
1
1
N/A
0
N/A
0
A4 (4)
X
X
N/A
1
4
0
VREF+/VeREF+ (4) (5)
X
X
N/A
1
N/A
0
TCK (6)
X
X
N/A
X
X
1
0/1
0
0
0
N/A
0
N/A
0
1
0
0
N/A
0
Timer_A2.TA0
1
1
0
0
N/A
0
SCLK
X
X
1
0
N/A
0
A5 (4)
X
X
X
1
5
0
TMS (6)
X
X
X
X
X
1
0/1
0
0
0
N/A
0
Timer_A2.CCI1B
0
1
0
0
N/A
0
Timer_A2.TA1
1
1
0
0
N/A
0
SDO (SPI) / SCL (I2C)
X
X
1
0
N/A
0
A6 (4)
X
X
X
1
6
0
TDI (6)
X
X
X
X
X
1
0/1
0
0
0
N/A
0
N/A
0
1
0
0
N/A
0
DVSS
1
1
0
0
N/A
0
SDI (SPI) / SDA (I2C)
X
X
1
0
N/A
0
A7 (4)
X
X
X
1
7
0
TDO/TDI (6) (7)
X
X
X
X
X
1
P1.4 (3) input/output
P1.4/SMCLK/A4/
VREF+/VeREF+/TCK
4
P1.5 (3) input/output
P1.5/TA0/SCLK/A5/TMS
5
P1.6 (3) input/output
P1.6/TA1/SDO/SCL/A6/TDI
6
P1.7 (3) input/output
P1.7/SDI/SDA/A7/TDO/TDI
(1)
(2)
(3)
(4)
(5)
(6)
(7)
7
CONTROL BITS / SIGNALS (1) (2)
X = Don't care
N/A = Not available or not applicable
Default after reset (PUC/POR)
Setting the ADC10AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
The reference voltage is output if bit REFOUT in register ADC10CTL0 is set. An applied voltage is used as positive reference if bits
SREF0/1 in register ADC10CTL0 are set to 10 or 11.
In JTAG mode the internal pullup/down resistors are disabled.
Function controlled by JTAG.
Copyright © 2005–2011, Texas Instruments Incorporated
63
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P2 (P2.6) Pin Schematics, MSP430F20x2
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT
LFXT1 off
0
LFXT1CLK
1
P2SEL.7
Pad Logic
P2REN.6
P2DIR.6
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.6
DVSS
P2.6/XIN/TA1
Bus
Keeper
P2SEL.6
EN
P2IN.6
EN
Module X IN
D
P2IE.6
P2IRQ.6
EN
Q
P2IFG.6
P2SEL.6
P2IES.6
Set
Interrupt
Edge
Select
Table 26. Port P2 (P2.6) Pin Functions, MSP430F20x2
PIN NAME (P2.x)
x
CONTROL BITS / SIGNALS
FUNCTION
P2DIR.x
P2SEL.x
0/1
0
XIN (1) (2)
0
1
Timer_A2.TA1
1
1
P2.6 input/output
P2.6/XIN/TA1
(1)
(2)
64
6
Default after reset (PUC/POR)
XIN is used as digital clock input if the bits LFXT1Sx in register BCSCTL3 are set to 11.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P2 (P2.7) Pin Schematics, MSP430F20x2
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
LFXT1 off
0
LFXT1CLK
From P2.6/XIN
1
P2.6/XIN/TA1
Pad Logic
P2SEL.6
P2REN.7
P2DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.7
DVSS
P2.7/XOUT
Bus
Keeper
P2SEL.7
EN
P2IN.7
EN
Module X IN
D
P2IE.7
P2IRQ.7
EN
Q
Set
P2IFG.7
Interrupt
Edge
Select
P2SEL.7
P2IES.7
Table 27. Port P2 (P2.7) Pin Functions, MSP430F20x2
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL.x
0/1
0
DVSS
0
1
XOUT (1) (2)
1
1
P2.7 input/output
P2.7/XOUT
(1)
(2)
7
CONTROL BITS / SIGNALS
Default after reset (PUC/POR)
If the pin P2.7/XOUT is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this
pin after reset.
Copyright © 2005–2011, Texas Instruments Incorporated
65
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
APPLICATION INFORMATION, MSP430F20X3
Port P1 (P1.0) Pin Schematics, MSP430F20x3
INCH=0
Pad Logic
A0+
SD16AE.0
P1REN.0
P1DIR.0
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.0
DVSS
P1.0/TACLK/ACLK/A0+
Bus
Keeper
P1SEL.0
EN
P1IN.0
EN
Module X IN
D
P1IE.0
P1IRQ.0
P1IFG.0
P1SEL.0
P1IES.0
66
EN
Q
Set
Interrupt
Edge
Select
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P1 (P1.1) Pin Schematics, MSP430F20x3
INCH=4
Pad Logic
A4+
INCH=0
0
A0−
AV SS
1
SD16AE.1
P1REN.1
P1DIR.1
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.1
DVSS
P1.1/TA 0/A0−/A4+
Bus
Keeper
P1SEL.1
EN
P1IN.1
EN
Module X IN
D
P1IE.1
P1IRQ.1
EN
Q
Set
P1IFG.1
P1SEL.1
P1IES.1
Interrupt
Edge
Select
Copyright © 2005–2011, Texas Instruments Incorporated
67
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P1 (P1.2) Pin Schematics, MSP430F20x3
INCH=1
Pad Logic
A1+
INCH=4
0
A4−
AV SS
1
SD16AE.2
P1REN.2
P1DIR.2
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.2
DVSS
P1.2/TA 1/A1+/A4−
Bus
Keeper
P1SEL.2
EN
P1IN.2
EN
Module X IN
D
P1IE.2
P1IRQ.2
P1IFG.2
P1SEL.2
P1IES.2
68
EN
Q
Set
Interrupt
Edge
Select
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P1 (P1.3) Pin Schematics, MSP430F20x3
Pad Logic
VREF
INCH=1
0
A1−
AV SS
1
SD16AE.3
P1REN.3
P1DIR.3
0
0
1
1
Direction
0: Input
1: Output
1
P1OUT.3
DVSS
DVCC
0
1
P1.3/VREF/A1−
Bus
Keeper
P1SEL.3
EN
P1IN.3
P1IE.3
P1IRQ.3
EN
Q
P1IFG.3
P1SEL.3
P1IES.3
Set
Interrupt
Edge
Select
Copyright © 2005–2011, Texas Instruments Incorporated
69
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Table 28. Port P1 (P1.0 to P1.3) Pin Functions, MSP430F20x3
PIN NAME (P1.x)
x
FUNCTION
P1.0
P1.0/TACLK/ACLK/A0+
0
1
0
N/A
1
0
N/A
ACLK
1
1
0
N/A
A0+ (4)
X
X
1
0
0/1
0
0
N/A
Timer_A2.CCI0A
input/output
0
1
0
N/A
Timer_A2.TA0
1
1
0
N/A
X
X
1
0
X
X
1
4
0/1
0
0
N/A
Timer_A2.CCI1A
0
1
0
N/A
Timer_A2.TA1
1
1
0
N/A
A1+ (4)
X
X
1
1
A4- (4) (5)
X
X
1
4
(4) (5)
P1.2 (3) input/output
P1.3
P1.3/VREF/A1-
(1)
(2)
(3)
(4)
(5)
70
3
INCHx
0
A4+ (4)
2
SD16AE.x
0
A0-
P1.2/TA1/A1+/A4-
P1SEL.x
0/1
(3)
input/output
P1DIR.x
Timer_A2.TACLK/INCLK
P1.1
P1.1/TA0/A0-/A4+
(3)
CONTROL BITS / SIGNALS (1) (2)
(3)
0/1
0
0
N/A
VREF
input/output
X
1
0
N/A
A1- (4) (5)
X
X
1
1
X = Don't care
N/A = Not available or not applicable
Default after reset (PUC/POR)
Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
With SD16AE.x = 0 the negative inputs are connected to VSS if the corresponding input is selected.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P1 (P1.4) Pin Schematics, MSP430F20x3
INCH=2
Pad Logic
A2+
SD16AE.4
P1REN.4
P1DIR.4
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P1OUT.4
DVSS
DVCC
P1.4/SMCLK/A2+/TCK
Bus
Keeper
P1SEL.4
EN
P1IN.4
EN
Module X IN
D
P1IE.4
P1IRQ.4
EN
Q
P1IFG.4
P1SEL.4
P1IES.4
Set
Interrupt
Edge
Select
To JTAG
From JTAG
Copyright © 2005–2011, Texas Instruments Incorporated
71
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P1 (P1.5) Pin Schematics, MSP430F20x3
Pad Logic
INCH=2
0
A2−
AV SS
1
SD16AE.5
P1REN.5
P1SEL.5
USIPE5
P1DIR.5
0
USI Module Direction
1
P1OUT.5
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.5/TA 0/SCLK/A2−/TMS
Bus
Keeper
EN
P1IN.5
EN
Module X IN
D
P1IE.5
P1IRQ.5
EN
Q
P1IFG.5
P1SEL.5
P1IES.5
Set
Interrupt
Edge
Select
To JTAG
From JTAG
72
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P1 (P1.6) Pin Schematics, MSP430F20x3
Pad Logic
INCH=3
A3+
SD16AE.6
P1REN.6
P1SEL.6
USIPE6
P1DIR.6
0
USI Module Direction
1
P1OUT.6
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.6/TA1/SDO/SCL/A3+/TDI
USI Module Output
(I2C Mode)
Bus
Keeper
EN
P1IN.6
EN
Module X IN
D
P1IE.6
P1IRQ.6
EN
Q
P1IFG.6
P1SEL.6
P1IES.6
Set
Interrupt
Edge
Select
To JTAG
From JTAG
Copyright © 2005–2011, Texas Instruments Incorporated
73
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P1 (P1.7) Pin Schematics, MSP430F20x3
Pad Logic
INCH=3
0
A3−
AV SS
1
SD16AE.x
P1REN.x
P1SEL.x
USIPE7
P1DIR.x
0
USI Module Direction
1
P1OUT.x
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.7/SDI/SDA/A3−/TDO/TDI
USI Module Output
(I2C Mode)
Bus
Keeper
EN
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
74
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Table 29. Port P1 (P1.4 to P1.7) Pin Functions, MSP430F20x3
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
USIP.x
SD16AE.x
INCHx
JTAG Mode
0/1
0
N/A
0
N/A
0
N/A
0
1
N/A
0
N/A
0
SMCLK
1
1
N/A
0
N/A
0
A2+ (4)
X
X
N/A
1
2
0
TCK (5)
X
X
N/A
X
X
1
0/1
0
0
0
N/A
0
N/A
0
1
0
0
N/A
0
Timer_A2.TA0
1
1
0
0
N/A
0
SCLK
X
X
1
0
N/A
0
X
X
X
1
2
0
X
X
X
X
X
1
0/1
0
0
0
N/A
0
Timer_A2.CCI1B
0
1
0
0
N/A
0
Timer_A2.TA1
1
1
0
0
N/A
0
SDO (SPI) / SCL (I2C)
X
X
1
0
N/A
0
A3+ (4)
X
X
X
1
3
0
TDI (5)
X
X
X
X
X
1
0/1
0
0
0
N/A
0
N/A
0
1
0
0
N/A
0
DVSS
1
1
0
0
N/A
0
SDI (SPI) / SDA (I2C)
X
X
1
0
N/A
0
A3- (4) (6)
X
X
X
1
3
0
TDO/TDI (5) (7)
X
X
X
X
X
1
P1.4 (3) input/output
P1.4/SMCLK/A2+/TCK
4
P1.5 (3) input/output
P1.5/TA0/SCLK/A2-/TMS
5
A2-
(4) (6)
TMS (5)
P1.6 (3) input/output
P1.6/TA1/SDO/SCL/
A3+/TDI
6
P1.7 (3) input/output
P1.7/SDI/SDA/A3-/
TDO/TDI
(1)
(2)
(3)
(4)
(5)
(6)
(7)
7
CONTROL BITS / SIGNALS (1) (2)
X = Don't care
N/A = Not available or not applicable
Default after reset (PUC/POR)
Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
In JTAG mode the internal pullup/down resistors are disabled.
With SD16AE.x = 0 the negative inputs are connected to VSS if the corresponding input is selected.
Function controlled by JTAG
Copyright © 2005–2011, Texas Instruments Incorporated
75
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P2 (P2.6) Pin Schematics, MSP430F20x3
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT
LFXT1 off
0
LFXT1CLK
1
P2SEL.7
Pad Logic
P2REN.6
P2DIR.6
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.6
DVSS
P2.6/XIN/TA1
Bus
Keeper
P2SEL.6
EN
P2IN.6
EN
Module X IN
D
P2IE.6
P2IRQ.6
EN
Q
P2IFG.6
P2SEL.6
P2IES.6
Set
Interrupt
Edge
Select
Table 30. Port P2 (P2.6) Pin Functions, MSP430F20x3
PIN NAME (P2.x)
x
CONTROL BITS / SIGNALS
FUNCTION
P2DIR.x
P2SEL.x
0/1
0
XIN (1) (2)
0
1
Timer_A2.TA1
1
1
P2.6 input/output
P2.6/XIN/TA1
(1)
(2)
76
6
Default after reset (PUC/POR)
XIN is used as digital clock input if the bits LFXT1Sx in register BCSCTL3 are set to 11.
Copyright © 2005–2011, Texas Instruments Incorporated
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
Port P2 (P2.7) Pin Schematics, MSP430F20x3
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
LFXT1 off
0
LFXT1CLK
From P2.6/XIN
1
P2.6/XIN/TA1
Pad Logic
P2SEL.6
P2REN.7
P2DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.7
DVSS
P2.7/XOUT
Bus
Keeper
P2SEL.7
EN
P2IN.7
EN
Module X IN
D
P2IE.7
P2IRQ.7
EN
Q
Set
P2IFG.7
Interrupt
Edge
Select
P2SEL.7
P2IES.7
Table 31. Port P2 (P2.7) Pin Functions, MSP430F20x3
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL.x
0/1
0
DVSS
0
1
XOUT (1) (2)
1
1
P2.7 input/output
P2.7/XOUT
(1)
(2)
7
CONTROL BITS / SIGNALS
Default after reset (PUC/POR)
If the pin P2.7/XOUT is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this
pin after reset.
Copyright © 2005–2011, Texas Instruments Incorporated
77
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491G – AUGUST 2005 – REVISED APRIL 2011
www.ti.com
REVISION HISTORY
LITERATURE
NUMBER
SLAS491
78
SUMMARY
Preliminary PRODUCT PREVIEW data sheet release
SLAS491A
Production data sheet release for MSP430F20x3I.
Updated specification and added characterization graphs.
SLAS491B
Production data sheet release for MSP430F20x3T, MSP430F20x1I and MSP430F20x1T.
105°C characterization results added.
SD16_A SINAD characterization results for MSP430F20x3
RSA package added.
Updated SD16_A Power Supply Rejection specification.
DCO Calibration Register names: lower case "z" changed to upper case "Z".
Vhys(B_IT-) MAX specification increased from 180 mV to 210 mV.
MIN and MAX percentages for "calibrated DCO frequencies - tolerance over supply voltage VCC" corrected from 2.5% to
3.0% to match the specified frequency ranges.
SLAS491C
Production data sheet release for MSP430F20x2I and MSP430F20x2T.
SLAS491D
Changed fACLK to 0 Hz in ILPM4 test conditions on page 23.
SLAS491E
Changed Tstg maximum for programmed devices to 150°C (page 20)
SLAS491F
Added ADC10 data transfer registers to Peripheral File Map (page 18, 19)
SLAS491G
Changed Test Conditions for "Duty cycle, LF mode" in Crystal Oscillator, XT1, Low-Frequency Mode
Changed note (1) on 10-Bit ADC, Built-In Voltage Reference.
Changed USIP.x Control Bits in Table 25 and Table 29
Copyright © 2005–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
MSP430F2001IN
ACTIVE
PDIP
N
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2001IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2001IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2001IRSAR
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2001IRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2001TN
ACTIVE
PDIP
N
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2001TPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2001TPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2001TRSAR
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2001TRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2002IN
ACTIVE
PDIP
N
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2002IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2002IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2002IRSAR
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2002IRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2002TN
ACTIVE
PDIP
N
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2002TPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2002TPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
Samples
(Requires Login)
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
11-Jun-2011
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
MSP430F2002TRSAR
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2002TRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2003IN
ACTIVE
PDIP
N
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2003IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2003IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2003IRSAR
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2003IRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2003TN
ACTIVE
PDIP
N
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2003TPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2003TPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2003TRSAR
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2003TRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2011IN
ACTIVE
PDIP
N
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2011IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2011IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2011IRSAR
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2011IRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2011TN
ACTIVE
PDIP
N
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2011TPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 2
Samples
(Requires Login)
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
11-Jun-2011
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
MSP430F2011TPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2011TRSAR
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2011TRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2012IN
ACTIVE
PDIP
N
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2012IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2012IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2012IRSAR
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2012IRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2012TN
ACTIVE
PDIP
N
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2012TPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2012TPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2012TRSAR
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2012TRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2013IN
ACTIVE
PDIP
N
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2013IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2013IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2013IRSAR
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2013IRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2013TN
ACTIVE
PDIP
N
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 3
Samples
(Requires Login)
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
11-Jun-2011
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
MSP430F2013TPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2013TPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430F2013TRSAR
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430F2013TRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430F2001IPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
MSP430F2001IRSAR
QFN
RSA
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2001IRSAT
QFN
RSA
16
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2001TRSAR
QFN
RSA
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2001TRSAT
QFN
RSA
16
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2002IPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
MSP430F2002IRSAR
QFN
RSA
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2002IRSAT
QFN
RSA
16
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2002TPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
MSP430F2002TRSAR
QFN
RSA
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2002TRSAT
QFN
RSA
16
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2003IPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
MSP430F2003IRSAR
QFN
RSA
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2003IRSAT
QFN
RSA
16
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2003TPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
MSP430F2003TRSAR
QFN
RSA
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2003TRSAT
QFN
RSA
16
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2011IPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2011
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430F2011IRSAR
QFN
RSA
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2011IRSAT
QFN
RSA
16
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2011TPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
MSP430F2011TRSAR
QFN
RSA
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2011TRSAT
QFN
RSA
16
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2012IPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
MSP430F2012IRSAR
QFN
RSA
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2012IRSAT
QFN
RSA
16
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2012TPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
MSP430F2012TRSAR
QFN
RSA
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2012TRSAT
QFN
RSA
16
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2013IPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
MSP430F2013IRSAR
QFN
RSA
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2013IRSAT
QFN
RSA
16
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2013TPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
MSP430F2013TRSAR
QFN
RSA
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430F2013TRSAT
QFN
RSA
16
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
*All dimensions are nominal
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2011
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430F2001IPWR
TSSOP
PW
14
2000
346.0
346.0
29.0
MSP430F2001IRSAR
QFN
RSA
16
3000
346.0
346.0
29.0
MSP430F2001IRSAT
QFN
RSA
16
250
190.5
212.7
31.8
MSP430F2001TRSAR
QFN
RSA
16
3000
346.0
346.0
29.0
MSP430F2001TRSAT
QFN
RSA
16
250
190.5
212.7
31.8
MSP430F2002IPWR
TSSOP
PW
14
2000
346.0
346.0
29.0
MSP430F2002IRSAR
QFN
RSA
16
3000
346.0
346.0
29.0
MSP430F2002IRSAT
QFN
RSA
16
250
190.5
212.7
31.8
MSP430F2002TPWR
TSSOP
PW
14
2000
346.0
346.0
29.0
MSP430F2002TRSAR
QFN
RSA
16
3000
346.0
346.0
29.0
MSP430F2002TRSAT
QFN
RSA
16
250
190.5
212.7
31.8
MSP430F2003IPWR
TSSOP
PW
14
2000
346.0
346.0
29.0
MSP430F2003IRSAR
QFN
RSA
16
3000
346.0
346.0
29.0
MSP430F2003IRSAT
QFN
RSA
16
250
190.5
212.7
31.8
MSP430F2003TPWR
TSSOP
PW
14
2000
346.0
346.0
29.0
MSP430F2003TRSAR
QFN
RSA
16
3000
346.0
346.0
29.0
MSP430F2003TRSAT
QFN
RSA
16
250
190.5
212.7
31.8
MSP430F2011IPWR
TSSOP
PW
14
2000
346.0
346.0
29.0
MSP430F2011IRSAR
QFN
RSA
16
3000
346.0
346.0
29.0
MSP430F2011IRSAT
QFN
RSA
16
250
190.5
212.7
31.8
MSP430F2011TPWR
TSSOP
PW
14
2000
346.0
346.0
29.0
MSP430F2011TRSAR
QFN
RSA
16
3000
346.0
346.0
29.0
MSP430F2011TRSAT
QFN
RSA
16
250
190.5
212.7
31.8
MSP430F2012IPWR
TSSOP
PW
14
2000
346.0
346.0
29.0
MSP430F2012IRSAR
QFN
RSA
16
3000
346.0
346.0
29.0
MSP430F2012IRSAT
QFN
RSA
16
250
190.5
212.7
31.8
MSP430F2012TPWR
TSSOP
PW
14
2000
346.0
346.0
29.0
MSP430F2012TRSAR
QFN
RSA
16
3000
346.0
346.0
29.0
MSP430F2012TRSAT
QFN
RSA
16
250
190.5
212.7
31.8
MSP430F2013IPWR
TSSOP
PW
14
2000
346.0
346.0
29.0
MSP430F2013IRSAR
QFN
RSA
16
3000
346.0
346.0
29.0
MSP430F2013IRSAT
QFN
RSA
16
250
190.5
212.7
31.8
MSP430F2013TPWR
TSSOP
PW
14
2000
346.0
346.0
29.0
MSP430F2013TRSAR
QFN
RSA
16
3000
346.0
346.0
29.0
MSP430F2013TRSAT
QFN
RSA
16
250
190.5
212.7
31.8
Pack Materials-Page 3
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