PRELIMINARY Integrated Circuit Systems, Inc. ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS858012 is a high speed 1-to-2 Differentialto-2.5V, 3.3V LVPECL Fanout Buffer and is a HiPerClockS™ member of the HiPerClockS™ family of high performance clock solutions from ICS. The ICS858012 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVPECL, LVDS, LVHSTL and HCSL to be easily interfaced to the input with minimal use of external components. The ICS858012 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications. • Two differential LVPECL outputs ICS • One differential LVPECL clock input • IN, nIN pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency: 2GHz (typical) • Output skew: <15ps (typical) • Part-to-part skew: TBD • Additive phase jitter, RMS: TBD • Propagation delay: 350ps (typical) • Operating voltage supply range: VCC = 2.375V to 3.63V, VEE = 0V • -40°C to 85°C ambient operating temperature • Availabe in both standard and lead-free RoHS compliant packages VCC VEE IN 1 16 15 14 13 12 Q0 nQ1 nIN 4 9 Q1 Q1 nQ1 VREF_AC 5 6 7 8 VCC nQ0 10 VEE 11 VEE VT 2 VREF_AC 3 VCC IN VT nIN Q0 nQ0 VEE PIN ASSIGNMENT VCC BLOCK DIAGRAM ICS858012 16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 858012AK www.icst.com/products/hiperclocks.html 1 REV. A NOVEMBER 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 IN Input Non-inver ting LVPECL differential clock input. 2 VT Input Termination input. 3 VREF_AC Output 4 nIN Input Inver ting differential LVPECL clock input. 5, 8, 13, 16 VCC Power Positive supply pins. 6, 7, 14, 15 VEE Power Negative supply pin. 9, 10 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 11, 12 nQ0, Q0 Output Differential output pair. LVPECL interface levels. 858012AK Reference voltage for AC-coupled applications. VREF_AC = to VCC - 1.38V. www.icst.com/products/hiperclocks.html 2 REV. A NOVEMBER 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Input Current, IN, nIN 4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -0.5V to VCC + 0.5 V to the device. These ratings are stress specifi50mA cations only. Functional operation of product at 100mA these conditions or any conditions beyond those ±50mA listed in the DC Characteristics or AC Character- VT Current, IVT ±100mA Input Sink/Source, IREF_AC ± 0.5mA Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 51.5°C/W (0 lfpm) (Junction-to-Ambient) TABLE 2A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current TO 3.63V; VEE = 0V Test Conditions Minimum Typical Maximum Units 2.375 3.3 3.63 V Max., VCC, No Load 30 mA TABLE 2B. DC CHARACTERISTICS, VCC = 2.375V TO 3.63V; VEE = 0V Symbol Parameter RIN Differential Input Resistance Test Conditions Minimum Typical Maximum Units (IN, nIN) 40 50 60 Ω VIH Input High Voltage (IN, nIN) 1.2 VCC V VIL Input Low Voltage (IN, nIN) 0 VIH - 0.15 V VIN Input Voltage Swing; NOTE 1 0.1 1.7 VDIFF_IN Differential Input Voltage Swing 0.3 IN to VT VREF_AC Output Reference Voltage VCC - 1.525 V V VCC - 1.4 1.28 V VCC - 1.325 V Maximum Units VCC - 0.895 V NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing Diagram TABLE 2C. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.63V; VEE = 0V Symbol Parameter VOH Output High Voltage; NOTE 1 Conditions VCC - 1.145 Minimum Typical VOL Output Low Voltage; NOTE 1 VCC - 1.945 VOUT Output Voltage Swing 550 800 mV VDIFF_OUT Differential Output Voltage Swing 1100 1600 mV VCC - 1.695 V NOTE 1: Outputs terminated with 100Ω across differential output pair. 858012AK www.icst.com/products/hiperclocks.html 3 REV. A NOVEMBER 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER TABLE 3. AC CHARACTERISTICS, VCC = 0V; VEE = -3.63V TO -2.375V OR VCC = 2.375 TO 3.63V; VEE = 0V Symbol Parameter Condition fMAX Output Frequency fIN Input Frequency Propagation Delay; (Differential); NOTE 1 Output Skew; NOTE 2, 4 t PD tsk(o) tsk(pp) t jit tR/tF Minimum Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time 20% to 80% Typical Maximum Units 2 GHz 2.5 GHz 350 ps <15 ps TBD ps TBD fs 152 ps All parameters characterized at ≤ 1GHz unless otherwise noted. RL = 100Ω after each output pair. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 858012AK www.icst.com/products/hiperclocks.html 4 REV. A NOVEMBER 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V VCC Qx VCC SCOPE nIN LVPECL V Cross Points IN nQx VEE V IH IN V IL V EE -0.375V to -1.63V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nQx nQy nQy Qx PART 2 Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nIN VDIF_IN VIN IN nQ0, nQ1 VIN, VOUT VDIFF_IN, VDIFF_OUT 800mV (typical) 1.6V (typical) Q0, Q1 tPD PROPAGATION DELAY SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING 80% 80% VSW I N G Clock Outputs 20% 20% tR tF OUTPUT RISE/FALL TIME 858012AK www.icst.com/products/hiperclocks.html 5 REV. A NOVEMBER 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION LVPECL INPUT WITH Ω TERMINATION INTERFACE (2.5V) BUILT-IN 50Ω The IN/nIN with built-in 50Ω terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 1A to 1E show interface examples for the HiPerClockS IN/nIN input with built-in 50Ω terminations driven 3.3V or 2.5V by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm IN IN VT Zo = 50 Ohm nIN LVDS nIN Receiver With Built-In 50 Ohm Receiver With Built-In 50 Ohm 2.5V LVPECL R1 18 FIGURE 1A. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN LVDS DRIVER BUILT-IN 50Ω 2.5V VT Zo = 50 Ohm FIGURE 1B. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN LVPECL DRIVER BUILT-IN 50Ω 2.5V 2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm IN IN VT Zo = 50 Ohm nIN CML - Open Collector Zo = 50 Ohm VT nIN Receiver With Built-In 50 Ohm CML - Built-in 50 Ohm Pull-up Receiver With Built-In 50 Ohm FIGURE 1D. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY A CML DRIVER BUILT-IN 50Ω Ω PULLUP WITH BUILT-IN 50Ω FIGURE 1C. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN OPEN COLLECTOR BUILT-IN 50Ω CML DRIVER 2.5V 2.5V R1 25 Zo = 50 Ohm IN Zo = 50 Ohm VT nIN R2 SSTL 25 Receiver With Built-In 50Ω FIGURE 1E. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN SSTL DRIVER BUILT-IN 50Ω 858012AK www.icst.com/products/hiperclocks.html 6 REV. A NOVEMBER 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER LVPECL INPUT WITH BUILT-IN 50Ω Ω TERMINATION INTERFACE (3.3V) The IN /nIN with built-in 50Ω terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS IN/nIN input with built-in 50Ω terminations driven 3.3V by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 3.3V 3.3V 3.3V Zo = 50 Ohm Zo = 50 Ohm IN IN Zo = 50 Ohm VT nIN Receiver With Built-In 50 Ohm LVDS 3.3V Receiver With Built-In 50 Ohm LVPECL R1 50 FIGURE 2A. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN LVDS DRIVER BUILT-IN 50Ω FIGURE 2B. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN LVPECL DRIVER BUILT-IN 50Ω 3.3V 3.3V 3.3V Zo = 50 Ohm Zo = 50 Ohm IN IN Zo = 50 Ohm VT Zo = 50 Ohm nIN VT nIN CML- Open Collector Zo = 50 Ohm nIN Receiver With Built-In 50 Ohm CML- Built-in 50 Ohm Pull-Up Receiver With Built-In 50 Ohm FIGURE 2D. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY A CML DRIVER BUILT-IN 50Ω Ω PULLUP WITH BUILT-IN 50Ω FIGURE 2C. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY A CML DRIVER BUILT-IN 50Ω WITH OPEN COLLECTOR 3.3V VT 3.3V R1 25 Zo = 50 Ohm IN Zo = 50 Ohm VT nIN SSTL R2 25 Receiver With Built-In 50 Ohm FIGURE 2E. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN SSTL DRIVER BUILT-IN 50Ω 858012AK www.icst.com/products/hiperclocks.html 7 REV. A NOVEMBER 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. 2.5V DIFFERENTIAL INPUT WITH ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER Ω TERMINATION UNUSED INPUT HANDLING BUILT-IN 50Ω To prevent oscillation and to reduce noise, it is recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in Figure 3. 2.5V 2.5V R1 680 IN VT nIN Receiver with Built-In 50 Ohm R2 680 FIGURE 3. UNUSED INPUT HANDLING 3.3V DIFFERENTIAL INPUT WITH Ω TERMINATION UNUSED INPUT HANDLING BUILT-IN 50Ω To prevent oscillation and to reduce noise, it is recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in Figure 4. 3.3V 3.3V R1 1K IN VT nIN Receiver with Built-In 50 Ohm R2 1K FIGURE 4. UNUSED INPUT HANDLING 858012AK www.icst.com/products/hiperclocks.html 8 REV. A NOVEMBER 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. TERMINATION FOR 3.3V LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 5A. LVPECL OUTPUT TERMINATION 858012AK FIN 50Ω 84Ω FIGURE 5B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 9 REV. A NOVEMBER 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER TERMINATION FOR 2.5V LVPECL OUTPUT Figure 6A and Figure 6B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 6B can be eliminated and the termination is shown in Figure 6C. 2.5V VCC=2.5V 2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm R3 250 + Zo = 50 Ohm + Zo = 50 Ohm - Zo = 50 Ohm 2,5V LVPECL Driv er - R1 50 2,5V LVPECL Driv er R2 62.5 R2 50 R4 62.5 R3 18 FIGURE 6A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 6B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 6C. 2.5V LVPECL TERMINATION EXAMPLE 858012AK www.icst.com/products/hiperclocks.html 10 REV. A NOVEMBER 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS858012. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS858012 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 30mA = 108.9mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW Total Power_MAX (3.63V, with all outputs switching) = 108.9mW + 60.4mW = 169.3mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5°C/W per Table 4 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.169W * 51.5°C/W = 93.7°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 4. THERMAL RESISTANCE θJA FOR 16 LEAD VFQFN, FORCED CONVECTION θJA at 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 858012AK 51.5°C/W www.icst.com/products/hiperclocks.html 11 REV. A NOVEMBER 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER 3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 7. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CC_MAX • – 0.895V OH_MAX OL_MAX CC_MAX CC_MAX ) = 0.895V -V For logic low, VOUT = V (V =V -V OL_MAX =V CC_MAX – 1.695V ) = 1.695V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX ))/R ] * (V CC_MAX L -V OH_MAX )= [(2V - 0.895V)/50Ω] * 0.895V = 19.78mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.695V)/50Ω] * 1.695V = 10.34mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 858012AK www.icst.com/products/hiperclocks.html 12 REV. A NOVEMBER 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 5. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN θJA at 0 Air Flow (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 51.5°C/W TRANSISTOR COUNT The transistor count for ICS858012 is: 113 Pin compatible with SY58012U 858012AK www.icst.com/products/hiperclocks.html 13 REV. A NOVEMBER 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - K SUFFIX FOR ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER 16 LEAD VFQFN TABLE 6. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM MAXIMUM 16 N A 0.80 1.0 A1 0 0.05 0.25 Reference A3 b 0.18 0.30 e 0.50 BASIC ND 4 NE 4 3.0 D D2 0.25 1.25 3.0 E E2 0.25 1.25 L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 858012AK www.icst.com/products/hiperclocks.html 14 REV. A NOVEMBER 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS858012AK 012A 16 Lead VFQFN tube -40°C to 85°C ICS858012AKT 012A 16 Lead VFQFN 2500 tape & reel -40°C to 85°C ICS858012AKLF TBD 16 Lead "Lead-Free" VFQFN tube -40°C to 85°C ICS858012AKLFT TBD 16 Lead "Lead-Free" VFQFN 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark. HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 858012AK www.icst.com/products/hiperclocks.html 15 REV. A NOVEMBER 28, 2005