a Precision Dual Voltage Regulator Controllers ADM1051/ADM1051A GENERAL DESCRIPTION FEATURES Two Independent Controllers on One Chip 1.515 V and 1.818 V Outputs Shutdown Inputs to Control Each Channel Compatible with PC Motherboard TYPEDET Signal ⴞ2.5% Accuracy Over, Line, Load, and Temperature Low Quiescent Current Low Shutdown Current Works with External N-Channel MOSFETs for Low Cost “Hiccup Mode” Fault Protection No External Voltage or Current Setting Resistors 1.8 V/3.3 V ICH Sequenced Power-Up on ADM1051A Small, 8-Lead SOIC Package The ADM1051/ADM1051A are dual, precision, voltage regulator controllers intended for power rail generation and active bus termination on personal computer motherboards. They contain a precision 1.2 V bandgap reference and two channels consisting of control amplifiers driving external power devices. Each channel has a shutdown input to turn off amplifier output and Hiccup Mode protection circuitry for the external power device. The shutdown input on the 1.5 V channel can also be used with the TYPEDET signal on a PC motherboard to select the output voltage. The ADM1051/ADM1051A operate from a 12 V supply, which gives sufficient headroom for the amplifiers to drive external N-channel MOSFETs, operating as source-followers, as the external series pass devices. This has the advantage that Nchannel devices are cheaper than P-channel devices of similar performance, and the circuit is easier to stabilize than one using P-channel devices in a common-source configuration. APPLICATIONS Desktop Computers Servers Workstations FUNCTIONAL BLOCK DIAGRAM VIN 3.3V VCC ADM1051/ADM1051A CONTROL AMPLIFIER BANDGAP REFERENCE 100F FORCE 1 VCC SENSE 1 VOUT1 2ⴛ100F 50A SHUTDOWN CONTROL SHDN1 HICCUP COMPARATOR VIN 3.3V CONTROL AMPLIFIER 100F FORCE 2 NO CONNECTION ON ADM1051A VCC SENSE 2 VOUT2 2ⴛ100F 50A SHUTDOWN CONTROL SHDN2 HICCUP COMPARATOR VCC POWER-ON RESET CLK/DELAY GENERATOR CLOCK OSCILLATOR GND REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 = 12 V ⴞ 6%, V = 3.3 V, T = 0ⴗC to 70ⴗC, both ADM1051/ADM1051A–SPECIFICATIONS (Vchannels, unless otherwise noted. See Test Circuit.) CC Parameter Min OUTPUT VOLTAGE Channel 1 Channel 2 OUTPUT VOLTAGE ACCURACY Load Regulation Line Regulation 5 VSB Supply Voltage Required for Channel 2 Regulation Max 1.515 1.818 –2.5 –5 –5 +2.5 +5 +5 4.6 CONTROL AMPLIFIER Control Amplifier Open-Loop Gain Control Amplifier Slew Rate Closed-Loop Settling Time Turn-On Time Sense Input Impedance1 Force Output Voltage Swing, VF (High) Force Output Voltage Swing, VF (Low) 100 3 5 50 10 2 0.5 20 6 SHUTDOWN, SHDN1 Mode 1 (Shutdown) Mode 2 (1.5 V Out) Mode 3 (3.3 V Out) Mode 4 (1.5 V Out) 2 4.3 6.2 30 60 100 1.0 40 90 0.8 × VOUT 2.4 600 Test Conditions/Comments V V SHDN1 Floating % mV mV V VIN = 3.0 V to 3.6 V, IOUT = 10 mA to 1 A VIN = 3.3 V, IOUT = 10 mA to 1 A1 VIN = 3.0 V to 3.6 V, IOUT = 1 A1 Test Circuit as Figure 7.2 ILOAD = 500 mA 1.5 60 9 ms V µs ms ms V 0.8 3.9 5.3 12 V V V V 0.8 V V mA µA 2.0 4.0 1000 A Unit dB V/µs µs µs kΩ V V 5 HICCUP MODE Hiccup Mode Hold-Off Time Hiccup Mode Threshold Hiccup Comparator Glitch Immunity Hiccup Mode On-Time Hiccup Mode Off-Time Power-On Reset Threshold SHUTDOWN, SHDN2 Shutdown Input Low Voltage, VIL Shutdown Input High Voltage, VIH Supply Current, Normal Operation Supply Current, Shutdown Mode Typ IN IO = 10 mA to 2 A To 90% of Force High Output Level (CL = 470 pF) RL = 10 kΩ to GND RL = 10 kΩ to VCC See Figure 4 Shutdown Inputs Floating Both Channels Shut Down NOTES 1 Guaranteed by design. 2 5 VSB Supply is connected to, and measured at anode of Schottky Diode. Specifications subject to change without notice. –2– REV. 0 ADM1051/ADM1051A ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS (TA = 25°C unless otherwise noted) VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V SHDN1, SHDN2 to GND . . . . . . . . –0.3 V to (VCC + 0.3 V) SENSE 1, SENSE 2 to GND . . . . . . . . . . . –0.3 V to +5.5 V FORCE 1, FORCE 2 . . . . . . . Short-Circuit to GND or VCC Continuous Power Dissipation (TA = 70°C) . . . . . . . 650 mW 8-Lead SOIC (Derate 8.3 mW/°C Above 70°C) Operating Temperature Range Commercial (J Version) . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage Temperature Range . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C *This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Pin No. Mnemonic Function 1 FORCE 2 2 SENSE 2 3 SHDN2 4 5 GND SHDN1 6 SENSE 1 Output of Channel 2 control amplifier to gate of external N-channel MOSFET. Input from source of external MOSFET to inverting input of Channel 2 control amplifier, via output voltage-setting feedback resistor network. Digital Input. Active-low shutdown control with 50 µA internal pull-up. The output of Channel 2 control amplifier goes to ground when SHDN2 is taken low. Device Ground Pin. Digital Input. Active-low shutdown control with 50 µA internal pull-up. See text for more details of SHDN1 functionality. Input from source of external MOSFET to inverting input of Channel 1 control amplifier, via output voltage-setting feedback resistor network. Output of Channel 1 control amplifier to gate of external N-channel MOSFET. 12 V Supply. THERMAL CHARACTERISTICS 8-Lead Small Outline Package: θJA = 150°C/W ORDERING GUIDE Model Temperature Range Package Description Package Option 7 FORCE 1 ADM1051JR ADM1051AJR 0°C to 70°C 0°C to 70°C 8-Lead SOIC 8-Lead SOIC R-8 R-8 8 VCC PIN CONFIGURATION 12V VIN 3.3V 1F VCC PHD55N03LT FORCE 2 1 100F FORCE 1 SENSE 2 2 SHDN2 3 SENSE 1 2ⴛ100F VCC 7 FORCE 1 VIN 3.3V ADM1051/ ADM1051A SHDN2 8 6 SENSE 1 TOP VIEW GND 4 (Not to Scale) 5 SHDN1 VOUT1 SHDN1 LEAVE OPEN OR CONNECT TO LOGIC SIGNALS IF SHUTDOWN REQUIRED ADM1051/ ADM1051A MTD3055VL FORCE 2 SENSE 2 100F VOUT2 2ⴛ100F Figure 1. Test Circuit CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADM1051/ADM1051A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE ADM1051/ADM1051A –Typical Performance Characteristics Tek STOP : Single Seq 50.0MS/S 1.55 OUTPUT – V 1.54 1.53 1.52 1.51 2 1 Ch 1 500mV Ch2 Ch4 500mV 500mV M 1.00s Ch1 1.50 3.46 V 0 1 CURRENT – A TPC 4. Load Regulation, Channel 1 TPC 1. Line Transient Response, Channel 1 and Channel 2 1.825 1.514 25ⴗC 1.512 1.820 1.510 OUTPUT – V VOUT – V 1.815 1.508 85ⴗC 1.506 1.810 1.805 1.504 1.800 1.502 1.500 3.0 3.1 3.2 3.3 VIN – V 3.4 3.5 1.795 3.6 1 CURRENT – A TPC 5. Load Regulation, Channel 2 TPC 2. Line Regulation, Channel 1 1.8205 10 IL = 10mA 1.8200 0 25ⴗC RIPPLE REJECTION – dB 1.8195 1.8190 VOUT – V 0 1.8185 1.8180 85ⴗC 1.8175 1.8170 –10 –20 –30 –40 CHANNEL 1 –50 1.8165 –60 1.8160 1.8155 3.0 3.1 3.2 3.3 VIN – V 3.4 3.5 –70 3.6 TPC 3. Line Regulation, Channel 2 CHANNEL 2 10 100 1k 10k 100k FREQUENCY – Hz 1M 10M TPC 6. VCC Supply Ripple Rejection –4– REV. 0 ADM1051/ADM1051A Tek 1.85 Single Seq 50.0ms/S 1.8V CHANNEL 1.80 1.75 OUTPUT – V 1.70 1.65 1.60 1.55 1.50 1.5V CHANNEL 1.45 1.40 25 0 Ch2 20.0mV 85 BW M 1.00s Ch2 –16.8 mV TEMPERATURE – ⴗC TPC 7. Regulator Output Voltage vs. Temperature TPC 10. Transient Response Channel 2, 10 mA to 2 A Output Load Step Tek STOP : Single Seq 50.0ms/S 20.0mV Tek BW M 1.00s Ch2 Ch2 20.0mV –13.6 mV TPC 8. Transient Response Channel 1, 10 mA to 2 A Output Load Step Tek Tek BW M 1.00s Ch2 14.8 mV 10.0kS/S Ch1 TPC 9. Transient Response Channel 1, 2 A to 10 mA Output Load Step REV. 0 BW M 1.00s Ch2 10.4 mV TPC 11. Transient Response Channel 2, 2 A to 10 mA Output Load Step Single Seq 50.0ms/S Ch2 20.0mV Single Seq 50.0ms/S 10.0 V 4 Acqs M 5.00ms Ch1 1.0 V TPC 12. Force Output in Hiccup Mode, Channel 1 –5– ADM1051/ADM1051A VCH2 V's 5VSB ILOADⴝ500m 1.855 1.805 1.805 1.755 1.755 70ⴗC 70ⴗC 1.705 CHANNEL 2O/P – V 1.705 CHANNEL 2O/P – V VCH2 V's 5VSB ILOADⴝ1 1.855 1.655 0ⴗC 1.605 25ⴗC 1.555 1.505 1.655 25ⴗC 1.505 1.455 1.455 1.405 1.405 1.355 1.355 1.305 0ⴗC 1.605 1.555 1.305 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 3.7 5.3 3.9 4.1 4.3 5VSB – V 4.5 4.7 4.9 5.1 5.3 5VSB – V TPC 13. ADM1051A Channel 2 Output Voltage vs. 5 VSB Voltage. Test Circuit as Figure 7, ILOAD = 500 mA TPC 14. ADM1051A Channel 2 Output Voltage vs. 5 VSB Voltage. Test Circuit as Figure 7, ILOAD = 1 A GENERAL DESCRIPTION CIRCUIT DESCRIPTION The ADM1051/ADM1051A are dual, precision, voltage regulator controllers intended for power rail generation and active bus termination in AGP and ICH applications on personal computer motherboards. They contain a precision 1.2 V bandgap reference and two almost identical channels consisting of control amplifiers driving external power devices. The main difference between the two channels is the regulated output voltage, defined by the resistor ratios on the voltage sense inputs of each channel. Channel 1 has an output of nominally 1.515 V, but can be switched to a 3.3 V output, while Channel 2 has a nominal output of 1.818 V. Channel 1 is also optimized for driving MOSFETs with lower on-resistance and higher gate capacitance, as explained later. CONTROL AMPLIFIERS The reference voltage is amplified and buffered by the control amplifiers and external MOSFETs, the output voltage of each channel being determined by the feedback resistor network between the sense input and the inverting input of the control amplifier. The two control amplifiers in the ADM1051/ADM1051A are almost identical, apart, from the ratios of the feedback resistor networks on the sense inputs. A power-on reset circuit disables the amplifier output until VCC has risen above the reset threshold (not Channel 2 of ADM1051A). Each amplifier output drives the gate of an N-channel power MOSFET, whose drain is connected to the unregulated supply input and whose source is the regulated output voltage, which is also fed back to the appropriate sense input of the ADM1051/ ADM1051A. The control amplifiers have high current-drive capability so they can quickly charge and discharge the gate capacitance of the external MOSFET, thus giving good transient response to changes in load or input voltage. In particular, Channel 1 is optimized to drive MOSFETs with very low on resistance and correspondingly higher gate capacitance such as the PHD55N03LT from Philips. This is to minimize voltage drop across the MOSFET when Channel 1 is used in 3.3 V mode, as explained later. Each channel has a shutdown input to turn off amplifier output and protection circuitry for the external power device. The shutdown input of Channel 1 has additional functionality as described later. The ADM1051A has some minor differences from the ADM1051 to support power-supply sequencing and voltage requirements of some I/O control hub chipsets, which dictate that the 1.818 V rail must never be more than 2 V below the 3.3 V rail. The ADM1051/ADM1051A operates from a 12 V VCC supply. The outputs are disabled until VCC climbs above the Power-On Reset threshold (6 V–9 V). POR does not apply to Channel 2 of the ADM1051A. This output will begin to rise as soon as there is sufficient gate drive to turn on the external MOSFET. SHUTDOWN INPUTS AND TYPEDET COMPATIBILITY Each channel has a separate shutdown input, which may be controlled by a logic signal, and allows the output of the regulator to be turned on or off. If the shutdown input is held high or not connected, the regulator operates normally. If the shutdown input is held low, the enable input of the control amplifier is turned off and the amplifier output goes low, turning off the regulator. The outputs from the ADM1051/ADM1051A are used to drive external N-channel MOSFETs, operating as source-followers. This has the advantage that N-channel devices are cheaper than P-channel devices of similar performance, and the circuit is easier to stabilize than one using P-channel devices in a commonsource configuration. The SHDN1 input on Channel 1 has additional functionality that can be controlled by the TYPEDET signal on PC motherboards. The external power devices are protected by a “Hiccup Mode” circuit that operates if the circuit goes out of regulation due to an output short-circuit. In this case the power device is pulsed on/off with a 1:40 duty-cycle to limit the power dissipation until the fault condition is removed. Again, to prevent Channel 2 falling more than 2 V below Channel 1, Hiccup Mode does not operate on Channel 2 of the ADM1051A. The AGP bus on a PC motherboard can have two different modes of operation, requiring different regulated voltages of 3.3 V or 1.5 V. These two modes are signaled by the TYPEDET signal on the PC motherboard, as follows: TYPEDET = 0 V – Regulated Voltage 1.5 V (4× AGP Graphics) TYPEDET Floating – Regulated Voltage 3.3 V (2× AGP Graphics) –6– REV. 0 ADM1051/ADM1051A For compatibility with the TYPEDET signal, the regulator output voltage of Channel 1 may be selected using the Shutdown pin. This is a multilevel, dual-function input that allows selection of the regulator output voltage as well as shutdown of the regulator. PC 5V SUPPLY 3k⍀ TYPEDET By setting SHDN1 to different voltages, the regulator can be put into four different operating modes. Table I. Shutdown Functionality for 1.5 V Channel SHDN1 Voltage Mode Function < 0.8 V 1 Force Output Low, Regulator Shutdown 1.5 V Output Force Output High, VOUT = 3.3 V 1.5 V Output 2 V–3.9 V 4.3 V–5.3 V >6.2 V or Floating 2 3 4 Figure 2. Using SHDN1 with TYPEDET Signal A shutdown function can be added by connecting an open-drain/ open-collector logic output to SHDN1, or by using a totem-pole logic output with a Schottky diode, as shown in Figure 3. PC 5V SUPPLY COMPLEMENTARY OR TOTEM-POLE OUTPUT EN If the SHDN1 pin is connected to a voltage less than 0.8 V, the FORCE output will go low and the regulator will be shut down. SCHOTTKY DIODE TYPEDET SHDN1 ADM1051/ ADM1051A SHDN1 ADM1051/ ADM1051A 3k⍀ PC 5V SUPPLY 3k⍀ EN 3k⍀ TYPEDET If the SHDN1 pin is connected to a voltage between 2 V and 3.9 V, the regulator will also operate normally and provide 1.5 V out. The latter two modes allow the regulator to be controlled by the TYPEDET signal simply by using potential divider, as shown in Figure 2. 3k⍀ OPEN-DRAIN OR OPEN-COLLECTOR OUTPUT If the SHDN1 pin is connected to a voltage greater than 6.2 V, or simply left open-circuit, the regulator will operate normally and provide 1.5 V out. This allows the regulator to operate normally with no external connection to SHDN1. If the SHDN1 pin is connected to a voltage between 4.3 V and 5.3 V, the FORCE output will be high and the external MOSFET will be turned hard on, making the output voltage equal to the 3.3 V input (less any small drop due to the on-resistance of the MOSFET). In this mode it is not actually regulating, but simply acting as a switch for the 3.3 V supply. The voltage drop across the Channel 1 MOSFET in Mode 3 can be minimized by using a MOSFET with very low on resistance, for which Channel 1 is optimized, such as the PHD55N03LT. SHDN1 3k⍀ Figure 3. TYPEDET Voltage Selection Combined with Shutdown Function When the logic output is high or turned off, the regulator mode will be controlled by TYPEDET. When the logic output is low, the regulator will be shut down. Table II. TYPEDET and Shutdown Truth Table TYPEDET EN Regulator Mode X 0 1 0 1 1 Shutdown 1.5 V 3.3 V X = Don’t care. Note that when Channel 1 of the ADM1051 is set to 3.3 V, Channel 2 should not be shut down while Channel 1 is active. POR THRESHOLD 4V – 7V VREF TURN-ON THRESHOLD 12V SUPPLY 3.3V SUPPLY TO EXTERNAL MOSFET DRAIN GATE DRIVE TO EXTERNAL MOSFET CHANNEL 1 OR CHANNEL 2 OUTPUT VOLTAGE CHANNEL 1 OR CHANNEL 2 OUTPUT CURRENT MOSFET GATE THRESHOLD NORMAL OUTPUT VOLTAGE OUTPUT < 0.8 ⴛ VREG DEVICE ENTERS HICCUP MODE FAULT CURRENT HICCUP MODE HOLD-OFF TIME 2 AMPS OFF ON 1:40 DUTY CYCLE Figure 4. Power-On Reset and Hiccup Mode REV. 0 –7– FAULT REMOVED ADM1051/ADM1051A HICCUP MODE FAULT PROTECTION APPLICATIONS INFORMATION Hiccup Mode Fault Protection is a simple method of protecting the external power device without the added cost of external sense resistors or a current sense pin on the ADM1051/ADM1051A. In the event of a short-circuit condition at the output, the output voltage will fall. When the output voltage of a channel falls 20% below the nominal voltage, this is sensed by the hiccup comparator and the channel will go into Hiccup Mode, where the enable signal to the control amplifier is pulsed on and off with a 1:40 duty cycle. As mentioned earlier, Hiccup Mode does not operate on Channel 2 of the ADM1051A. PCB LAYOUT For optimum voltage regulation, the loads should be placed as close as possible to the source of the output MOSFETs and feedback to the sense inputs should be taken from a point as close to the loads as possible. The PCB tracks from the loads back to the sense inputs should be separate from the output tracks and not carry any load current. Similarly, the ground connection to the ADM1051/ADM1051A should be made as close as possible to the ground of the loads, and the ground track from the loads to the ADM1051/ADM1051A should not carry load current. Good and bad layout practice is illustrated in Figure 5. To prevent the device inadvertently going into Hiccup Mode during power-up or during channel enabling, the Hiccup Mode is held off for approximately 60 ms on both channels. By this time the output voltage should have reached its correct value. In the case of power-up, the hold-off period starts when VCC reaches the power-on reset threshold of 6 V–9 V. In the case of channel enabling, the hold-off period starts when SHDN is taken high. Note that the hold-off timeout applies to both channels even if only one channel is disabled/enabled. GOOD 12V VCC FORCE 1 VIN 3.3V As the 3.3 V input to the drain of the MOSFET is not monitored, it should ideally rise at the same or a faster rate than VCC. At the very least it must be available in time for VOUT to reach its final value before the end of the power-on delay. If the output voltage is still less than 80% of the correct value after the power-on delay, the device will go into Hiccup Mode until the output voltage exceeds 80% of the correct value during a Hiccup Mode onperiod. Of course, if there is a fault condition at the output during power-up, the device will go into Hiccup Mode after the power-up delay and remain there until the fault condition is removed. SENSE 1 FORCE 2 SENSE 2 GND I1 I2 VOUT1 VOUT2 LOAD 1 LOAD 2 BAD 12V VCC FORCE 1 VIN 3.3V The effect of power-on delay is illustrated in Figure 4. This shows an ADM1051/ADM1051A being powered up with a fault condition. The output current rises to a very high value during the power-on delay, then the device goes into Hiccup Mode and the output is pulsed on and off at 1:40 duty cycle. When the fault condition is removed, the output voltage recovers to its normal value at the end of the Hiccup Mode off period. VOUT1 SENSE 1 FORCE 2 VOUT2 SENSE 2 I1 GND LOAD 1 I2 VOLTAGE DROP BETWEEN OUTPUT AND LOAD LOAD 2 I1 ⴙ I2 VOLTAGE DROP IN GROUND LEAD The load current at which the ADM1051/ADM1051A will go into Hiccup Mode is determined by three factors: Figure 5. Good and Bad Layout Practice • the input voltage to the drain of the MOSFET, VIN • the output voltage VOUT (–20%) • the on-resistance of the MOSFET, RON IHICCUP = (VIN – (0.8 × VOUT))/RON It should be emphasized that the Hiccup Mode is not intended as a precise current limit but as a simple method of protecting the external MOSFET against catastrophic fault conditions such as output short-circuits. –8– REV. 0 ADM1051/ADM1051A SUPPLY DECOUPLING POWERING SUPPLY SEQUENCING The supply to the drain of an external MOSFET should be decoupled as close as possible to the drain pin of the device, with at least 100 µF to ground. The output from the source of the MOSFET should be decoupled as close as possible to the source pin of the device. Decoupling capacitors should be chosen to have a low Equivalent Series Resistance (ESR), typically 50 mΩ or lower. With the MOSFETs specified, and two 100 µF capacitors in parallel, the circuit will be stable for load currents up to 2 A. The VCC pin of the ADM1051/ADM1051A should be decoupled with at least 1 µF to ground, connected as close as possible to the VCC and GND pins. Some I/O control hub chipsets have power-supply sequencing requirements, which dictate that the 1.818 V supply must never be more than 2 V below the 3.3 V supply. This requirement can be met using the ADM1051A, as shown in Figure 7. In this circuit, VCC is supplied from the 5 V standby rail (5 VSB) and from the 12 V rail via Schottky diodes. 5 VSB is always present when ac power is supplied to the system, so the ADM1051A is powered up, but VCC is below the POR threshold. When the main power supplies are turned on, the Channel 2 output will rise at the same rate as the 3.3 V rail until it regulates at 1.818 V. The 12 V supply will take over from 5 VSB when it exceeds the 5 VSB rail, and Channel 1 will then be subject to the POR delay. This ensures that Channel 2 can never be more than 2 V below Channel 1. In practice, the amount of decoupling required will depend on the application. PC motherboards are notoriously noisy environments, and it may be necessary to employ distributed decoupling to achieve acceptable noise levels on the supply rails. BAT45C 12V 12V VIN 3.3V 1F VCC 5VSB BAT45C VCC VIN 3.3V 0.1 F PHD55N03LT 100F FORCE 1 PHD55N03LT 100F FORCE 1 SENSE 1 SENSE 1 VOUT1 SHDN1 LEAVE OPEN OR CONNECT TO LOGIC SIGNALS IF SHUTDOWN REQUIRED SHDN1 2ⴛ100F SHDN2 10k⍀ MTD3055VL FORCE 2 VIN 3.3V ADM1051A 3.3V VIN 3.3V ADM1051 SHDN2 MTD3055VL FORCE 2 100F SENSE 2 SENSE 2 VOUT1 2ⴛ100F VOUT2 100F VOUT2 2ⴛ100F 2ⴛ100F Figure 7. Typical ADM1051A Application Circuit Figure 6. Typical ADM1051 Application Circuit CHOICE OF MOSFET As previously discussed, the load current at which an output goes into Hiccup Mode depends on the on resistance of the external MOSFET. If the on resistance is too low, this current may be very high; if the on resistance is high, the trip current may be lower than the maximum required load current. For the primary application of AGP and ICH power supplies and bus termination on personal computer motherboards, devices with very low on resistance, such as the PHD55N03LT from Philips, or the SUB60N06-18 from Siliconix, are suitable. For Channel 2, suitable devices are the MTD3055VL from Motorola and the PHB11N06LT from Philips. THERMAL CONSIDERATIONS Heat generated in the external MOSFET must be dissipated and the junction temperature of the device kept within acceptable limits. The power dissipated in the device is, of course, the drain-source voltage multiplied by the load current. The required thermal resistance to ambient is given by JA = TJ(MAX) – TAMB(MAX)/(VDS(MAX) × IOUT(MAX)) Surface-mount MOSFETs, such as those specified, must rely on heat conduction through the device leads and the PCB. One square inch of copper (645 sq. mm) gives a thermal resistance of around 60°C/W for an SOT-223 surface-mount package and 80°C/W for an SO-8 surface-mount package. For high power dissipation that can be accommodated by a surface-mount package, D2PAK or TO-220 devices are recommended. These should be mounted on a heat sink with a thermal resistance low enough to maintain the required maximum junction temperature. REV. 0 –9– ADM1051/ADM1051A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C00400–2.5–7/00 (rev. 0) 8-Lead Small Outline Package (Narrow Body) (R-8) 0.1968 (5.00) 0.1890 (4.80) 0.1574 (4.00) 0.1497 (3.80) 8 5 1 4 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.0196 (0.50) ⴛ 45ⴗ 0.0099 (0.25) 0.0500 (1.27) BSC SEATING PLANE 0.102 (2.59) 0.094 (2.39) 8ⴗ 0.0098 (0.25) 0ⴗ 0.0500 (1.27) 0.0160 (0.41) 0.0075 (0.19) 0.0192 (0.49) 0.0138 (0.35) PRINTED IN U.S.A. 0.0098 (0.25) 0.0040 (0.10) –10– REV. 0