ISSI IS61VPS102436A 1mb x 36, 2mb x 18 36mb synchronous pipelined, single cycle deselect static ram Datasheet

IS61VPS102436A IS61LPS102436A
IS61VPS204818A IS61LPS204818A
1Mb x 36, 2Mb x 18
36Mb SYNCHRONOUS PIPELINED,
SINGLE CYCLE DESELECT STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• Power Supply
LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5%
• JEDEC 100-Pin TQFP and 165-ball PBGA
packages
• Lead-free available
MARCH 2008
DESCRIPTION
The ISSI IS61LPS/VPS102436A and IS61LPS/VPS
204818A are high-speed, low-power synchronous static
RAMs designed to provide burstable, high-performance memory
for communication and networking applications. The
IS61LPS/VPS102436A is organized as 1,048,476 words
by 36 bits. The IS61LPS/VPS204818A is organized as
2M-word by 18 bits. Fabricated with ISSI's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positiveedge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
200
3.1
5
200
166
3.5
6
166
Units
ns
ns
MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
1
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
BLOCK DIAGRAM
MODE
Q0
CLK
CLK
A0
A0'
BINARY
COUNTER
CE
ADV
ADSC
ADSP
Q1
A1'
1Mx36;
2Mx18
MEMORY ARRAY
A1
CLR
20/21
18/19
D
A
20/21
Q
ADDRESS
REGISTER
CE
CLK
36,
or 18
GW
BWE
BW(a-h)
x18: a,b
x36: a-d
D
36,
or 18
Q
DQ(a-h)
BYTE WRITE
REGISTERS
CLK
CE
36,
or 18
2/4/8
D
CE2
CE2
Q
ENABLE
REGISTER
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
DQa - DQd
OE
CE
CLK
D
ZZ
POWER
DOWN
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
165-PIN BGA
165-Ball, 13x15 mm BGA
1mm Ball Pitch, 11x15 Ball Array
BOTTOM VIEW
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
3
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
165 PBGA PACKAGE PIN CONFIGURATION
1M X 36 (TOP VIEW)
1
2
3
A
NC
A
CE
B
NC
A
CE2
C
DQPc
NC
VDDQ
D
DQc
DQc
E
DQc
DQc
F
DQc
G
H
4
5
6
7
8
9
10
11
BWc
BWb
CE2
BWE
ADSC
ADV
A
NC
BWd
BWa
CLK
GW
OE
ADSP
A
NC
Vss
Vss
Vss
Vss
Vss
VDDQ
NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQb
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQb
DQb
DQc
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQb
DQb
DQc
DQc
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQb
DQb
NC
NC
NC
VDD
Vss
Vss
Vss
VDD
NC
NC
ZZ
J
DQd
DQd
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
DQa
K
DQd
DQd
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
DQa
L
DQd
DQd
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
DQa
M
DQd
DQd
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
DQa
N
DQPd
NC
VDDQ
Vss
NC
A
NC
Vss
VDDQ
NC
DQPa
P
NC
NC
A
A
NC
A1*
NC
A
A
A
A
R
MODE
A
A
A
NC
A0*
NC
A
A
A
A
DQPb
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
Symbol
Pin Name
BWE
Byte Write Enable
A0, A1
Synchronous Burst Address Inputs
ADV
OE
Output Enable
ZZ
Power Sleep Mode
ADSP
Synchronous Burst Address
Advance
Address Status Processor
MODE
Burst Sequence Selection
ADSC
Address Status Controller
GW
Global Write Enable
CLK
Synchronous Clock
CE, CE2, CE2
Synchronous Chip Select
NC
DQx
DQPx
V DD
VDDQ
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
Vss
Ground
BWx (x=a,b,c,d) Synchronous Byte Write
Controls
4
Isolated Output Power Supply
3.3V/2.5V
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
165 PBGA PACKAGE PIN CONFIGURATION
2M X 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE
BWb
NC
CE2
BWE
ADSC
ADV
A
A
B
NC
A
CE2
NC
BWa
CLK
GW
OE
ADSP
A
NC
C
NC
NC
VDDQ
Vss
Vss
Vss
Vss
Vss
VDDQ
NC
DQPa
D
NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
E
NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
F
NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
G
NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
H
NC
NC
NC
VDD
Vss
Vss
Vss
VDD
NC
NC
ZZ
J
DQb
NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
NC
K
DQb
NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
NC
L
DQb
NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
NC
M
DQb
NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
NC
N
DQPb
NC
VDDQ
Vss
NC
A
NC
Vss
VDDQ
NC
NC
P
NC
NC
A
A
NC
A1*
NC
A
A
A
A
R
MODE
A
A
A
NC
A0*
NC
A
A
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
Symbol
BWE
Byte Write Enable
A0, A1
Synchronous Burst Address Inputs
ADV
OE
Output Enable
ZZ
Power Sleep Mode
ADSP
Synchronous Burst Address
Advance
Address Status Processor
MODE
Burst Sequence Selection
ADSC
Address Status Controller
GW
Global Write Enable
CLK
Synchronous Clock
CE, CE2, CE2
Synchronous Chip Select
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
BWx (x=a,b)
Synchronous Byte Write
Controls
NC
DQx
DQPx
VDD
VDDQ
Vss
Ground
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
Pin Name
Isolated Output Power Supply
3.3V/2.5V
5
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
PIN CONFIGURATION
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-PIN TQFP
DQPc
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
MODE
A
A
A
A
A1
A0
NC
A
VSS
VDD
A
A
A
A
A
A
A
A
A
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1M x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
DQa-DQd
Synchronous Data Input/Output
DQPa-DQPd
Parity Data Input/Output
GW
Synchronous Global Write Enable
A
Synchronous Address Inputs
ADSC
Synchronous Controller Address
Status
MODE
Burst Sequence Mode Selection
OE
Output Enable
ADSP
Synchronous Processor Address
Status
VDD
3.3V/2.5V Power Supply
ADV
VDDQ
Synchronous Burst Address Advance
Isolated Output Buffer Supply:
3.3V/2.5V
BWa-BWd
Synchronous Byte Write Enable
Vss
Ground
BWE
Synchronous Byte Write Enable
ZZ
Snooze Enable
CE, CE2, CE2 Synchronous Chip Enable
CLK
6
Synchronous Clock
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
PIN CONFIGURATION
A
A
CE
CE2
NC
NC
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-PIN TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
MODE
A
A
A
A
A1
A0
NC
A
VSS
VDD
A
A
A
A
A
A
A
A
A
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
2M x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A
Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
Synchronous Burst Address Advance
BWa-BWb
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
CE, CE2, CE2 Synchronous Chip Enable
CLK
Synchronous Clock
DQa-DQb
Synchronous Data Input/Output
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
DQPa-DQPb
Parity Data I/O; DQPa is parity for
DQa1-8; DQPb is parity for DQb1-8
GW
Synchronous Global Write Enable
MODE
Burst Sequence Mode Selection
OE
Output Enable
VDD
3.3V/2.5V Power Supply
VDDQ
Isolated Output Buffer Supply:
3.3V/2.5V
Vss
Ground
ZZ
Snooze Enable
7
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
TRUTH TABLE(1-8) (3CE option)
ADDRESS
CE
CE2
CE2
ZZ
OE
CLK
DQ
Deselect Cycle, Power-Down
None
H
X
X
L
X
L
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
X
L
L
L
X
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
H
X
L
L
X
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
X
L
L
H
L
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
H
X
L
H
L
X
X
X
L-H
High-Z
Snooze Mode, Power-Down
None
X
X
X
H
X
X
X
X
X
X
High-Z
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
H
L-H
High-Z
Write Cycle, Begin Burst
External
L
L
H
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
L
L-H
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
High-Z
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
High-Z
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
OPERATION
ADSP ADSC
ADV WRITE
Q
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all
BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa-DQPd are available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the
input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
8
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
TRUTH TABLE(1-8) (1CE option)
ADDRESS CE
NEXT CYCLE
Deselected
ADSP
ADSC
ADV
WRITE
OE
DQ
None
H
X
L
X
X
X
High-Z
Read, Begin Burst
External
L
L
X
X
X
L
Q
Read, Begin Burst
External
L
L
X
X
X
H
High-Z
Write, Begin Burst
External
L
H
L
X
L
X
D
Read, Begin Burst
External
L
H
L
X
H
L
Q
Read, Begin Burst
External
L
H
L
X
H
H
High-Z
Read, Continue Burst
Next
X
H
H
L
H
L
Q
Read, Continue Burst
Next
X
H
H
L
H
H
High-Z
Read, Continue Burst
Next
H
X
H
L
H
L
Q
Read, Continue Burst
Next
H
X
H
L
H
H
High-Z
Write, Continue Burst
Next
X
H
H
L
L
X
D
Write, Continue Burst
Next
H
X
H
L
L
X
D
Read, Suspend Burst
Current
X
H
H
H
H
L
Q
Read, Suspend Burst
Current
X
H
H
H
H
H
High-Z
Read, Suspend Burst
Current
H
X
H
H
H
L
Q
Read, Suspend Burst
Current
H
X
H
H
H
H
High-Z
Write, Suspend Burst
Current
X
H
H
H
L
X
D
Write, Suspend Burst
Current
H
X
H
H
L
X
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all
BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa-DQPd are available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the
input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
GW
BWE
BWa
BWb
BWc
BWd
H
H
H
H
L
H
L
L
L
X
X
H
L
L
X
X
H
H
L
X
X
H
H
L
X
X
H
H
L
X
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
9
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
TSTG
PD
IOUT
VIN, VOUT
VIN
Parameter
Storage Temperature
Power Dissipation
Output Current (per I/O)
Voltage Relative to Vss for I/O Pins
Voltage Relative to Vss for
for Address and Control Inputs
VDD
Voltage on VDD Supply Relative to Vss
Value
Unit
–55 to +150
°C
1.6
W
100
mA
–0.5 to VDDQ + 0.5
V
–0.5 to VDD + 0.5
V
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or
electric fields; however, precautions may be taken to avoid application of any voltage higher than
maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
10
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
OPERATING RANGE (IS61LPSXXXXX)
Range
Commercial
Ambient Temperature
0°C to +70°C
VDD
3.3V + 5%
VDDQ
3.3V / 2.5V + 5%
–40°C to +85°C
3.3V + 5%
3.3V / 2.5V + 5%
Ambient Temperature
0°C to +70°C
VDD
2.5V + 5%
VDDQ
2.5V + 5%
–40°C to +85°C
2.5V + 5%
2.5V + 5%
Industrial
OPERATING RANGE (IS61VPSXXXXX)
Range
Commercial
Industrial
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
3.3V
Symbol
Parameter
Test Conditions
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
2.5V
Min.
Max.
Min.
Max.
IOH = –4.0 mA (3.3V)
IOH = –1.0 mA (2.5V)
2.4
—
2.0
—
V
IOL = 8.0 mA (3.3V)
IOL = 1.0 mA (2.5V)
—
0.4
—
0.4
V
2.0
VDD + 0.3
1.7
VDD + 0.3
V
-0.3
0.8
-0.3
0.7
V
-5
5
-5
5
µA
-5
5
-5
5
µA
Vss ≤ VIN ≤ VDD
(1)
ILI
Input Leakage Current
ILO
Output Leakage Current Vss ≤ VOUT ≤ VDDQ,
OE = VIH
Unit
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Temp. range
-200
MAX
x18
x36
-166
MAX
x18
x36
Symbol Parameter
Test Conditions
ICC
AC Operating
Supply Current
Device Selected,
OE = VIH, ZZ ≤ VIL,
All Inputs ≤ 0.2V or ≥ VDD – 0.2V,
Cycle Time ≥ tKC min.
Com.
Ind.
typ.(2)
450
475
450
475
390
400
450
ISB
Standby Current
TTL Input
Device Deselected,
VDD = Max.,
All Inputs ≤ VIL or ≥ VIH,
ZZ ≤ VIL, f = Max.
Com.
Ind.
150
150
150
150
120
120
120
120
mA
ISBI
Standby Current
CMOS Input
Device Deselected,
VDD = Max.,
VIN ≤ VSS + 0.2V or ≥VDD – 0.2V
f=0
Com.
Ind.
typ.(2)
110
140
110
140
110
140
110
140
mA
75
Unit
400 mA
450
340
75
Note:
1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits ±100µA maximum leakage current when tied to ≤
VSS + 0.2V or ≥ VDD – 0.2V.
2. Typical values are measured at Vcc = 3.3V, TA = 25oC and not 100% tested.
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
11
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
317 Ω
3.3V
ZO = 50Ω
Output
50Ω
1.5V
Figure 1
12
OUTPUT
5 pF
Including
jig and
scope
351 Ω
Figure 2
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
2.5V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 2.5V
1.5 ns
1.25V
See Figures 3 and 4
2.5 I/O OUTPUT LOAD EQUIVALENT
317 Ω
2.5V
ZO = 50Ω
Output
50Ω
1.25V
Figure 3
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
OUTPUT
5 pF
Including
jig and
scope
351 Ω
Figure 4
13
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-200
Symbol
Parameter
Min.
Max.
-166
Min.
Max.
Unit
fMAX
Clock Frequency
—
200
—
166
MHz
tKC
Cycle Time
5
—
6
—
ns
tKH
Clock High Time
2
—
2.4
—
ns
tKL
Clock Low Time
2
—
2.4
—
ns
Clock Access Time
—
3.1
—
3.5
ns
tKQ
(2)
tKQX
Clock High to Output Invalid
1.5
—
1.5
—
ns
(2,3)
tKQLZ
Clock High to Output Low-Z
1
—
1
—
ns
tKQHZ(2,3)
Clock High to Output High-Z
—
3.0
—
3.4
ns
tOEQ
Output Enable to Output Valid
—
3.1
—
3.5
ns
(2)
Output Disable to Output Invalid
0
—
0
—
ns
(2,3)
tOELZ
Output Enable to Output Low-Z
0
—
0
—
ns
tOEHZ(2,3)
Output Disable to Output High-Z
—
3.0
—
3.4
ns
tAS
Address Setup Time
1.4
—
1.5
—
ns
tSS
Address Status Setup Time
1.4
—
1.5
—
ns
tWS
Read/Write Setup Time
1.4
—
1.5
—
ns
tCES
Chip Enable Setup Time
1.4
—
1.5
—
ns
tAVS
Address Advance Setup Time
1.4
—
1.5
—
ns
tDS
Data Setup Time
1.4
—
1.5
—
ns
tAH
Address Hold Time
0.4
—
0.5
—
ns
tSH
Address Status Hold Time
0.4
—
0.3
—
ns
tWH
Write Hold Time
0.4
—
0.5
—
ns
tCEH
Chip Enable Hold Time
0.4
—
0.5
—
ns
tAVH
Address Advance Hold Time
0.4
—
0.5
—
ns
tDH
Data Hold Time
0.4
—
0.5
—
ns
tPDS
ZZ High to Power Down
—
2
—
2
cyc
tPUS
ZZ Low to Power Down
—
2
—
2
cyc
tOEQX
Note:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
14
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
READ/WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
tSS
tSH
ADSC initiate read
ADSC
tAVH
tAVS
Suspend Burst
ADV
tAS
Address
tAH
RD1
RD3
RD2
tWS
tWH
tWS
tWH
GW
BWE
BWx
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE Masks ADSP
CE
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
CE2
CE2
tOEHZ
tOEQ
OE
DATAOUT
tKQX
tOEQX
tOELZ
High-Z
1a
2a
2b
2c
tKQLZ
2d
tKQHZ
tKQ
DATAIN
High-Z
Pipelined Read
Single Read
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
Burst Read
Unselected
15
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
ADSC initiate Write
ADSC
ADV must be inactive for ADSP Write tAVS
tAVH
ADV
tAS
Address
tAH
WR1
WR3
WR2
tWS
tWH
tWS
tWH
tWS
tWH
GW
BWE
BWx
WR1
tCES
tCEH
tCES
tCEH
tCES
tCEH
tWS
tWH
WR2
WR3
CE Masks ADSP
CE
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
CE2
CE2
OE
DATAOUT
High-Z
tDS
DATAIN
High-Z
Single Write
16
tDH
1a
BW4-BW1 only are applied to first cycle of WR2
2a
2b
2c
2d
Burst Write
3a
Write
Unselected
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Temperature
Conditions
Min.
Max.
Unit
ISB2
Current during SNOOZE MODE
Com.
Ind.
ZZ ≥ Vih
—
—
60
90
mA
tPDS
ZZ active to input ignored
—
2
cycle
tPUS
ZZ inactive to input sampled
2
—
cycle
tZZI
ZZ active to SNOOZE current
—
2
cycle
tRZZI
ZZ inactive to exit SNOOZE current
0
—
ns
SNOOZE MODE TIMING
CLK
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All Inputs
(except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
17
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O)
Commercial Range: 0°C to +70°C
Configuration
Frequency
Order Part Number
Package
166
IS61LPS102436A-166TQ
IS61LPS102436A-166TQL
IS61LPS102436A-166B3
100 TQFP
100 TQFP, Lead-free
165 PBGA
166
IS61LPS204818A-166TQ
IS61LPS204818A-166TQL
IS61LPS204818A-166B3
100 TQFP
100 TQFP, Lead-free
165 PBGA
Order Part Number
Package
166
IS61LPS102436A-166TQI
IS61LPS102436A-166TQLI
IS61LPS102436A-166B3I
IS61LPS102436A-166B3LI
100 TQFP
100 TQFP, Lead-free
165 PBGA
165 PBGA, Lead-free
166
IS61LPS204818A-166TQI
IS61LPS204818A-166B3I
100 TQFP
165 PBGA
1Mx36
2Mx18
Industrial Range: -40°C to +85°C
Configuration
Frequency
1Mx36
2Mx18
18
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
ORDERING INFORMATION (2.5V core/2.5V I/O)
Commercial Range: 0°C to +70°C
Configuration
Frequency
Order Part Number
Package
IS61VPS102436A-166TQ
IS61VPS102436A-166TQL
100 TQFP
100 TQFP, Lead-free
IS61VPS102436A-166B3
165 PBGA
IS61VPS204818A-166TQ
IS61VPS204818A-166TQL
100 TQFP
100 TQFP, Lead-free
IS61VPS204818A-166B3
165 PBGA
Order Part Number
Package
IS61VPS204818A-166TQI
IS61VPS204818A-166B3I
100 TQFP
165 PBGA
1Mx36
166
2Mx18
166
Industrial Range: -40°C to +85°C
Configuration
Frequency
2Mx18
166
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
19
PACKAGING INFORMATION
Ball Grid Array
Package Code: B (165-pin)
BOTTOM VIEW
TOP VIEW
A1 CORNER
1
2
3
4
A1 CORNER
φ b (165X)
5
6
7
8
9
10
11 10
11
9
8
7
6
5
4
3
2
1
A
A
B
B
C
C
D
D
E
E
e
F
F
G
G
D D1
H
H
J
J
K
K
L
L
M
M
N
N
P
P
R
R
e
E1
E
A2
A
A1
BGA - 13mm x 15mm
MILLIMETERS
Sym.
Min.
N0.
Leads
Nom. Max.
Notes:
1. Controlling dimensions are in millimeters.
INCHES
Min.
165
Nom. Max.
165
A
—
—
1.20
—
A1
0.25
0.33
0.40
0.010
—
0.047
0.013 0.016
A2
—
0.79
—
—
0.031
—
D
14.90
15.00
15.10
0.587
0.591
0.594
D1
13.90
14.00
14.10
0.547
0.551
0.555
E
12.90
13.00
13.10
0.508
0.512
0.516
E1
9.90
10.00
10.10
0.390
0.394
0.398
e
—
1.00
—
—
0.039
—
b
0.40
0.45
0.50
0.016
0.018
0.020
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
06/11/03
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package)
Package Code: TQ
D
D1
E
E1
N
L1
L
C
1
e
SEATING
PLANE
A2
A
b
A1
Millimeters
Min
Max
Thin Quad Flat Pack (TQ)
Inches
Millimeters
Min
Max
Min
Max
Symbol
Ref. Std.
No. Leads (N)
100
A
—
1.60
—
0.063
A1
0.05 0.15
0.002 0.006
A2
1.35 1.45
0.053 0.057
b
0.22 0.38
0.009 0.015
D
21.90 22.10
0.862 0.870
D1
19.90 20.10
0.783 0.791
E
15.90 16.10
0.626 0.634
E1
13.90 14.10
0.547 0.555
e
0.65 BSC
0.026 BSC
L
0.45 0.75
0.018 0.030
L1
1.00 REF.
0.039 REF.
o
o
C
0
7
0o
7o
128
—
1.60
0.05 0.15
1.35 1.45
0.17 0.27
21.80 22.20
19.90 20.10
15.80 16.20
13.90 14.10
0.50 BSC
0.45 0.75
1.00 REF.
0o
7o
Integrated Silicon Solution, Inc. — 1-800-379-4774
PK13197LQ Rev. D 05/08/03
Inches
Min
Max
—
0.063
0.002 0.006
0.053 0.057
0.007 0.011
0.858 0.874
0.783 0.791
0.622 0.638
0.547 0.555
0.020 BSC
0.018 0.030
0.039 REF.
0o
7o
Notes:
1. All dimensioning and
tolerancing conforms to
ANSI Y14.5M-1982.
2. Dimensions D1 and E1 do
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
3. Controlling dimension:
millimeters.