Samsung K6X4008C1F-BF55 512kx8 bit low power full cmos static ram Datasheet

CMOS SRAM
K6X4008C1F Family
Document Title
512Kx8 bit Low Power full CMOS Static RAM
Revision History
Revision No.
History
Draft Date
Remark
0.0
Initial draft
July 30, 2002
Preliminary
0.1
Revised
- Added Commercial Product.
November 30, 2002
Preliminary
1.0
Finalized
- Added Lead Free 32-SOP-525 Product
- Changed ICC from 10mA to 5mA
- Changed ICC1 from 8mA to 7mA
- Changed ICC2 from 40mA to 30mA
- Changed ISB from 3mA to 0.4mA
- Changed IDR(Commercial) from 15µA to 12µA
- Changed IDR(industrial) from 20µA to 12µA
- Changed IDR(Automotive) from 30µA to 25µA
September 16, 2003 Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
September 2003
CMOS SRAM
K6X4008C1F Family
512Kx8 bit Low Power full CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Process Technology: Full CMOS
• Organization: 512Kx8
• Power Supply Voltage: 4.5~5.5V
• Low Data Retention Voltage: 2V(Min)
• Three state output and TTL compatible
• Package Type: 32-DIP-600, 32-SOP-525,
32-TSOP2-400F/R
The K6X4008C1F families are fabricated by SAMSUNG′s
advanced full CMOS process technology. The families supports various operating temperature range and various
package types for user flexibility of system design. The families also support low data retention voltage for battery backup operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
K6X4008C1F-B
Commercial (0~70°C)
Vcc Range
Speed
4.5~5.5V
551)/70ns
PKG Type
Standby Operating
(ISB1, Max) (ICC2, Max)
32-DIP-600, 32-SOP-525,
32-TSOP2-400F/R
20µA
K6X4008C1F-F
Industrial (-40~85°C)
K6X4008C1F-Q
Automotive (-40~125°C)
30mA
30µA
32-SOP-525, 32-TSOP2-400F
1. The parameter is measured with 50pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A18
1
32
VCC
VCC
32
1
A18
A16
2
31
A15
A15
31
2
A16
A14
3
30
A17
A17
30
3
A14
A12
4
29
WE
WE
29
4
A12
A7
5
28
A13
A13
28
5
A7
A6
6
27
A8
A8
27
6
A6
A5
7
26
A9
A9
26
7
A5
25
A11
A11
25
8
A4
24
OE
OE
24
9
A3
23
10
A2
32-DIP
32-SOP
32-TSOP2
(Forward)
32-TSOP2
(Reverse)
Clk gen.
Row
Addresses
A4
8
A3
9
A2
10
23
A10
A10
A1
11
22
CS
CS
22
11
A1
A0
12
21
I/O8
I/O8
21
12
A0
I/O1
13
20
I/O7
I/O7
20
13
I/O1
I/O1
I/O2
14
19
I/O6
I/O6
19
14
I/O2
I/O8
I/O3
15
18
I/O5
I/O5
18
15
I/O3
VSS
16
17
I/O4
I/O4
17
16
VSS
Pin Name
Write Enable Input
CS
Chip Select Input
OE
Output Enable Input
A0~A18
I/O1~I/O8
Data
cont
Memory array
I/O Circuit
Column select
Data
cont
Function
WE
Row
select
Precharge circuit.
Column Addresses
CS
WE
Address Inputs
Control
logic
OE
Data Inputs/Outputs
Vcc
Power
Vss
Ground
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 1.0
September 2003
CMOS SRAM
K6X4008C1F Family
PRODUCT LIST
Commercial Products(0~70°C)
Part Name
Industrial Products(-40~85°C)
Function
K6X4008C1F-DB55
K6X4008C1F-DB70
K6X4008C1F-GB55
K6X4008C1F-GB70
K6X4008C1F-BB551)
K6X4008C1F-BB701)
K6X4008C1F-VB55
K6X4008C1F-VB70
K6X4008C1F-MB55
K6X4008C1F-MB70
32-DIP, 55ns, LL
32-DIP, 70ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-TSOP2-F, 55ns, LL
32-TSOP2-F, 70ns, LL
32-TSOP2-R, 55ns, LL
32-TSOP2-R, 70ns, LL
Part Name
Automotive Products(-40~125°C)
Function
K6X4008C1F-DF55
K6X4008C1F-DF70
K6X4008C1F-GF55
K6X4008C1F-GF70
K6X4008C1F-BF551)
K6X4008C1F-BF701)
K6X4008C1F-VF55
K6X4008C1F-VF70
K6X4008C1F-MF55
K6X4008C1F-MF70
Part Name
32-DIP, 55ns, LL
32-DIP, 70ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-TSOP2-F, 55ns, LL
32-TSOP2-F, 70ns, LL
32-TSOP2-R, 55ns, LL
32-TSOP2-R, 70ns, LL
K6X4008C1F-GQ55
K6X4008C1F-GQ70
K6X4008C1F-VQ55
K6X4008C1F-VQ70
Function
32-SOP, 55ns, L
32-SOP, 70ns, L
32-TSOP2-F, 55ns, L
32-TSOP2-F, 70ns, L
1. Lead Free Product
FUNCTIONAL DESCRIPTION
CS
OE
WE
I/O Pin
Mode
Power
H
X1)
X1)
High-Z
Deselected
Standby
L
H
H
High-Z
Output disbaled
Active
L
L
H
Dout
Read
Active
L
X1)
L
Din
Write
Active
1. X means don′t care.( Must be in low or high state.)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
Ratings
Unit
Remark
VIN,VOUT
-0.5 to VCC+0.5V(max. 7.0V)
V
-
Voltage on Vcc supply relative to Vss
VCC
-0.3 to 7.0
V
-
Power Dissipation
PD
1.0
W
-
TSTG
-65 to 150
°C
Voltage on any pin relative to Vss
Storage temperature
0 to 70
Operating Temperature
TA
-40 to 85
-40 to 125
K6X4008C1F-B
°C
K6X4008C1F-F
K6X4008C1F-Q
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
September 2003
CMOS SRAM
K6X4008C1F Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input high voltage
VIH
2.2
-
Vcc+0.52)
V
Input low voltage
VIL
-
0.8
V
-0.5
3)
Note:
1.Commercial Product: TA=0 to 70°C, otherwise specified
Industrial Product: TA=-40 to 85°C, otherwise specified
Automotive Product: TA=-40 to 125°C, otherwise specified
2. Overshoot: VCC+3.0V in case of pulse width ≤ 30ns
3. Undershoot: -3.0V in case of pulse width ≤ 30ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Output capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Symbol
ILI
Min
Typ
Max
Unit
VIN=Vss to Vcc
Test Conditions
-1
-
1
µA
Output leakage current
ILO
CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc
-1
-
1
µA
Operating power supply current
ICC
IIO=0mA, CS=VIL, VIN=VIL or VIH, Read
-
-
5
mA
ICC1
Cycle time=1µs, 100% duty, IIO=0mA
CS≤0.2V, VIN≥0.2V or VIN≥Vcc-0.2V
-
-
7
mA
Average operating current
ICC2
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL
-
-
30
mA
Output low voltage
VOL
IOL=2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH=-1.0mA
2.4
-
-
V
Standby Current(TTL)
ISB
CS=VIH, Other inputs = VIL or VIH
-
-
0.4
mA
K6X4008C1F-B
-
-
Standby Current(CMOS)
ISB1
CS≥Vcc-0.2V, Other inputs=0~Vcc
20
µA
K6X4008C1F-F
-
-
K6X4008C1F-Q
-
-
30
µA
4
Revision 1.0
September 2003
CMOS SRAM
K6X4008C1F Family
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL=100pF+1TTL
CL=50pF+1TTL
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS
(Vcc=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40 to 125°C)
Speed Bins
Parameter List
Symbol
Read cycle time
Read
Write
55ns
Units
70ns
Min
Max
Min
Max
tRC
55
-
70
-
ns
Address access time
tAA
-
55
-
70
ns
Chip select to output
tCO
-
55
-
70
ns
Output enable to valid output
tOE
-
25
-
35
ns
Chip select to low-Z output
tLZ
10
-
10
-
ns
Output enable to low-Z output
tOLZ
5
-
5
-
ns
Chip disable to high-Z output
tHZ
0
20
0
25
ns
Output disable to high-Z output
tOHZ
0
20
0
25
ns
Output hold from address change
tOH
10
-
10
-
ns
Write cycle time
tWC
55
-
70
-
ns
Chip select to end of write
tCW
45
-
60
-
ns
Address set-up time
tAS
0
-
0
-
ns
Address valid to end of write
tAW
45
-
60
-
ns
Write pulse width
tWP
40
-
50
-
ns
Write recovery time
tWR
0
-
0
-
ns
Write to output high-Z
tWHZ
0
20
0
25
ns
Data to write time overlap
tDW
25
-
30
-
ns
Data hold from write time
tDH
0
-
0
-
ns
End write to output low-Z
tOW
5
-
5
-
ns
Min
Typ
Max
Unit
2.0
-
5.5
V
-
-
12
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Vcc for data retention
VDR
CS≥Vcc-0.2V
Data retention current
IDR
Vcc=3.0V, CS≥Vcc-0.2V
K6X4008C1F-B
K6X4008C1F-F
12
K6X4008C1F-Q
Data retention set-up time
tSDR
Recovery time
tRDR
See data retention waveform
5
µA
25
0
-
-
5
-
-
ms
Revision 1.0
September 2003
CMOS SRAM
K6X4008C1F Family
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS
tHZ
tOE
OE
Data out
High-Z
tOHZ
tOLZ
tLZ
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 1.0
September 2003
CMOS SRAM
K6X4008C1F Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS
tAW
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
Data out
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS
Controlled)
tWC
Address
tCW(2)
tAS(3)
tWR(4)
CS
tAW
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write
to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
VCC
tSDR
Data Retention Mode
tRDR
4.5V
2.2V
VDR
CS≥VCC - 0.2V
CS
GND
7
Revision 1.0
September 2003
CMOS SRAM
K6X4008C1F Family
PACKAGE DIMENSIONS
Units : millimeter(Inch)
32 PIN DUAL INLINE PACKAGE (600mil)
+0.10
-0.05
0.010+0.004
-0.002
0.25
#17
#1
#16
15.24
0.600
#32
13.60±0.20
0.535±0.008
0~15°
3.81±0.20
0.150±0.008
42.31
1.666 MAX
5.08
0.200 MAX
41.91±0.20
1.650±0.008
3.30±0.30
0.130±0.012
0.46±0.10
0.018±0.004
1.52±0.10
0.060±0.004
( 1.91 )
0.075
0.38 MIN
0.015
2.54
0.100
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8°
#17
14.12±0.30
0.556±0.012
#1
11.43±0.20
0.450±0.008
#16
2.74±0.20
0.108±0.008
3.00
0.118 MAX
20.87MAX
0.822
20.47±0.20
0.806±0.008
0.20 +0.10
-0.05
0.008+0.004
-0.002
13.34
0.525
#32
0.80±0.20
0.031±0.008
0.10 MAX
0.004 MAX
( 0.71 )
0.028
+0.100
-0.050
+0.004
0.016 -0.002
0.41
1.27
0.050
0.05
0.002 MIN
8
Revision 1.0
September 2003
CMOS SRAM
K6X4008C1F Family
PACKAGE DIMENSIONS
Units : millimeter(Inch)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0.25
( 0.010 )
#32
0~8°
#17
11.76±0.20
0.463±0.008
#1
10.16
0.400
0.45 ~0.75
0.018 ~ 0.030
#16
21.35 MAX
0.841
( 0.50 )
0.020
0.15 +0.10
-0.05
0.006 +0.004
-0.002
1.00±0.10
0.039±0.004
1.20
0.047MAX
20.95±0.10
0.825±0.004
0.10 MAX
0.004 MAX
( 0.95 )
0.037
0.40±0.10
0.016±0.004
0.05
0.002MIN
1.27
0.050
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
0~8°
( 0.25 )
0.010
#1
#16
11.76±0.20
0.463±0.008
#32
10.16
0.400
0.45 ~0.75
0.018 ~ 0.030
#17
1.00 ±0.10
0.039±0.004
21.35
0.841 MAX
+0.10
-0.05
0.006 +0.004
-0.002
0.15
( 0.50 )
0.020
1.20
0.047 MAX
20.95±0.10
0.825±0.004
0.10 MAX
0.004 MAX
( 0.95 )
0.037
0.40±0.10
0.016±0.004
1.27
0.050
0.05
0.002MIN
9
Revision 1.0
September 2003
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