LTC6947
Ultralow Noise 0.35GHz to
6GHz Fractional-N Synthesizer
Description
Features
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Low Noise Fractional-N PLL
No ∆Σ Modulator Spurs
18-Bit Fractional Denominator
350MHz to 6GHz VCO Input Range
–226dBc/Hz Normalized In-Band Phase Noise Floor
–274dBc/Hz Normalized In-Band 1/f Noise
–157dBc/Hz Wideband Output Phase Noise Floor
Excellent Integer Boundary Spurious Performance
Output Divider (1 to 6, 50% Duty Cycle)
Output Buffer Muting
Charge Pump Supply from 3.15V to 5.25V
Charge Pump Current from 1mA to 11.2mA
Reference Input Frequency Up to 425MHz
Fast Frequency Switching
FracNWizard™ Software Design Tool Support
The LTC®6947 is a high performance, low noise, 6GHz
phase-locked loop (PLL), including a reference divider,
phase-frequency detector (PFD), ultralow noise charge
pump, fractional feedback divider, and VCO output divider.
The fractional divider uses an advanced, 4th order Δ∑
modulator which provides exceptionally low spurious
levels. This allows wide loop bandwidths, producing
extremely low integrated phase noise values.
The programmable VCO output divider, with a range of 1
through 6, extends the output frequency range. The differential, low-noise output buffer has user-programmable
output power ranging from –4.3dBm to +4.5dBm, and may
be muted through either a digital input pin or software.
The ultralow noise charge pump contains selectable high
and low voltage clamps useful for VCO monitoring, and
also may be set to provide a V+/2 bias.
Applications
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All device settings are controlled through a SPI-compatible
serial port.
Wireless Basestations (LTE, WiMAX, W-CDMA, PCS)
Broadband Wireless Access
Microwave Data Links
Military and Secure Radio
Test and Measurement
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
FracNWizard is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
Typical Application
11GHz Source for Satellite Communications
60.4Ω 5V
3.3V
0.1µF
–
3.3V
3.3V
GND
VVCO+
CP
VCP+
VREF+
GND
REF–
68nH
VRF+
BB
RF+
RF–
GND
3.3V
LTC6947IUFD
MUTE
3.3V
STAT
CS
SCLK
SDI
SDO
LDO
VD+
100pF
–90
–100
100pF
fLO/2
100pF
1µF
220nF
60.4Ω
0.1µF 5V
GND
GND
GND
VCO+
VCO–
3.3V
68nH 100pF
–80
10nF
3.3nF
GND
GND
GND
0.01µF
0.01µF
0.1µF
LT1678IS8
0.01µF
REF+
SPI BUS
0.1µF
+
0.1µF
OUT
1µF
51.1Ω
0.1µF
47µF
0.01µF
1µF
100MHz
+
4.99k
5V
System Phase Noise,
fRF = 11.260GHz
13V
4.99k
VTUNE
MA-COM
MAOC-009266
47nF
75Ω
1nF
fLO = 10.2GHz TO 11.3GHz IN 381.4Hz STEPS
PHASE NOISE (dBc/Hz)
10nF
–110
–120
–130
–140
RMS NOISE = 0.549°
–150 RMS JITTER = 135fs
–160 fPFD = 50MHz
LOOP BW = 34kHz
–170 INTN = 0
CPLE = 1
–180
100
1k
10k 100k
1M
10M
OFFSET FREQUENCY (Hz)
100M
6946 TA01b
R = 2, fPFD = 50MHz
N = 102 TO 113
LBW = 33.6kHz
AUXILIARY OUTPUTS
fLO/2, /4, /6, /8, /10 OR /12
6947 TA01a
6947f
For more information www.linear.com/LTC6947
1
LTC6947
Absolute Maximum Ratings
Pin Configuration
(Note 1)
VVCO+
GND
VCP+
CP
REF–
VREF+
TOP VIEW
Supply Voltages
V+ (VREF+, VRF+, V VCO+, VD+) to GND....................3.6V
VCP+ to GND..........................................................5.5V
Voltage on CP Pin..................GND – 0.3V to VCP+ + 0.3V
Voltage on all other Pins............GND – 0.3V to V+ + 0.3V
Operating Junction Temperature Range, TJ
LTC6947I (Note 2).............................. –40°C to 105°C
Junction Temperature, TJMAX................................. 125°C
Storage Temperature Range................... –65°C to 150°C
28 27 26 25 24 23
REF+ 1
22 GND
STAT 2
21 GND
CS 3
20 GND
SCLK 4
19 GND
29
GND
SDI 5
18 GND
SDO 6
17 GND
LDO 7
16 VCO+
VD+ 8
15 VCO–
BB
VRF+
RF+
RF
–
GND
MUTE
9 10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJCbottom = 7°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
LTC6947IUFD#PBF
LTC6947IUFD#TRPBF
6947
28-Lead (4mm × 5mm) Plastic QFN –40°C to 105°C
JUNCTION TEMPERATURE RANGE
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Electrical Characteristics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VRF+ = VVCO+ = 3.3V, VCP+ = 5V unless otherwise
specified (Note 2). All voltages are with respect to GND.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
425
MHz
2.7
VP-P
Reference Inputs (REF+, REF–)
fREF
Input Frequency
VREF
Input Signal Level
Single-Ended, 1µF AC-Coupling Capacitors
Input Slew Rate
l
10
l
0.5
l
20
l
1.65
1.85
2.25
V
l
5.8
8.4
11.6
kΩ
Input Duty Cycle
2
V/µs
50
Self-Bias Voltage
Input Resistance
Differential
Input Capacitance
Differential
14
%
pF
6947f
2
For more information www.linear.com/LTC6947
LTC6947
Electrical Characteristics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VRF+ = VVCO+ = 3.3V, VCP+ = 5V unless otherwise
specified (Note 2). All voltages are with respect to GND.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
6000
MHz
dBm
VCO Input (VCO+, VCO–)
fVCO
Input Frequency
PVCOI
Input Power Level
Input Resistance
l
350
RZ = 50Ω, Single-Ended
l
–8
0
6
Single-Ended, Each Input
l
94
132
161
Ω
l
350
6000
MHz
l
1
6
RF Output (RF+, RF–)
fRF
Output Frequency
O
Output Divider Range
All Integers Included
Output Duty Cycle
PRF-SE
50
%
Output Resistance
Single-Ended, Each Output to VRF
+
l
100
136
175
Ω
Output Power, Single-Ended, fRF = 900MHz
RFO[1:0] = 0, RZ = 50Ω, LC Match
RFO[1:0] = 1, RZ = 50Ω, LC Match
RFO[1:0] = 2, RZ = 50Ω, LC Match
RFO[1:0] = 3, RZ = 50Ω, LC Match
l
l
l
l
–9
–6.1
–2.9
0.1
–7.3
–4.5
–1.4
1.5
–5.5
–2.8
0.2
3.0
dBm
dBm
dBm
dBm
Output Power, Muted, fRF = 900MHz
RZ = 50Ω, Single-Ended, O = 2 to 6
l
–80
dBm
Mute Enable Time
l
110
ns
Mute Disable Time
l
170
ns
l
100
MHz
l
l
l
l
l
76.1
66.3
56.1
45.9
34.3
MHz
MHz
MHz
MHz
MHz
11.2
mA
±6
%
±3.5
±2
%
%
1.0
%/V
Phase/Frequency Detector
fPFD
Input Frequency
Integer mode
Fractional mode
LDOEN = 0
LDOV = 3, LDOEN = 1
LDOV = 2, LDOEN = 1
LDOV = 1, LDOEN = 1
LDOV = 0, LDOEN = 1
Charge Pump
ICP
Output Current Range
8 Settings (See Table 6)
Output Current Source/Sink Accuracy
All Settings, V(CP) = VCP+/2
Output Current Source/Sink Matching
ICP = 1.0mA to 2.8mA, V(CP) = VCP+/2
ICP = 4.0mA to 11.2mA, V(CP) = VCP+/2
Output Current vs Output Voltage Sensitivity (Note 3)
170
ppm/°C
0.03
nA
CPCLO = 1
0.84
V
CPCHI = 1, Referred to VCP+
–0.96
V
0.48
V/V
V(CP) = VCP
Output Hi-Z Leakage Current
ICP = 11.2mA, CPCLO = CPCHI = 0 (Note 3)
VCLMP-LO
Low Clamp Voltage
VCLMP-HI
High Clamp Voltage
Mid-Supply Output Bias Ratio
0.2
l
+/2
Output Current vs Temperature
VMID
1
l
+ – GND)
Referred to (VCP
Reference (R) Divider
R
Divide Range
All Integers Included
l
1
31
Counts
All Integers Included, Integer Mode
All Integers Included, Fractional Mode
l
l
32
35
1023
1019
Counts
Counts
All Integers Included
l
1
262143
Counts
VCO (N) Divider
N
Divide Range
Fractional ∆∑ Modulator
Numerator Range
6947f
For more information www.linear.com/LTC6947
3
LTC6947
Electrical Characteristics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VRF+ = VVCO+ = 3.3V, VCP+ = 5V unless otherwise
specified (Note 2). All voltages are with respect to GND.
SYMBOL
PARAMETER
CONDITIONS
MIN
Output Voltage
LDO Enabled, Four Values
LDO Disabled
External Pin Capacitance
Required for LDO Stability
l
0.047
1.55
TYP
MAX
UNITS
Modulator LDO
V
V
1.7 to 2.6
VD+
0.1
1
µF
Digital Pin Specifications
VIH
High Level Input Voltage
MUTE, CS, SDI, SCLK
l
VIL
Low Level Input Voltage
MUTE, CS, SDI, SCLK
l
VIHYS
Input Voltage Hysteresis
MUTE, CS, SDI, SCLK
Input Current
MUTE, CS, SDI, SCLK
V
0.8
250
l
+ – 400mV
IOH
High Level Output Current
SDO and STAT, VOH = VD
l
IOL
Low Level Output Current
SDO and STAT, VOL = 400mV
l
SDO Hi-Z Current
–3.3
2.0
mV
±1
µA
–1.9
mA
3.4
mA
±1
l
V
µA
Digital Timing Specifications (See Figure 7 and Figure 8)
tCKH
SCLK High Time
l
25
ns
tCKL
SCLK Low Time
l
25
ns
tCSS
CS Setup Time
l
10
ns
tCSH
CS High Time
l
10
ns
tCS
SDI to SCLK Setup Time
l
6
ns
tCH
SDI to SCLK Hold Time
l
6
ns
tDO
SCLK to SDO Time
To VIH/VIL/Hi-Z with 30pF Load
l
16
ns
Power Supply Voltages
VREF+ Supply Range
l
3.15
3.3
3.45
V
+ Supply Range
l
3.15
3.3
3.45
V
l
3.15
3.3
3.45
V
l
3.15
3.3
3.45
V
l
3.15
5.25
V
VD
VRF+ Supply Range
VVCO
+ Supply Range
VCP+ Supply Range
Power Supply Currents
IDD
VD+ Supply Current
Digital Inputs at Supply Levels, PDFN = 1
Digital Inputs at Supply Levels, Fractional
Mode, fPFD = 66.3MHz MHz, LDOV[1:0] = 3
l
l
18.2
1500
22
µA
mA
ICC(5V)
Sum VCP+ Supply Currents
ICP = 11.2mA
ICP = 1.0mA
PDALL = 1
l
l
l
34
12
230
40
14
650
mA
mA
µA
ICC(3.3V)
Sum VREF+, VRF+, VVCO+ Supply Currents
RF Muted, OD[2:0] = 1
RF Enabled, RFO[1:0] = 0, OD[2:0] = 1
RF Enabled, RFO[1:0] = 3, OD[2:0] = 1
RF Enabled, RFO[1:0] = 3, OD[2:0] = 2
RF Enabled, RFO[1:0] = 3, OD[2:0] = 3
RF Enabled, RFO[1:0] = 3, OD[2:0] = 4 to 6
PDALL = 1
l
l
l
l
l
l
l
70.4
81.1
91.3
109.2
114.8
119.6
53
80
95
105
125
135
140
250
mA
mA
mA
mA
mA
mA
µA
6947f
4
For more information www.linear.com/LTC6947
LTC6947
Electrical Characteristics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VRF+ = VVCO+ = 3.3V, VCP+ = 5V unless otherwise
specified (Note 2). All voltages are with respect to GND.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Phase Noise and Spurious
LMIN
Output Phase Noise Floor (Note 5)
RFO[1:0] = 3, OD[2:0] = 1, fRF = 6GHz
–155
dBc/Hz
RFO[1:0] = 3, OD[2:0] = 2, fRF = 3GHz
–155
dBc/Hz
RFO[1:0] = 3, OD[2:0] = 3, fRF = 2GHz
–156
dBc/Hz
RFO[1:0] = 3, OD[2:0] = 4, fRF = 1.5GHz
–156
dBc/Hz
RFO[1:0] = 3, OD[2:0] = 5, fRF = 1.2GHz
–157
dBc/Hz
RFO[1:0] = 3, OD[2:0] = 6, fRF = 1.0GHz
–158
dBc/Hz
LNORM(INT)
Integer Normalized In-Band Phase Noise
Floor
INTN = 1, ICP = 5.6mA (Notes 6, 7, 9)
–226
dBc/Hz
LNORM(FRAC)
Fractional Normalized In-Band Phase Noise
Floor
INTN = 0, CPLE = 1, ICP = 5.6mA
(Notes 6, 7, 9)
–225
dBc/Hz
L1/f
Normalized In-Band 1/f Phase Noise
ICP = 11.2mA (Notes 6, 10)
–274
dBc/Hz
In-Band Phase Noise Floor
Fractional Mode, CPLE = 1
(Notes 4, 6, 7, 10, 11)
–109
dBc/Hz
Integrated Phase Noise from 100Hz to
40MHz
Fractional Mode, CPLE = 1 (Notes 4, 7, 11)
0.076
°RMS
Spurious
Fractional Mode, fOFFSET = fPFD, PLL Locked
(Notes 4, 7, 11, 12)
–97
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6947I is guaranteed to meet specified performance limits
over the full operating junction temperature range of –40°C to 105°C.
Note 3: For 0.9V < V(CP) < (VCP+ – 0.9V).
Note 4: VCO is Crystek CVCO55C-2328-2536.
Note 5: fVCO = 6GHz, fOFFSET = 40MHz.
Note 6: Measured inside the loop bandwidth with the loop locked.
Note 7: Reference frequency supplied by Wenzel 501-04516, fREF =
100MHz, PREF = 10dBm.
dBc
Note 8: Reference frequency supplied by Wenzel 500-23571, fREF =
61.44MHz, PREF = 10dBm.
Note 9: Output phase noise floor is calculated from normalized phase
noise floor by LOUT = LNORM + 10log10 (fPFD) + 20log10 (fRF/fPFD).
Note 10: Output 1/f noise is calculated from normalized 1/f phase noise by
LOUT(1/f) = L1/f + 20log10 (fRF) – 10log10 (fOFFSET).
Note 11: ICP = 5.6mA, fPFD = 50MHz, FILT[1:0] = 0, Loop BW = 31kHz;
fRF = 2415MHz, fVCO = 2415MHz.
Note 12: Measured using DC1846.
Note 13: VCO is RFMD UMX-918-D16-G.
6947f
For more information www.linear.com/LTC6947
5
LTC6947
Typical Performance Characteristics
VCP+ = 5V, INTN = 0, DITHEN = 1, CPLE = 1, RFO[1:0] = 3, unless otherwise noted.
REF Input Sensitivity vs
Frequency
CP Hi-Z Current vs Voltage,
Temperature
–20
–30
–35
4
3
2
–40
–45
1
–3
–4
–4
3
2
2
1
1
–1
ICP = 11.2mA
CPLE = 0
105°C
25°C
–40°C
–1
1.0
–4
–4
0
–30
HD2 (dBc)
0.5
0
–0.5
LC = 68nH
CS = 100pF
105°C
25°C
–40°C
2.25 3.25 4.25
FREQUENCY (GHz)
–5
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
–35
6.25
6947 G07
–60
0.25
O=4 O=5
–10
O=2
O=6
2.25
3.25 4.25
fVCO (GHz)
O=2
–20
O=1
–25
O=5
5.25
6.25
6947 G08
O=6
O=3
–15
O=4
1.25
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
RF Output HD3 vs Output Divide
(Single-Ended on RF–)
–40
–55
0
–5
O=1
–45
ICP = 11.2mA
CPLE = 0
105°C
25°C
–40°C
6947 G06
O=3
–50
5.25
–1
–3
LC = 68nH, CS = 100pF
–25 fRF = fVCO/O
1.25
0
–3
–20
–2.5
0.25
1
RF Output HD2 vs Output Divide
(Single-Ended on RF–)
1.5
POUT (dBm)
2
6947 G05
2.0
–2.0
3
–2
RF Output Power vs Frequency
(Single-Ended on RF–)
–1.5
4
–2
6947 G04
–1.0
5
CPLE = 0
1mA
5.6mA
11.2mA
0
–5
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
Charge Pump Source Current
Error vs Voltage, Temperature
ERROR (%)
3
ERROR (%)
ERROR (%)
4
0
0
6947 G03
Charge Pump Source Current
Error vs Voltage, Output Current
5
0
–5
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
6947 G02
4
–5
0
–1
–3
5
–4
1
–2
Charge Pump Sink Current Error
vs Voltage, Temperature
–3
2
–2
6947 G01
–2
3
–1
0
CPLE = 0
1mA
5.6mA
11.2mA
4
0
–5
50 100 150 200 250 300 350 400 450
FREQUENCY (MHz)
0
5
ICP = 11.2mA
CPRST = 1
CPLE = 0
105°C
25°C
–40°C
HD3 (dBc)
SENSITIVITY (dBm)
–25
5
Charge Pump Sink Current Error
vs Voltage, Output Current
ERROR (%)
BST = 1
FILT = 0
105°C
25°C
–40°C
CURRENT (nA)
–15
–50
TA = 25°C. VREF+ = VD+ = VRF+ = VVCO+ = 3.3V,
–30 LC = 68nH
CS = 100pF
fRF = fVCO/O
–35
0.25 1.25 2.25
3.25 4.25
fVCO (GHz)
5.25
6.25
6947 G09
6947f
6
For more information www.linear.com/LTC6947
LTC6947
Typical Performance Characteristics
VCP+ = 5V, INTN = 0, DITHEN = 1, CPLE = 1, RFO[1:0] = 3, unless otherwise noted.
VCO Input Sensitivity vs
Frequency
–30
–10
O=1
–60
O=2
O=4
–90 O = 3
–30
O=6
–100
–110
0.25
O=5
1.25
3.25
2.25
4.25
–35
0.25
6.25
5.25
fVCO (MHz)
–25
6947 G10
–226
–227
0
–20
–60
–80
INTEGER-N
1
3
5
7
ICP (mA)
–120
0
–20
–40
–91dBc
–60
–80
–100
–100
–120
–120
–140
RMS NOISE = 0.076°
RMS JITTER = 87fs
fPFD = 50MHz
LOOP BW = 31kHz
VCO = NOTE 4
INTN = 0
CPLE = 1
NOTE 11
1M
10k
100k
OFFSET FREQUENCY (Hz)
–200 –150 –100 –50 0 50 100 150 200
FREQUENCY OFFSET (MHz IN 10kHz SEGMENTS)
6947 G16
–140
4
fVCO (GHz)
5
6
6947 G12
–130
–140
–150
RMS NOISE = 0.074°
RMS JITTER = 62fs
fPFD = 61.44MHz
LOOP BW = 14.5kHz
VCO = NOTE 13
INTN = 0
CPLE = 1
–170
100
10M 40M
1k
6947 G14
Spurious Response
fRF = 3330MHz, fREF = 61.44MHz,
fPFD = 61.44MHz, Loop BW = 14.5kHz
1M
10k
100k
OFFSET FREQUENCY (Hz)
10M 40M
6947 G15
Supply Current vs Temperature
26
90
RBW = 10Hz
VBW = 10Hz
INTN = 0
CPLE = 1
O=1
VCO = NOTE 13
NOTE 8
–89dBc
3
–120
–160
6947 G13
Spurious Response
fRF = 2415MHz, fREF = 100MHz,
fPFD = 50MHz, Loop BW = 31kHz
–88dBc
–110
1k
2
Closed-Loop Phase Noise
fRF = 3330MHz
–110
–150
1
6947 G11
–100
–140
INTEGER-N
–226
–100
–130
FRACTIONAL-N
–225
–90
–170
100
11
RBW = 10Hz
VBW = 10Hz
INTN = 0
CPLE = 1
O=1
VCO = NOTE 4
NOTES 7, 11
–224
–90
–160
9
–223
–227
6.25
5.25
–222
89
–90dBc
88
24
87
23
86
22
85
21
84
–246 –184 –123–61.4 0 61.4 123 184 246
FREQUENCY OFFSET (MHz IN 10kHz SEGMENTS)
6947 G17
25
EXCLUDES VD+
83
–40
O = 1, MUTE = 0
RFO = 3, ICP = 5.6mA
–20
0
20
40
TJ (°C)
60
80
100
5V CURRENT (mA)
–40
POUT (dBm)
PHASE NOISE (dBc/Hz)
–225
POUT (dBm)
PHASE NOISE FLOOR (dBc/Hz)
–223
FRACTIONAL-N
4.25
ICP = 5.6mA
CPLE = 1
–221
Closed-Loop Phase Noise
fRF = 2415MHz
fVCO = 5GHz
CPLE = 1
–224
3.25
FREQUENCY (GHz)
Normalized In-Band Phase Noise
Floor vs CP Current
–222
2.25
1.25
PHASE NOISE (dBc/Hz)
–80
–20
3.3V CURRENT (mA)
–70
–220
105°C
25°C
–40°C
–15
SENSITIVITY (dBm)
POUT AT fVCO/O (dBm)
LC = 68nH, CS = 100pF,
–40 PVCO = 0dBm, fRF = fVCO/O
Normalized In-Band Phase Noise
Floor vs fVCO
PHASE NOISE FLOOR (dBc/Hz)
MUTE Output Power vs fVCO and
Output Divide (Single-Ended on RF–)
–50
TA = 25°C. VREF+ = VD+ = VRF+ = VVCO+ = 3.3V,
20
19
6947 G18
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LTC6947
Typical Performance Characteristics
VCP+ = 5V, INTN = 0, DITHEN = 1, CPLE = 1, RFO[1:0] = 3, unless otherwise noted.
VD+ Supply Current vs LDOV, fPFD
(INTN = 0, PDFN = 0)
20
20
18
LDOV = 2
10
8
LDOV = 1
6
LDOV = 0
4
2
0
15
25
LDOEN = 0, 75MHz
16
LDOV = 3, 65MHz
14
12
LDOV = 2, 55MHz
10
LDOV = 1, 45MHz
8
6
LDOEN = 0
5
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
14
12
VD+ Supply Current vs LDOV,
Temperature
(INTN = 0, PDFN = 0, fPFD Noted)
18
LDOV = 3
16
TA = 25°C. VREF+ = VD+ = VRF+ = VVCO+ = 3.3V,
35 45 55
fPFD (MHz)
65
75
4
–40
6947 G19
LDOV = 0, 30MHz
–20
0
20
40
TJ (°C)
60
80
100
6947 G20
Pin Functions
REF+, REF– (Pins 1, 28): Reference Input Signals. This
differential input is buffered with a low noise amplifier,
which feeds the reference divider. They are self-biased and
must be AC-coupled with 1µF capacitors. If used singleended with VREF+ ≤ 2.7VP-P, bypass REF– to GND with a
1µF capacitor. If used single-ended with VREF+ > 2.7VP-P,
bypass REF– to GND with a 47pF capacitor.
STAT (Pin 2): Status Output. This signal is a configurable
logical OR combination of the UNLOK, LOK, THI, and TLO
status bits, programmable via the STATUS register. See
the Operation section for more details.
CS (Pin 3): Serial Port Chip Select. This CMOS input initiates a serial port communication burst when driven low,
ending the burst when driven back high. See the Operation
section for more details.
SCLK (Pin 4): Serial Port Clock. This CMOS input clocks
serial port input data on its rising edge. See the Operation
section for more details.
SDI (Pin 5): Serial Port Data Input. The serial port uses
this CMOS input for data. See the Operation section for
more details.
SDO (Pin 6): Serial Port Data Output. This CMOS threestate output presents data from the serial port during a
read communication burst. Optionally attach a resistor of
>200k to GND to prevent a floating output. See the Applications Information section for more details.
LDO (Pin 7): Δ∑ Modulator LDO Bypass Pin. This pin
should be bypassed directly to the ground plane using a
low ESR (<0.8Ω) 0.1µF ceramic capacitor as close to the
pin as possible.
VD+ (Pin 8): 3.15V to 3.45V Positive Supply Pin for Serial
Port and Δ∑ Modulator Circuitry. This pin should be bypassed directly to the ground plane using a 0.1µF ceramic
capacitor as close to the pin as possible.
MUTE (Pin 9): RF Mute. The CMOS active-low input mutes
the RF± differential outputs while maintaining internal bias
levels for quick response to de-assertion.
6947f
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LTC6947
Pin Functions
GND (Pins 10, 17, 18, 19, 20, 21, 22, Exposed Pad Pin
29): Negative Power Supply (Ground). These pins should
be tied directly to the ground plane with multiple vias for
each pin. The package exposed pad must be soldered
directly to the PCB land. The PCB land pattern should
have multiple thermal vias to the ground plane for both
low ground inductance and also low thermal resistance.
RF–, RF+ (Pins 11, 12): RF Output Signals. The VCO
output divider is buffered and presented differentially on
these pins. The outputs are open-collector, with 136Ω
(typical) pull-up resistors tied to VRF+ to aid impedance
matching. If used single-ended, the unused output should
be terminated to 50Ω. See the Applications Information
section for more details on impedance matching.
VRF+ (Pin 13): 3.15V to 3.45V Positive Supply Pin for
RF Circuitry. This pin should be bypassed directly to the
ground plane using a 0.01µF ceramic capacitor as close
to the pin as possible.
BB (Pin 14): RF Reference Bypass. This output has a 2.5k
resistance and must be bypassed with a 1µF ceramic capacitor to GND. Do not couple this pin to any other signal.
VCO–, VCO+ (Pins 15, 16): VCO Input Signals. The differential signal placed on these pins is buffered with a low
noise amplifier and fed to the internal output and feedback
dividers. These self-biased inputs must be AC-coupled
and present a single-ended 121Ω (typical) resistance
to aid impedance matching. They may be used singleended by bypassing VCO– to GND with a capacitor. See
the Applications Information section for more details on
impedance matching.
VVCO+ (Pin 23): 3.15V to 3.45V Positive Supply Pin for
VCO Circuitry. This pin should be bypassed directly to the
ground plane using a 0.01µF ceramic capacitor as close
to the pin as possible.
GND (24): Negative Power Supply (Ground). This pin is
attached directly to the die attach paddle (DAP) and should
be tied directly to the ground plane.
VCP+ (Pin 25): 3.15V to 5.25V Positive Supply Pin for Charge
Pump Circuitry. This pin should be bypassed directly to
the ground plane using a 0.1µF ceramic capacitor as close
to the pin as possible.
CP (Pin 26): Charge Pump Output. This bidirectional current
output is normally connected to the external loop filter.
See the Applications Information section for more details.
VREF+ (Pin 27): 3.15V to 3.45V Positive Supply Pin for
Reference Input Circuitry. This pin should be bypassed
directly to the ground plane using a 0.1µF ceramic capacitor as close to the pin as possible.
6947f
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9
LTC6947
Block Diagram
1
28
REF+
2
3
4
5
6
8
7
REF–
STAT
≤425MHz
CS
27
25
VREF+
VCP+
≤100MHz
R_DIV
PFD
24
GND
1mA TO
11.2mA
CP
VVCO+
÷1 TO 31
LOCK
SCLK
SERIAL
PORT
÷32 TO 1023
GND 21
N_DIV
GND 20
SDO
VD+
∆∑
÷1 TO 6, 50%
350MHz TO 6GHz
1.7V TO 2.6V
LDO
REGULATOR
+
–
23
GND 22
SDI
LDO
26
O_DIV
MUTE
VCO+
16
– 15
350MHz VCO
TO 6GHz
GND 19
GND 18
GND 17
EXPOSED PAD
29
MUTE
9
GND
10
RF–
11
RF
12
+
+
VRF
13
BB
14
6947 BD
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LTC6947
Operation
The LTC6947 is a high performance fractional-N PLL,
and, combined with an external high performance VCO,
can produce low noise LO signals up to 6GHz. The output
frequency range may be further extended by utilizing the
output divider. The device is able to achieve superior integrated phase noise by the combination of its extremely low
in-band phase noise performance and the wide bandwidth
allowed by its low spurious products.
The fractional-N feedback divider uses an advanced Δ∑
modulator, resulting in virtually no discrete modulator
spurious tones. The modulator may be disabled if integer-N
feedback is required.
Reference Input Buffer
The PLL’s reference frequency is applied differentially on
pins REF+ and REF–. These high impedance inputs are
self-biased and must be AC-coupled with 1µF capacitors
(see Figure 1 for a simplified schematic). Alternatively, the
inputs may be used single-ended by applying the reference frequency at REF+ and bypassing REF– to GND with
a 1µF capacitor. If the single-ended signal is greater than
2.7VP-P, then use a 47pF capacitor for the GND bypass.
Additional options are available through serial port register
h0B to further refine the application. Bits FILT[1:0] control
the reference input buffer’s lowpass filter, and should be
set based upon fREF to limit the reference’s wideband
noise. The FILT[1:0] bits must be set correctly to reach the
LNORM normalized in-band phase noise floor. See Table 1
for recommended settings.
Table 1. FILT[1:0] Programming
FILT[1:0]
fREF
3
<20MHz
2
NA
1
20MHz to 50MHz
0
>50MHz
The BST bit should be set based upon the input signal level
to prevent the reference input buffer from saturating. See
Table 2 for recommended settings and the Applications
Information section for programming examples.
Table 2. BST Programming
BST
VREF
1
<2VP-P
0
≥2VP-P
A high quality signal must be applied to the REF± inputs
VREF+
Reference (R) Divider
VREF+
BIAS
LOWPASS
1.9V
1
REF+
4.2k
4.2k
FILT[1:0]
28
REF –
6947 F01
A 5-bit divider, R_DIV, is used to reduce the frequency
seen at the PFD. Its divide ratio R may be set to any integer from 1 to 31, inclusive. Use the RD[4:0] bits found in
registers h06 to directly program the R divide ratio. See
the Applications Information section for the relationship
between R and the fREF, fPFD, fVCO, and fRF frequencies.
Phase/Frequency Detector (PFD)
BST
Figure 1. Simplified REF Interface Schematic
as they provide the frequency reference to the entire PLL.
To achieve the part’s in-band phase noise performance,
apply a CW signal of at least 6dBm into 50Ω, or a square
wave of at least 0.5VP-P with slew rate of at least 40V/µs.
The phase/frequency detector (PFD), in conjunction with
the charge pump, produces source and sink current pulses
proportional to the phase difference between the outputs
of the R and N dividers. This action provides the necessary
feedback to phase-lock the loop, forcing a phase alignment at the PFD’s inputs. The PFD may be disabled with
the CPRST bit which prevents UP and DOWN pulses from
being produced. See Figure 2 for a simplified schematic
of the PFD.
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LTC6947
Operation
D
Q
UP
R DIV
RST
CPRST
Table 4. LKWIN[2:0] Integer Mode Programming
DELAY
D
When using the device as an integer-N synthesizer (integer
mode), the phase difference seen at the PFD is minimized
by the feedback of the PLL and no longer depends upon
fVCO. Table 4 contains recommended settings for different
fPFD frequencies when used in integer mode.
Q
DOWN
6947 F02
N DIV
RST
LKWIN[2:0]
tLWW
fPFD
0
5.0ns
>6.8MHz
1
7.35ns
≤6.8MHz
2
10.7ns
≤4.7MHz
3
15.8ns
≤3.2MHz
4
23.0ns
≤2.2MHz
5
34.5ns
≤1.5MHz
Lock Indicator
6
50.5ns
≤1.0MHz
The lock indicator uses internal signals from the PFD to
measure phase coincidence between the R and N divider
output signals. It is enabled by programming LKCT[1:0]
in the serial port register h0C (see Table 5), and produces
both LOCK and UNLOCK status flags, available through
both the STAT output and serial port register h00.
7
76.0ns
≤660kHz
Figure 2. Simplified PFD Schematic
The user sets the phase difference lock window time tLWW
for a valid LOCK condition with the LKWIN[2:0] bits. When
using the device as a fractional-N synthesizer (fractional
mode), the Δ∑ modulator changes the instantaneous phase
seen at the PFD on every R_DIV and N_DIV cycle. The
maximum allowable time difference in this case depends
upon both the VCO frequency fVCO and also the charge
pump linearization enable bit CPLE (see the Charge Pump
Linearizer section for an explanation of this function). Table
3 contains recommended settings for LKWIN[2:0] when
using the device in fractional mode. See the Applications
Information section for examples.
Table 3. LKWIN[2:0] Fractional Mode Programming
LKWIN[2:0]
tLWW
fVCO (CPLE = 1)
fVCO (CPLE = 0)
0
5.0ns
≥2.97GHz
≥1.35GHz
1
7.35ns
≥2.00GHz
≥919MHz
2
10.7ns
≥1.39GHz
≥632MHz
3
15.8ns
≥941MHz
≥428MHz
4
23.0ns
≥646MHz
≥294MHz
5
34.5ns
≥431MHz
≥196MHz
6
50.5ns
≥294MHz
≥134MHz
7
76.0ns
≥196MHz
≥89MHz
The PFD phase difference must be less than tLWW for the
COUNTS number of successive counts before the lock
indicator asserts the LOCK flag. The LKCT[1:0] bits found
in register h0C are used to set COUNTS depending upon
the application. Set LKCT[1:0] = 0 to disable the lock indicator. See Table 5 for LKCT[1:0] programming and the
Applications Information section for examples.
Table 5. LKCT[1:0] Programming
LKCT[1:0]
COUNTS
0
Lock Indicator Disabled
1
32
2
256
3
2048
When the PFD phase difference is greater than tLWW, the
lock indicator immediately asserts the UNLOCK status
flag and clears the LOCK flag, indicating an out-of-lock
condition. The UNLOCK flag is immediately de-asserted
when the phase difference is less than tLWW. See Figure 3
below for more details.
Note that fREF must be present for the LOCK and UNLOCK
flags to properly assert and clear.
Charge Pump
The charge pump, controlled by the PFD, forces sink
(DOWN) or source (UP) current pulses onto the CP pin,
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LTC6947
Operation
Table 6. CP[2:0] Programming
+tLWW
PHASE
DIFFERENCE
AT PFD
CP[2:0]
ICP
0
1.0mA
1
1.4mA
2
2.0mA
3
2.8mA
4
4.0mA
5
5.6mA
0
–tLWW
UNLOCK FLAG
t = COUNTS/fPFD
LOCK FLAG
6947 F03
Figure 3. UNLOCK and LOCK Timing
VCP+
CPMID
0.9V
–
+
THI
ICP
VCP+/2
–
+
DOWN
CPDN
+
–
CP
26
TLO
0.9V
CP[2:0]
ND[9:0]
CPINV
INTN
CPLE
11.2mA
Charge Pump Functions
The charge pump contains additional features to aid in
system startup. See Table 7 for a summary.
Table 7. Charge Pump Function Bit Descriptions
BIT
VCP+
CP LINEARIZER
CONTROL
8.0mA
7
The CPINV bit found in register h0D should be set for applications requiring signal inversion from the PFD, such
as for external loops using an op amp. A passive loop
filter as shown in Figure 14 requires CPINV = 0. An active
loop filter as shown in Figure 15 requires CPINV = 1 for
a positive KVCO.
VCP+
+
–
UP
CPUP
6
ILIN
ENABLE
DESCRIPTION
CPCHI
Enable High Voltage Output Clamp
CPCLO
Enable Low Voltage Output Clamp
CPDN
Force Sink Current
CPINV
Invert PFD Phase
CPLE
Linearizer Enable
6947 F04
CPMID
Enable Mid-Voltage Bias
Figure 4. Simplified Charge Pump Schematic
CPRST
Reset PFD
CPUP
Force Source Current
which should be connected to an appropriate loop filter.
See Figure 4 for a simplified schematic of the charge pump.
The output current magnitude ICP may be set from 1mA to
11.2mA using the CP[2:0] bits found in serial port register
h0C. A larger ICP can result in lower in-band noise due
to the lower impedance of the loop filter components,
although currents larger than 5.6mA typically cause worse
spurious performance. See Table 6 for programming
specifics and the Applications Information section for
loop filter examples.
CPWIDE
Extend Current Pulse Width
THI
High Voltage Clamp Flag
TLO
Low Voltage Clamp Flag
The CPCHI and CPCLO bits found in register h0D enable
the high and low voltage clamps, respectively. When CPCHI
is enabled and the CP pin voltage exceeds approximately
VCP+ – 0.9V, the THI status flag is set, and the charge pump
sourcing current is disabled. Alternately, when CPCLO is
enabled and the CP pin voltage is less than approximately
0.9V, the TLO status flag is set, and the charge pump sinking
current is disabled. See Figure 4 for a simplified schematic.
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LTC6947
Operation
The CPMID bit also found in register h0D enables a resistive VCP+/2 output bias which may be used to pre-bias
troublesome loop filters into a valid voltage range. When
using CPMID, it is recommended to also assert the CPRST
bit, forcing a PFD reset. Both CPMID and CPRST must be
set to 0 for normal operation.
The CPUP and CPDN bits force a constant ICP source or
sink current, respectively, on the CP pin. The CPRST bit
may also be used in conjunction with the CPUP and CPDN
bits, allowing a pre-charge of the loop to a known state,
if required. CPUP, CPDN, and CPRST must be set to 0 to
allow the loop to lock.
The CPWIDE bit extends the charge pump output current
pulse width by increasing the PFD reset path’s delay value
(see Figure 2). CPWIDE is normally set to 0.
Charge Pump Linearizer
When the LTC6947 is operated in fractional mode, the
charge pump’s current output versus its phase stimulus
(its gain linearity) must be extremely accurate. The CP
gain linearizer automatically adds a correction current ILIN
to minimize the charge pump’s impact on in-band phase
noise and spurious products during fractional operation.
The CP gain linearizer is enabled by setting CPLE = 1. It is
automatically disabled when in integer mode. CPLE should
be set to 0 if CPRST or CPMID are asserted to prevent the
linearizer from producing unintended currents.
VCO Input Buffer
The VCO frequency is applied differentially on pins VCO+ and
VCO–. The inputs are self-biased and must be AC-coupled.
Alternatively, the inputs may be used single-ended by applying the VCO frequency at VCO+ and bypassing VCO– to
GND with a capacitor. Each input provides a single-ended
121Ω resistance to aid in impedance matching at high
frequencies. See the Applications Information section for
matching guidelines.
The BB pin is used to bias internal VCO buffer circuitry.
The BB pin has a 2k output resistance and should be
bypassed with a 1µF ceramic capacitor to GND, giving a
time constant of 2ms. Stable bias voltages are achieved
after approximately 3 time constants following power-up.
VVCO+
+
–
16
15
VCO+
121Ω
0.9V
VVCO+
VVCO+
121Ω
VC0–
6947 F05
Figure 5. Simplified VCO Interface Schematic
VCO (N) Divider
The 10-bit N divider provides the feedback from the VCO to
the PFD. Its divide ratio N is restricted to any integer from
35 to 1019, inclusive, when in fractional mode. The divide
ratio may be programmed from 32 to 1023, inclusive, when
in integer mode. Use the ND[9:0] bits found in registers
h06 and h07 to directly program the N divide ratio. See
the Applications Information section for the relationship
between N and the fREF, fPFD, fVCO, and fRF frequencies.
Δ∑ Modulator
The Δ∑ modulator changes the N divider’s ratio each PFD
cycle to achieve an average fractional divide ratio. The
fractional numerator NUM[17:0] is programmable from
1 to 262143, or 218 – 1. The fractional denominator is
fixed at 262144 (or 218), with the resulting fractional ratio
F given by Equation 3. See the Applications Information
section for the relationship between NUM, F, and the fREF,
fPFD, fVCO, and fRF frequencies.
The Δ∑ modulator uses digital signal processing (DSP)
techniques to achieve an average fractional divide ratio.
The modulator is clocked at the fPFD rate. This process
produces output modulation noise known as quantization
noise with a highpass frequency response. The external
lowpass loop filter is used to filter this quantization noise to
a level beneath the phase noise of the VCO. This prevents
the noise from contributing to the overall phase noise of
the system. The loop filter must be designed to adequately
filter the quantization noise.
The oversampling ratio OSR is defined as the ratio of the
Δ∑ modulator clock frequency fPFD to the loop bandwidth
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LTC6947
Operation
BW of the PLL (see Equation 10). See the Applications
Information section for guidelines concerning the OSR
and the loop filter.
When the desired output frequency is such that the needed
NUM value is 0, the LTC6947 should be operated in integer
mode (INTN = 1). In integer mode, the modulator is placed
in standby, with all blocks still powered up, thus allowing
it to resume fractional operation immediately.
Enable numerator dither mode (DITHEN = 1) to further
reduce spurious produced by the modulator. Dither has no
measurable impact on in-band phase noise, and is enabled
by default. See Table 8 for a complete list of modulator
bit descriptions.
Modulator Reset
To achieve consistent spurious performance, the modulator
DSP circuitry should be re-initialized by setting RSTFN = 1
whenever NUM[17:0] is changed. Setting AUTORST = 1
causes the RSTFN bit to be set automatically whenever
any of serial port registers h05 through h0A are written.
When AUTORST is enabled, there is no need for a separate register write to set the RSTFN bit. See Table 8 for a
summary of the modulator bits.
BIT
DITHEN
INTN
Table 9. LDOV[1:0] and LDOEN Programming
LDOV[1:0]
LDOEN
V(LDO)
fPFD
0
1
1.7V
≤34.3MHz
1
1
2.0V
≤45.9MHz
2
1
2.3V
≤56.1MHz
3
1
2.6V
≤66.3MHz
X
0
VD+
≤76.1MHz
Output (O) Divider
The 3-bit O divider can reduce the frequency from the VCO
to extend the output frequency range. Its divide ratio O
may be set to any integer from 1 to 6, inclusive, outputting
a 50% duty cycle even with odd divide values. Use the
OD[2:0] bits found in register h0B to directly program the
O divide ratio. See the Applications Information section
for the relationship between O and the fREF, fPFD, fVCO,
and fRF frequencies.
RF Output Buffer
Table 8. Fractional Modulator Bit Descriptions
AUTORST
the LDOEN bit to 0. When disabled by using either the
LDOEN or PDFN bits, the LDO pin is connected directly
to VD+ using a low impedance switch, and the regulator
is powered down. See Table 9 for programming details.
DESCRIPTION
Automatically Reset Modulator when Registers h05 to h0A
Are Written
Enable Fractional Numerator Dither
Integer Mode; Fractional Modulator Placed in Standby
RSTFN
Reset Modulator (Auto Clears)
SEED
Seed Value for Pseudorandom Dither Algorithm
The low noise, differential output buffer produces a differential output power of –4.3dBm to +4.5dBm, settable
with bits RFO[1:0] according to Table 10. The outputs may
be combined externally, or used individually. Terminate
any unused output with a 50Ω resistor to VRF+.
Table 10. RFO[1:0] Programming
RFO[1:0}
PRF (DIFFERENTIAL)
PRF (SINGLE-ENDED)
0
–4.3dBm
–7.3dBm
LDO Regulator
1
–1.5dBm
–4.5dBm
The adjustable low dropout (LDO) regulator supplies power
to the Δ∑ modulator. The regulator requires a low ESR
ceramic capacitor (ESR < 0.8Ω) connected to the LDO pin
(pin 7) for stability. The capacitor value may range from
0.047µF to 1µF.
2
1.6dBm
–1.4dBm
3
4.5dBm
1.5dBm
The LDO voltage is set using the LDOV[1:0] bits, and should
be chosen based upon the fPFD frequency to minimize
power and spurious. The regulator is disabled by setting
Each output is open-collector with 136Ω pull-up resistors
to VRF+, easing impedance matching at high frequencies.
See Figure 6 for circuit details and the Applications Information section for matching guidelines. The buffer may be
muted with either the OMUTE bit, found in register h02,
or by forcing the MUTE input low.
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15
LTC6947
Operation
VRF+
communication burst is terminated by the serial bus master
returning CS high. See Figure 7 for details.
VRF+
136Ω
136Ω
RF+
RF–
9
MUTE
Data is read from the part during a communication burst
using SDO. Readback may be multidrop (more than one
LTC6947 connected in parallel on the serial bus), as SDO
is three-stated (Hi-Z) when CS = 1, or when data is not
being read from the part. If the LTC6947 is not used in
a multidrop configuration, or if the serial port master is
not capable of setting the SDO line level between read
sequences, it is recommended to attach a high value
resistor of greater than 200k between SDO and GND to
ensure the line returns to a known level during Hi-Z states.
See Figure 8 for details.
12
11
MUTE
OMUTE
RFO[1:0]
6947 F06
Figure 6. Simplified RF Interface Schematic
Serial Port
The SPI-compatible serial port provides control and
monitoring functionality. A configurable status output
STAT gives additional instant monitoring.
Single Byte Transfers
The serial port is arranged as a simple memory map, with
status and control available in 15 byte-wide registers. All
data bursts are comprised of at least two bytes. The seven
most significant bits of the first byte are the register address,
with an LSB of 1 indicating a read from the part, and LSB
of 0 indicating a write to the part. The subsequent byte,
or bytes, is data from/to the specified register address.
See Figure 9 for an example of a detailed write sequence,
and Figure 10 for a read sequence.
Communication Sequence
The serial bus is comprised of CS, SCLK, SDI, and SDO.
Data transfers to the part are accomplished by the serial bus master device first taking CS low to enable the
LTC6947’s port. Input data applied on SDI is clocked on
the rising edge of SCLK, with all transfers MSB first. The
MASTER–CS
tCSS
tCKL
tCKH
tCSS
tCSH
MASTER–SCLK
tCS
MASTER–SDI
tCH
DATA
DATA
6947 F07
Figure 7. Serial Port Write Timing Diagram
MASTER–CS
8TH CLOCK
MASTER–SCLK
tDO
LTC6947–SDO
Hi-Z
tDO
tDO
tDO
DATA
DATA
Hi-Z
6947 F08
Figure 8. Serial Port Read Timing Diagram
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LTC6947
Operation
MASTER–CS
16 CLOCKS
MASTER–SCLK
7-BIT REGISTER ADDRESS
MASTER–SDI
LTC6947–SD0
8 BITS OF DATA
A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0
0 = WRITE
Hi-Z
6947 F09
Figure 9. Serial Port Write Sequence
MASTER–CS
16 CLOCKS
MASTER–SCLK
7-BIT REGISTER ADDRESS
MASTER–SDI
1 = READ
A6 A5 A4 A3 A2 A1 A0 1
8 BITS OF DATA
LTC6947–SDO
Hi-Z
X D7 D6 D5 D4 D3 D2 D1 D0 DX
Hi-Z
6947 F10
Figure 10. Serial Port Read Sequence
Figure 11 shows an example of two write communication
bursts. The first byte of the first burst sent from the serial
bus master on SDI contains the destination register address (Addr0) and an LSB of 0 indicating a write. The next
byte is the data intended for the register at address Addr0.
CS is then taken high to terminate the transfer. The first
byte of the second burst contains the destination register
address (Addr1) and an LSB indicating a write. The next
byte on SDI is the data intended for the register at address
Addr1. CS is then taken high to terminate the transfer.
Multiple Byte Transfers
More efficient data transfer of multiple bytes is accomplished by using the LTC6947’s register address autoincrement feature as shown in Figure 12. The serial port
master sends the destination register address in the first
byte and its data in the second byte as before, but continues
sending bytes destined for subsequent registers. Byte 1’s
address is Addr0+1, Byte 2’s address is Addr0+2, and so
on. If the register address pointer attempts to increment
past 14 (h0E), it is automatically reset to 0.
An example of an auto-increment read from the part is
shown in Figure 13. The first byte of the burst sent from
the serial bus master on SDI contains the destination register address (Addr0) and an LSB of 1 indicating a read.
Once the LTC6947 detects a read burst, it takes SDO out
of the Hi-Z condition and sends data bytes sequentially,
beginning with data from register Addr0. The part ignores
all other data on SDI until the end of the burst.
Multidrop Configuration
Several LTC6947s may share the serial bus. In this multidrop configuration, SCLK, SDI, and SDO are common
between all parts. The serial bus master must use a separate
CS for each LTC6947 and ensure that only one device has
CS asserted at any time. It is recommended to attach a
high value resistor to SDO to ensure the line returns to a
known level during Hi-Z states.
Serial Port Registers
The memory map of the LTC6947 may be found in Table
11, with detailed bit descriptions found in Table 12. The
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LTC6947
Operation
MASTER–CS
BYTE 0
ADDR0 + Wr
MASTER–SDI
ADDR1 + Wr
BYTE 1
Hi-Z
LTC6947–SDO
6947 F11
Figure 11. Serial Port Single Byte Write
MASTER–CS
ADDR0 + Wr
MASTER–SDI
BYTE 0
BYTE 1
BYTE 2
Hi-Z
LTC6947–SDO
6947 F12
Figure 12. Serial Port Auto-Increment Write
MASTER–CS
ADDR0 + Rd
MASTER–SDI
Hi-Z
LTC6947–SDO
DON’T CARE
BYTE 0
BYTE 1
Hi-Z
BYTE 2
6947 F13
Figure 13. Serial Port Auto-increment Read
Table 11. Serial Port Register Contents
ADDR
MSB
[6]
[5]
[4]
[3]
[2]
[1]
LSB
R/W
h00
*
*
UNLOCK
*
*
LOCK
THI
TLO
R
DEFAULT
h01
*
*
x[5]
*
*
x[2]
x[1]
x[0]
R/W
h04
h02
PDALL
PDPLL
*
PDOUT
PDFN
*
OMUTE
POR
R/W
h06
h03
*
*
*
*
*
AUTORST
DITHEN
INTN
R/W
h06
h04
*
*
*
*
CPLE
LDOEN
LDOV[1]
LDOV[0]
R/W
h07
h05
SEED[7]
SEED[6]
SEED[5]
SEED[4]
SEED[3]
SEED[2]
SEED[1]
SEED[0]
R/W
h11
h06
RD[4]
RD[3]
RD[2]
RD[1]
RD[0]
*
ND[9]
ND[8]
R/W
h08
h07
ND[7]
ND[6]
ND[5]
ND[4]
ND[3]
ND[2]
ND[1]
ND[0]
R/W
hFA
h08
*
*
NUM[17]
NUM[16]
NUM[15]
NUM[14]
NUM[13]
NUM[12]
R/W
h3F
h09
NUM[11]
NUM[10]
NUM[9]
NUM[8]
NUM[7]
NUM[6]
NUM[5]
NUM[4]
R/W
hFF
h0A
NUM[3]
NUM[2]
NUM[1]
NUM[0]
*
*
RSTFN
*
R/W
hF0
h0B
BST
FILT[1]
FILT[0]
RFO[1]
RFO[0]
OD[2]
OD[1]
OD[0]
R/W
hF9
h0C
LKWIN[2]
LKWIN[1]
LKWIN[0]
LKCT[1]
LKCT[0]
CP[2]
CP[1]
CP[0]
R/W
h4F
h0D
CPCHI
CPCLO
CPMID
CPINV
CPWIDE
CPRST
CPUP
CPDN
R/W
hE4
h0E
REV[3]
REV[2]
*unused †varies depending on version
REV[1]
REV[0]
PART[3]
PART[2]
PART[1]
PART[0]
R
hxx†
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LTC6947
Operation
Table 12. Serial Port Register Bit Field Summary
BITS
AUTORST
DESCRIPTION
DEFAULT
Reset Modulator Whenever Registers H05
to h0A Are Written
1
REF Buffer Boost Current
1
CP[2:0]
CP Output Current
h7
CPCHI
Enable Hi-Voltage CP Output Clamp
1
CPCLO
Enable Low-Voltage CP Output Clamp
1
CPDN
Force CP Pump Down
0
CPINV
Invert CP Phase
0
CPLE
CP Linearizer Enable
0
CPMID
CP Bias to Mid-Rail
1
CPRST
CP Tri-State
1
CPUP
Force CP Pump Up
0
CPWIDE
Extend CP Pulse Width
0
DITHEN
Enable Fractional Numerator Dither
1
FILT[1:0]
REF Input Buffer Filter
h3
Integer Mode; Fractional Modulator Placed
in Standby
0
LDO Enable
1
BST
INTN
LDOEN
LDOV[1:0] LDO Voltage
h3
LKCT[1:0]
h1
PLL Lock Cycle Count
LKWIN[2:0] PLL Lock Indicator Window
LOCK
ND[9:0]
h2
PLL Lock Indicator Flag
N Divider Value (ND[9:0] ≥ 32)
NUM[17:0] Fractional Numerator Value
h0FA
h3FFF
register address shown in hexadecimal format under
the ADDR column is used to specify each register. Each
register is denoted as either read-only (R) or read-write
(R/W). The register’s default value on device power-up or
after a reset is shown at the right.
The read-only register at address h00 is used to determine
different status flags. These flags may be instantly output
on the STAT pin by configuring register h01. See the STAT
Output section for more information.
The read-only register at address h0E is a ROM byte for
device identification.
STAT Output
The STAT output pin is configured with the x[5,2:0] bits
of register h01. These bits are used to bit-wise mask, or
enable, the corresponding status flags of status register
h00, according to Equation 1. The result of this bit-wise
Boolean operation is then output on the STAT pin.
STAT = OR (Reg00[5,2:0] AND Reg01[5,2:0])
(1)
or, expanded,
STAT = (UNLOCK AND x[5]) OR
(LOCK AND x[2]) OR
(THI AND x[1]) OR
(TLO AND x[0])
OD[2:0]
Output Divider Value (0 < OD[2:0] < 7)
h1
OMUTE
Mutes RF Output
1
For example, if the application requires STAT to go high
whenever the LOCK or THI flags are set, then x[2] and x[1]
should be set to 1, giving a register value of h06.
PART[3:0]
Part Code
h0
PDALL
Full Chip Powerdown
0
PDFN
Powers Down LDO and Modulator Clock
0
PDOUT
Powers Down N_DIV, RF Output Buffer
0
PDPLL
Powers Down REF, R_DIV, PFD, CPUMP
0
Force Power-On-Reset
0
POR
RD[4:0]
R Divider Value (RD[4:0] > 0)
REV[3:0]
Rev Code
h1
RFO[1:0]
RF Output Power
h3
RSTFN
Force Modulator Reset (Auto Clears)
SEED[7:0] Modulator Dither Seed Value
THI
CP Clamp High Flag
TLO
CP Clamp Low Flag
UNLOK
PLL Unlock Flag
x[5,2:0]
STAT Output OR Mask
h001
0
h11
Block Power-Down Control
The LTC6947’s power-down control bits are located in
register h02, described in Table 12. Different portions of
the device may be powered down independently. Care must
be taken with the LSB of the register, the POR (power-onreset) bit. When written to a 1, this bit forces a full reset
of the part’s digital circuitry to its power-up default state.
h04
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LTC6947
Applications Information
Introduction
where the fractional value F is given by Equation 3:
A PLL is a complex feedback system that may conceptually
be considered a frequency multiplier. The system multiplies
the frequency input at REF± and outputs a higher frequency
at RF±. The PFD, charge pump, N divider, external VCO,
and loop filter form a feedback loop to accurately control
the output frequency (see Figure 14).
F=
The PFD frequency fPFD is given by the following equation:
fPFD =
fREF
R
fVCO = fPFD • (N + F)
fRF =
fVCO
O
fSTEP(MIN) =
fPFD
(7)
LOOP FILTER
(FOURTH ORDER)
LTC6947
R_DIV
fREF
R • O • 218
Alternatively, to calculate the numerator step size NUMSTEP
needed to produce a given frequency step fSTEP(FRAC), use
Equation 8:
(2)
REF±
(6)
Using the above equations, the minimum output frequency
resolution fSTEP(MIN) produced by a unit change in the
fractional numerator NUM while in fractional mode is
given by Equation 7:
When the loop is locked, the frequency fVCO (in Hz)
produced at the output of the VCO is determined by the
reference frequency fREF, the R and N divider values, and
the fractional value F, given by Equation 2:
(fREF)
(5)
The output frequency fRF produced at the output of the O
divider is given by Equation 6:
Output Frequency
KPFD
(4)
and fVCO may be alternatively expressed as:
The R and O divider and input frequency fREF are used to
set the output frequency resolution. When in fractional
mode, the Δ∑ modulator changes the N divider’s ratio
each PFD cycle to produce an average fractional divide
ratio. This achieves a much smaller frequency resolution
for a given fPFD as compared to integer mode.
fREF • (N + F )
R
(3)
NUM is programmable from 1 to 262143, or 218 – 1. When
using the LTC6947 in integer mode, F = 0.
The external loop filter is used to set the PLL’s loop
bandwidth BW. Lower bandwidths generally have better
spurious performance and lower Δ∑ modulator quantization
noise. Higher bandwidths can have better total integrated
phase noise.
fVCO =
NUM
218
ICP
CP
÷R
26
C2
L1
R1
÷(N + F)
RZ
CP
CI
N_DIV
LF(s)
∆∑
RF±
(fRF)
O_DIV
÷O
VCO±
fVCO
KVCO
6947 F14
Figure 14. PLL Loop Diagram
6947f
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LTC6947
Applications Information
fSTEP(FRAC) • R • O • 218
NUMSTEP =
fREF
(8)
The output frequency resolution fSTEP(INT) produced by a
unit change in N while in integer mode is given by Equation 9:
f
fSTEP(INT) = REF
R•O
(9)
A stable PLL system requires care in designing the external
loop filter. The Linear Technology FracNWizard application, available from www.linear.com, aids in design and
simulation of the complete system.
The loop design should use the following algorithm:
1) Determine the output frequency fRF and frequency step
size fSTEP based on application requirements. Using
Equations 2, 4, 6, and 7, change fREF, N, R, and O until
the application frequency constraints are met. Use the
minimum R value that still satisfies the constraints.
2) Select the open loop bandwidth BW constrained by
fPFD and oversampling ratio OSR. The OSR is the ratio
of fPFD to BW (see Equation 10):
(10)
BW ≅
ICP • RZ • K VCO
2 • π •N
(11)
RZ =
2 • π • BW • N
ICP • K VCO
where KVCO is in Hz/V, ICP is in Amps, and RZ is in
Ohms. KVCO is the VCO’s frequency tuning sensitivity,
and may be determined from the VCO specifications. Use
ICP = 5.6mA to lower in-band noise unless component
values force a lower setting.
4) Select loop filter components CI and CP based on BW
and RZ. A reliable second-order loop filter design can
be achieved by using the following equations for the
loop capacitors (in Farads).
CI =
3.5
2 • π • BW • RZ
(12)
1
7 • π • BW • RZ
(13)
CP =
Use FracNWizard to aid in the design of higher order
loop filters.
or
BW =
3) Select loop filter component RZ and charge pump current ICP based on BW and the VCO gain factor, KVCO.
BW (in Hz) is approximated by the following equation:
or
Loop Filter Design
f
OSR = PFD
BW
loop bandwidth. Linear Technology’s FracNWizard helps
choose the appropriate OSR and BW values.
fPFD
OSR
Loop Filters Using an Op Amp
where BW and fPFD are in Hz.
A stable loop, both in integer and fractional mode,
requires that the OSR is greater than or equal to 10.
Further, in fractional mode, OSR must be high enough
to allow the loop filter to reduce modulator quantization
noise to an acceptable level.
Choosing a higher-order loop filter when using the Δ∑
modulator allows for a smaller OSR, and thus a larger
Some VCO tune voltage ranges are greater than the
LTC6947’s charge pump voltage range. An active loop filter
using an op amp can increase the tuning voltage range.
To maintain the LTC6947’s high performance, care must
be given to picking an appropriate op amp.
The op amp input common mode voltage should be biased
within the LTC6947 charge pump’s voltage range, while
its output voltage should achieve the VCO tuning range.
See Figure 15 for an example op amp loop filter.
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LTC6947
Applications Information
Design and Programming Example
LOOP FILTER
(FOURTH ORDER)
CI
ICP
This programming example uses the DC1846 with the
LTC6947. Assume the following parameters of interest:
CP
LF(s)
RZ
CP
C2 R1
fSTEP = 50kHz
L1
fRF = 2415.15MHz
fVCO = 2328MHz to 2536MHz
–
LTC6947
VCP+
5k
5k
VCO±
fREF = 100MHz at 7dBm into 50Ω
KVCO = 78MHz/V
+
LM(VCO) = –127dBc/Hz at 100kHz offset
VCP+/2
RP2
47µF
KVCO
(fVCO)
CP2
6947 F15
Figure 15. Op Amp Loop Filter
The op amp’s input bias current is supplied by the charge
pump; minimizing this current keeps spurs related to fPFD
low. The input bias current should be less than the charge
pump leakage (found in the Electrical Characteristics section) to avoid increasing spurious products.
Op amp noise sources are highpass filtered by the PLL
loop filter and should be kept at a minimum, as their effect raises the total system phase noise beginning near
the loop bandwidth. Choose a low noise op amp whose
input-referred voltage noise is less than the thermal noise
of RZ. Additionally, the gain-bandwidth of the op amp
should be at least 20 times the loop bandwidth to limit
phase margin degradation. The LT®1678 is an op amp that
works very well in most applications.
An additional R-C lowpass filter (formed by RP2 and CP2
in Figure 15) connected at the input of the VCO will limit
the op amp output noise sources. The bandwidth of this
filter should be approximately 15 to 20 times the PLL loop
bandwidth to limit loop phase margin degradation. RP2
should be small (preferably less than RZ) to minimize its
noise impact on the loop. However, picking too small of
a value can make the op amp unstable as it has to drive
the capacitor in this filter.
Determining Divider Values
Following the Loop Filter Design algorithm, first determine
all the divider values. The maximum fPFD while in fractional
mode is less than 100MHz, so R must be greater than 1.
Further, the minimum N value in fractional mode is 35,
setting the lower limit on R:
R=2
Then, using Equations 4 and 6, calculate the following
values:
O =1
fPFD = 50MHz
Then using Equation 5:
N+F =
2415.15MHz
= 48.303
50MHz
Therefore:
N = 48
F = 0.303
Then, from Equation 3,
NUM = 0.303 • 218 = 79430
Selecting Filter Type and Loop Bandwidth
The next step in the algorithm is choosing the open loop
bandwidth. Select the minimum bandwidth resulting from
the below constraints.
1) The OSR must be at least 10 (sets absolute maximum BW).
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2) The integrated phase noise due to thermal noise should
be minimized, neglecting any modulator noise.
3) However, the loop bandwidth must also be narrow
enough to adequately filter the modulator’s quantization
noise.
FracNWizard reports loop bandwidths resulting from each
of the above constraints. The quantization noise constrained
results vary according to the shape of the external loop
filter. FracNWizard reports an optimal bandwidth for
several filter types.
FracNWizard reports the thermal noise optimized loop
bandwidth is 31.6kHz. Filter 2 (third order response) has
a quantization noise constrained BW of 56.2kHz, making
it a good choice. Select Filter 2 and use the smaller of the
two bandwidths (31.6kHz) for optimal integrated phase
noise. Use Equation 10 to calculate OSR:
OSR =
50MHz
= 1582
31.6kHz
Status Output Programming
This example will use the STAT pin to indicate the LTC6947
is locked. Program x[2] = 1 to force the STAT pin high
whenever the LOCK flag asserts:
Reg01 = h04
Power Register Programming
For correct PLL operation all internal blocks should be
enabled. OMUTE may remain asserted (or the MUTE pin
held low) until programming is complete. For OMUTE = 1:
Reg02 = h02
AUTORST Programming
Set the modulator auto reset option (AUTORST = 1) and
the Δ∑ modulator modes (DITHEN = 1, INTN = 0) at the
same time:
Reg03 = h06
Loop Filter Component Selection
Now set loop filter resistor RZ and charge pump current
ICP. Using an ICP of 5.6mA and the specified KVCO of
78MHz/V, FracNWizard uses Equation 11 to determine RZ:
2 • π • 31.6k • 48
RZ =
5.6m• 78M
R Z = 21.8Ω
The Δ∑ modulator will be reset at the end of the SPI write
communication burst (assuming an auto-increment write
is used to write all registers).
LDO Programming
Use Table 9 and fPFD = 50MHz to determine V(LDO) and
LDOV[1:0]:
V(LDO) = 2.3V and LDOV[1:0] = 1
For the 3rd order Filter 2, FracNWizard uses modified
Equations 7 and 8 to calculate CI, CP:
Use LDOV[1:0] and LDOEN = 1 (to enable the LDO) to set
Reg04. CPLE should be set to 1 to reduce in-band noise
and spurious due to the Δ∑ modulator:
Reg04 = h0E
4
= 924nF
2 • π • 31.6k • 21.8
1
CP =
= 44nF
10.5 • π • 31.6k • 21.8
CI =
SEED Programming
The SEED[7:0] value is used to initialize the Δ∑ modulator
dither circuitry. Use the default value:
FracNWizard calculates R1 and C2 to be:
Reg05 = h11
R1 = 21.8Ω
R and N Divider and Numerator Programming
C2 = 29.3nF
These values are used with the schematic of Figure 15
(with L1 unused).
Program registers Reg06 to Reg0A with the previously
determined R and N divider and numerator values. Because
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LTC6947
Applications Information
the AUTORST bit was previously set to 1, RSTFN does not
need to be set:
Reg06 = h10
Reg07 = h30
Reg08 = h13
Reg09 = h64
Reg0A = h60
Reference Input Settings and Output Divider
Programming
From Table 1, FILT = 0 for a 100MHz reference frequency.
Next, convert 7dBm into VP-P. For a CW tone, use the following equation with R = 50:
VP-P ≅ R • 10(dBm – 21)/20
(14)
This gives VP-P = 1.41V, and, according to Table 2, set
BST = 1.
RF±
output
Now program Reg0B, assuming maximum
power (RFO[1:0] = 3 according to Table 10) and OD[2:0] = 1:
Reg0B = h99
Lock Detect and Charge Pump Current Programming
Next, determine the lock indicator window from fPFD. From
Table 3 we see that LKWIN[1:0] = 1 with a tLWW of 7.35ns
for CPLE = 1 and fVCO = 2415MHz. The LTC6947 will consider the loop locked as long as the phase coincidence at
the PFD is within 132°, as calculated below.
phase = 360° • tLWW • fPFD = 360 • 7.35n • 50M
≈ 132°
Choosing the correct COUNTS value depends upon the
OSR. Smaller ratios dictate larger COUNTS values, although
application requirements will vary. A COUNTS value of
32 will work for the OSR ratio of 1582. From Table 5,
LKCT[1:0] = 1 for 32 counts.
Using Table 6 with the previously selected ICP of 5.6mA
gives CP[3:0] = 5. This gives enough information to program Reg0C:
Reg0C = h2D
Charge Pump Function Programming
The DC1846 includes an LT1678I op amp in the loop filter.
This allows the circuit to reach the voltage range specified for the VCO’s tuning input. However, it also adds an
inversion in the loop transfer function. Compensate for
this inversion by setting CPINV = 1.
This example does not use the additional voltage clamp
features to allow fault condition monitoring. The loop
feedback provided by the op amp will force the charge
pump output to be equal to the op amp positive input pin’s
voltage. Disable the charge pump voltage clamps by setting
CPCHI = 0 and CPCLO = 0. Disable all the other charge
pump functions (CPMID, CPRST, CPUP, and CPDN) to
allow the loop to lock:
Reg0D = h10
The loop should now lock. Now un-mute the output by
setting OMUTE = 0 (assumes the MUTE pin is high).
Reg02 = h00
Reference Source Considerations
A high quality signal must be applied to the REF± inputs as
they provide the frequency reference to the entire PLL. As
mentioned previously, to achieve the part’s in-band phase
noise performance, apply a CW signal of at least 6dBm
into 50Ω, or a square wave of at least 0.5VP-P with slew
rate of at least 40V/µs.
The LTC6947 may be driven single-ended to CMOS levels
(greater than 2.7VP-P). Apply the reference signal at REF+,
and bypass REF– to GND with a 47pF capacitor. The BST
bit must also be set to 0, according to guidelines given
in Table 2.
The LTC6947 achieves an integer mode in-band normalized
phase noise floor LNORM(INT) = –226dBc/Hz typical, and
a fractional mode phase noise floor LNORM(FRAC) = –225
dBc/Hz typical. To calculate its equivalent input phase
noise floor LIN, use the following Equation 15.
LIN = LNORM + 10 • log10 (fREF)
(15)
For example, using a 10MHz reference frequency in integer
mode gives an input phase noise floor of –156dBc/Hz.
The reference frequency source’s phase noise must be at
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Applications Information
least 3dB better than this to prevent limiting the overall
system performance.
The in-band phase noise floor LOUT produced at fRF may
be calculated by using Equation 16.
LOUT = LNORM + 10 • log10 (fPFD)
(16)
+ 20 • log10 (fRF/fPFD)
PHASE NOISE (dBc/Hz)
In-Band Output Phase Noise
–90
–100
LOUT ≈ LNORM + 10 • log10 (fPFD)
TOTAL NOISE
fPFD = 100MHz
–110
–120
1/f NOISE
CONTRIBUTION
–130
or
TOTAL NOISE
fPFD = 3MHz
10
1k
10k
100
OFFSET FREQUENCY (Hz)
100k
6947 F16
Figure 16. Theoretical Integer Mode In-Band
Phase Noise, fRF = 2500MHz
+ 20 • log10 (N/O)
where LNORM is –226dBc/Hz for integer mode and
–225dBc/Hz for fractional mode.
As can be seen, for a given PFD frequency fPFD, the output
in-band phase noise increases at a 20dB-per-decade rate
with the N divider count. So, for a given output frequency
fRF, fPFD should be as large as possible (or N should be as
small as possible) while still satisfying the application’s
frequency step size requirements.
Output Phase Noise Due to 1/f Noise
In-band phase noise at very low offset frequencies may
be influenced by the LTC6947’s 1/f noise, depending upon
fPFD. Use the normalized in-band 1/f noise L1/f of –274dBc/
Hz with Equation 17 to approximate the output 1/f phase
noise at a given frequency offset fOFFSET.
LOUT(1/f) (fOFFSET) = L1/f + 20 • log10 (fRF)
(17)
– 10 • log10 (fOFFSET)
Unlike the in-band noise floor LOUT, the 1/f noise LOUT(1/f)
does not change with fPFD, and is not constant over offset
frequency. See Figure 16 for an example of integer mode
in-band phase noise for fPFD equal to 3MHz and 100MHz.
The total phase noise will be the summation of LOUT and
LOUT(1/f).
VCO Input Matching
The VCO± inputs may be used differentially or single-ended.
Each input provides a single-ended 121Ω resistance to aid
in impedance matching at high frequencies. The inputs are
self-biased and must be AC-coupled using 100pF capacitors (or 270pF for VCO frequencies less than 500MHz).
The inputs may be used single-ended by applying the ACcoupled VCO frequency at VCO+ and bypassing VCO– to
GND with a 100pF capacitor (270pF for frequencies less
than 500MHz). Measured VCO+ s-parameters (with VCO–
bypassed with 100pF to GND) are shown in Table 13 to aid
in the design of external impedance matching networks.
Table 13. Single-Ended VCO+ Input Impedance
FREQUENCY (MHz)
IMPEDANCE (Ω)
S11 (dB)
250
118 – j78
–5.06
500
83.6 – j68.3
–5.90
1000
52.8 – j56.1
–6.38
1500
35.2 – j41.7
–6.63
2000
25.7 – j30.2
–6.35
2500
19.7 – j20.6
–5.94
3000
17.6 – j11.2
–6.00
3500
17.8 – j3.92
–6.41
4000
19.8 + j4.74
–7.20
4500
21.5 + j15.0
–7.12
5000
21.1 + j19.4
–6.52
5500
27.1 + j22.9
–7.91
6000
38.3 + j33.7
–8.47
6500
36.7 + j42.2
–6.76
7000
46.2 + j40.9
–8.11
7500
76.5 + j36.8
–9.25
8000
84.1+ j52.2
–7.27
6947f
For more information www.linear.com/LTC6947
25
LTC6947
Applications Information
Integer Boundary Spurs
Integer boundary spurs are caused by intermodulation
between harmonics of the PFD frequency fPFD and the
VCO frequency fVCO. The coupling between the frequency
source harmonics can occur either on- or off-chip. The
spurs are located at offset frequencies defined by the beat
frequency between the reference harmonics and the VCO
frequency, and are attenuated by the loop filter. The spurs
only occur while in fractional mode.
Integer boundary spurs are most commonly seen when
the fractional value F approaches either zero or one such
that the VCO frequency offset from an integer frequency
is within the loop bandwidth:
fPFD • F ≤ BW
or
fPFD • (1 – F) ≤ BW
–40
fVCO ≈ 3.256GHZ
fPFD = 61.44MHz
LOOP BW = 15kHz
CPLE = 1
O=1
N = 53
SWEPT NUM
NOTE 13
IB SPUR LEVEL (dBc)
–50
–60
–70
–80
–90
–100
–110
1k
both cases requires external chokes tied to VRF+. Measured
RF± S-parameters are shown below in Table 14 to aid in
the design of impedance matching networks.
Table 14. Single-Ended RF Output Impedance
FREQUENCY (MHz)
IMPEDANCE (Ω)
S11 (dB)
100
133.0 – j16.8
–6.7
500
110.8 – j46.1
–6.8
1000
74.9 – j57.0
–6.9
1500
49.0 – j51.3
–6.7
2000
34.4 – j41.4
–6.5
2500
27.0 – j32.1
–6.5
3000
23.2 – j24.1
–6.6
3500
21.6 – j15.9
–7.1
4000
20.9 – j7.7
–7.5
4500
20.1 – j0.2
–7.4
5000
18.1 + j7.4
–6.4
5500
16.7 + j12.5
–5.6
6000
17.1 + j16.1
–5.5
6500
20.2 + j20.1
–6.2
7000
26.9 + j24.6
–7.6
7500
38.8 + j32.3
–8.8
8000
52.9 + j43.1
–8.2
Single-ended impedance matching is accomplished using
the circuit of Figure 18, with component values found in
Table 15. Using smaller inductances than recommended
can cause phase noise degradation, especially at lower
center frequencies.
10k
100k
1M
10M
FREQUENCY OFFSET FROM 3.256GHz (Hz)
VRF+
6947 F17
Figure 17. Integer Boundary Spur Power vs Frequency
Offset from Boundary
LC
RF+(–)
The spur will have a relatively constant power in-band, and
is attenuated by the loop out-of-band. An example integer
boundary spur measurement is shown in Figure 17.
50Ω
VRF+
RF Output Matching
LC
The RF± outputs may be used in either single-ended or differential configurations. Using both RF outputs differentially
will result in approximately 3dB more output power than
single-ended. Impedance matching to an external load in
CS
RF–(+)
CS
TO 50Ω
LOAD
6947 F18
Figure 18. Single-Ended Output Matching Schematic
6947f
26
For more information www.linear.com/LTC6947
LTC6947
Applications Information
Table 15. Suggested Single-Ended Matching Component Values
fRF (MHz)
LC (nH)
CS (pF)
350 to 1500
180
270
1000 to 6000
68
100
Return loss measured on the DC1846 using the above
component values is shown in Figure 19. A broadband
match is achieved using an {LC, CS} of either {68nH, 100pF}
or {180nH, 270pF}. However, for maximum output power
and best phase noise performance, use the recommended
component values of Table 15. LC should be a wirewound
inductor selected for maximum Q factor and SRF, such
as the Coilcraft HP series of chip inductors.
0
68nH, 100pF
180nH, 270pF
–2
VRF+ voltage. Figure 20 shows a surface mount balun’s
connections with a DC FEED pin.
Table 16. Suggested Baluns
fRF (MHz)
PART NUMBER
MANUFACTURER
TYPE
350 to 900
#617DB-1673
TOKO
TL
400 to 600
HHM1589B1
TDK
SMT
600 to 1400
BD0810J50200
Anaren
SMT
600 to 3000
MABACT0065
M/A-COM
TL
1000 to 2000
HHM1518A3
TDK
SMT
1400 to 2000
HHM1541E1
TDK
SMT
1900 to 2300
2450BL15B100E
Johanson
SMT
2000 to 2700
HHM1526
TDK
SMT
3700 to 5100
HHM1583B1
TDK
SMT
4000 to 6000
HHM1570B1
TDK
SMT
VRF+
S11 (dB)
–4
–6
–8
–12
LTC6947
–14
RF–
–16
3
RF+ 12
–10
0
1
2
3
4
5
FREQUENCY (GHz)
6
2
1
TO 50Ω
LOAD
BALUN
11
4
5
6
6947 F20
7
BALUN PIN CONFIGURATION
1
UNBALANCED PORT
2
GND OR DC FEED
3
BALANCED PORT
4
BALANCED PORT
5
GND
6
NC
6947 F19
Figure 19. RF Single-Ended Return Loss
The LTC6947’s differential RF± outputs may be combined
using an external balun to drive a single-ended load. The
advantages are approximately 3dB more output power than
each output individually and better 2nd order harmonic
performance.
For lower frequencies, transmission line (TL) baluns such as
the M/A-COM MABACT0065 and the TOKO #617DB-1673
provide good results. At higher frequencies, surface mount
(SMT) baluns such as those produced by TDK, Anaren,
and Johanson Technology, can be attractive alternatives.
See Table 16 for recommended balun part numbers versus
frequency range.
The listed SMT baluns contain internal chokes to bias RF±
and also provide input-to-output DC isolation. The pin
denoted as GND or DC FEED should be connected to the
Figure 20. Example SMT Balun Connection
The listed TL baluns do not provide input-to-output DC
isolation and must be AC-coupled at the output. Figure 21
displays RF± connections using these baluns.
VRF+
TO 50Ω
LOAD
RF+ 12
LTC6947
PRI
RF– 11
SEC
6947 F21
Figure 21. Example TL Balun Connection
6947f
For more information www.linear.com/LTC6947
27
LTC6947
Applications Information
Supply Bypassing and PCB Layout Guidelines
Care must be taken when creating a PCB layout to minimize power supply decoupling and ground inductances.
All power supply V+ pins should be bypassed directly to
the ground plane using a 0.1µF ceramic capacitor as close
to the pin as possible. Multiple vias to the ground plane
should be used for all ground connections, including to
the power supply decoupling capacitors.
The package’s exposed pad is a ground connection, and
must be soldered directly to the PCB land pattern. The
PCB land pattern should have multiple thermal vias to the
ground plane for both low ground inductance and also low
thermal resistance (see Figure 22 for an example). See
QFN Package Users Guide, page 8, on Linear Technology
website’s Packaging Information page for specific recommendations concerning land patterns and land via solder
masks. A link is provided below.
http://www.linear.com/designtools/packaging
Reference Signal Routing, Spurious, and
Phase Noise
The charge pump operates at the PFD’s comparison
frequency fPFD. The resultant output spurious energy is
small and is further reduced by the loop filter before it
modulates the VCO frequency.
However, improper PCB layout can degrade the LTC6947’s
inherent spurious performance. Care must be taken to
prevent the reference signal fREF from coupling onto the
VCO’s tune line, or into other loop filter signals. Example
suggestions are the following.
1) Do not share power supply decoupling capacitors
between same-voltage power supply pins.
2) Use separate ground vias for each power supply decoupling capacitor, especially those connected to VREF+,
VD+, LDO, VCP+, and VVCO+.
3) Physically separate the reference frequency signal from
the loop filter and VCO.
6947 F22
Figure 22. Example Exposed Pad Land Pattern
6947f
28
For more information www.linear.com/LTC6947
LTC6947
Typical Applications
Modulator LO for Low Image Rejection and Low Noise Floor
6.8nF
–
3.3V
220nF
100pF
VTUNE
5V
0.01µF
0.01µF
68nH 100pF
100pF
50Ω
UNUSED OUTPUT
AVAILABLE FOR
OTHER USE
6.8nF
3.3V
0.1µF
10nH
75Ω
RFMD
UMX-918-D16-G
100pF
1µF
47nF
100pF
1Ω
4.7µF
LPF
AVAGO
VMMK-2503
3.3V
1nF
BASEBAND
I-CHANNEL
MINI-CIRCUITS
LFCN-3800+
4.7µF
EN
50Ω 1nF
fLO = 3230MHz TO 3410MHz IN 234.4Hz STEPS
PLO = 13dBm, ~ <–40dBc HARMONIC CONTENT
1.3Ω
1nF
GND
GND
VRF+
BB
RF+
GND
GND
GND
VCO+
VCO–
470nF
68.1Ω
0.1µF 8V
GND
GND
VVCO+
CP
VCP+
VREF+
68nH
6.8nF
GND
GND
GND
3.3V
R = 1, fPFD = 61.44MHz
N = 52.6 TO 55.5
LBW = 14.5kHz
O=1
22nF
VCC1
3.3V
RF–
3.3V
0.1µF
GND
3.3V
LTC6947IUFD
MUTE
SPI BUS
GND
REF–
1µF
REF+
STAT
CS
SCLK
SDI
SDO
LDO
VD+
0.1µF
LT1678IS8
OUT
0.01µF
51.1Ω
LOP
VCC2
LOM
GNDRF
GND
RF
LTC5588-1
NC
GND
GNDRF
GND
BBPQ
BBMQ
GND
Measured Image Rejection and LO
Leakage Ratio vs Output Frequency
–150
–152
NOISE FLOOR (dBm/Hz)
–40
–45
–50
3220
LO LEAKAGE RATIO
3270
3320
3370
OUTPUT FREQUENCY (MHz)
0.2pF
6947 TA02a
Measured Noise Floor at 70MHz
Offset vs RF Output Power
BASEBAND = 100kHz AT 500mVPK
UNADJUSTED
IMAGE REJECTION
RF OUTPUT, 3230MHz TO 3410MHz CARRIER
NC
BASEBAND
Q-CHANNEL
–35
6.8pF
NC
100nF
–30
1nF
GNDRF
LINOPT
(dBc)
0.1µF
+
47µF
0.1µF
GNDRF
1µF
61.44MHz
4.99k
68.1Ω
0.01µF
GNDRF
5V
BBPI
3.3V
0.1µF
18V
4.99k
5V
68µH
BBMI
22nF
fLO = 3300MHz
BASEBAND = 2kHz SINE
–154
–156
–158
–160
3420
–162
–20
6947 TA02b
–15
0
–10
–5
OUTPUT POWER (dBm)
5
6947 TA02c
6947f
For more information www.linear.com/LTC6947
29
LTC6947
Typical Applications
Integer Boundary Spur Avoidance
6.8nF
22nF
315.5MHz DATACONVERTER CLOCK
0.1µF
3.3V
68nH
GND
CP
VCP+
VVCO+
BB
VRF+
3.3V
LTC6947IUFD
RF+
3.3V
VREF+
51.1Ω
RF–
REF+
STAT
CS
SCLK
SDI
SDO
LDO
VD+
SPI BUS
0.1µF
0.1µF
47µF
+
OUT
–
22nF
6.8nF
GND
GND
GND
0.1µF 8V
GND
GND
GND
VCO+
VCO–
470nF
68.1Ω
220nF
100pF
47nF
VTUNE
75Ω
RFMD
UMX-918-D16-G
100pF
3.3V
0.1µF
LT1678IS8
0.01µF
GND
16.5Ω
4.99k
1µF
16.5Ω
16.5Ω
68.1Ω
0.01µF
18V
4.99k
3.3V
GND
REF–
315.5MHz, 15dBm
5V
1µF
MUTE
CRYSTEK
CCSO-914X
68µH
3.3V
0.1µF
5V
6.8nF
1µF
O=1
0.01µF
68nH 100pF
0.01µF
100pF
50Ω
fLO = 3230MHz TO 3410MHz
UNUSED OUTPUT
AVAILABLE FOR
OTHER USE
6947 TA03a
Integer Boundary Spur Avoidance Results
(Measured at Nearest Integer Boundary)
THIS APPLICATION EXAMPLE ILLUSTRATES A STRAIGHTFORWARD
PROGRAMMING METHOD TO MINIMIZE INTEGER BOUNDARY SPURS. SWITCH
THE REFERENCE DIVIDER VALUE, R, BETWEEN TWO PREDETERMINED VALUES
TO AVOID FRACTIONAL VALUES, F, CLOSE TO 0 OR 1.
–95
fREF = 315.5MHz
R1 = 6
R2 = 5
FOR R2 = 5: fPFD(R2) = 63.10MHz, fSTEP(R2) = 240.7Hz
FIRST, CALCULATE fSPUR(R), FREQUENCY OFFSET OF THE INTEGER-BOUNDARY
SPUR NEAREST INTEGER BOUNDARY AS A DISTANCE FROM THE CARRIER,
FOR EACH R VALUE.
SPUR LEVEL (dBc)
–100
FOR R1 = 6: fPFD(R1) = 52.58MHz, fSTEP(R1) = 200.59Hz
–105
–110
fREF
, FOR F < 0.5
R
f
fSPUR (R) = (1 – F) • REF , FOR F ≥ 0.5
R
NUM
WHERE F = 18
2
fSPUR (R) = F •
–115
3220
NEXT, LET R = R1 for fSPUR(R1) > fSPUR(R2), ELSE LET R = R2
3270
3320
3370
LO FREQUENCY (MHz)
3420
NOTE: SPURS UP TO –70dBC CAN BE FOUND
NEAR F VALUES OF 0.5 IN VERY NARROW BANDS
(10s OF kHz) AND UP TO –75dBc NEAR F VALUES
OF 0.333 OR 0.667. APPROPRIATELY SWITCHING
BETWEEN R1 AND R2 CAN AVOID THESE SPURS.
6947 TA03b
6947f
30
For more information www.linear.com/LTC6947
LTC6947
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.50 REF
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
27
28
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ±0.10
(2 SIDES)
3.50 REF
3.65 ±0.10
2.65 ±0.10
(UFD28) QFN 0506 REV B
0.25 ±0.05
0.200 REF
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6947f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC6947
31
LTC6947
Typical Applications
Modulator LO for Low Image Rejection and Low Noise Floor
6.8nF
220nF
100pF
VTUNE
5V
68nH 100pF
10nH
100pF
50Ω
UNUSED OUTPUT
AVAILABLE FOR
OTHER USE
AVAGO
VMMK-2503
6.8nF
3.3V
0.01µF
0.01µF
75Ω
RFMD
UMX-918-D16-G
100pF
1µF
47nF
0.1µF
100pF
1Ω
4.7µF
LPF
3.3V
1nF
BASEBAND
I-CHANNEL
MINI-CIRCUITS
LFCN-3800+
1.3Ω
4.7µF
EN
50Ω 1nF
fLO = 3230MHz TO 3410MHz IN 234.4Hz STEPS
PLO = 13dBm, ~ <–40dBc HARMONIC CONTENT
1nF
GND
GND
VRF+
BB
RF+
GND
GND
GND
VCO+
VCO–
470nF
68.1Ω
0.1µF 8V
GND
GND
VVCO+
CP
VCP+
VREF+
GND
REF–
68nH
6.8nF
GND
GND
GND
3.3V
R = 1, fPFD = 61.44MHz
N = 52.6 TO 55.5
LBW = 14.5kHz
O=1
22nF
VCC1
3.3V
RF–
3.3V
GND
3.3V
LTC6947IUFD
MUTE
SPI BUS
0.1µF
–
3.3V
1µF
REF+
STAT
CS
SCLK
SDI
SDO
LDO
VD+
0.1µF
LT1678IS8
OUT
0.01µF
51.1Ω
0.1µF
+
47µF
0.1µF
GNDRF
1µF
61.44MHz
4.99k
68.1Ω
0.01µF
LOP
VCC2
LOM
GNDRF
GND
RF
LTC5588-1
NC
1nF
6.8pF
NC
RF OUTPUT, 3230MHz TO 3410MHz CARRIER
0.2pF
GNDRF
LINOPT
100nF
BASEBAND
Q-CHANNEL
GND
GNDRF
GND
BBPQ
BBMQ
GND
NC
GNDRF
5V
BBPI
3.3V
0.1µF
18V
4.99k
5V
68µH
BBMI
22nF
6947 TA04
Related Parts
PART NUMBER DESCRIPTION
COMMENTS
LTC6946-x
Ultralow Noise and Spurious Integer-N Synthesizer with
Integrated VCO
370MHz to 6.4GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor,
–157dBc/Hz Wideband Output Phase Noise Floor
LTC6945
Ultralow Noise and Spurious Integer-N Synthesizer
350MHz to 6GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor,
–157dBc/Hz Wideband Output Phase Noise Floor
LTC6948-x
Ultralow Noise Fractional-N Synthesizer with Integrated VCO
370MHz to 6.4GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor,
–157dBc/Hz Wideband Output Phase Noise Floor
LTC6957
Low Phase Noise, Dual Output Buffer/Driver/Logic Converter Optimized Conversion of Sine Waves to Logic Levels, LVPECL/LVDS/CMOS
Outputs, DC-300MHz, 45fsRMS additive jitter (LVPECL)
LTC5588-1
Ultrahigh OIP3 I/Q Modulator
200MHz to 6GHz, 31dBm OIP3, –160.6dBm/Hz Noise Floor
6947f
32 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC6947
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC6947
LT 0814 • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2014