Intersil ISL28486FAZ-T7 Dual micropower single supply rail-to-rail input and output (rrio) precision op-amp Datasheet

ISL28286, ISL28486
®
Data Sheet
September 22, 2006
Dual Micropower Single Supply
Rail-to-Rail Input and Output (RRIO)
Precision Op-Amp
Features
• 120µA typ supply current for both channels
The ISL28286 and ISL28486 are Dual and Quad channel
micropower precision operational amplifiers optimized for
single supply operation at 5V down to 2.4V. For equivalent
performance in a single channel op-amp reference EL8186.
The ISL28286 and ISL28486 feature an Input Range
Enhancement Circuit (IREC) which enables both parts to
maintain CMRR performance for input voltages equal to the
positive and negative supply rails. The input signal is
capable of swinging 10% above the positive supply rail and
to ground with only a slight degradation of the CMRR
performance. The output operation is rail to rail.
Both parts draw minimal supply current while meeting
excellent DC-accuracy, AC-performance, noise and output
drive specifications.
The ISL28286 and ISL28486 can be operated from a single
lithium cell or two Ni-Cd batteries. The input range includes
both positive and negative rail.
ISL28286FUZ
(See Note)
PART
MARKING
TAPE &
REEL
8286Z
50/Tube
ISL28286FUZ-T7 8286Z
(See Note)
Coming Soon
ISL28486FAZ
(Note)
28486FAZ
28486FAZ
Coming Soon
ISL28486FAZ-T7
(Note)
• 600µV max offset voltage
• 500pA typ input bias current
• 400kHz gain-bandwidth product
• 115dB PSRR and CMRR
• Single supply operation down to 2.4V
• Input is capable of swinging above V+ and to V- (ground
sensing)
• Rail-to-rail input and output (RRIO)
• Pb-free plus anneal available (RoHS compliant)
Applications
• Battery- or solar-powered systems
• 4mA to 25mA current loops
• Handheld consumer products
• Medical devices
• Thermocouple amplifiers
Ordering Information
PART NUMBER
FN6312.0
PACKAGE
PKG.
DWG. #
• Photodiode pre-amps
• pH probe amplifiers
10 Ld MSOP MDPOO43
(Pb-free)
7”
10 Ld MSOP MDP0043
(1500 pcs) (Pb-free)
97/Tube
16 Ld QSOP MDP0040
(Pb-free)
7”
16 Ld QSOP MDP0040
(1000 pcs) (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL28286, ISL28486
Pinouts
ISL28486
(16 LD QSOP)
TOP VIEW
ISL28286
(10 LD MSOP)
TOP VIEW
OUT_A 1
IN-_A 2
8 V+
IN+_A 3
15 IN-_D
V- 3
EN_B 4
+
-
IN+_B 5
7 OUT_B
6 IN-_B
14 IN+_D
V+ 4
13 V-
IN+_B 5
OUT_B 7
NC 8
12 IN+_C
+
-
IN-_B 6
2
+
9 OUT_A
16 OUT_D
+
EN_A 2
10 IN-_A
+
+
-
IN+_A 1
11 IN-_C
10 OUT_C
9 NC
FN6312.0
September 22, 2006
ISL28286, ISL28486
Absolute Maximum Ratings (TA = +25°C)
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite
Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/μs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
ESD tolerance, Human Body Model . . . . . . . . . . . . . . . . . . . . . .3kV
ESD tolerance, Machine Model . . . . . . . . . . . . . . . . . . . . . . . . .300V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Operating Junction
Electrical Specifications
PARAMETER
V+ = 5V, V- = 0V,VCM = 2.5V, TA = +25°C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C, temperature data
guaranteed by characterization
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
-600
-650
±20
600
650
µV
VOS
Input Offset Voltage
ΔV OS
-----------------ΔTime
Long Term Input Offset Voltage Stability
1.2
µV/Mo
ΔV OS
---------------ΔT
Input Offset Drift vs Temperature
0.3
µV/°C
IOS
Input Offset Current
-1.5
-1.5
±0.25
2.5
2.5
nA
IB
Input Bias Current
-2
-2.5
±0.5
2
2.5
nA
eN
Input Noise Voltage Peak-to-Peak
f = 0.1Hz to 10Hz
4.5
µVPP
Input Noise Voltage Density
fO = 1kHz
48
nV/√Hz
iN
Input Noise Current Density
fO = 1kHz
0.18
pA/√Hz
CMIR
Input Voltage Range
Guaranteed by CMRR test
0
CMRR
Common-Mode Rejection Ratio
VCM = 0V to 5V
90
80
115
dB
PSRR
Power Supply Rejection Ratio
V+ = 2.4V to 5V
90
80
115
dB
AVOL
Large Signal Voltage Gain
VO = 0.5V to 4.5V, RL = 100kΩ
275
275
500
V/mV
VO = 0.5V to 4.5V, RL = 1kΩ
25
V/mV
Output low, RL = 100kΩ
3
6
30
mV
130
175
225
mV
VOUT
Maximum Output Voltage Swing
Output low, RL = 1kΩ
5
V
Output high, RL = 100kΩ
4.990
4.97
4.996
V
Output high, RL = 1kΩ
4.800
4.750
4.880
V
SR+
Positive Slew Rate
0.13
0.10
0.17
0.20
0.25
V/µs
SR-
Negative Slew Rate
0.10
0.09
0.13
0.17
0.19
V/µs
3
FN6312.0
September 22, 2006
ISL28286, ISL28486
Electrical Specifications
PARAMETER
V+ = 5V, V- = 0V,VCM = 2.5V, TA = +25°C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C, temperature data
guaranteed by characterization (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
GBW
Gain Bandwidth Product
400
kHz
IS,ON
Supply Current, Enabled
All channels enabled.
120
156
175
µA
IS,OFF
Supply Current, Disabled
All channels disabled.
4
7
9
µA
ISC+
Short Circuit Sourcing Capability
RL = 10Ω
29
23
31
mA
ISC-
Short Circuit Sinking Capability
RL = 10Ω
24
19
26
mA
VS
Minimum Supply Voltage
VINH
Enable Pin High Level
VINL
Enable Pin Low Level
IENH
Enable Pin Input Current
VEN = 5V
IENL
Enable Pin Input Current
VEN = 0V
2.4
V
2
V
-0.1
0.8
V
0.7
1.3
1.5
µA
0
+0.1
µA
Typical Performance Curves
45
+1
0
VS = ±2.5V
RL = 1k
GAIN (dB)
-2
35
VS = ±1.2V
RL = 10k
30
GAIN (dB)
-1
40
VS = ±1.2V
RL = 1k
VS = ±2.5V
RL = 10k
-3
-4
Vout = 50mVp-p
AV = 1
CL = 3pF
RF = 0/RG = INF
-5
-6
-7
8
10k
1k
100k
FREQUENCY (Hz)
1M
5M
VS = ±1.25V
AV = 100
V
=
±2.5V
15 RL = 10kΩ
S
CL = 2.7pF
10 R /R = 99.02
VS = ±1.0V
F G
RF = 221kΩ
5
RG = 2.23kΩ
0
100
1k
10k
100k
20
1M
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
FIGURE 2. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
0
200
VCM = VDD/2
150 AV = -1
INPUT OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE (µV)
25
100
50
VDD = 5V
0
VDD = 2.5V
-50
-100
-150
-200
-20
VOS, µV
-40
-60
-80
-100
0
1
2
3
4
5
OUTPUT VOLTAGE (V)
FIGURE 3. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE
4
0
1
2
3
4
5
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 4. INPUT OFFSET VOLTAGE vs COMMON-MODE
INPUT VOLTAGE
FN6312.0
September 22, 2006
ISL28286, ISL28486
(Continued)
120
80
80
40
200
100
150
80
0
0
-40
-40
50
40
0
20
-80
-80
1
100
10
10k
1k
100k
GAIN
-100
-20
10
100
100
120
110
PSRR +
80
CMRR(dB)
PSRR (dB)
60
50
PSRR -
100
70
60
50
40
VS = 5VDC
VSOURCE = 1Vp-p
RL = 100kΩ
AV = +1
0
10
30
20
1k
10k
100k
10
10
1M
100
FREQUENCY (Hz)
1k
10k
100k
FREQUENCY (Hz)
FIGURE 7. PSRR vs FREQUENCY
FIGURE 8. CMRR vs FREQUENCY
5.0
2.56
VIN
VIN
2.54
VOUT
4.0
VS = 5VDC
VOUT = 0.1Vp-p
RL = 500Ω
AV = -2
2.52
VOUT
2.50
VOLTS (V)
VOLTS (V)
-150
1M
100k
VS = 5VDC
VSOURCE = 1Vp-p
RL = 100kΩ
AV = +1
90
80
70
20
10
10k
FIGURE 6. AVOL vs FREQUENCY @ 1kΩ LOAD
FIGURE 5. AVOL vs FREQUENCY @ 100kΩ LOAD
40
30
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
100
90
-50
0
-120
10M
1M
100
60
GAIN (dB)
40
PHASE (°)
GAIN (dB)
PHASE
PHASE (°)
Typical Performance Curves
2.48
VS = 5VDC
VOUT = 0.1Vp-p
RL = 500Ω
AV = +1
2.46
2.44
2
4
6
8
10 12
TIME (µs)
VOUT
VIN
0
14
16
18
20
FIGURE 9. SMALL SIGNAL TRANSIENT RESPONSE
5
2.0
1.0
2.42
0
3.0
0
100
200
300
TIME (µs)
400
500
FIGURE 10. LARGE SIGNAL TRANSIENT RESPONSE
FN6312.0
September 22, 2006
ISL28286, ISL28486
Typical Performance Curves
(Continued)
1k
VOLTAGE NOISE (nV/√Hz)
CURRENT NOISE (pA/√Hz)
10.00
1.00
0.10
100
10
1
0.01
1
10
100
1k
10k
1
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 11. CURRENT NOISE vs FREQUENCY
FIGURE 12. VOLTAGE NOISE vs FREQUENCY
6
V+ = 5V
VIN
VOLTAGE NOISE (1µV/DIV)
5
VOLTS (V)
4
100K
VS +
100K
3
DUT
+
1K
VOUT
VS -
Function
Generator
33140A
2
1
4.5µVP-P
0
0
50
100
150
200
TIME (ms)
TIME (1s/DIV)
FIGURE 13. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE
FIGURE 14. INPUT VOLTAGE SWING ABOVE THE V+ SUPPLY
AV = -1
VIN = 200mVp-p
V+ = 5V
V- = 0V
EN
Input
1V/DIV
135
115
95
0
75
55
35
2
2.5
3
3.5
4
4.5
5
5.5
SUPPLY VOLTAGE (V)
FIGURE 15. SUPPLY CURRENT vs SUPPLY VOLTAGE
6
VOUT
0.1V/DIV
SUPPLY CURRENT (µA)
155
0
10µs/DIV
FIGURE 16. ENABLE TO OUTPUT DELAY TIME
FN6312.0
September 22, 2006
ISL28286, ISL28486
Typical Performance Curves
(Continued)
150
4.8
n = 12
MAX
CURRENT (µA)
CURRENT (µA)
140
130
120
MEDIAN
110
n = 12
4.6
4.4
MAX
4.2
MEDIAN
4
3.8
3.6
100
MIN
3.2
-40
90
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
n = 12
1.4
20
n = 12
1.4
MAX
1.2
40
60
80
100
120
MAX
1.2
1
CURRENT (nA)
CURRENT (nA)
0
FIGURE 18. SUPPLY CURRENT vs TEMPERATURE VS = ±2.5V
DISABLED. RL = INF
1.6
1.6
-20
TEMPERATURE (°C)
FIGURE 17. SUPPLY CURRENT vs TEMPERATURE VS = ±2.5V
ENABLED. RL = INF
0.8
0.6
0.4
MEDIAN
0.2
0
1
0.8
0.6
0.4
MEDIAN
0.2
0
-0.2
-0.4
-0.2
MIN
-0.6
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
-0.4
-40
120
MIN
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 19. I BIAS(+) vs TEMPERATURE VS = ±2.5V
FIGURE 20. I BIAS(+) vs TEMPERATURE VS = ±1.2V
1.5
1.5
n = 12
n = 12
1
MAX
1
0.5
CURRENT (nA)
CURRENT (nA)
MIN
3.4
0
-0.5
MEDIAN
MAX
0.5
0
-0.5
MEDIAN
-1
-1
-1.5
MIN
MIN
-1.5
-2
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 21. I BIAS(-) vs TEMPERATURE VS = ±2.5V
7
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 22. I BIAS(-) vs TEMPERATURE VS = ±1.2V
FN6312.0
September 22, 2006
ISL28286, ISL28486
Typical Performance Curves
2.5
(Continued)
2.5
n = 12
2
CURRENT (pA)
CURRENT (nA)
1
0.5
MEDIAN
0
-0.5
MIN
-1
1.5
1
0.5
MEDIAN
0
-0.5
MIN
-1.5
-1
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 23. INPUT OFFSET CURRENT vs TEMPERATURE
VS = ±2.5V
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 24. INPUT OFFSET CURRENT vs TEMPERATURE
VS = ±1.2V
300
400
n = 12
n = 12
200
MAX
VOS (µV)
200
0
MEDIAN
-100
MEDIAN
100
0
-200
-100
-300
-200
-400
-300
MIN
MIN
-500
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
-400
-40
120
FIGURE 25. INPUT OFFSET VOLTAGE vs TEMPERATURE
VS = ±2.5V
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 26. INPUT OFFSET VOLTAGE vs TEMPERATURE\
VS = ±1.2V
130
140
n = 12
125
MAX
300
100
n = 12
MAX
130
MAX
PSRR (dB)
120
CMRR (dB)
MAX
2
1.5
VOS (µV)
n = 12
MAX
115
110
MEDIAN
105
120
110
100
MEDIAN
100
MIN
95
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 27. CMRR vs TEMPERATURE VCM = +2.5V TO -2.5V
8
MIN
90
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 28. PSRR vs TEMPERATURE VS = ±2.5V
FN6312.0
September 22, 2006
ISL28286, ISL28486
Typical Performance Curves
(Continued)
4.91
200
n = 12
n = 12
MAX
4.9
180
MAX
160
VOUT (mV)
VOUT (V)
4.89
4.88
4.87 MEDIAN
4.86
MEDIAN
140
120
MIN
MIN
100
4.85
4.84
-40
80
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 29. POSITIVE VOUT vs TEMPERATURE RL = 1k
VS = ±2.5V
4.9985
6
MAX
n = 12
5.5
MAX
5
VOUT (mV)
4.9975
VOUT (V)
FIGURE 30. NEGATIVE VOUT vs TEMPERATURE RL = 1k
VS = ±2.5V
n = 12
4.998
120
MEDIAN
4.997
MIN
4.9965
4.5
MEDIAN
4
3.5
4.996
4.9955
-40
2.5
-20
0
20
40
60
80
TEMPERATURE (°C)
100
-40
120
FIGURE 31. POSITIVE VOUT vs TEMPERATURE RL = 100k
VS = ±2.5V
0.032
MIN
3
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 32. NEGATIVE VOUT vs TEMPERATURE RL = 100k
VS = ±2.5V
0.95
n = 12
n = 12
MAX
0.9
0.031
IIL (µA)
IIH (µA)
0.85
0.03
MAX
0.029
0.028
MEDIAN
0.75
MIN
0.7
MIN
MEDIAN
0.027
0.026
-40
0.8
0.65
0.6
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 33. IIL (EN) vs TEMPERATURE VS = ±2.5V
9
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 34. IIH (EN) vs TEMPERATURE VS = ±2.5V
FN6312.0
September 22, 2006
ISL28286, ISL28486
Typical Performance Curves
(Continued)
0.23
0.17
n = 12
n = 12
MAX
0.19
0.17
MEDIAN
0.15
0.13
0.15
0.14
MEDIAN
0.13
0.12
MIN
0.11
MIN
0.11
0.09
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
0.1
120
FIGURE 35. + SLEW RATE vs TEMPERATURE VS = ±2.5V
INPUT = ±0.75V AV = 2
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
750
n = 12
n = 12
120
MAX
MAX
700
100
FIGURE 36. - SLEW RATE vs TEMPERATURE VS = ±2.5V
INPUT = ±0.75V AV = 2
800
600
AVOL (V/mV)
600
AVOL (V/mV)
MAX
0.16
CURRENT (pA)
SLEW RATE (V/µs)
0.21
500
MEDIAN
400
300
MIN
MEDIAN
450
MIN
300
200
100
150
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 37. AVOL CH A vs TEMPERATURE RL = 100K
VO = ±2V VS = ±2.5V
-40
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 38. AVOL CH B vs TEMPERATURE RL = 100K
VO = ±2V VS = ±2.5V
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.4
1.2
1.2
POWER DISSIPATION (W)
POWER DISSIPATION (W)
-20
893mW
1
QS
OP
θ
JA
16
=1
12
°C
/W
0.8
0.6
0.4
0.2
0
1
0.8
633mW
0.6
θJ
0.4
QS
O
A =1
58
P1
°C
6
/W
0.2
0
0
25
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 39. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
10
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 40. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN6312.0
September 22, 2006
ISL28286, ISL28486
Typical Performance Curves
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
0.9
0.8 870mW
θ
0.7
M
JA
=
0.6
0.5
0.6
POWER DISSIPATION (W)
POWER DISSIPATION (W)
1
(Continued)
SO
P
11 8/10
5°
C/
W
0.4
0.3
0.2
0.1
JEDEC JESD51-3 LOW EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
0.5
486mW
0.4
θ
M
JA
=
0.3
SO
P
20 8/10
6°
C/
W
0.2
0.1
0
0
0
25
50
75 85
100
0
125
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 42. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 41. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Pin Descriptions
ISL28286
ISL28486
(10 LD MSOP) (16 LD QSOP)
1
3
2
3
13
4
PIN NAME
EQUIVALENT
CIRCUIT
IN+_A
Circuit 1
Amplifier A non-inverting input
EN_A
Circuit 2
Amplifier A enable pin internal pull-down; Logic “1” selects the disabled state;
Logic “0” selects the enabled state.
V-
Circuit 4
Negative power supply
EN_B
Circuit 2
Amplifier B enable pin with internal pull-down; Logic “1” selects the disabled state;
Logic “0” selects the enabled state.
DESCRIPTION
5
5
IN+_B
Circuit 1
Amplifier B non-inverting input
6
6
IN-_B
Circuit 1
Amplifier B inverting input
7
7
OUT_B
Circuit 3
Amplifier B output
8
4
V+
Circuit 4
Positive power supply
9
1
OUT_A
Circuit 3
Amplifier A output
10
2
IN-_A
Circuit 1
Amplifier A inverting input
10
OUT_C
Circuit 3
Amplifier C output
11
IN-_C
Circuit 1
Amplifier C inverting input
12
IN+_C
Circuit 1
Amplifier C non-inverting input
14
IN+_D
Circuit 1
Amplifier D non-inverting input
15
IN-_D
Circuit 1
Amplifier D inverting input
16
OUT_D
Circuit 3
Amplifier D output
8, 9
NC
-
V+
V+
IN-
IN+
V+
LOGIC
PIN
CAPACITIVELY
COUPLED
ESD CLAMP
V-
VCIRCUIT 2
11
V+
OUT
V-
CIRCUIT 1
No internal connection
VCIRCUIT 3
CIRCUIT 4
FN6312.0
September 22, 2006
ISL28286, ISL28486
Applications Information
Introduction
The ISL28286 and ISL28486 are enhanced rail-to-rail input
micropower precision operational amplifiers with an enable
feature. The part is designed to operate from single supply
(2.4V to 5.0V) or dual supply (±1.2V to ±2.5V). The device is
capable of swinging 10% above the positive supply rail and
to ground. The parts maintains CMRR performance for input
voltages equal to the positive supply. The output operation
can swing within about 4mV of the supply rails with a 100kΩ
load (reference Figures 29 through 32).
Rail-to-Rail Input
The input common-mode voltage range of both parts goes
from 10mV above the negative supply to the positive supply
without introducing additional offset errors or degrading
performance associated with a conventional rail-to-rail input
operational amplifier. Many rail-to-rail input stages use two
differential input pairs, a long-tail PNP (or PFET) and an
NPN (or NFET). Severe penalties have to be paid for this
circuit topology. As the input signal moves from one supply
rail to another, the operational amplifier switches from one
input pair to the other causing drastic changes in input offset
voltage and an undesired change in magnitude and polarity
of input offset current.
The ISL28286 and ISL28486 achieves input rail-to-rail
without sacrificing important precision specifications and
degrading distortion performance. The devices’ input offset
voltage exhibits a smooth behavior throughout the entire
common-mode input range. The input bias current versus
the common-mode voltage range gives us an undistorted
behavior from the negative rail and 10% higher than the V+
rail (0.5V higher than V+ when V+ equals 5V).
Input Protection
All input terminals have internal ESD protection diodes to
both positive and negative supply rails, limiting the input
voltage to within one diode beyond the supply rails. Both
parts have additional back-to-back diodes across the input
terminals. If overdriving the inputs is necessary, the external
input current must never exceed 5mA. External series
resistors may be used as an external protection to limit
excessive external voltage and current from damaging the
inputs.
Input Bias Current Compensation
The input bias currents are decimated down to a typical of
500pA while maintaining an excellent bandwidth for a micropower operational amplifier. Inside the ISL28286 and
ISL28478 is an input bias canceling circuit. The input stage
transistors are still biased with an adequate current for
speed but the canceling circuit sinks most of the base
current, leaving a small fraction as input bias current.
12
Rail-to-Rail Output
A pair of complementary MOSFET devices are used to
achieve the rail-to-rail output swing. The NMOS sinks
current to swing the output in the negative direction. The
PMOS sources current to swing the output in the positive
direction. Both parts with a 100kΩ load will swing to within
4mV of the supply rails.
Enable/Disable Feature
The ISL28286 and ISL28486 offer an EN pin that disables
the device when pulled up to at least 2.0V. In the disabled
state (output in a high impedance state), the part consumes
typically 4µA. By disabling the part, multiple parts can be
connected together as a MUX. The outputs are tied together
in parallel and a channel can be selected by the EN pin. The
EN pin also has an internal pull down. If left open, the EN pin
will pull to the negative rail and the device will be enabled by
default.
Using Only One Channel
The ISL28286 and ISL28486 are Dual and Quad channel
op-amps. If the application only requires one channel when
using the ISL28286 or less than 4 channels when using the
ISL28486, the user must configure the unused channel (s) to
prevent them from oscillating. The unused channel (s) will
oscillate if the input and output pins are floating. This will
result in higher than expected supply currents and possible
noise injection into the channel being used. The proper way
to prevent this oscillation is to short the output to the
negative input and ground the positive input (as shown in
Figure 43).
+
1/2 ISL28286
1/4 ISL28486
FIGURE 43. PREVENTING OSCILLATIONS IN UNUSED
CHANNELS
Proper Layout Maximizes Performance
To achieve the maximum performance of the high input
impedance and low offset voltage of the ISL28286 and
ISL28486, care should be taken in the circuit board layout.
The PC board surface must remain clean and free of
moisture to avoid leakage currents between adjacent traces.
Surface coating of the circuit board will reduce surface
moisture and provide a humidity barrier, reducing parasitic
resistance on the board. When input leakage current is a
concern, the use of guard rings around the amplifier inputs
will further reduce leakage currents. Figure 44 shows a
guard ring example for a unity gain amplifier that uses the
low impedance amplifier output at the same voltage as the
high impedance input to eliminate surface leakage. The
guard ring does not need to be a specific width, but it should
form a continuous loop around both inputs. For further
reduction of leakage currents, components can be mounted
FN6312.0
September 22, 2006
ISL28286, ISL28486
Current Limiting
to the PC board using Teflon standoff insulators.
The ISL28286 and ISL28486 have no internal currentlimiting circuitry. If the output is shorted, it is possible to
exceed the Absolute Maximum Rating for output current or
power dissipation, potentially resulting in the destruction of
the device.
V+
HIGH IMPEDANCE INPUT
1/2 ISL28286
IN
Power Dissipation
FIGURE 44. GUARD RING EXAMPLE FOR UNITY GAIN
AMPLIFIER
Example Application
Thermocouples are the most popular temperature-sensing
device because of their low cost, interchangeability, and
ability to measure a wide range of temperatures. The
ISL28286 (Figure 45) is used to convert the differential
thermocouple voltage into single-ended signal with 10X gain.
The ISL28286's rail-to-rail input characteristic allows the
thermocouple to be biased at ground and the converter to
run from a single 5V supply.
R2
K TYPE
THERMOCOUPLE
10kΩ
(EQ. 1)
where:
• PDMAXTOTAL is the sum of the maximum power
dissipation of each amplifier in the package (PDMAX)
V OUTMAX
PD MAX = 2*V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------R
(EQ. 2)
100kΩ
10kΩ
T JMAX = T MAX + ( θ JA xPD MAXTOTAL )
• PDMAX for each amplifier can be calculated as follows:
R4
R3
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power-supply
conditions. It is therefore important to calculate the
maximum junction temperature (TJMAX) for all applications
to determine if power supply voltages, load conditions, or
package type need to be modified to remain in the safe
operating area. These parameters are related as follows:
V+
+
ISL28286
V-
L
410µV/°C
+
5V
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
R1
100kΩ
FIGURE 45. THERMOCOUPLE AMPLIFIER
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Supply voltage
• IMAX = Maximum supply current of 1 amplifier
• VOUTMAX = Maximum output voltage swing of the
application
• RL = Load resistance
13
FN6312.0
September 22, 2006
ISL28286, ISL28486
Mini SO Package Family (MSOP)
0.25 M C A B
D
MINI SO PACKAGE FAMILY
(N/2)+1
N
E
MDP0043
A
E1
PIN #1
I.D.
1
B
(N/2)
e
H
C
SEATING
PLANE
SYMBOL
MSOP8
MSOP10
TOLERANCE
NOTES
A
1.10
1.10
Max.
-
A1
0.10
0.10
±0.05
-
A2
0.86
0.86
±0.09
-
b
0.33
0.23
+0.07/-0.08
-
c
0.18
0.18
±0.05
-
D
3.00
3.00
±0.10
1, 3
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
Rev. C 6/99
0.10 C
N LEADS
0.08 M C A B
b
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
L1
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
A
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
A1
L
0.25
3° ±3°
DETAIL X
14
FN6312.0
September 22, 2006
ISL28286, ISL28486
Quarter Size Outline Plastic Packages Family (QSOP)
MDP0040
A
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
D
(N/2)+1
N
E
SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
PIN #1
I.D. MARK
E1
1
(N/2)
A
0.068
0.068
0.068
Max.
-
A1
0.006
0.006
0.006
±0.002
-
A2
0.056
0.056
0.056
±0.004
-
b
0.010
0.010
0.010
±0.002
-
c
0.008
0.008
0.008
±0.001
-
D
0.193
0.341
0.390
±0.004
1, 3
E
0.236
0.236
0.236
±0.008
-
E1
0.154
0.154
0.154
±0.004
2, 3
e
0.025
0.025
0.025
Basic
-
L
0.025
0.025
0.025
±0.009
-
L1
0.041
0.041
0.041
Basic
-
N
16
24
28
Reference
-
B
0.010
C A B
e
H
C
SEATING
PLANE
0.007
0.004 C
b
C A B
Rev. E 3/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
L1
A
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
c
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SEE DETAIL "X"
0.010
A2
GAUGE
PLANE
L
A1
4°±4°
DETAIL X
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15
FN6312.0
September 22, 2006