eorex EM42AM3284LBC Revision History Revision 0.1 (Mar. 2008) - First release. Revision 0.2 (Jun. 2009).. - Add Extend Temperature Grade (-25°C ~85°C) product. - Add IDD6 “PASR” Spec.(page 8) Jun. 2009 www.eorex.com 1/24 eorex EM42AM3284LBC 512Mb (4M×4Bank×32) Double DATA RATE SDRAM Features Description • Internal Double-Date-Rate architecture with 2 Accesses per clock cycle. • 1.8V ±0.1V VDD/VDDQ • 1.8V LV-COMS compatible I/O • Burst Length (B/L) of 2, 4, 8, 16 • 3 Clock read latency • Bi-directional,intermittent data strobe(DQS) • All inputs except data and DM are sampled at the positive edge of the system clock. • Data Mask (DM) for write data • Sequential & Interleaved Burst type available • Auto Precharge option for each burst accesses • DQS edge-aligned with data for Read cycles • DQS center-aligned with data for Write cycles • No DLL;CK to DQS is not synchronized • Deep power down mode • Partial Array Self-Refresh(PASR) • Auto Temperature Compensated Self-Refresh (TCSR) by built-in temperature sensor • Auto Refresh and Self Refresh • 8,192 Refresh Cycles / 64ms The EM42AM3284LBC is high speed Synchronous graphic RAM fabricated with ultra high performance CMOS process containing 536,870,912 bits which organized as 4Meg words x 4 banks by 32 bits. The 512Mb DDR SDRAM uses a double data rate architecture to accomplish high-speed operation. The data path internally prefetches multiple bits and It transfers the datafor both rising and falling edges of the system clock.It means the doubled data bandwidth can be achieved at the I/O pins. Available packages:TFBGA-90B(13mmx10mm). Ordering Information Part No Organization Max. Freq Package Grade Pb EM42AM3284LBC-75F 16M X 32 133MHz/DDR266 @CL3 TFBGA-90B Commercial Free EM42AM3284LBC-6F 16M X 32 166MHz/DDR333 @CL3 TFBGA-90B Commercial Free EM42AM3284LBC-75FE 16M X 32 133MHz/DDR266 @CL3 TFBGA-90B Extend temp. Free EM42AM3284LBC-6FE 16M X 32 166MHz/DDR333 @CL3 TFBGA-90B Extend temp. Free Jun. 2009 www.eorex.com 2/24 eorex EM42AM3284LBC * EOREX reserves the right to change products or specification without notice. Jun. 2009 www.eorex.com 3/24 eorex EM42AM3284LBC Pin Assignment 1 2 3 7 8 9 VSS DQ31 VSSQ A VDDQ DQ16 VDD VDDQ DQ29 DQ30 B DQ17 DQ18 VSSQ VSSQ DQ27 DQ28 C DQ19 DQ20 VDDQ VDDQ DQ25 DQ26 D DQ21 DQ22 VSSQ VSSQ DQS3 DQ24 E DQ23 DQS2 VDDQ VDD DM3 NC F NC DM2 VSS CKE CLK /CLK G /WE /CAS /RAS A9 A11 A12 H /CS BA0 BA1 A6 A7 A8 J A10 A0 A1 A4 DM1 A5 K A2 DM0 A3 VSSQ DQS1 DQ8 L DQ7 DQS0 VDDQ VDDQ DQ9 DQ10 M DQ5 DQ6 VSSQ VSSQ DQ11 DQ12 N DQ3 DQ4 VDDQ VDDQ DQ13 DQ14 P DQ1 DQ2 VSSQ VSS DQ15 VSSQ R VDDQ DQ0 VDD 90ball TFBGA / (13mm x 10mm x 1.2mm) Jun. 2009 www.eorex.com 4/24 eorex EM42AM3284LBC Pin Description (Simplified) Pin Name G2,G3 CLK,/CLK H7 /CS G1 CKE J8,J9,K7,K9,K1, K3,J1~J3,H1~H3, A0~12 H8,H9 BA0, BA1 G9 /RAS G8 /CAS G7 /WE L8,L2,E8,E2 DQS0~3 K8,K2,F8,F2 DM0~3 R8,P7,P8,N7,N8,M7, M8,L7,L3,M2,M3,N2, N3,P2,P3,R2,A8,B7, B8,C7,C8,D7,D8,E7, E3,D2,D3,C2,C3,B2, B3,A2 A9,F1,R9/ A1,F9,R1 A7,B1,C9,D1,E9,L9, M1,N9,P1,R7/A3,B9, C1,D9,E1,L1,M9,N1, P9,R3 F3,F7 Function (System Clock) Clock input active on the Positive rising edge except for DQ and DM are active on both edge of the DQS. CLK and /CLK are differential clock inputs. (Chip Select) /CS enables the command decoder when ”L” and disable the command decoder when “H”.The new command are overLooked when the command decoder is disabled but previous operation will still continue. (Clock Enable) Activates the CLK when “H” and deactivates when “L”. When deactivate the clock,CKE low signifies the power down or self refresh mode. (Address) Row address (A0 to A12) and Calumn address (CA0 to CA8) are multiplexed on the same pin. CA10 defines auto precharge at Calumn address. (Bank Address) Selects which bank is to be active. (Row Address Strobe) Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. (Column Address Strobe) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Write Enable) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Data Input/Output) Data Inputs and Outputs are synchronized with both edge of DQS. (Data Input/Output Mask) DM controls data inputs.DM0 corresponds to the data on DQ0~DQ7.DM1 corresponds to the data on DQ8~DQ15…….. DQ0~31 (Data Input/Output) Data inputs and outputs are multiplexed on the same pin. VDD/VSS (Power Supply/Ground) VDD and VSS are power supply pins for internal circuits. VDDQ/VSSQ NC/RFU (Power Supply/Ground) VDDQ and VSSQ are power supply pins for the output buffers. (No Connection/Reserved for Future Use) This pin is recommended to be left No Connection on the device. Jun. 2009 www.eorex.com 5/24 eorex EM42AM3284LBC Absolute Maximum Rating Symbol Item Rating Units VIN, VOUT Input, Output Voltage -0.5 ~ +2.3 V VDD, VDDQ Power Supply Voltage -0.5 ~ +2.3 Commercial 0 ~ +70 Extended -25 ~ +85 -55 ~ +125 V °C 1 W TOP Operating Temperature Range TSTG Storage Temperature Range PD Power Dissipation °C IOS Short Circuit Current 50 mA Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (VCC=1.8V ± 0.1V, f=1MHz, TA=25°C) Symbol Parameter Min. CCLK Clock Capacitance Input Capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML, DQMU Input/Output Capacitance CI CO Typ. Max. Units 2.0 4.5 pF 2.0 4.5 pF 3.5 6.0 pF Recommended DC Operating Conditions (TA=0°C ~70°C) Symbol Parameter Min. Typ. Max. Units VDD Power Supply Voltage 1.7 1.8 1.9 V VDDQ Power Supply Voltage (for I/O Buffer) 1.7 1.8 1.9 V 0.8* VDDQ VDDQ+0.3 V -0.3 0.2*VDDQ V VIH Input Logic High Voltage VIL Input Logic Low Voltage Note: * All voltages referred to VSS. Jun. 2009 www.eorex.com 6/24 eorex EM42AM3284LBC Recommended DC Operating Conditions (VDD=1.8V±0.1V, TA=0°C ~ 70°C) Symbol Parameter Test Conditions Max. -75 Units Burst length=2, tRC≥tRC(min.), IOL=0mA, One bank active 80 mA Precharge Standby Current in Power Down Mode CKE≤VIL(max.), tCK=min 1 mA IDD2N Precharge Standby Current in Non-power Down Mode CKE≥VIL(min.), tCK=min, /CS≥VIH(min.) Input signals are changed one time during 2 clks 4 mA IDD3P Active Standby Current in Power Down Mode CKE≤VIL(max.), tCK=min 3 mA IDD3N Active Standby Current in Non-power Down Mode CKE≥VIH(min.), tCK=min, /CS≥VIH(min.) Input signals are changed one time during 2 clks 10 mA IDD4 Operating Current (Burst (Note 2) Mode) tCK ≥ tCK(min.), IOL=0mA, All banks active 120 mA IDD5 Refresh Current tRC≥ tRFC (min.), All banks active 90 mA IDD6 Self Refresh Current CKE≤0.2V 0.8 mA IDD1 Operating Current IDD2P (Note 1) (Note 3) *All voltages referenced to VSS. Note 1: IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 2: IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 3: Min. of tRFC (Auto refresh Row Cycle Times) is shown at AC Characteristics. Jun. 2009 www.eorex.com 7/24 eorex EM42AM3284LBC Advanced Data Retention Current (TJ = –25 to +85°C, VDD and VDDQ = 1.7V to 1.9V, VSS and VSSQ = 0V) Symbol Parameter PASR="000" (Full) IDD6 PASR="001" (2BK) Conditions Max. Units 300 uA 250 uA 220 uA 560 uA 390 uA 300 uA 800 uA 650 uA 500 uA -25°C ≤ TJ ≤ +40°C CKE≤0.2V PASR="010" (1BK) PASR="000" (Full) IDD6 PASR="001" (2BK) +40°C < TJ ≤ +70°C CKE≤0.2V PASR="010" (1BK) PASR="000" (Full) IDD6 PASR="001" (2BK) +70°C < TJ ≤ +85°C CKE≤0.2V PASR="010" (1BK) Recommended DC Operating Conditions (Continued) Symbol Parameter Test Conditions IIL Input Leakage Current IOL Output Leakage Current 0≤VI≤VDDQ, VDDQ=VDD All other pins not under test=0V 0≤VO≤VDDQ, DOUT is disabled VOH High Level Output Voltage IO=-0.1mA VOL Low Level Output Voltage IO=+0.1mA Min. Typ. Max. Units -2 +2 uA -1.5 +1.5 uA 0.9*VDDQ V 0.1*VDDQ Jun. 2009 V www.eorex.com 8/24 eorex EM42AM3284LBC Block Diagram Auto/ Self Refresh Counter A0 A1 DM A5 A6 A7 A8 A9 Address Register A4 Row Decoder A3 Row Add. Buffer A2 Memory Array Write DQM Control Data In DOi S/ A & I/ O Gating A10 A11 Data Out Col. Decoder A12 BA0 BA1 Col. Add. Buffer Mode Register Set Col Add. Counter Burst Counter Timing Register /CLK CLK CKE /CS / RAS / CAS Jun. 2009 /WE DM DQS www.eorex.com 9/24 eorex EM42AM3284LBC AC Operating Test Conditions (VDD=1.8V ± 0.1V, TA=0°C ~70°C) Item Conditions Output Reference Level 0.9V/0.9V Output Load See diagram as below Input Signal Level 1.6V/0.2V Transition Time of Input Signals 0.5ns Input Reference Level 0.9V AC Operating Test Characteristics (VDD=1.8V±0.1V, TA=0°C ~70°C) Symbol Parameter -6 Min. Max. -7.5 Min. Max. Units tDQCK DQ output access from CLK,/CLK 2 5.5 2 6 ns tDQSCK DQS output access from CLK,/CLK 2 5.5 2 6 ns tCL,tCH CL low/high level width 0.45 0.55 0.45 0.55 tCK tCK tDH,tDS tDIPW tHZ,tLZ tDQSQ tDQSS tDSL,tDS Clock Cycle Time ( CL3 ) DQ and DM hold/setup time DQ and DM input pulse width for each input Data out high/low impedance time from CLK,/CLK DQS-DQ skew for associated DQ signal Write command to first latching DQS transition 6 7.5 ns 0.6 0.8 ns 1.2 1.75 ns 1 5.5 1 0.5 0.75 DQS input valid window 1.25 0.75 6 ns 0.6 ns 1.25 tCK 0.2 0.2 tCK 2 2 tCK 0 0 ns H tMRD tWPRES tWPST tIH,tIS tRPRE Mode Register Set command cycle time Write Preamble setup time Write Preamble Address/control input hold/setup time Read Preamble 0.4 0.6 0.4 1.1 0.9 Jun. 2009 0.6 1.3 1.1 0.9 tCK ns 1.1 tCK www.eorex.com 10/24 eorex EM42AM3284LBC AC Operating Test Characteristics (Continued) (VDD=1.8V±0.1V, TA=0°C ~70°C) Symbol Parameter -6 -75 Min. 0.4 Max. 0.6 Min. 0.4 Max. 0.6 42 120k 45 120k Units tRPST Read Postamble tRAS Active to Precharge command period tRC Active to Active command period 72 75 ns tRFC Auto Refresh Row Cycle Time 90 108 ns tRCD Active to Read or Write delay 24 30 ns tRP Precharge command period 18 22.5 ns tRRD Active bank A to B command period 12 15 ns tCCD Column address to column address delay 1 1 tCK tCDLW Last data in to Write command 1 1 tCK Last data in to Precharge command 3 3 tCK tBSTW Burst stop to write delay 3 3 tCK tWPD Write to pre-charge delay(same bank) 3+BL/2 3+BL/2 tCK tRPD Read to pre-charge delay(same bank) BL/2 BL/2 tCK tSREX Exit self refresh to non-col. command 20 16 tCK tWTR Internal Write to Read command delay 1 1 tCK tWRD Write recovery 2 2 tCK tCKE CKE minimum pulse width 2 2 tCK tREFI Average periodic refresh interval tDPL 7.8 Jun. 2009 7.8 tCK ns us www.eorex.com 11/24 eorex EM42AM3284LBC Simplified State Diagram Jun. 2009 www.eorex.com 12/24 eorex EM42AM3284LBC 1. Command Truth Table Command Symbol CKE n-1 n H X /CS /RAS /CAS /WE BA0, BA1 A10 A12~A0 H X X X X X X Ignore Command DESL No Operation NOP H X L H H H X X X Burst Stop BSTH H X L H H L X X X Read READ H X L H L H V L V READA H X L H L H V H V Write WRIT H X L H L L V L V Write with Auto Pre-charge WRITA H X L L H H V H V Read with Auto Pre-charge Bank Activate ACT H X L L H H V V V Pre-charge Select Bank PRE H X L L H L V L X Pre-charge All Banks PALL H X L L H L X H X L V Mode Register Set MRS H X L L L L L H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 2. CKE Truth Table Item Command Symbol Idle CBR Refresh Command REF Idle Self Refresh Entry SELF Self Refresh Self Refresh Exit Idle Power Down Entry CKE n-1 n H H /CS /RAS /CAS /WE Addr. L L L H X H L L L L L H X H L H H H X L H H X X X X H L X X X X X X X X X Power Down Power Down Exit L H X Remark H = High level, L = Low level, X = High or Low level (Don't care) Jun. 2009 www.eorex.com 13/24 eorex EM42AM3284LBC 3. Operative Command Table Current State Idle Row Active /CS /R /C /W Addr. Command H X X X X DESL NOP L H H H X NOP NOP L H H L X TERM NOP L H L X BA/CA/A10 READ/WRIT/BW ILLEGAL (Note 1) Bank active,Latch RA L L H H BA/RA ACT L L H L BA, A10 PRE/PREA L L L H REFA L L L L MRS Mode register H L X H X H X H X Op-Code, Mode-Add X X NOP (Note 4) Auto refresh DESL NOP L H H L BA/CA/A10 READ/READA L H L L BA/CA/A10 WRIT/WRITA NOP NOP Begin read,Latch CA, Determine auto-precharge Begin write,Latch CA, Determine auto-precharge L L H H BA/RA ACT L L H L BA/A10 PRE/PREA L L L H REFA ILLEGAL L L L L MRS ILLEGAL H L L X H H X H H X H L X Op-Code, Mode-Add X X X DESL NOP TERM L H L H BA/CA/A10 READ/READA L L H H BA/RA ACT L L L L H L L H PRE/PREA REFA L L L L H L L X H H X H H X H L BA, A10 X Op-Code, Mode-Add X X X L H L H BA/CA/A10 READ/READA Read Write Action MRS DESL NOP TERM L H L L BA/CA/A10 WRIT/WRITA L L H H BA/RA ACT L L H L BA, A10 PRE/PREA L L L L L L H L X Op-Code, REFA MRS Jun. 2009 (Note 3) (Note 1) ILLEGAL Precharge/Precharge all NOP(Continue burst to end) NOP(Continue burst to end) Terminal burst Terminate burst,Latch CA, Begin new read, Determine Auto-precharge ILLEGAL (Note 1) Terminate burst, PrecharE ILLEGAL ILLEGAL NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL Terminate burst with DM=”H”,Latch CA,Begin read,Determine (Note 2) auto-precharge Terminate burst,Latch CA,Begin new write, Determine (Note 2) auto-precharge ILLEGAL (Note 1) Terminate burst with DM=”H”, Precharge ILLEGAL ILLEGAL www.eorex.com 14/24 eorex EM42AM3284LBC 3. Operative Command Table (Continued) Current State Read with AP Write with AP Pre-charging Row Activating /CS /R /C /W Addr. Command H L L L X H H H X H H L X H L X X X BA/CA/A10 BA/RA DESL NOP TERM READ/WRITE L L H H BA/A10 ACT ILLEGAL L L L L H L L H PRE/PREA REFA ILLEGAL ILLEGAL L L L L MRS ILLEGAL H L L L X H H H X H H L X H L X X X Op-Code, Mode-Add X X X BA/CA/A10 DESL NOP TERM READ/WRITE L L H H BA/RA ACT ILLEGAL L L L L H L L H PRE/PREA REFA ILLEGAL ILLEGAL L L L L MRS ILLEGAL H L L L X H H H X H H L X H L X BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 DESL NOP TERM READ/WRITE L L H H BA/RA ACT L L L L H L L H PRE/PREA REFA L L L L H L L L X H H H X H H L X H L X BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 DESL NOP TERM READ/WRITE L L H H BA/RA ACT ILLEGAL L L L L H L L H PRE/PREA REFA ILLEGAL ILLEGAL L L L L BA/A10 X Op-Code, Mode-Add MRS ILLEGAL MRS Action NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL (Note 1) ILLEGAL (Note 1) (Note 1) NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL (Note 1) ILLEGAL (Note 1) (Note 1) NOP(idle after tRP) NOP(idle after tRP) NOP (Note 1) ILLEGAL (Note 1) ILLEGAL (Note 3) NOP(idle after tRP) ILLEGAL ILLEGAL NOP(Row active after tRCD) NOP(Row active after tRCD) NOP (Note 1) ILLEGAL (Note 1) (Note 1) Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Jun. 2009 www.eorex.com 15/24 eorex EM42AM3284LBC 3. Operative Command Table (Continued) Current State Write Recovering Refreshing /CS /R /C /W Addr. Command H L L L X H H H X H H L X H L H X X X BA/CA/A10 DESL NOP TERM READ L H L L BA/CA/A10 WRIT/WRITA L L H H BA/RA ACT ILLEGAL L L L L H L L H PRE/PREA REFA ILLEGAL ILLEGAL L L L L MRS ILLEGAL H L L L L L L X H H H L L L X H H L H H L X H L X H L H L L L L BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add DESL NOP TERM READ/WRIT ACT PRE/PREA REFA MRS Action NOP NOP NOP (Note 1) ILLEGAL New write, Determine AP (Note 1) (Note 1) NOP(idle after tRP) NOP(idle after tRP) NOP ILLEGAL ILLEGAL NOP(idle after tRP) ILLEGAL ILLEGAL Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Note 1: ILLEGAL to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. Note 2: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Note 3: NOP to bank precharging or in idle state.May precharge bank indicated by BA. Note 4: ILLEGAL of any bank is not idle. Jun. 2009 www.eorex.com 16/24 eorex EM42AM3284LBC 4. Command Truth Table for CKE Current State Self Refresh Both bank precharge power down All Banks Idle Any State Other than Listed above CKE n-1 n /CS /R /C /W Addr. Action INVALID Exist Self-Refresh Exist Self-Refresh ILLEGAL ILLEGAL ILLEGAL NOP(Maintain self refresh) INVALID Exist Power down Exist Power down ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Power down) Refer to function true table (Note 3) Enter power down mode (Note 3) Enter power down mode ILLEGAL ILLEGAL Row active/Bank active (Note 3) Enter self-refresh Mode register access Special mode register access H L L L L L L H L L L L L L H H X H H H H H L X H H H H H L H L X H L L L L X X H L L L L X X H X X H H H L X X X H H H L X X X X X H H L X X X X H H L X X X X X X H L X X X X X H L X X X X X X X X X X X X X X X X X X X X X H H H H H H H L L L L L L L L L L L L L L H H H L L L L H H L H L L L H L X H H L L X X X RA X Op-Code Op-Code L X X X X X X Refer to current state H H X X X X X Refer to command truth table Remark: H = High level, L = Low level, X = High or Low level (Don't care) Notes 1: After CKE’s low to high transition to exist self refresh mode.And a time of tRC(min) has to be Elapse after CKE’s low to high transition to issue a new command. Notes 2:CKE low to high transition is asynchronous as if restarts internal clock. Notes 3:Power down and self refresh can be entered only from the idle state of all banks. Jun. 2009 www.eorex.com 17/24 eorex EM42AM3284LBC Mode Register Definition Mode Register Set The mode register stores the data for controlling the various operating modes of DDR SDRAM which contains addressing mode, burst length, /CAS latency, test mode, DLL reset and various vendor＇s specific opinions. The defaults values of the register is not defined, so the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE and BA0 ( The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register. ) The state of the address pins A0-A12 in the same cycle as /CS, /RAS, /CAS, /WE and BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operating as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0-A2, addressing mode uses A3, /CAS latency ( read latency from column address ) uses A4-A6. A7 is used for test mode. A8 is used for DDR reset. A7 must be set to low for normal MRS operation. Jun. 2009 www.eorex.com 18/24 eorex EM42AM3284LBC Address input for Mode Register Set Jun. 2009 www.eorex.com 19/24 eorex EM42AM3284LBC Burst Type (A3) Burst Length 2 4 8 16 A3 A2 A1 A0 Sequential Addressing Interleave Addressing X X X 0 01 01 X X X 1 10 10 X X 0 0 0123 0123 X X 0 1 1230 1032 X X 1 0 2301 2301 X X 1 1 3012 3210 X 0 0 0 01234567 01234567 X 0 0 1 12345670 10325476 X 0 1 0 23456701 23016745 X 0 1 1 34567012 32107654 X 1 0 0 45670123 45670123 X 1 0 1 56701234 54761032 X 1 1 0 67012345 67452301 X 1 1 1 70123456 76543210 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 0 3 2 5 4 7 6 9 8 11 10 13 12 15 14 0 0 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 0 1 6 7 4 5 10 11 8 9 14 15 12 13 0 0 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12 0 1 0 0 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 0 1 2 3 12 13 14 15 8 9 10 11 0 1 0 1 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 4 7 6 1 0 3 2 13 12 15 14 9 8 11 10 0 1 1 0 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 4 5 2 3 0 1 14 15 12 13 10 11 8 9 0 1 1 1 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 1 0 0 0 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 1 0 0 1 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 8 11 10 13 12 15 14 1 0 3 2 5 4 7 6 1 0 1 0 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 8 9 14 15 12 13 2 3 0 1 6 7 4 5 1 0 1 1 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 10 9 8 15 14 13 12 3 2 1 0 7 6 5 4 1 1 0 0 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 8 9 10 11 4 5 6 7 0 1 2 3 1 1 0 1 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 12 15 14 9 8 11 10 5 4 7 6 1 0 3 2 1 1 1 0 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 12 13 10 11 8 9 6 7 4 5 2 3 0 1 1 1 1 1 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * Page length is a function of I/O organization and column addressing Jun. 2009 www.eorex.com 20/24 eorex EM42AM3284LBC Extended Mode Register Set ( EMRS ) The Extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA1 ( The DDR SDRAM should be in all bank precharge with CKE already prior to writing into the extended mode register. ) The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE going low is written in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. High on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. Jun. 2009 www.eorex.com 21/24 eorex EM42AM3284LBC Output Drive Strength The normal drive strength got all outputs is specified to be LV-CMOS. By setting EMRS specific parameter on A6 and A5, driving capability of data output drivers is selected. Temperature Compensated Self-Refresh TCSR controlled by programming in the extended mode register (EMRS). The memory automatically changes the self-refresh cycle by temperature fluctuations. Partial Array Self Refresh In EMRS setting ,memory array size to be refreshed during self-refresh operation is programmable in order to reduce power. Data outside the defined area will not be retained during self-refresh. Jun. 2009 www.eorex.com 22/24 eorex EM42AM3284LBC Package Description Jun. 2009 www.eorex.com 23/24 eorex EM42AM3284LBC Jun. 2009 www.eorex.com 24/24