FUJITSU SEMICONDUCTOR DATA SHEET DS05-11422-3E MEMORY Mobile FCRAMTM CMOS 32M Bit (2 M word × 16 bit) Mobile Phone Application Specific Memory MB82DP02183C-65L CMOS 2,097,152-WORD x 16 BIT Fast Cycle Random Access Memory with Low Power SRAM Interface ■ DESCRIPTION The Fujitsu MB82DP02183C is a CMOS Fast Cycle Random Access Memory (FCRAM*) with asynchronous Static Random Access Memory (SRAM) interface containing 33,554,432 storages accessible in a 16-bit format. MB82DP02183C is utilized using a FUJITSU advanced FCRAM core technology and improved integration in comparison to regular SRAM. This MB82DP02183C is suited for mobile applications such as Cellular Handset and PDA. *: FCRAM is a trademark of Fujitsu Limited, Japan ■ FEATURES • • • • • • • Asynchronous SRAM Interface Fast Access Cycle Time : tAA = tCE = 65 ns Max 8 words Page Access Capability : tPAA = 20 ns Max Low Voltage Operating Condition : VDD = +2.6 V to +3.5 V Wide Operating Temperature : TA = -30 °C to +85 °C Byte Control by LB and UB Low Power Consumption : IDDA1 = 30 mA Max IDDS1 = 80 µA Max • Various Power Down mode : Sleep 4M-bit Partial 8M-bit Partial • Shipping Form : Wafer/Chip, 71-ball plastic FBGA package Copyright© 2004-2006 FUJITSU LIMITED All rights reserved MB82DP02183C-65L ■ PIN ASSIGNMENT (TOP VIEW) A B 8 NC NC 7 NC NC D E F G H J A15 NC NC A16 NC VSS A11 A12 A13 A14 NC DQ16 DQ8 DQ15 6 A8 A19 A9 A10 DQ7 DQ14 DQ13 DQ6 5 WE CE2 A20 DQ5 VDD NC 4 DU DU DU DQ4 VDD DQ12 3 LB UB A18 A17 DQ2 DQ10 DQ11 DQ3 A7 A6 A5 A4 VSS OE DQ1 A3 A2 A1 A0 NC CE1 2 NC 1 NC NC C (BGA-71P-M03) 2 K DQ9 L M NC NC NC NC NC NC NC NC MB82DP02183C-65L ■ PIN DESCRIPTION Pin Name A20 to A0 Description Address Input CE1 Chip Enable 1 (Low Active) CE2 Chip Enable 2 (High Active) WE Write Enable (Low Active) OE Output Enable (Low Active) LB Lower Byte Control (Low Active) UB Upper Byte Control (Low Active) DQ8 to DQ1 Lower Byte Data Input/Output DQ16 to DQ9 Upper Byte Data Input/Output VDD Power Supply VSS Ground NC No Connection DU Don’t Use 3 MB82DP02183C-65L ■ BLOCK DIAGRAM VDD VSS A20 to A0 DQ8 to DQ1 Address Latch & Buffer I/O Data Buffer DQ16 to DQ9 Row Decoder Memory Cell Array 33,554,432 bit Input Data Latch & Control Sense/Switch Column Decoder Address Latch & Buffer CE2 CE1 WE LB UB OE 4 Power Control Timing Control Output Data Control MB82DP02183C-65L ■ FUNCTION TRUTH TABLE CE2 CE1 WE OE LB UB A20 to A0 DQ8 to DQ1 DQ16 to DQ9 H H X X X X X High-Z High-Z H H X X *3 High-Z High-Z Output Disable (No Read) H H Valid High-Z High-Z Read (Upper Byte) H L Valid High-Z Output Valid L H Valid Output Valid High-Z L L Valid Output Valid Output Valid H H Valid Invalid Invalid H L Valid Invalid Input Valid Write (Lower Byte) L H Valid Input Valid Invalid Write (Word) L L Valid Input Valid Input Valid X X X Mode Standby (Deselect) Output Disable*1 H L Read (Lower Byte) Read (Word) H L No Write Write (Upper Byte) L Power Down*2 L X X H* X 4 High-Z High-Z Notes : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance *1 : Should not be kept this logic condition longer than 1 µs. *2 : Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the selection of Power Down Program. Refer to “■ Power Down” for the detail. *3 : Can be either VIL or VIH but must be valid before Read or Write. *4 : OE can be VIL during Write operation if the following conditions are satisfied; (1) Write pulse is initiated by CE1. See “(12) READ/WRITE Timing #1-1 (CE1 Control)” in “■ TIMING DIAGRAMS”. (2) OE stays VIL during Write cycle. 5 MB82DP02183C-65L ■ POWER DOWN Power Down The Power Down is low power idle state controlled by CE2. CE2 Low drives the device in power down mode and maintains low power idle state as long as CE2 is kept Low. CE2 High resumes the device from power down mode. This device has 3 power down modes, Sleep, 4M-bit Partial and 8M-bit Partial. These can be programmed by series of read/write operation. Each mode has following features. Mode Data Retention Retention Address Sleep (default) No N/A 4M-bit Partial 4M bits 00000h to 3FFFFh 8M-bit Partial 8M bits 00000h to 7FFFFh The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2 is brought to Low for Power Down. It is not required to program to Sleep mode after power-up. Power Down Program Sequence The program requires total six read/write operations with unique address. Between each read/write operation requires that device be in standby mode. Following table shows the detail sequence. Cycle # Operation Address Data 1st Read 1FFFFFh (MSB) Read Data (RDa) 2nd Write 1FFFFFh RDa 3rd Write 1FFFFFh RDa 4th Write 1FFFFFh Don’t care (X) 5th Write 1FFFFFh X 6th Read Address Key Read Data (RDb) The first cycle is to read from most significant address (MSB). The second and third cycle are to write back the data (RDa) read by first cycle. If the second or third cycle is written into the different address, the program is cancelled and the data written by the second or third cycle is valid as a normal write operation. The forth and fifth cycle is to write to MSB. The data of forth and fifth cycle are don’t-care. If the forth or fifth cycle is written into different address, the program is also cancelled but write data may not be written as normal write operation. The last cycle is to read from specific address key for power down mode selection. Once this program sequence is performed from a Partial mode to other Partial mode, the write data stored in memory cell array may be lost. So, it should perform this program prior to regular read/write operation if Partial power down mode is used. Address Key The address key has following format. Mode 6 Address A20 A19 A18 to A0 Hexadecimal Sleep (default) 1 1 1 1FFFFFh 4M-bit Partial 1 0 1 17FFFFh 8M-bit Partial 0 1 1 0FFFFFh MB82DP02183C-65L ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Min Max VDD − 0.5 + 3.6 V VIN, VOUT − 0.5 + 3.6 V Short Circuit Output Current IOUT − 50 + 50 mA Storage Temperature TSTG − 55 + 125 Voltage of VDD Supply Relative to VSS Voltage at Any Pin Relative to VSS o C WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Min Max VDD (31) 3.1 3.5 V VDD (26) 2.6 3.1 V VSS 0 0 V VIH (31) VDD × 0.8 VDD + 0.2 ( ≤ 3.6) V VIH (26) VDD × 0.8 VDD + 0.2 V Low Level Input Voltage *1, *4 VIL − 0.3 VDD × 0.2 V Ambient Temperature TA − 30 + 85 °C Supply Voltage*1, *2 High Level Input Voltage *1, *2, *3 *1 : All voltages are referenced to VSS. *2 : This device supports both VDD(31) and VDD(26) voltage ranges on identical device. VDD range is divided into two ranges as VDD(31) and VDD(26) on the table due to VIH varied according to VDD supply voltage. *3 : Maximum DC voltage on input and I/O pins are VDD + 0.2 V. During voltage transitions, inputs may overshoot to VDD + 1.0 V for periods of up to 5 ns. *4 : Minimum DC voltage on input or I/O pins are -0.3 V. During voltage transitions, inputs may undershoot VSS to -1.0 V for periods of up to 5 ns. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. ■ PACKGE CAPACITANCE (f = 1 MHz, TA = +25 °C) Parameter Symbol Test conditions Address Input Capacitance CIN1 Control Input Capacitance Data Input/Output Capacitance Value Unit Min Typ Max VIN = 0 V ⎯ ⎯ 5 pF CIN2 VIN = 0 V ⎯ ⎯ 5 pF CI/O VIO = 0 V ⎯ ⎯ 8 pF 7 MB82DP02183C-65L ■ ELECTRICAL CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) 1. DC CHARACTERISTICS Parameter Symbol Test conditions Value Min Max Unit Input Leakage Current ILI VSS ≤ VIN ≤ VDD −1.0 +1.0 µA Output Leakage Current ILO 0 V ≤ VOUT ≤ VDD, Output Disable −1.0 +1.0 µA Output High Voltage Level VOH VDD = VDD Min, IOH = −0.5 mA 2.4 ⎯ V Output Low Voltage Level VOL IOL = 1 mA ⎯ 0.4 V IDDPS VDD = VDD (26) Max, VIN = VIH or VIL, CE2 ≤ 0.2 V SLEEP ⎯ 10 µA 4M-bit partial ⎯ 40 µA 8M-bit partial ⎯ 50 µA VDD Power Down Current IDDP4 IDDP8 IDDS VDD = VDD (26) Max, VIN = VIH or VIL, CE1 = CE2 = VIH ⎯ 1.5 mA IDDS1 VDD = VDD (26) Max, VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, CE1 = CE2 ≥ VDD − 0.2 V ⎯ 80 µA tRC/tWC = Min ⎯ 30 mA tRC/tWC = 1 µs ⎯ 3 mA ⎯ 10 mA VDD Standby Current IDDA1 VDD Active Current IDDA2 VDD Page Read Current IDDA3 VDD = VDD (26) Max, VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA VDD = VDD (26) Max, VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA, tPRC = Min Notes : • All voltages are referenced to VSS. • IDD depends on the output termination, load conditions, and AC characteristics. • After power on, initialization following POWER-UP timing is required. DC characteristics are guaranteed after the initialization. 8 MB82DP02183C-65L 2. AC CHARACTERISTICS (1) READ OPERATION Parameter Symbol Value Min Max Unit Notes Read Cycle Time tRC 65 1000 ns *1, *2 CE1 Access Time tCE ⎯ 65 ns *3 OE Access Time tOE ⎯ 40 ns *3 Address Access Time tAA ⎯ 65 ns *3, *5 LB, UB Access Time tBA ⎯ 30 ns *3 Page Address Access Time tPAA ⎯ 20 ns *3, *6 Page Read Cycle Time tPRC 20 1000 ns *1, *6, *7 Output Data Hold Time tOH 5 ⎯ ns *3 CE1 Low to Output Low-Z tCLZ 5 ⎯ ns *4 OE Low to Output Low-Z tOLZ 0 ⎯ ns *4 LB, UB Low to Output Low-Z tBLZ 0 ⎯ ns *4 CE1 High to Output High-Z tCHZ ⎯ 20 ns *3 OE High to Output High-Z tOHZ ⎯ 15 ns *3 LB, UB High to Output High-Z tBHZ ⎯ 20 ns *3 Address Setup Time to CE1 Low tASC −5 ⎯ ns Address Setup Time to OE Low tASO 10 ⎯ ns Address Invalid Time tAX ⎯ 10 ns *5, *8 Address Hold Time from CE1 High tCHAH −6 ⎯ ns *9 Address Hold Time from OE High tOHAH −6 ⎯ ns WE High to OE Low Time for Read tWHOL 12 1000 ns tCP 12 ⎯ ns CE1 High Pulse Width *10 *1 : Maximum value is applicable if CE1 is kept at Low without change of address input of A20 to A3. *2 : Address should not be changed within minimum tRC. *3 : The output load 50 pF. *4 : The output load 5 pF. *5 : Applicable to A20 to A3 when CE1 is kept at Low. *6 : Applicable only to A2, A1 and A0 when CE1 is kept at Low for the page address access. *7 : In case Page Read Cycle is continued with keeping CE1 stays Low, CE1 must be brought to High within 4 µs. In other words, Page Read Cycle must be closed within 4 µs. *8 : Applicable when at least two of address inputs among applicable are switched from previous state. *9 : tRC(Min) and tPRC(Min) must be satisfied. *10 : If actual value of tWHOL is shorter than specified minimum values, the actual tAA of following Read may become longer by the amount of subtracting actual value from specified minimum value. 9 MB82DP02183C-65L (2) WRITE OPERATION Parameter Symbol Value Min Max Unit Notes Write Cycle Time tWC 65 1000 ns *1, *2 Address Setup Time tAS 0 ⎯ ns *3 CE1 Write Pulse Width tCW 40 ⎯ ns *3 WE Write Pulse Width tWP 40 ⎯ ns *3 LB, UB Write Pulse Width tBW 40 ⎯ ns *3 LB, UB Byte Mask Setup Time tBS −5 ⎯ ns *4 LB, UB Byte Mask Hold Time tBH −5 ⎯ ns *5 Write Recovery Time tWR 0 ⎯ ns *6 CE1 High Pulse Width tCP 12 ⎯ ns WE High Pulse Width tWHP 12 1000 ns LB, UB High Pulse Width tBHP 12 1000 ns Data Setup Time tDS 12 ⎯ ns Data Hold Time tDH 0 ⎯ ns OE High to CE1 Low Setup Time for Write tOHCL −5 ⎯ ns *7 OE High to Address Setup Time for Write tOES 0 ⎯ ns *8 LB and UB Write Pulse Overlap tBWO 30 ⎯ ns *1 : Maximum value is applicable if CE1 is kept at Low without any address change. *2 : Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWR). *3 : Write pulse is defined from High to Low transition of CE1, WE, LB or UB, whichever occurs last. *4 : Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1 or WE whichever occurs last. *5 : Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1 or WE whichever occurs first. *6 : Write recovery is defined from Low to High transition of CE1, WE, LB or UB, whichever occurs first. *7 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5 ns after CE1 is brought to Low. *8 : If OE is Low after new address input, read cycle is initiated. In other word, OE must be brought to High at the same time or before new address valid. 10 MB82DP02183C-65L (3) POWER DOWN PARAMETERS Parameter Symbol Value Min Max Unit Note CE2 Low Setup Time for Power Down Entry tCSP 10 ⎯ ns CE2 Low Hold Time after Power Down Entry tC2LP 65 ⎯ ns CE1 High Hold Time following CE2 High after Power Down Exit [Sleep mode only] tCHH 300 ⎯ µs *1 CE1 High Hold Time following CE2 High after Power Down Exit [not in Sleep mode] tCHHP 1 ⎯ µs *2 CE1 High Setup Time following CE2 High after Power Down Exit tCHS 0 ⎯ ns *1 *1 : Applicable also to power-up. *2 : Applicable when 4M-bit and 8M-bit Partial mode is programmed. (4) OTHER TIMING PARAMETERS Parameter Symbol Value Min Max Unit CE1 High to OE Invalid Time for Standby Entry tCHOX 10 ⎯ ns CE1 High to WE Invalid Time for Standby Entry tCHWX 10 ⎯ ns CE2 Low Hold Time after Power-up tC2LH 50 ⎯ µs CE1 High Hold Time following CE2 High after Power-up tCHH 300 ⎯ µs tT 1 25 ns Input Transition Time Note *1 *2 *1 : Some data might be written into any address location if tCHWX(Min) is not satisfied. *2 : The Input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns, it may violate AC specification of some timing parameters. (5) AC TEST CONDITIONS Description Symbol Test Setup Value Unit Input High Level VIH ⎯ VDD × 0.8 V Input Low Level VIL ⎯ VDD × 0.2 V VREF ⎯ VDD × 0.5 V tT Between VIL and VIH 5 ns Input Timing Measurement Level Input Transition Time Note • AC MEASUREMENT OUTPUT LOAD CIRCUIT VDD 0.1 µF VSS Device under Test Output 50 pF 11 MB82DP02183C-65L ■ TIMING DIAGRAMS (1) READ Timing #1 (Basic Timing) tRC Address Address Valid tASC tCHAH tCE CE1 tASC tCP tCHZ tOE OE tOHZ tBA LB, UB tBHZ tBLZ tOLZ DQ (Output) tOH tCLZ Valid Data Output Note : This timing diagram assumes CE2 = H and WE = H. 12 MB82DP02183C-65L (2) READ Timing #2 (OE & Address Access) tRC Address tAX Address Valid tRC Address Valid tAA tOHAH tAA CE1 Low tASO tOE OE LB, UB tOHZ tOLZ DQ (Output) tOH Valid Data Output tOH Valid Data Output Note : This timing diagram assumes CE2 = H and WE = H. 13 MB82DP02183C-65L (3) READ Timing #3 (LB , UB Byte Access) tAX tRC Address tAX Address Valid tAA CE1, OE Low tBA tBA LB tBA UB tBHZ tBLZ tBHZ tOH tBLZ tOH DQ8 to DQ1 (Output) Valid Data Output Valid Data Output tBLZ tOH DQ16 to DQ9 (Output) Valid Data Output Note : This timing diagram assumes CE2 = H and WE = H. 14 tBHZ MB82DP02183C-65L (4) READ Timing #4 (Page Address Access after CE1 Control Access) tRC Address Address Valid (A20 to A3) tRC Address Address Valid (A2 to A0) tASC tPRC tPRC Address Valid Address Valid tPAA tPRC Address Valid tPAA tPAA tCHAH CE1 tCE tCHZ OE LB, UB tCLZ tOH tOH tOH tOH DQ (Output) Valid Data Output (Normal Access) Valid Data Output (Page Access) Note : This timing diagram assumes CE2 = H and WE = H. 15 MB82DP02183C-65L (5) READ Timing #5 (Random and Page Address Access) tAX tRC Address tRC Address tPRC Address Valid (A2 to A0) tRC tPRC Address Valid Address Valid tAA CE1 Address Valid Address Valid (A20 to A3) tAX tRC tPAA Address Valid tAA tPAA LOW tASO tOE OE tBA LB, UB tOLZ DQ (Output) tOH tOH tOH tBLZ Valid Data Output (Normal Access) Valid Data Output (Page Access) Notes : • This timing diagram assumes CE2 = H and WE = H. • Either or both LB and UB must be Low when both CE1 and OE are Low. 16 tOH MB82DP02183C-65L (6) WRITE Timing #1 (Basic Timing) tWC Address Address Valid tAS tWR tCW tAS CE1 tCP tAS tWR tWP WE tAS tWHP tAS tWR tBW LB, UB tAS tBHP tOHCL OE tDS tDH DQ (Input) Valid Data Input Note : This timing diagram assumes CE2 = H. 17 MB82DP02183C-65L (7) WRITE Timing #2 (WE Control) tWC tWC Address Valid Address Address Valid tOHAH CE1 Low tAS tWR tWP WE tAS tWR tWP tWHP LB, UB tOES OE tOHZ tDS tDH tDS tDH DQ (Input) Valid Data Input Note : This timing diagram assumes CE2 = H. 18 Valid Data Input MB82DP02183C-65L (8) WRITE Timing #3-1 (WE, LB, UB Byte Write Control) tWC Address CE1 tWC Address Valid Address Valid Low tAS tAS tWP tWP tWHP WE tWR tBH tBS LB tBH tBS tWR UB tDS tDH DQ8 to DQ1 (Input) tDS DQ16 to DQ9 (Input) tDH Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = H and OE = H. 19 MB82DP02183C-65L (9) WRITE Timing #3-2 (WE, LB, UB Byte Write Control) tWC Address CE1 tWC Address Valid Address Valid Low tWR WE tWR tWHP tAS tBW tBS tBH LB tBH tBS tAS tBW UB tDS tDH DQ8 to DQ1 (Input) tDS DQ16 to DQ9 tDH Valid Data Input (Input) Valid Data Input Note : This timing diagram assumes CE2 = H and OE = H. 20 MB82DP02183C-65L (10) WRITE Timing #3-3 (WE, LB, UB Byte Write Control) tWC Address CE1 tWC Address Valid Address Valid Low WE tWHP tAS tWR tBW tBH tBS LB tBS tBH tAS tWR tBW UB tDS tDH DQ8 to DQ1 (Input) tDS DQ16 to DQ9 tDH Valid Data Input (Input) Valid Data Input Note : This timing diagram assumes CE2 = H and OE = H. 21 MB82DP02183C-65L (11) WRITE Timing #3-4 (WE, LB, UB Byte Write Control) tWC Address CE1 tWC Address Valid Address Valid Low WE tAS tBW tAS tWR LB tBW tWR tBHP tBWO tDS tDS tDH tDH DQ8 to DQ1 (Input) Valid Data Input tAS tBW Valid Data Input UB (Input) tDH Valid Data Input Note : This timing diagram assumes CE2 = H and OE = H. 22 tBWO tBW tWR tBHP tDS DQ16 to DQ9 tAS tWR tDS tDH Valid Data Input MB82DP02183C-65L (12) READ / WRITE Timing #1-1 (CE1 Control) tWC Address tRC Write Address tAS tCHAH Read Address tWR tCHAH tASC tCW tCE CE1 tCP tCP WE UB, LB tOHCL OE tCHZ tOH tDS tDH tCLZ tOH DQ Read Data Output Write Data Input Read Data Output Notes : • This timing diagram assumes CE2 = H. • Write address is valid from either CE1 or WE of last falling edge. 23 MB82DP02183C-65L (13) READ / WRITE Timing #1-2 (CE1, WE, OE Control) tWC Address tRC Write Address tAS tCHAH Read Address tWR tASC tCHAH tCE CE1 tCP tCP tWP WE UB, LB tOHCL tOE OE tCHZ tOH tDS tDH tOLZ tOH DQ Read Data Output Write Data Input Read Data Output Notes : • This timing diagram assumes CE2 = H. • OE can be fixed Low during write operation if it is CE1 controlled write at Read-Write-Read sequence. 24 MB82DP02183C-65L (14) READ / WRITE Timing #2 (OE, WE Control) tWC Address tRC Write Address Read Address tAA tOHAH tOHAH CE1 Low tAS tWR tWP WE tOES UB, LB tASO OE tOE tWHOL tOHZ tOH tOHZ tDS tDH tOLZ tOH DQ Read Data Output Write Data Input Read Data Output Notes : • This timing diagram assumes CE2 = H. • CE1 can be tied to Low for WE and OE controlled operation. 25 MB82DP02183C-65L (15) READ / WRITE Timing #3 (OE, WE, LB, UB Control) tWC Address tRC Read Address Write Address tAA tOHAH tOHAH CE1 Low WE tOES tAS tBW tWR tBA UB, LB tASO tBHZ OE tWHOL tBHZ tOH tDS tDH tBLZ tOH DQ Read Data Output Write Data Input Read Data Output Notes : • This timing diagram assumes CE2 = H. • CE1 can be tied to Low for WE and OE controlled operation. (16) POWER-UP Timing #1 CE1 tCHS tC2LH tCHH CE2 VDD Min VDD 0V Note : The tC2LH specifies after VDD reaches specified minimum level. 26 MB82DP02183C-65L (17) POWER-UP Timing #2 CE1 tCHH CE2 VDD Min VDD 0V Note : The tCHH specifies after VDD reaches specified minimum level and applicable both CE1 and CE2. If transition time of VDD (from 0 V to VDD Min) is longer than 50 ms, POWER-UP Timing #1 must be applied. (18) POWER DOWN Entry and Exit Timing CE1 tCHS CE2 tCSP tC2LP tCHH (tCHHP) High-Z DQ Power Down Entry Power Down Mode Power Down Exit Note : This Power Down mode can be also used as a reset timing if “POWER-UP timing” above could not be satisfied and Power Down program was not performed prior to this reset. 27 MB82DP02183C-65L (19) Standby Entry Timing after Read or Write CE1 tCHOX tCHWX OE WE Active (Read) Standby Active (Write) Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. 28 Standby MB82DP02183C-65L (20) POWER DOWN PROGRAM Timing tRC Address tWC MSB*1 MSB*1 tCP tWC tWC tWC MSB*1 MSB*1 MSB*1 tCP tCP tRC tCP Key*2 tCP*3 tCP CE1 OE WE LB, UB DQ*3 RDa RDa RDa Cycle #1 Cycle #2 Cycle #3 X Cycle #4 X Cycle #5 RDb Cycle #6 *1 : The all address inputs must be High from Cycle #1 to #5. *2 : The address key must confirm the format specified in “■ POWER DOWN”. If not, the operation and data are not guaranteed. *3 : After tCP following Cycle #6, the Power Down Program is completed and returned to the normal operation. 29 MB82DP02183C-65L ■ BONDING PAD INFORMATION Please contact local FUJITSU representative for pad layout and pad coordinate information. ■ ORDERING INFORMATION Part Number 30 Shipping Form / Package MB82DP02183C-65LWT Wafer MB82DP02183C-65LPBT 71-ball plastic FBGA (BGA-71P-M03) Remarks MB82DP02183C-65L ■ PACKAGE DIMENSION 71-ball plastic FBGA Ball pitch 0.80 mm Package width × package length 7.00 × 11.00 mm Lead shape Soldering ball Sealing method Plastic mold Ball size ∅0.45 mm Mounting height 1.20 mm Max. Weight 0.14 g (BGA-71P-M03) 71-ball plastic FBGA (BGA-71P-M03) 11.00±0.10(.433±.004) B 0.20(.008) S B 1.09 .043 +0.11 –0.10 +.004 –.004 0.80(.031) REF 0.40(.016) REF (Seated height) 0.80(.031) REF 8 7 6 5 4 3 2 1 A 7.00±0.10 (.276±.004) 0.40(.016) REF 0.10(.004) S 0.39±0.10 (Stand off) (.015±.004) INDEX-MARK AREA S 0.20(.008) S A M L K J H G F E D C B A 71-ø0.45 +0.10 –0.05 71-ø.018 –+.004 .002 ø0.08(.003) M S AB 0.10(.004) S C 2003 FUJITSU LIMITED B71003S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. 31 MB82DP02183C-65L FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. 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