Hynix GMS81C5024 8-bit single chip microcontroller Datasheet

Nov. 1999
Ver 2.2
HYUNDAI
GMS81C50 Series
CONTENTS
1. OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. PIN ASSIGNMENT (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4. PACKAGE DIMENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 28 SOP PIN DIMENSION (DIMENSIONS IN INCH) . . . . . . . . . . . . 7
4.2 28 Skinny DIP PIN DIMENSION (DIMENSIONS IN INCH) . . . . . . . 7
4.3 40 PDIP Pin Dimension (dimension in inch) . . . . . . . . . . . . . . . . . . . 8
4.4 44 PLCC Pin Dimension (dimension in mm) . . . . . . . . . . . . . . . . . . 8
4.5 44 QFP Pin Dimension (dimension in mm) . . . . . . . . . . . . . . . . . . . . 9
5. PIN FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6. PORT STRUCTURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1 R0 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2 R1 Ports (R10, R11, R12, R13, R14) . . . . . . . . . . . . . . . . . . . . . . . 12
6.3 R1 Ports (R15, R16, R17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.4 R2, R3, R4 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.5 REMOUT Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.6 Xin, Xout Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.7 RESET Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.8 TEST Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1 Absolute maximum ratings ( Ta=25 ’C) . . . . . . . . . . . . . . . . . . . . . 16
7.2 Recommended Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.3 DC characteristics (VDD=2.2~4.0, Vss=0, Ta=0~70 ‘C) . . . . . . . . 17
7.4 REMOUT Port Ioh characteristics graph . . . . . . . . . . . . . . . . . . . . 18
7.5 REMOUT port Iol characteristics graph . . . . . . . . . . . . . . . . . . . . . 18
7.6 AC characteristics (VDD=2.2~4.0V, Vss=0V, Ta=0~70’C) . . . . . . . 19
8. MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.4 Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
GMS81C50 Series
9. I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.1 R0 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.2 R1 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.3 R2 Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10. CLOCK GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10.1 Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11. TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.1 Basic Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.2 Timer0, Timer1, Timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12. INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.1 Interrupt priority and sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.2 INTERRUPT CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . 58
12.3 INTERRUPT ACCEPT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
12.4 INTERRUPT PROCESSING SEQUENCE . . . . . . . . . . . . . . . . . . 60
12.5 SOFTWARE INTERRUPT (Interrupt by Break (BRK) Instruction) 61
12.6 MULTIPLE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.7 Key Scan Input Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
13. WATCH DOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.1 Control of WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.2 WDT Interrupt Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
14. STANDBY FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.1 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.2 STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.3 STANDBY MODE RELEASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
14.4 RELEASE OPERATION OF STANDBY MODE . . . . . . . . . . . . . . 72
15. OSCILLATION CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
16. RESET FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
16.1 EXTERNAL RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
16.2 POWER ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
16.3 Low Voltage Detection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
16.4 Low Voltage Indicator Register (LVIR) . . . . . . . . . . . . . . . . . . . . . 79
HYUNDAI
HYUNDAI
GMS81C50 Series
GMS81C50 Series
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
FOR UR (Universal Remocon) & KEYBOARD
1. OVERVIEW
1.1 Description
The GMS81C50 Series is an advanced CMOS 8-bit microcontroller with 16K/24K/32K bytes of ROM. The device is one of
GMS800 family. The LG Semicon GMS81C50 Series is a powerful microcontroller which provides a highly flexible and
cost effective solution to many UR & Keyboard applications. The GMS81C50 Series provides the following standard features: 16K/24K/32K bytes of ROM, 448 bytes of RAM, 8-bit timer/counter, on-chip oscillator and clock circuitry. In addition, the GMS81C50 Series supports power saving modes to reduce power consumption.
1.2 Features
Device Name
ROM Size
GMS81C5016
16K Bytes
GMS81C5024
24K Bytes
GMS81C5032
32K Bytes
• Instruction Cycle Time:
- 1us at 4MHz
RAM Size
Package
448 Bytes
( included
256 bytes
stack memory )
28 SOP
28 Skinny DIP
40 PDIP
44 PLCC
44 QFP
- Watch Dog Timer ............ 6Bit * 1ch
• 8 Interrupt sources
* Nested Interrupt control is available.
- External input: 2
- Keyscan input
- Basic Interval Timer
- Watchdog timer
- Timer : 3
• Programmable I/O pins
28 PIN
40 PIN
44 PIN
INPUT
3
3
3
OUTPUT
2
2
2
I/O
21
33
33
• Power On Reset
• Power saving Operation Modes
- STOP
- SLEEP
• Operating Voltage
- 2.2 ~ 4.0 V @ 4MHz
• Low Voltage Detection Circuit
• Timer
- Timer / Counter
• Watch Dog Timer Auto Start (During 1second
after Power on Reset)
......... 16 Bit * 1 ch
......... 8 Bit * 2 ch
- Basic Interval Timer ...... 8 Bit * 1 ch
1.3 Development Tools
The GMS81C50 Series is supported by a full-featured
1
GMS81C50 Series
HYUNDAI
macro assembler, an in-circuit emulator CHOICE-DrTM.
In Circuit Emulators
CHOICE-Dr. (with EVA81C)
Assembler
LGS Macro Assembler
2
HYUNDAI
GMS81C50 Series
2. BLOCK DIAGRAM
G8MC
R0
Port
R00 ~ R07
R1
Port
R10 ~ R17
R2
Port
R20 ~ R27
R3
Port
R30 ~ R37
Core
Watchdog
Timer
RAM
REMOUT
R17 / T0
R16 / T1
R15 / T2
R14 / EC
Timer
R12 / INT2
R11 / INT1
Interrupt
R00 ~ R07
R10 ~ R17
Key Scan
INT.
Generation
Block
TEST
RESET
XIN
XOUT
Clock Gen.
&
System
Control
(448byte)
ROM
(32 Kbyte)
Prescaler
&
B.I.T
VDD VSS
3
R4
Port
R40
GMS81C50 Series
HYUNDAI
3. PIN ASSIGNMENT (Top View)
R01
R02
R03
R04
R05
R06
R07
VDD
XOUT
XIN
R10
R11/ INT1
R12/ INT2
R13
R00
R24
R23
R22
R21
R20
VSS
R17/ T0
R16/ T1
REMOUT
R15/ T2
R14/ EC
RESET
TEST
R00
1
40
R27
R01
2
39
R26
R02
3
38
R25
R03
4
37
R24
R04
5
36
R23
R05
6
35
R22
R06
7
34
R21
R07
8
33
R20
R34
9
32
R33
31
VSS
40PDIP
R35
10
VDD
11
30
R32
R36
12
29
R31
R37
13
28
R30
XOUT
14
27
R17 / T0
XIN
15
26
R16 / T1
R10
16
25
R40
R11/ INT1
17
24
REMOUT
R12/ INT2
18
23
R15 / T2
R13
19
22
R14 / EC
TEST
20
21
RESET
4
R22
R21
R20
R33
VSS
VSS
R32
R31
R30
R17 / T0
R16 / T1
5
4
3
2
1
44
43
42
41
40
GMS81C50 Series
6
HYUNDAI
R23
7
39
R40
R24
8
38
REMOUT
R25
9
37
R15 / T2
R26
10
36
R14 / EC
R27
11
35
RESET
VDD
12
34
VSS
R00
13
33
TEST
R01
14
32
R13
R02
15
31
R12 / INT2
R03
16
30
R11 / INT1
R04
17
29
R10
18
19
20
21
22
23
24
25
26
27
28
R05
R06
R07
R34
R35
VDD
VDD
R36
R37
XOUT
XIN
44PLCC
5
R22
R21
R20
R33
VSS
VSS
R32
R31
R30
R17 / T0
R16 / T1
32
31
30
29
28
27
26
25
24
23
HYUNDAI
33
GMS81C50 Series
R23
34
22
R40
R24
35
21
REMOUT
R25
36
20
R15 / T2
R26
37
19
R14 / EC
R27
38
18
RESET
VDD
39
17
VSS
R00
40
16
TEST
R01
41
15
R13
R02
42
14
R12 / INT2
R03
43
13
R11 / INT1
R04
44
12
R10
1
2
3
4
5
6
7
8
9
10
11
R05
R06
R07
R34
R35
VDD
VDD
R36
R37
XOUT
XIN
44QFP
6
HYUNDAI
GMS81C50 Series
4. PACKAGE DIMENSION
4.1 28 SOP PIN DIMENSION (DIMENSIONS IN INCH)
4.2 28 Skinny DIP PIN DIMENSION (DIMENSIONS IN INCH)
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GMS81C50 Series
HYUNDAI
4.3 40 PDIP Pin Dimension (dimension in inch)
0.200 max.
0.022
0.015
0.065
0.045
0.100 BSC
4.4 44 PLCC Pin Dimension (dimension in mm)
8
0.600 BSC
0.550
0.530
0.140
0.120
MIN 0.015
2.075
2.045
0.012
0.008
HYUNDAI
GMS81C50 Series
4.5 44 QFP Pin Dimension (dimension in mm)
9
GMS81C50 Series
HYUNDAI
5. PIN FUNCTION
ing special features.
VDD: Supply voltage.
VSS: Circuit ground.
Port pin
TEST: Used for shipping inspection of the IC. For normal
operation, it should be connected to VDD.
R11
R12
R14
R15
R16
R17
RESET: Reset the MCU.
XIN: Input to the inverting oscillator amplifier and input to
the internal main clock operating circuit.
Alternate function
INT1 (External Interrupt input 1)
INT2 (External Interrupt input 2)
/EC (Event Counter input )
T2 (Timer / Counter input 2)
T1 (Timer / Counter input 1)
T0 (Timer / Counter input 0)
XOUT: Output from the inverting oscillator amplifier.
R20~R22, R30~R37 : R2 & R3 is a 8-bit CMOS bidirectional I/O port. Each pins 1 or 0 written to the their Port Direction Register can be used as outputs or inputs.
R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
R40 : R40 is 1-bit CMOS bidirectional I/O port. This pin 1
or 0 written to the its Port Direction Register can be used
as outputs or inputs.
R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
In addition, R1 serves the functions of the various follow-
10
HYUNDAI
GMS81C50 Series
PIN NAME
Pin Numbers
INPUT/
OUTPUT 28Pin 40PDIP 44PLCC 44QFP
Function
R00
R01
R02
R03
R04
R05
R06
R07
R10
R11/INT1
R12/INT2
R13
R14/EC
R15/T2
R16/T1
R17/T0
R20
R21
R22
R23
R24
R25
R26
R27
R30
R31
R32
R33
R34
R35
R36
R37
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
28
1
13
41
1
2
14
42
2
3
15
43
3
4
16
44
4
5
17
1
5
6
18
2
6
7
19
3
7
8
20
4
11
16
29
12
12
17
30
13
13
18
31
14
14
19
32
15
17
22
36
19
18
23
37
20
20
26
40
23
21
27
41
24
23
33
4
31
24
34
5
32
25
35
6
33
26
36
7
34
27
37
8
35
-
38
9
36
-
39
10
37
-
40
11
38
-
28
42
25
-
29
43
26
-
30
44
27
-
32
3
30
-
9
21
4
-
10
22
5
-
12
25
8
-
13
26
9
R40
I/O
-
25
39
22
XIN
XOUT
REMOUT
I
O
O
10
15
28
11
9
14
27
10
- Oscillator Input
- Oscillator Output
19
24
38
21
- High Current Output
RESET
I
16
21
35
18
- Includes pull-up resistor
TEST
I
15
20
33
16
- Includes pull-up resistor
VDD
P
8
11
VSS
P
22
31
12,23,24 6,7,39
1,2.34 17,28,29
@ RESET @ STOP
- Each bit of the port can be
individually configured as an
input or an output by user software
- Push-pull output
- CMOS input with pull-up resistor
(can be selectable by user software)
- Can be programmable as Key
Scan Input or Open drain output
- Pull-ups are automatically
disabled at output mode
INPUT
State
of before
STOP
- Each bit of the port can be
individually configured as an
input or an output by user software
- CMOS input with pull-up resistor
(can be selectable by user software)
- Push-pull output
- Can be programmable as
Open drain output
- Direct Driving of LED(N-TR)
- Pull-ups are disabled at output
mode
- Positive power supply
- Ground
11
Low
High
`L` output `L` Output
state
`L` level
of before
STOP
GMS81C50 Series
HYUNDAI
6. PORT STRUCTURES
6.1 R0 Ports
Pin Name
Circuit Type
@ RESET
Open drain Selection
VDD
Pull-up Selection
VDD
Data Register
PAD
R00 ~ R07
Direction Register
Hi - Z
or
High-Input
(with pullup)
VSS
MUX
Data Bus
Rd Data Bus
Rd 6.2 R1 Ports (R10, R11, R12, R13, R14)
Pin Name
Circuit Type
@ RESET
VDD
Open drain Selection
Pull-up Selection
VDD
Function Selection
R10
R11 / INT1
R12 / INT2
R13
R14 / EC
Data Register
PAD
Direction Register
Data Bus
VSS
MUX
Rd
to R11...INT1
to R12...INT2
to R14...EC
NOISE
FILTER
12
Hi - Z
or
High-Input
(with pullup)
HYUNDAI
GMS81C50 Series
6.3 R1 Ports (R15, R16, R17)
Pin Name
Circuit Type
@ RESET
VDD
Open drain Selection
Pull-up Selection
VDD
Function Selection
from R15...T2
from R16...T1
from R17...T0
R15 / T2
R16 / T1
R17 / T0
MUX
PAD
Data Register
Direction Register
Hi - Z
or
High-Input
(with pullup)
VSS
Data Bus
MUX
Rd
6.4 R2, R3, R4 Ports
Pin Name
Circuit Type
@ RESET
VDD
Open drain Selection
Pull-up Selection
R20 ~ R27
R30 ~ R37
R40
VDD
Data Register
PAD
Direction Register
VSS
MUX
Data Bus
Rd 13
Hi - Z
or
High-Input
(with pullup)
GMS81C50 Series
HYUNDAI
6.5 REMOUT Port
Pin Name
Circuit Type
@ RESET
VDD
REMOUT
PAD
internal signal
Low level
VSS
6.6 Xin, Xout Ports
Pin Name
Circuit Type
@ RESET
Xout
Xin
Xout
NOISE
FILTER
Xin
oscillation
VSS
from STOP circuit
6.7 RESET Port
Pin Name
Circuit Type
@ RESET
VDD
Pull - up resistor
RESET
NOISE
FILTER
PAD
from POWER
on RESET circuit
VSS
14
VSS
Low level
HYUNDAI
GMS81C50 Series
6.8 TEST Port
Pin Name
Circuit Type
@ RESET
VDD
Pull - up resistor
TEST
High level
NOISE
FILTER
PAD
VSS
15
GMS81C50 Series
HYUNDAI
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute maximum ratings ( Ta=25 ’C)
Parameter
Symbol
Supply Voltage
Rating
VDD
Unit
-0.3 ~ +7.0
V
Input Voltage
VI
-0.3 ~ VDD + 0.3
V
Output Voltage
VO
-0.3 ~ VDD + 0.3
V
Operating Temperature
Topr
0 ~ 70
Storage Temperature
Tstg
-65 ~ 150
Power Dissipation
PD
700
mW
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at any other conditions above those indicated in
7.2 Recommended Operating Ranges
Parameter
Symbol
Condition
min.
fXin = 4MHz
typ.
max.
Unit
2.2
4.0
V
Supply Voltage
VDD
Oscillation Frequency
fXin
1.0
4.0
MHz
Operating Temperature
Topr
0
70
16
HYUNDAI
GMS81C50 Series
7.3 DC characteristics (VDD=2.2~4.0, Vss=0, Ta=0~70 ‘C)
* "
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#
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2
- #
7 1
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- #
7 .
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,
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,
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7 )
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7 )
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18 ; 7
,
23$
45
$6%
,
. * +
+
* +
* ! "! #! $$%
,
* +
; ; 7 #89:
7 #89:
; ; 7 #
7 ""
#
1
"#
/
1
7 #
"
)
1
7 ""
"
1
7 #
)
1
7 "
"
1
&
17
GMS81C50 Series
HYUNDAI
7.4 REMOUT Port Ioh characteristics graph
0.0
-5.0
VDD=2V
-10.0
IOH(mA)
-15.0
VDD=3V
-20.0
-25.0
-30.0
VDD=4V
-35.0
0
1
2
3
4
VOH(V)
7.5 REMOUT port Iol characteristics graph
8.00
7.00
VDD=4V
6.00
IOL(mA)
5.00
4.00
VDD=3V
3.00
2.00
1.00
VDD=2V
0.00
0
1
2
VOL(V)
18
3
4
HYUNDAI
GMS81C50 Series
7.6 AC characteristics (VDD=2.2~4.0V, Vss=0V, Ta=0~70’C)
No.
Parameter
Symbol
Specification
Pin
Xin
Unit
min.
typ.
max.
250
500
1000
ns
500
1000
2000
ns
1
External clock input cycle time
tcp
2
System clock cycle time
tsys
3
External clock pulse width High
tcpH
Xin
40
ns
4
External clock pulse width Low
tcpL
Xin
40
ns
5
External clock rising time
trcp
Xin
40
ns
6
External clock falling time
tfcp
Xin
40
ns
7
interrupt pulse width High
tIH
INT1~ INT2
2
tsys
8
Interrupt pulse width Low
tIL
INT1~ INT2
2
tsys
9
Reset input pulse width low
tRSTL
RESET
8
tsys
10
Event counter input pulse width high
tECH
EC
2
tsys
11
Event counter input pulse width low
tECL
EC
2
tsys
12
Event counter input pulse rising time
trEC
EC
40
ns
13
Event counter input pulse falling time
tfEC
EC
40
ns
(Continued)
19
GMS81C50 Series
HYUNDAI
tCP
tCPH
tCPL
Vcc-0.5V
XIN
0.5V
trCP
tfCP
tIH
tIL
0.8Vcc
INT1
INT2
0.2Vcc
tRSTL
RESET
0.2Vcc
tECL
tECH
0.8Vcc
EC
0.2Vcc
trEC
tfEC
Figure 7-1 Clock, Interrupt, RESET, EC Input Timing
20
HYUNDAI
GMS81C50 Series
8. MEMORY ORGANIZATION
The GMS81C50 Series has separate address spaces for
Program memory, Data Memory and Display memory.
Program memory can only be read, not written to. It can be
up to 32K bytes of Program memory. Data memory can be
read and written to up to 448 bytes including the stack area.
8.1 Registers
X, Y Registers:
This device has six registers that are the Program Counter
(PC), an Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.
A
ACCUMULATOR
X
X REGISTER
Y
Y REGISTER
SP
PCH
In the addressing mode which uses these index registers,
the register contents are added to the specified address,
which becomes the actual address. These modes are extremely effective for referencing subroutine tables and
memory tables. The index registers also have increment,
decrement, comparison and data transfer functions, and
they can be used as simple accumulators.
* X Register : In the case of division instruction, execute
as register.
STACK POINTER
PCL
PROGRAM COUNTER
PSW
PROGRAM STATUS
WORD
* Y Register : In the case of 16-bit operation instruction,
execute as the upper 8-bit of YA. (16-bit accumulator). In
the case of multiplication instruction, execute as a multiplicand register. After multiplication operation, the upper 8bit of the result enters. In the case of division instruction,
execute as the upper 8-bit of dividend. After division operation, remains enters. Y register can be used as loop
counter of conditional branch command. (e.g.DBNE Y,
rel)
Figure 8-1 Configuration of Registers
Accumulator:
The Accumulator is the 8-bit general purpose register, used
for data operation such as transfer, temporary saving, and
conditional judgement, etc. The Accumulator can be used
as a 16-bit register with Y Register as shown below.
Stack Pointer:
The Stack Pointer is an 8-bit register used for occurrence
interrupts, calling out subroutines and PUSH, POP, RETI,
RET instruction. Stack Pointer identifies the location in the
stack to be accessed (save or restore).
In the case of multiplication instruction, execute as a multiplier register. After multiplication operation, the lower 8bit of the result enters. (Y*A => YA). In the case of division instruction, execute as the lower 8-bit of dividend. After division operation, quotient enters.
Generally, SP is automatically updated when a subroutine
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost. The SP is post-decremented when a subroutine call or a push instruction is executed, or when an interrupt is accepted. The SP is pre-incremented when a return
or a pop instruction is executed.
Y
Y
A
A
Two 8-bit Registers can be used as a "YA" 16-bit Register
The stack can be located at any position within 100H to
1FFH of the internal data memory. The SP is not initialized
by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "FFH" is
Figure 8-2 Configuration of YA 16-bit Register
21
GMS81C50 Series
HYUNDAI
used.
Caution:
Stack Address ( 100H ~ 1FFH )
15
8
7
The Stack Pointer must be initialized by software because its value is undefined after RESET.
0
1
SP
Example: To initialize the SP
LDX
TXSP
Hardware fixed
At acceptance
of interrupt
At execution of
a CALL/TCALL/PCALL
01FC
01FC
01FD
01FD
01FE
PCL
01FF
PCH
Push
down
At execution
of RET instruction
PSW
01FE
PCL
01FF
PCH
Push
down
#0FFH
; SP ← FFH
At execution
of RETI instruction
01FC
01FC
01FD
01FD
PSW
01FE
PCL
01FE
PCL
01FF
PCH
01FF
PCH
Pop
up
SP before
execution
01FF
01FF
01FD
01FC
SP after
execution
01FD
01FC
01FF
01FF
At execution
of PUSH instruction
PUSH A (X,Y,PSW)
At execution
of POP instruction
POP A (X,Y,PSW)
01FC
01FC
01FD
01FD
01FE
01FF
Pop
up
0100H
Stack
depth
01FE
A
Push
down
01FF
A
SP before
execution
01FF
01FE
SP after
execution
01FE
01FF
Pop
up
01FFH
Figure 8-3 Stack Operation
Program Counter:
reflect the current state of the CPU. The PSW is described
in Figure 8-4 . It contains the Negative flag, the Overflow
flag, the Break flag the Half Carry (for BCD operation),
the Interrupt enable flag, the Zero flag, and the Carry flag.
The Program Counter is a 16-bit wide which consists of
two 8-bit registers, PCH and PCL. This counter indicates
the address of the next instruction to be executed. In reset
state, the program counter has reset routine address
(PCH:0FFH, PCL:0FEH).
[Carry flag C]
This flag stores any carry or borrow from the ALU of CPU
after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.
Program Status Word:
The Program Status Word (PSW) contains several bits that
22
HYUNDAI
GMS81C50 Series
[Zero flag Z]
This flag is set when the result of an arithmetic operation
or data transfer is "0" and is cleared by any other result.
MSB
PSW
N
LSB
V
G
B
H
I
Z
C
RESET VALUE : 00H
CARRY FLAG RECEIVES
CARRY OUT
NEGATIVE FLAG
OVERFLOW FLAG
ZERO FLAG
SELECT DIRECT PAGE
when g=1, page is addressed by RPR
INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS
BRK FLAG
Figure 8-4 PSW (Program Status Word) Register
[Interrupt disable flag I]
This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.
the direct addressing mode, addressing area is from zero
page 00H to 0FFH when this flag is "0". If it is set to "1",
addressing area is 1 Page. It is set by SETG instruction and
cleared by CLRG.
[Overflow flag V]
This flag is set to "1" when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction exceeds +127(7FH) or -128(80H). The CLRV instruction
clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.
[Half carry flag H]
After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).
[Break flag B]
This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector address.
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
[Direct page flag G]
This flag assigns RAM page for direct addressing mode. In
23
GMS81C50 Series
HYUNDAI
8.2 Program Memory
A 16-bit program counter is capable of addressing up to
64K bytes, but this device has 16K/24K/32K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around
to 0000H.
Example: Usage of TCALL
LDA
#5
TCALL 0FH
:
:
;1BYTE INSTR UCTIO N
;INSTEAD OF 2 BYTES
;NOR M AL C ALL
;
;TABLE CALL ROUTINE
;
FUNC_A: LDA
LRG0
RET
;
FUNC_B: LDA
LRG1
2
RET
;
;TABLE CALL ADD. AREA
;
ORG
0FFC0H
DW
FUNC_A
DW
FUNC_B
Figure 8-5 , shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFEH and FFFFH as shown in Figure 8-6 .
As shown in Figure 8-5 , each area is assigned a fixed location in Program Memory. Program Memory area contains the user program.
8000H
32KByte
Range
1
;TCALL ADDRESS AREA
A000H
24KByte
Range
C000H
PROGRAM
MEMORY
16KByte
Range
FF00H
PCALL
AREA
FFC0H
TCALL
AREA
FFE0H
INTERRUPT
VECTOR AREA
FFFFH
The interrupt causes the CPU to jump to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte
interval: 0FFF8H and 0FFF9H for External Interrupt 1,
0FFFAH and 0FFFBH for External Interrupt 0, etc.
U-PAGE
Any area from 0FF00H to 0FFFFH, if it is not going to be
used, its service location is available as general purpose
Program Memory.
Address
Figure 8-5 Program Memory Map
0FFDEH
Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently
called, it is more useful to save program byte length.
Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0H for TCALL15, 0FFC2H for
TCALL14, etc., as shown in Figure 8-7 .
Vector Area Memory
S/W Interrupt Vector Area
E0
-
E2
-
E4
-
E6
Basic Interval Timer Interrupt Vector Area
E8
Watch Dog Timer Interrupt Vector Area
EA
-
EC
-
EE
Timer2 Interrupt Vector Area
F0
Timer1 Interrupt Vector Area
F2
Timer0 Interrupt Vector Area
F4
-
F6
External Interrupt 2 Vector Area
F8
External Interrupt 1 Vector Area
FA
FC
Key Scan Interrupt Vector Area
-
FE
RESET Vector Area
NOTE:
"-" means reserved area.
Figure 8-6 Interrupt Vector Area
24
HYUNDAI
GMS81C50 Series
Address
Address
Program Memory
0FFC0H
C1
TCALL 15
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
PCALL Area Memory
0FF00H
PCALL Area
(192 Bytes)
0FFBFH
TCALL 14
TCALL 13
TCALL 12
TCALL 11
TCALL 10
TCALL 9
TCALL 8
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
TCALL 7
TCALL 6
TCALL 5
TCALL 4
TCALL 3
TCALL 2
TCALL 1
TCALL 0 / BRK *
NOTE:
* means that the BRK software interrupt is using
same address with TCALL0.
Figure 8-7 PCALL and TCALL Memory Area
PCALL→
→ rel
TCALL→
→n
4F35
4A
PCALL 35H
TCALL 4
4A
4F
35
~
~
~
~
~
~
0D125H
~
~
NEXT
0FF00H
0FF35H
01001010
➊
PC: 11111111 11010110
FH FH
DH 6H
➌
0FF00H
NEXT
0FFFFH
0FFD6H
25
0FFD7H
D1
0FFFFH
25
Reverse
➋
GMS81C50 Series
HYUNDAI
Example: The usage software example of Vector address and the initialize part.
ORG
0FFE0H
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
NOT_USED
NOT_USED
NOT_USED
BIT_INT
WDT_INT
NOT_USED
NOT_USED
TMR2_INT
TMR1_INT
TMR0_INT
NOT_USED
INT2
INT1
KEY_INT
NOT_USED
RESET
ORG
08000H
; BIT
; Watch Dog Timer
;
;
;
;
;
;
;
;
;
Timer-2
Timer-1
Timer-0
Int.2
Int.1
Key Scan
Reset
;********************************************
;
MAIN
PROGRAM
*
;********************************************
;
RESET:
DI
;Disable All Interrupts
LDX
#0
RAM_CLR: LDA
#0
;RAM Clear(!0000H->!00BFH)
STA
{X}+
CMPX
#0C0H
BNE
RAM_CLR
;
;
LDX
#03FH
;Stack Pointer Initialize
TXSP
LDM
LDM
LDM
LDM
:
:
LDM
:
:
R0, #0
R0DD,#1000_0010B
PUR0,#1000_0010B
PMR0,#0000_0001B
;Normal Port 0
;Normal Port Direction
;Pull Up Selection Set
;R0 port / int
PCOR,#1
;Enable Peripheral clock
26
HYUNDAI
GMS81C50 Series
8.3 Data Memory
Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into 3 groups, a user RAM,
control registers, Stack.
Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
0000H
More detailed informations of each register are explained
in each peripheral section.
RAM
(192 Bytes)
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction.
PAGE0
00BFH
00C0H
00FFH
CONTROL
REGISTERS
Example; To write at CKCTLR
0100H
LDM
RAM (STACK)
(256 Bytes)
CLCTLR,#09H ;Divide ratio ÷8
Stack Area
The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.
PAGE1
01FFH
When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the program counter and flags.
Figure 8-8 Data Memory Map
User Memory
The GMS81C50 Series has 448 × 8 bits for the user memory (RAM).
The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save. Refer to Figure 8-3 on page 22.
Control Registers
The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0H to 0FFH.
Address
Function Register
Read
Write
Symbol
RESET Value
00C0h
PORT R0 DATA REG.
R/W
R0
undefined
00C1h
PORT R0 DATA DIRECTION REG.
W
R0DD
00000000b
00C2h
PORT R1 DATA REG.
R/W
R1
undefined
00C3h
PORT R1 DATA DIRECTION REG.
W
R1DD
00000000b
00C4h
PORT R2 DATA REG.
R/W
R2
undefined
00C5h
PORT R2 DATA DIRECTION REG.
W
R2DD
00000000b
00C6h
reserved
27
GMS81C50 Series
HYUNDAI
CLOCK CONTROL REG.
W
CKCTLR
--110111b
BASIC INTERVAL REG.
R
BTR
undefined
00C8h
WATCH DOG TIMER REG.
W
WDTR
-0001111b
00C9h
PORT R1 MODE REG.
W
PMR1
00000000b
00CAh
INT. MODE REG.
R/W
IMOD
-0000000b
00CBh
EXT. INT. EDGE SELECTION
W
IEDS
00000000b
00CCh
INT. ENABLE REG. LOW
R/W
IENL
-00-----b
00CDh
INT. REQUEST FLAG REG. LOW
R/W
IRQL
-00-----b
00CEh
INT. ENABLE REG. HIGH
R/W
IENH
000-000-b
00CFh
INT. REQUEST FLAG REG. HIGH
R/W
IRQH
000-000-b
00D0h
TIMER0 (16bit) MODE REG.
R/W
TM0
00000000b
00D1h
TIMER1 (8bit) MODE REG.
R/W
TM1
00000000b
00D2h
TIMER2 (8bit) MODE REG.
R/W
TM2
00000000b
00D3h
TIMER0 HIGH-MSB DATA REG.
W
T0HMD
undefined
00D4h
TIMER0 HIGH-LSB DATA REG.
W
T0HLD
undefined
TIMER0 LOW-MSB DATA REG.
W
T0LMD
undefined
TIMER0 HIGH-MSB COUNT REG.
R
TIMER0 LOW-LSB DATA REG.
W
TIMER0 LOW-LSB COUNT REG.
W
TIMER1 HIGH DATA REG.
W
T1HD
undefined
TIMER1 LOW DATA REG.
W
T1LD
undefined
TIMER1 LOW COUNT REG.
R
TIMER2 DATA REG.
W
TIMER2 COUNT REG.
R
00DAh
TIMER0 / TIMER1 MODE REG.
R/W
TM01
00000000b
00DBh
Reserved
00DCh
STANDBY MODE RELEASE REG0
W
SMPR0
00000000b
00DDh
STANDBY MODE RELEASE REG0
W
SMPR1
00000000b
00DEh
PORT R1 OPEN DRAIN ASSIGN REG.
W
R1ODC
00000000b
00DFh
PORT R2 OPEN DRAIN ASSIGN REG.
W
R2ODC
00000000b
00E0h
PORT R3 OPEN DRAIN ASSIGN REG.
W
R3ODC
00000000b
00E1h
PORT R4 OPEN DRAIN ASSIGN REG.
W
R4ODC
- - - - - - - 0b
00E2h
Reserved
00E3h
Reserved
00E4h
PORT R0 OPEN DRAIN ASSIGN REG.
W
R0ODC
00000000b
00E5h
PORT R3 DATA REG.
R/W
R3
undefined
00E6h
PORT R3 DATA DIRECTION REG.
W
R3DD
00000000b
00C7h
00D5h
undefined
T0LLD
undefined
00D6h
00D7h
undefined
00D8h
undefined
T2DR
undefined
00D9h
28
undefined
HYUNDAI
GMS81C50 Series
00E7h
PORT R4 DATA REG.
R/W
R4
- - - - - - - Xb
00E8h
PORT R4 DATA DIRECTION REG.
W
R4DD
- - - - - - - 0b
00E9h
Reserved
00EAh
Reserved
00EBh
Reserved
00ECh
Reserved
00EDh
Reserved
00EEh
Reserved
00EFh
LOW VOLTAGE INDICATION REG.
R
LVIR
- - - - - - 00b
00F0h
SLEEP MODE REG.
W
SLPM
- - - - - - - 0b
00F1h
Reserved
00F2
Reserved
00F3h
Reserved
00F4h
Reserved
00F5h
Reserved
00F6h
STANDBY RELEASE LEVEL CONT. REG. 0
W
SRLC0
00000000b
00F7h
STANDBY RELEASE LEVEL CONT. REG. 1
W
SRLC1
00000000b
00F8h
PORT R0 PULL-UP REG. CONT. REG.
W
R0PC
00000000b
00F9h
PORT R1 PULL-UP REG. CONT. REG.
W
R1PC
00000000b
00FAh
PORT R2 PULL-UP REG. CONT. REG.
W
R2PC
00000000b
00FBh
PORT R3 PULL-UP REG. CONT. REG.
W
R3PC
00000000b
00FCh
PORT R4 PULL-UP REG. CONT. REG.
W
R4PC
- - - - - - - 0b
00FDh
Reserved
00FEh
Reserved
00FFh
Reserved
29
GMS81C50 Series
HYUNDAI
8.4 Addressing Mode
The GMS81C50 Series uses six addressing modes;
(3) Direct Page Addressing → dp
• Register addressing
In this mode, a address is specified within direct page.
• Immediate addressing
Example; G=0
• Direct page addressing
C535
LDA
;A ←RAM[35H]
35H
• Absolute addressing
• Indexed addressing
35H
• Register-indirect addressing
data
➋
~
~
(1) Register Addressing
Register addressing accesses the A, X, Y, C and PSW.
~
~
0E550H
C5
0E551H
35
➊
data → A
(2) Immediate Addressing → #imm
In this mode, second byte (operand) is accessed as a data
immediately.
(4) Absolute Addressing → !abs
Example:
0435
ADC
Absolute addressing sets corresponding memory data to
Data , i.e. second byte(Operand I) of command becomes
lower level address and third byte (Operand II) becomes
upper level address.
With 3 bytes command, it is possible to access to whole
memory area.
#35H
MEMORY
04
A+35H+C → A
35
ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY
Example;
0735F0
ADC
;A ←ROM[0F035H]
!0F035H
When G-flag is 1, then RAM address is difined by 16-bit
address which is composed of 8-bit RAM paging register
(RPR) and 8-bit immediate data.
Example: G=1, RPR=0CH
E45535
LDM
data
0F035H
~
~
➊
0F100H
data ← 55H
data
0C35H
➋
35H,#55H
~
~
~
~
➋
E4
0F101H
55
0F102H
35
30
~
~
0F100H
07
0F101H
35
0F102H
F0
A+data+C → A
➊
address: 0F035
HYUNDAI
GMS81C50 Series
X indexed direct page, auto increment→
→ {X}+
The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR
In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.
Example; Addressing accesses the address 0135H regardless of G-flag and RPR.
983501
INC
LDA, STA
;A ←ROM[135H]
!0135H
Example; G=0, X=35H
DB
data
135H
~
~
LDA
{X}+
➌
~
~
➋
35H
data+1 → data
0F100H
98
➊
0F101H
35
address: 0135
0F102H
01
➋
data
~
~
~
~
data → A
➊
36H → X
DB
(5) Indexed Addressing
X indexed direct page (no offset) → {X}
X indexed direct page (8 bit offset) → dp+X
In this mode, a address is specified by the X register.
This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA
Example; X=15H, G=1, RPR=01H
D4
LDA
{X}
ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR
;ACC←RAM[X].
Example; G=0, X=0F5H
C645
115H
data
~
~
0E550H
LDA
45H+X
➋
~
~
data → A
➊
3AH
data
➌
D4
~
~
31
➋
~
~
0E550H
C6
0E551H
45
data → A
➊
45H+0F5H=13AH
GMS81C50 Series
HYUNDAI
Y indexed direct page (8 bit offset) → dp+Y
3F35
JMP
[35H]
This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in
Direct page.
This is same with above (2). Use Y register instead of X.
35H
0A
36H
E3
Y indexed absolute → !abs+Y
~
~
Sets the value of 16-bit absolute address plus Y-register
data as Memory. This addressing mode can specify memory in whole area.
0E30AH
LDA
0FA00H
0F100H
D5
00
0F102H
FA
~
~
0FA55H
~
~
3F
35
!0FA00H+Y
0F101H
➋ jump to address 0E30AH
➊
NEXT
~
~
Example; Y=55H
D500FA
~
~
➊
X indexed indirect → [dp+X]
0FA00H+55H=0FA55H
~
~
Processes memory data as Data, assigned by 16-bit pair
memory which is determined by pair data
[dp+X+1][dp+X] Operand plusX-register data in Direct
page.
➋
data
➌
data → A
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; G=0, X=10H
1625
ADC
[25H+X]
(6) Indirect Addressing
Direct page indirect → [dp]
Assigns data address to use for accomplishing command
which sets memory data(or pair memory) by Operand.
Also index can be used with Index register X,Y.
35H
05
36H
E0
0E005H
~
~ ➋
~
~
0E005H
JMP, CALL
~
~
Example; G=0
0FA00H
~
~
16
25
32
➊ 25 + X(10) = 35H
data
➌ A + data + C → A
HYUNDAI
GMS81C50 Series
Y indexed indirect → [dp]+Y
Absolute indirect → [!abs]
Processes momory data as Data, assigned by the data
[dp+1][dp] of 16-bit pair memory paired by Operand in Direct pageplus Y-register data.
The program jumps to address specified by 16-bit absolute
address.
JMP
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; G=0
Example; G=0, Y=10H
1725
ADC
1F25E0
JMP
[!0C025H]
[25H]+Y
PROGRAM MEMORY
25H
05
0E025H
25
26H
E0
0E026H
E7
~
~
0E015H
~
~
0FA00H
0E005H + Y(10) = 0E015H
~
~
➊
data
~
~
➋
➊
0E725H
NEXT
~
~
~
~
0FA00H
17
25
~
~
~
~
1F
25
➌ A + data + C → A
E0
33
➋
jump to
address 0E30AH
GMS81C50 Series
HYUNDAI
9. I/O PORTS
The GMS81C50 Series has 33 I/O ports which are
PORT0(8 I/O), PORT1 (8 I/O), PORT2 (8 I/O), PORT3 (8
I/O), PORT4 (1 I/O). Pull-up resistor of each port can be
selectable by program. Each port contains data direction
register which controls I/O and data register which stores
port data.
(1) R0 I/O Data Direction Register (R0DD)
9.1 R0 Ports
(2) R0 Data Register (R0)
R0 is an 8-bit CMOS bidirectional I/O port (address
0C0H). Each I/O pin can independently used as an input or
an output through the R0DD register (address 0C1H).
R0 data register (R0) is 8-bit register to store data of port
R0. When set as the output state by R0DD, and data is written in R0, data is outputted into R0 pin. When set as the input state, input state of pin is read. The initial value of R0
is unknown in reset state.
R0 I/O Data Direction Register (R0DD) is 8-bit register,
and can assign input state or output state to each bit. If
R0DD is ``1``, port R0 is in the output state, and if ``0``, it
is in the input state. R0DD is write-only register. Since
R0DD is initialized as ``00 h`` in reset state, the whole port
R0 becomes input state.
R0 has internal pull-ups that is independently connected or
disconnected by R0PC. The control registers for R0 are
shown below.
R0 Data Register (R/W)
R0
(3) R0 Open drain Assign Register (R0ODC)
R0 Open Drain Assign Register (R0ODC) is 8bit register,
and can assign R0 port as open drain output port each bit,
if corresponding port is selected as output. If R0ODC is
selected as ``1``, port R0 is open drain output, and if selected as ``0``, it is push-pull output. R0ODC is write-only
register and initialized as ``00 h`` in reset state.
ADDRESS : 0C0H
RESET VALUE : Undefined
R07 R06 R05 R04 R03 R02 R01 R00
R0 Direction Register (W)
ADDRESS : 0C1H
RESET VALUE : 00H
(4) R0 Pull-up Resistor Control Register (R0PC)
R0DD
R0 pull-up resistor control register (R0PC) is 8-bit register
and can control pull-up on or off each bit, if corresponding
port is selected as input. If R0PC is selected as ``1``, pullup ia disabled and if selected as ``0``, it is enabled. R0PC
is write-only register and initialized as ``00 h`` in reset
state. The pull-up is automatically disabled, if corresponding port is selected as output.
Port Direction
0: Input
1: Output
R0 Pull-up Selection Register (W)
ADDRESS :0F8H
RESET VALUE : 00H
R0PC
Pull-up select
0: Without pull-up
1: With pull-up
9.2 R1 Ports
R0 Open drain Assign Register (W) ADDRESS :0E4H
RESET VALUE : 00H
R1 is an 8-bit CMOS bidirectional I/O port (address
0C2H). Each I/O pin can independently used as an input or
an output through the R1DD register (address 0C3H).
R0ODC
Open drain select
0: Push-pull
1: Open drain
R1 has internal pull-ups that is independently connected or
disconnected by register R1PC. The control registers for
R1 are shown below.
34
HYUNDAI
GMS81C50 Series
(3) R1 Mode Register (PMR1)
R1 Data Register (R/W)
R1
R1 Port Mode Register (PMR1) is 8-bit register, and can
assign the selection mode for each bit. When set as ``0``,
corresponding bit of PMR1 acts as port R1 selection mode,
and when set as ``1``, it becomes function selection mode.
ADDRESS : 0C2H
RESET VALUE : Undefined
R17 R16 R15 R14 R13 R12 R11 R10
R1 Direction Register (W)
ADDRESS : 0C3H
RESET VALUE : 00H
PMR1 is write-only register and initialized as ``00 h`` in
reset state. Therefore, becomes Port selection mode. Port
R1 can be I/O port by manipulating each R1DD bit, if corresponding PMR1 bit is selected as ``0``.
R1DD
Port Direction
0: Input
1: Output
R1 Pull-up Selection Register (W)
ADDRESS : 0F9H
RESET VALUE : 00H
Pin Name
R1PC
Pull-up select
0: Without pull-up
1: With pull-up
Selection
Mode
Remarks
0
R17 (I/O)
-
1
T0 (O)
Timer0
0
R16 (I/O)
-
1
T1 (O)
Timer1
0
R15 (I/O)
-
1
T2 (O)
Timer2
0
R14 (I/O)
-
1
/EC (I)
Timer0 Event
0
R12 (I/O)
1
INT2 (I)
0
R11 (I/O)
1
INT1 (I)
T0S
R1 Open drain Assign Register (W) ADDRESS : 0DEH
RESET VALUE : 00H
T1S
P1ODC
T2S
Open drain select
0: Push-pull
1: Open drain
R1 Port Mode Register (W)
PMR1
ECS
ADDRESS : 0C9H
RESET VALUE : 00H
PMR1
Mode select
0: Port R1 selection
1: Function selection
INT2S
Timer0 Input
Capture
INT1S
(1) R1 I/O Data Direction Register (R1DD)
R1 I/O Data Direction Register (R1DD) is 8-bit register,
and can assign input state or output state to each bit. If
R1DD is ``1``, port R1 is in the output state, and if ``0``, it
is in the input state. R1DD is write-only register. Since
R1DD is initialized as ``00 h`` in reset state, the whole port
R1 becomes input state.
Table 9-1 Selection mode of PMR1
(2) R1 Data Register (R1)
(4) R1 Pull-up Resistor Control Register (R1PC)
R1 data register (R1) is 8-bit register to store data of port
R1. When set as the output state by R1DD, and data is written in R1, data is outputted into R1 pin. When set as the input state, input state of pin is read. The initial value of R1
is unknown in reset state.
R1 pull-up resistor control register (R1PC) is 8-bit register
and can control pull-up on or off each bit, if corresponding
port is selected as input. If R1PC is selected as ``1``, pullup ia disabled and if selected as ``0``, it is enabled. R1PC
is write-only register and initialized as ``00 h`` in reset
state. The pull-up is automatically disabled, if corresponding port is selected as output.
35
GMS81C50 Series
HYUNDAI
9.3 R2 Port
(1) R2 I/O Data Direction Register (R2DD)
R2 I/O Data Direction Register (R2DD) is 8-bit register,
and can assign input state or output state to each bit. If
R2DD is ``1``, port R2 is in the output state, and if ``0``, it
is in the input state. R2DD is write-only register. Since
R2DD is initialized as ``00 h`` in reset state, the whole port
R2 becomes input state.
R2 is an 8-bit CMOS bidirectional I/O port (address
0C4H). Each I/O pin can independently used as an input or
an output through the R2DD register (address 0C5H).
R2 has internal pujll-ups that is independently connected
or disconnected by R2PC (address 0FAH). The control registers for R2 are shown as below.
R2 Data Register (R/W)
R2
(2) R2 Data Register (R2)
R2 data register (R2) is 8-bit register to store data of port
R2. When set as the output state by R2DD, and data is written in R2, data is outputted into R2 pin. When set as the input state, input state of pin is read. The initial value of R2
is unknown in reset state.
ADDRESS : 0C4H
RESET VALUE : Undefined
R27 R26 R25 R24 R23 R22 R21 R20
R2 Direction Register (W)
ADDRESS : 0C5H
RESET VALUE : 00H
(3) R2 Open drain Assign Register (R2ODC)
R2 Open Drain Assign Register (R2ODC) is 8bit register,
and can assign R2 port as open drain output port each bit,
if corresponding port is selected as output. If R2ODC is
selected as ``1``, port R2 is open drain output, and if selected as ``0``, it is push-pull output. R2ODC is write-only
register and initialized as ``00 h`` in reset state.
R2DD
Port Direction
0: Input
1: Output
R2 Pull-up Selection Register (W)
ADDRESS :0FAH
RESET VALUE : 00H
R2PC
(4) R2 Pull-up Resistor Control Register (R2PC)
R2 pull-up resistor control register (R2PC) is 8-bit register
and can control pull-up on or off each bit, if corresponding
port is selected as input. If R2PC is selected as ``1``, pullup ia disabled and if selected as ``0``, it is enabled. R2PC
is write-only register and initialized as ``00 h`` in reset
state. The pull-up is automatically disabled, if corresponding port is selected as output.
Pull-up select
0: Without pull-up
1: With pull-up
R2 Open drain Assign Register (W) ADDRESS :0DFH
RESET VALUE : 00H
R2ODC
Open drain select
0: Push-pull
1: Open drain
36
HYUNDAI
GMS81C50 Series
(1) R3 I/O Data Direction Register (R3DD)
R3 I/O Data Direction Register (R3DD) is 8-bit register,
and can assign input state or output state to each bit. If
R3DD is ``1``, port R3 is in the output state, and if ``0``, it
is in the input state. R3DD is write-only register. Since
R3DD is initialized as ``00 h`` in reset state, the whole port
R3 becomes input state.
R3 Port
R3 is an 8-bit CMOS bidirectional I/O port (address
0E5H). Each I/O pin can independently used as an input or
an output through the R3DD register (address 0E6H).
R3 has internal pull-ups that is independently connected or
disconnected by R3PC (address 0FBH). The control registers for R3 are shown as below.
R3 Data Register (R/W)
R3
(2) R3 Data Register (R3)
R3 data register (R3) is 8-bit register to store data of port
R3. When set as the output state by R3DD, and data is written in R3, data is outputted into R3 pin. When set as the input state, input state of pin is read. The initial value of R3
is unknown in reset state.
ADDRESS : 0E5H
RESET VALUE : Undefined
R37 R36 R35 R34 R33 R32 R31 R30
R3 Direction Register (W)
ADDRESS : 0E6H
RESET VALUE : 00H
(3) R3 Open drain Assign Register (R3ODC)
R3 Open Drain Assign Register (R3ODC) is 8bit register,
and can assign R3 port as open drain output port each bit,
if corresponding port is selected as output. If R3ODC is
selected as ``1``, port R3 is open drain output, and if selected as ``0``, it is push-pull output. R3ODC is write-only
register and initialized as ``00 h`` in reset state.
R3DD
Port Direction
0: Input
1: Output
R3 Pull-up Selection Register (W)
ADDRESS :0FBH
RESET VALUE : 00H
R3PC
(4) R3 Pull-up Resistor Control Register (R3PC)
R3 pull-up resistor control register (R3PC) is 8-bit register
and can control pull-up on or off each bit, if corresponding
port is selected as input. If R3PC is selected as ``1``, pullup ia disabled and if selected as ``0``, it is enabled. R3PC
is write-only register and initialized as ``00 h`` in reset
state. The pull-up is automatically disabled, if corresponding port is selected as output.
Pull-up select
0: Without pull-up
1: With pull-up
R3 Open drain Assign Register (W) ADDRESS :0E0H
RESET VALUE : 00H
R3ODC
Open drain select
0: Push-pull
1: Open drain
37
GMS81C50 Series
HYUNDAI
(1) R4 I/O Data Direction Register (R4DD)
R4 I/O Data Direction Register (R4DD) is 1-bit register,
and can assign input state or output state to each bit. If
R4DD is ``1``, port R4 is in the output state, and if ``0``, it
is in the input state. R4DD is write-only register. Since
R4DD is initialized as ``00 h`` in reset state, the whole port
R4 becomes input state.
R4 Port
R4 is an 1-bit CMOS bidirectional I/O port (address
0E7H). Each I/O pin can independently used as an input or
an output through the R4DD register (address 0E8H).
R3 has internal pull-ups that is independently connected or
disconnected by R4PC (address 0FCH). The control registers for R4 are shown as below.
R4 Data Register (R/W)
R4
R4 Direction Register (W)
(2) R4 Data Register (R4)
R4 data register (R4) is 1-bit register to store data of port
R4. When set as the output state by R4DD, and data is written in R4, data is outputted into R4 pin. When set as the input state, input state of pin is read. The initial value of R4
is unknown in reset state.
ADDRESS : 0E7H
RESET VALUE : Undefined
R40
ADDRESS : 0E8H
RESET VALUE : 00H
(3) R4 Open drain Assign Register (R4ODC)
R4 Open Drain Assign Register (R4ODC) is 1-bit register,
and can assign R4 port as open drain output port each bit,
if corresponding port is selected as output. If R4ODC is
selected as ``1``, port R4 is open drain output, and if selected as ``0``, it is push-pull output. R4ODC is write-only
register and initialized as ``00 h`` in reset state.
R4DD
Port Direction
0: Input
1: Output
R4 Pull-up Selection Register (W)
ADDRESS :0FCH
RESET VALUE : 00H
R4PC
(4) R4 Pull-up Resistor Control Register (R4PC)
R4 pull-up resistor control register (R4PC) is 1-bit register
and can control pull-up on or off each bit, if corresponding
port is selected as input. If R4PC is selected as ``1``, pullup ia disabled and if selected as ``0``, it is enabled. R4PC
is write-only register and initialized as ``00 h`` in reset
state. The pull-up is automatically disabled, if corresponding port is selected as output.
Pull-up select
0: Without pull-up
1: With pull-up
R4 Open drain Assign Register (W) ADDRESS :0E1H
RESET VALUE : 00H
R4ODC
Open drain select
0: Push-pull
1: Open drain
38
HYUNDAI
GMS81C50 Series
10. CLOCK GENERATOR
Clock generating circuit consists of Clock Pulse Generator
(C.P.G), Prescaler, Basic Interval Timer (B.I.T) and Watch
fex
Dog Timer. The clock applied to the Xin pin divided by
two is used as the internal system clock.
fcpu
OSC
Circuit
Internal System Clock
C.P.G
PRESCALER
IFBIT
PS1
0
ENPCK
7
0
5
8
WDTCL
B.I.T (8)
MUX
WDT (6)
9
BTCL
IFWDT
COMPARATOR
3
WDTON
Peripheral
CKCTLR
6
0
1
2
3
4
WDTR
5
To Reset
Circuit
6
0
5
6
Internal Data Bus
Figure 10-1 Block Diagram of Clock Generator
Prescaler consists of 12-bit binary counter. The clock supplied from oscillation circuit is input to prescaler (fex).
PS1
fex
PS2
PS3
PS4
The divided output from each bit of prescaler is provided
to peripheral hardware.
PS5
PS6
PS7
PS8
PS9
PS10
PS11
PS12
ENPCK
B.I.T
fcpu
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10 PS11
PS12
Peripheral
Figure 10-2 Block diagram of Prescaler
39
GMS81C50 Series
HYUNDAI
4 MHz
fex (MHz)
frequency
ps 0
ps 1
ps 2
ps 3
ps 4
ps 5
ps 6
ps 7
ps 8
ps 9
ps 10
ps 11
ps 12
2 MHz
period
frequency
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
62.5 KHz
31.25 KHz
15.63 KHz
7.183 KHz
3.906 KHz
1.953 KHz
0.976 KHz
0.488 KHz
250 ns
500 ns
1 us
2 us
4 us
8 us
16 us
32 us
64 us
128 us
256 us
512 us
1024 us
4 MHz
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
62.5 KHz
31.25 KHz
15.63 KHz
7.183 KHz
3.906 KHz
1.953 KHz
0.976 KHz
period
500 ns
1 us
2 us
4 us
8 us
16 us
32 us
64 us
128 us
256 us
512 us
1024 us
2048 us
Table 10-1 ps output period
Clock to peripheral hardware can be stopped by bit4 (ENPCK) of CKCTLR Register. ENPCK is set to ``1`` in reset
Clock Control Register
7
CKCTLR
-
state.
-
WDTON
ENPCK
BTCL
BTS2
0
BTS1
ENPCK
Periphral clock
0
stopped
1
provided
Figure 10-3 Clock Control Register
40
BTS0
W <00C7 h>
HYUNDAI
GMS81C50 Series
10.1 Operation Mode
The system clock controller starts or stops the main-frequency clock oscillator. Figure 10-2 shows the operating
mode transition diagram.
voked.
STOP mode
In this mode, the system operations are all stopped, holding
the internal states valid immediately before the stop at the
low power consumption level
Main-clock operating mode
This mode is fast-frequency operating mode.
The CPU and the peripheral hardwares are operated on the
high-frequency clock. At reset release, this mode is in-
Main - Oscillating
Main
Operating
NOTE:
Refer to 14.3 context
no
te
ST
R
e
ef
e
ot
Re
f
N
er
to
o
rt
Instruction
STOP
Mode
Reset
g
tin
et
O
P
rs
In
st
e
st
gi
ru
ct
Re
io
n
Mode
Release
Reset
RESET
Operation
Main: Stopped
SLEEP
Mode
Main: Oscillating
Figure 10-4 Operating Mode
41
GMS81C50 Series
HYUNDAI
11. TIMER
11.1 Basic Interval Timer
The GMS81C50 Series has one 8-bit Basic Interval Timer
that is free-run and can not stop. Block diagram is shown
in Figure 11-1 .
-8bit binary counter
-Use the bit output of prescaler as input to secure the oscillation stabilization time after power-on
The Basic Interval Timer generates the time base for key
scanning, watchdog timer counting, and etc. It also provides a Basic interval timer interrupt (IFBIT). As the count
overflow from FFH to 00H, this overflow causes the interrupt to be generated.
-Secures the oscillation stabilization time in standby mode
(stop mode) release
-Contents of B.I.T can be read
-Provides the clock for watch dog timer.
DATA BUS
-
-
WDTON
ENPCK
BTCL
BTS2
BTS1
BTS0
CKCTLR
PS3
PS4
PS5
BITR
PS6
MUX
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
IFBIT
PS7
PS8
DATA BUS
PS9
PS10
Figure 11-1 Block Diagram of Basic Interval Timer
(1) Control of B.I.T
The Basic Interval Timer is controlled by the clock control
register (CKCTLR) shown in Figure 11-2 . If bit3(BTCL)
of CKCTLR is set to ``1``, B.I.T is cleared, and then, after
one machine cycle, BTCL becomes ``0``, and B.I.T starts
counting. BTCL is set to ``0`` in reset state.
42
HYUNDAI
GMS81C50 Series
Clock Control Register
7
CKCTLR
-
-
WDTON
ENPCK
BTCL
0
BTS2
BTS1
BTS0
BTCL
Periphral clock
0
free-run
1
W <00C7 h>
Automatically cleared, after one cycle
Figure 11-2 BTCL mode of B.I.T
(2) Input clock selection of B.I.T
ate the wide range of basic interval time interrupt request
(IFBIT) by selecting prescaler output. Interrupt interval
can be selected to kinds of interval time as shown in
The input clock of B.I.T can be selected from the prescaler
within a range of 2us to 256us by clock input selection bits
(BTS2~BTS0). (at fex = 4MHz). In reset state, or power
on reset, BTS2=``1``, BTS1=``1``, BTS0=``1`` to secure
the longest oscillation stabilization time. B.I.T can gener-
Clock Control Register
7
CKCTLR
Figure 11-3 .
ENPCK
BTCL
0
-
-
WDTON
BTS2
BTS1
BTS0
BTS2
BTS1
BTS0
B.I.T. Input clock
Standby release time
0
0
0
PS3 (2us)
512 us
0
0
1
PS4 (4us)
1,024 us
0
1
0
PS5 (8us)
2,048 us
0
1
1
PS6 (16us)
4,096 us
1
0
0
PS7 (32us)
8,192 us
1
0
1
PS8 (64us)
16,384 us
1
1
0
PS9 (128us)
32,768 us
1
1
1
PS10 (256us)
65,536 us
W <00C7 h>
Figure 11-3 Basic Interval Timer Interrupt Time
(3) Reading Basic Interval Timer
By reading of the Basic Interval Timer Register (BITR),
we can read counter value of B.I.T. Because B.I.T can be
cleared or read, the spending time up to maximum 65.5ms
can be available. B.I.T is read-only register. If B.I.T reg-
43
GMS81C50 Series
HYUNDAI
ister is written, then CKCTLR register with same address
Basic Interval Timer Register
7
BITR
BIT7
is written.
BIT6
BIT5
BIT4
BIT3
BIT2
0
BIT1
BIT0
R <00C7 h>
11.2 Timer0, Timer1, Timer2
(1) Timer Operation Mode
Timer1 High Data Register (T1HD), Timer1 Low Data
Register (T1LD), Timer2 Data Register (T2DR). Any of
the PS0 ~ PS5, PS11 and external event input EC can be
selected as clock source for T0. Any of the PS0 ~ PS3, PS7
~ PS10 can be selected as clock T1. Any of the PS5 ~ PS12
can be selected as clock source for T2.
Timer consists of 16bit binary counter Timer0 (T0), 8bit
binary Timer1 (T1), Timer2 (T2), Timer Data Register,
Timer Mode Register (TM01, TM0, TM1, TM2) and control circuit. Timer Data Register Consists of Timer0 HighMSB Data Register (T0HMD), Timer0 High-LSB Data
Register (T0HLD), Timer0 Low-MSB Data Register
(T0LMD), Timer0 Low-LSB Data Register (T0LLD),
Timer0
- 16-bit Interval Timer
- 16-bit Event Counter
- 16-bit Input Capture
- 16-bit rectangular-wave output
Timer1
- 8-bit Interval Timer
- 8-bit rectangular-wave output
Timer2
- 8-bit Interval Timer
- 8-bit rectangular-wave output
- Modulo-N Mode
* Relevant Port Mode Register (PMR1 : 00C9 h) value
should be assigned for event counter,
- Single/Modulo-N Mode
- Timer Output Initial Value Setting
- Timer0~Timer1 combination Logic Output
- One Interrupt Generating Every 2nd
Counter Overflow
44
HYUNDAI
GMS81C50 Series
EC / R14
INT2 / R12
(Capture
Signal)
Polarity
Selection
TIMER0 (16 BIT)
16
EDGE
Selection
16
8
8
T0HMD
T0HLD
T1HD
T1LD
8
8
T0LMD
T0LLD
Tout LOGIC
8
T0 OUT / R17
REMOUT
8
TIMER1 (8 BIT)
T1 OUT / R16
TIMER2 (8 BIT)
T2 OUT / R15
T2DR
Figure 11-4 Timer / Counter Block diagram
(2) Function of Timer & Counter
fex = 4MHz
16bit Timer (T0)
8bit Timer (T1)
8bit Timer (T2)
Resolution (CK)
Max. Count
Resolution (CK)
Max. Count
PS0 ( 0.25 us)
16,384 us
PS0 ( 0.25 us)
64 us
PS5 (
8 us)
2.048 us
PS1 ( 0. 5 us)
32,768 us
PS1 (
0.5 us)
128 us
PS6 (
16 us)
4,096 us
PS2 (
1 us)
65,536 us
PS2 (
1 us)
256 us
PS7 (
32 us)
8,192 us
PS3 (
2 us)
131,072 us
PS3 (
2 us)
512us
PS8 (
64 us)
16,384 us
PS4 (
4 us)
262,144 us
PS7 (
32 us)
8,192 us
PS9 ( 128 us)
32,768 us
PS5 (
8 us)
524,288 us
PS8 (
64 us)
16,384 us
PS10 ( 256 us)
65,536 us
PS11 ( 512 us)
33,554,432 us
PS9 ( 128 us)
32,768 us
PS11 ( 512 us)
131,072 us
PS10 ( 256 us)
65,536 us
PS12 (1,024 us)
262,144 us
EC
-
45
Resolution (CK)
Max. Count
GMS81C50 Series
HYUNDAI
Internal Data Bus
<00D5 h>
R/W
<00D0 h>
TM0
7
6
5
4
3
2
1
0
TIMER0 H
COUNT
REG
<00D6 h>
<00D3 h>
TIMER0
HM
DATA
REG
TIMER0 L
COUNT
REG
<00D4 h>
TIMER0
HL
DATA
REG
<00D5 h>
TIMER0
LM
DATA
REG
<00D6 h>
TIMER0
LL
DATA
REG
DATA READ
SINGLE/
MODULO-N
SELECTION
16
16
MUX
16
PS0
PS1
CK
PS2
PS3
Int.
Gen.
MUX
T0 COUNTER
(16 BIT)
PS4
PS5
PS11
D
EC
E
M
U
X
IFT0
Clear
L
A
INT2
EDGE
SELECTION
Y
T0INT
OUTPUT GEN.
Figure 11-5 Block Diagram of Timer0
46
T0 OUT
HYUNDAI
GMS81C50 Series
Internal Data Bus
<00D7 h>
<00D8 h>
<00D8 h>
<00D1h>
TM1
7
6
5
4
3
2
1
0
R/W
TIMER1
H
DATA
REG
TIMER1
COUNT REG
X
TIMER1
L
DATA
REG
SINGLE/
MODULO-N
SELECTION
OUTPUT GEN.
PS0
PS1
CK
PS2
PS3
Int.
T1 COUNTER
(8 BIT)
MUX
PS7
Gen.
PS8
PS9
IFT1
PS10
T1INT
OUTPUT GEN.
Figure 11-6 Block Diagram of Timer1
47
T1OUT
GMS81C50 Series
HYUNDAI
Internal Data Bus
<00D9 h>
<00D9 h>
<00D2 h>
TM2
7
6
5
4
3
2
1
0
R/W
TIMER2
COUNT REG
TIMER2
DATA REG
PS5
PS6
CK
PS7
PS8
IFT2
T2 COUNTER
(8 BIT)
MUX
PS9
PS10
PS11
PS12
OUTPUT GEN.
Figure 11-7 Block Diagram of Timer2
48
T2 OUT
HYUNDAI
GMS81C50 Series
Timer0 / Timer1 Mode Register
7
TM01
TOUTS
TOUTB
-
T0OUTP
T0INIT
T1INIT
0
TOUT1
TOUT0
TOUT0
TOUT1
TOUT LOGIC
0
0
AND of T0 OUTPUT and T1 OUTPUT
0
1
NAND of T0 OUTPUT and T1 OUTPUT
1
0
OR of T0 OUTPUT and T1 OUTPUT
1
1
NOR of T0 OUTPUT and T1 OUTPUT
T1INIT
Timer1 Output Initial Value
0
Timer1 output low
1
Timer1 output high
T0INIT
Timer0 Output Initial Value
0
Timer0 Output Low
1
Timer0 Output High
T0OUTP
T0OUT Polarity Selection
0
T0OUT polarity equal to TOUT logic input signal
1
T0OUT polarity reverse to TOUT logic input signal
TOUTB
REMOUT Port Bit Control
0
REMOUT output low
1
REMOUT output high
TOUTS
REMOUT Port Output Selection
(TOUT logic or TOUTB)
0
Bit (TOUTB) output through REMOUT
1
TOUT logic output through REMOUT
Figure 11-8 Timer0 / Timer1 Mode Register
49
R / W <00DA h>
GMS81C50 Series
HYUNDAI
Timer0 Mode Register
7
TM0
CAP0
T0ST
T0CN
T0MOD
T0IFS
0
T0SL2
T0SL1
T0SL0
R / W <00D0 h>
T0SL2
T0SL1
T0SL0
0
0
0
PS0 (250ns)
0
0
1
PS1 (500ns)
0
1
0
PS2 (
1us)
0
1
1
PS3 (
2us)
1
0
0
PS4 (
4us)
1
0
1
PS5 (
8us)
1
1
0
PS11 (512us)
Event
1
1
1
EC
Counter
T0IFS
Input clock selection
Timer0 Interrupt Selection
0
Interrupt every counter overflow
1
Interrupt every 2nd counter overflow
Timer0 Single/Modulo-N Selection
T0MOD
0
Modulo-N
1
Single
T0CN
Timer0 Counter Continuation/Pause Control
0
Count pause
1
Count contination
Timer0 Start/Stop Control
T0ST
0
Timer0 Stop
1
Timer Start after clear
Timer0 Interrupt Selection
CAP0
0
Timer/Counter
1
Input capture *
* PS1 : not supporting input capture.
Figure 11-9 Timer0 Mode Register
50
Notes
*
HYUNDAI
GMS81C50 Series
Timer1 Mode Register
7
TM1
T1ST
T1CN
T1MOD
0
T1IFS
-
T1SL2
T1SL1
T1SL0
0
0
0
PS0 (250ns)
0
0
1
PS1 (500ns)
0
1
0
PS2 (
1us)
0
1
1
PS3 (
2us)
1
0
0
PS7 ( 32us)
1
0
1
PS8 ( 64us)
1
1
0
PS9 (128us)
1
1
1
PS10 (256us)
T1IFS
T1SL2
T1SL1
Input clock selection
Timer1 Interrupt Selection
0
Interrupt every counter overflow
1
Interrupt every 2nd counter overflow
T1MOD
Timer1 Single/Modulo-N Selection
0
Modulo-N
1
Single
T1CN
Timer1 Counter Continuation/Pause Control
0
Count pause
1
Count contination
T1ST
T1SL0
Timer1 Start/Stop Control
0
Timer1 Stop
1
Timer1 Start after clear
Figure 11-10 Timer1 Mode Register
51
R / W <00D1 h>
GMS81C50 Series
HYUNDAI
Timer2 Mode Register
7
TM2
-
-
-
T2ST
T2CN
0
T2SL2
T2SL1
T2SL2
T2SL1
T2SL0
0
0
0
PS5
(
0
0
1
PS6
( 16us)
0
1
0
PS7
( 32us)
0
1
1
PS8
( 64us)
1
0
0
PS9
( 128us)
1
0
1
PS10 ( 256us)
1
1
0
PS11 ( 512us)
1
1
1
PS12 (1024us)
T2CN
T2SL0
R / W <00D2 h>
Input clock selection
8us)
Timer2 Counter Continuation/Pause Control
0
Count pause
1
Count contination
T2ST
Timer2 Start/Stop Control
0
Timer2 Stop
1
Timer2 Start after clear
Figure 11-11 Timer2 Mode Register
7
IEDS
2)
External Interrupt Signal Edge Selection Register
-
-
IED2H
IED2L
IED1H
IED1L
-
IED*H
IED*L
INT*
0
0
-
0
1
Falling Edge Selection
1
0
Rising Edge Selection
1
1
Both Edge Selection
0
-
Figure 11-12 External Interrupt Signal Edge Selection Register
52
W <00CB h>
HYUNDAI
GMS81C50 Series
(3) Timer0, Timer1
TIMER0 and TIMER1 have an up-counter. When value of
the up-counter reaches the content of Timer Data Register
Concurrence
T0 Data
Registers
Value
(TDR), the up-counter is cleared to ``00 h``, and interrupt
(IFT0, IFT1) is occured at the next clock.
Concurrence
Concurrence
T0 Value
0
CLEAR
CLEAR
INTERRUPT
CLEAR
INTERRUPT
INTERRUPT
IFT0
Interval period
Figure 11-13 Operatiion of Timer0
= ``L``)
For Timer0, the internal clock (PS) and the external clock
(EC) can be selected as counter clock. But Timer1 and
Timer2 use only internal clock. As internal clock. Timer0
can be used as internal-timer which period is determined
by Timer Data Register (TDR). Chosen as external
clock, Timer0 executes as event-counter. The counter execution of Timer0 and Timer1 is controlled by T0CN,
T0ST, CAP0, T1CN, T1ST, of Timer Mode Register TM0
and TM1. T0CN, T1CN are used to stop and start Timer0
and Timer1 without clearing the counter. T0ST, T1ST is
used to clear the counter. For clearing and starting the
counter, T0ST or T1ST should be temporarily set to ``0``
and then set to ``1``. T0CN, T1CN, T0ST and T1ST
should be set ``1``, when Timer counting-up. Controlling
of CAP0 enables Timer0 as input capture. By programming of CAP0 to ``1``, the period of signal from INT2 can
be measured and then, event counter value for INT2 can
be read. During counting-up, value of counter can be read.
Note: In the process of reading 16-bit Timer Data, first
read the upper 8-bit data. Then read the lower 8-bit data,
and read the upper 8-bit data again. If the earlier read upper 8-bit data are matched with the later read upper 8-bit
data, read 16-bit data are correct. If not, caution should be
taken in the selection of upper 8-bit data.
(Example)
1) Upper 8-bit Read 0A 0A
2) Lower 8-bit Read FF 01
3) Upper 8-bit Read 0B 0B
=====================
-
-
0AFF 0B01
Timer execution is stopped by the reset signal (RESET
53
GMS81C50 Series
HYUNDAI
T0 Data
Register
Value
Concurrence
Concurrence
CLEAR
CLEAR
T0 Value
0
INTERRUPT
INTERRUPT
IFT0
0
T0ST
Clear & Start
1
0
T0CN
1
Counter
Stop
Count
Clear
& Count
Stop
Count Clear & Start
continue
Figure 11-14 Start/Stop operation of Timer0
T3
T2
T1
T0
INT2
Figure 11-15 Input capture operation of Timer0
54
HYUNDAI
GMS81C50 Series
* Single/Modulo-N Mode
value of Data Register and occurs Time-out interrupt. The
level of Timer Output port toggle and repeats process of
Timer0 (Timer1) can select initial (T0INIT, T1INIT of
TM01) output level of Timer Output port. If initial level is
``L``, Low-Data Register value of Timer Data Register is
transferred to comparator and T0OUT (T1OUT) is to be
``Low``, if initial level is High? High -Data Register is
transferred and to be ``High``. Single Mode can be set by
Mode Select bit (T0MOD, T1MOD) of Timer Mode Register (TM0, TM1) to ``1`` When used as Single Mode,
Timer counts up and compares with value of Data Register. If the result is same, Time Out interrupt occurs and
level of Timer Output port toggle, then counter stops as reset state. When used as Modulo-N Mode, T0MOD
(T1MOD) should be set ``0``. Counter counts up until the
counting the value which is selected in Data Register.
During Modulo-N Mode, If interrupt select bit (T0IFS,
T1IFS) of Mode Register is ``0``, Interrupt occurs on every Time-out. If it is ``1``, Interrupt occurs every second
time-out.
(*note. Timer Output is toggled whenever time
Note:
out happen)
[ Single Mode ]
8bit / 16bit
counting
Timer Enable initial.
value toggle.
Timer-output toggle.
interrupt occurs.
count stop.
[ Modulo-N Mode ]
8bit / 16bit
counting
Timer Enable initial.
value toggle.
Timer-Output Toggle.
Int occurs (IFS = 1) Each 2nd time out.
Int occurs (IFS = 0) When Time out.
Figure 11-16 Operation Diagram for Single/Modulo-N Mode
(4) Timer 2
When T2ST is set to ``1``, count value of Timer 2 is
cleared and starts counting-up. For clearing and starting
the Timer2. T2ST have to set to ``1`` after set to ``0``. In
order to write a value directly into the T2DR, T2ST should
be set to ``0``. Count value of Timer2 can be read at any
time.
Timer2 operates as a up-counter. The content of T2DR are
compared with the contents of up-counter. If a match is
found. Timer2 interrupt (IFT2) is generated and the upcounter is cleared to ``00 h``. Therefore, Timer2 executes
as a interval timer. Interrupt period is determined by the
count source clock for the Timer2 and content of T2DR.
55
GMS81C50 Series
HYUNDAI
T2 Data
Registers
Value
Concurrence
Concurrence
Concurrence
T2 Value
0
CLEAR
CLEAR
INTERRUPT
INTERRUPT
CLEAR
INTERRUPT
IFT0
Interval period
Figure 11-17 Operation of Timer2
T2 Data
Register
Value
Concurrence
Concurrence
CLEAR
CLEAR
T2 Value
0
INTERRUPT
INTERRUPT
IFT2
T2ST
count stop by 0
count start clear by 1
Counter
Count up
Count Stop
Count
continue
Figure 11-18 Start/Stop of Timer2
56
Count up after clear
HYUNDAI
GMS81C50 Series
12. INTERRUPTS
- 8 interrupt vector
The GMS81C50 Series interrupt circuits consist of Interrupt Mode Register (MOD), Interrupt enable register
(IENH, IENL), Interrupt request flags of IRQH, IRQL,
Priority circuit and Master enable flag ("I" flag of PSW). 8
interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 12-1 .
- Nested interrupt control is possible
- Programmable interrupt mode
- Hardware accept mode
- Software selection accept mode
The GMS81C50 Series contains 8 interrupt sources; 3 externals and 5 internals. Nested interrupt services with priority control is also possible. Software interrupt is nonmaskable interrupt, the others are all maskable interrupts.
- Read and write of interrupt request flag are possible.
- In interrupt accept, request flag is automatically cleared.
- 8 interrupt source (2Ext, 3Timer, BIT, WDT and Key
Scan)
Internal Data Bus
0
-
KSCN
KSCNR
INT1
INT1R
INT2
INT2R
IFT0
T0R
IFT1
T1R
IFT2
T2R
IFWDT
IFBIT
-
-
IENL
7
0
IENH
-
-
-
-
-
7
0
IMOD
7
-
-
INT.
VECTOR
ADDR.
PRIORITY
CONTROL
WDTR
BRK
BITR
IRQ
Standby Mode Release
Figure 12-1 Block Diagram of Interrupt
12.1 Interrupt priority and sources.
Each interrupt vector is independent and has its own priority. Software interrupt (BRK) is also available. Interrupt
source classification is shown in Table 12-1.
57
GMS81C50 Series
Hardwar
e
Interrupt
HYUNDAI
Mask
Priority
non-maskable
-
maskable
-
Interrupt Source
INT Vector High
INT Vector Low
RST (RESET pin)
FFFF
FFFE
0
KSCNR (Key Scan)
FFFB
FFFA
1
INT1R (External Interrupt1)
FFF9
FFF8
2
INT2R (External Interrupt2)
FFF7
FFF6
3
T0R (Timer0)
FFF3
FFF2
4
T1R (Timer1)
FFF1
FFF0
5
T2R (Timer2)
FFEF
FFEE
6
WDTR (Watctdog Timer)
FFE9
FFE8
7
BITR (Basic Interval Timer)
FFE7
FFE6
-
BRK instruction
FFDF
FFDE
Table 12-1 Interrupt Priority & Source
12.2 INTERRUPT CONTROL REGISTER
during interrupt cycle process. The interrupt request flag
maintains ``1`` until the interrupt is accepted or is cleared
in program. In reset state, interrupt request flag register
(IRQH, IRQL) is cleared to ``0``. It is possible to read the
state of interrupt register and to mainpulate the contents of
register and to generate interrupt. (Refer to software interrupt).
I flag of PSW is a interrupt mask enable flag. When I flag
= ``0``, all interrupts become disable. When I flag = ``1``,
interrupts can be selectively enabled and disabled by contents of corresponding Interrupt Enable Register. When interrupt is occured, interrupt request flag is set, and
Interrupt request is detected at the edge of interrupt signal.
The accepted interrupt request flag is automatically cleared
IEN L
IENH
IRQL
IRQH
R/W <00CCh>
-
WDTR
BITE
-
-
-
-
-
KSCNE
INT1E
INT2E
-
T0E
T1E
T2E
-
-
WDTR
BITE
-
-
-
-
-
KSCNE
INT1R
INT2R
-
T0R
T1R
T2R
-
IENL : INTERRUPT ENABLE REGISTER LOW
IENH : INTERRUPT ENABLE REGISTER HIGH
IRQL : INTERRUPT REQUEST REGISTER LOW
IRQH : INTERRUPT REQUEST REGISTER HIGH
58
R/W <00CEh>
R/W <00CDh>
R/W <00CFh>
HYUNDAI
GMS81C50 Series
12.3 INTERRUPT ACCEPT MODE
The interrupt priority order is determined by bit (IM1,
Interrupt Mode Register
7
IMOD
IM0) of IMOD register.
-
-
IM1
IM0
IP3
0
IP2
IP1
IP0
R/W <00CA h>
Assigning by interrupt accept mode bit
IM1
IM0
Priority
0
0
fixed by hardware
0
1
changeable by IP3~ IP0
1
*
Interrupt is inhibited
(1) Selection of Interrupt by IP3-IP0
The condition allow for accepting interrupt is set state of
the interrupt mask enable flag and
the interrupt enable bit must be ``1``. In Reset state, these
IP3 - IP0 registers become all ``0``.
IP3
IP2
IP1
IP0
Selection Interrupt
0
0
0
1
KSCNR (Key Scan)
0
0
1
0
INT1R (External interrupt 1)
0
0
1
1
INT2R (External interrupt 2)
0
1
0
0
Reserved
0
1
0
1
T0R (Timer 0)
0
1
1
0
T1R (Timer 1)
0
1
1
1
T2R (Timer 2)
1
0
0
0
Reserved
1
0
0
1
Reserved
1
0
1
0
WDTR (Watch Dog Timer)
1
0
1
1
BITR (Basic Interval Timer)
1
1
0
0
Reserved
Table 12-2 Interrupt Selection by IP3 - IP0
59
GMS81C50 Series
HYUNDAI
(2) Interrupt Timing
CLOCK
A command before interrupt
interrupt process step
SYNC
Interrupt Request Sampling
Figure 12-2 Interrupt Enable Accept Timing
*Interrupt preprocess step is 8 machine cycle
*Interrupt Request sampling time
*Interrupt overhead
-Maximum 12 machine cycle (When execute DIV
-Maximum 1 + 12 + 8 = 21 machine cycle
instruction)
-Minimum 1 + 0 + 8 = 9 machine cycle
-Minimum 0 machine cycle
(3) The valid timing after executing Interrupt control instructions
I flag is valid just after executing of EI/DI on the contrary.
Interrupt Enable register is valid one instruction after con-
trolling interrupt Enable Register.
12.4 INTERRUPT PROCESSING SEQUENCE
When an interrupt is accepted, the on-going process is
stopped and the interrupt service routine is executed. After
the interrupt service routine is completed it is necessary to
restore everything to the state before the interrupt occured.As soon as an interrupt is accepted, the content of the
program counter and PSW are savedin the stack area. At
the same time, the content of the vector address corresponding to the accepted interrupt, which is in the interrupt
vector table, enters into the program counter and interrupt
service is executed. In order to execute the interrupt service routine, it is necessary to write the jump addresses in
the vector table (FFE0 h ~ FFFF h) corresponding to each
interrupt
* Interrupt Processing Step
1) Store upper byte of Program Counter, SP <= SP
2) Store lower byte of Program Counter, SP <= SP - 1
3) Store Program Status Word, SP <= SP - 2
4) After resetting of I-flag, clear accepted Interrupt Request Flag. (Set B-flag for BRK Instruction)
5) Call Interrupt service routine
60
HYUNDAI
GMS81C50 Series
clock
Interrupt Process Step
ISR
*1
SYNC
R/W
internal
addr bus
SP
PC
internal
data bus
=
OP
CODE
=
OP
CODE
SP-1
=
PCH
SP-2
=
*2
*3
LVA
HVA
=
PCL
=
PSW
new PC
=
``L``
vector
``H``
vector
internal
READ
*1 ISR
*2 LVA
*3 HVA
internal
WRITE
: Interrupt Service
Routine
: Low Vector Address
: High Vector Address
Figure 12-3 Interrupt Procesing Step Timing
12.5 SOFTWARE INTERRUPT (Interrupt by Break (BRK) Instruction)
S o f t w ar e in t e r r u p t i s a v ai l ab l e j u s t b y w r i t in g
``Break(BRK)`` instruction. The values of PC and PSW is
stacked by BRK instruction and then B flag of PSW is set
and I flag is reset.
Flag change by BRK execution
PSW
N
V
G
B
PSW
N
V
G
1
H
I
H
0
set
Z
C
Z
C
reset
(Right after BRK execution)
Interrupt vector of BRK instruction is shared by vector of
Table Call (TCALL0). When both instruction of BRK and
TCALL0 are used, as shown in Figure 12-4 each process-
ing routine is judged by contents of B flag. There is no instruction to reset directly B flag.
61
GMS81C50 Series
HYUNDAI
0
B flag
1
BRK or
TCALL0
BRK INTERRUPT ROUTINE
TCALL0 ROUTINE
RETI
RET
Figure 12-4 Execution of BRK or TCALL0
12.6 MULTIPLE INTERRUPT
and each enable bit can accept interrupt request. When two
or more interrupts are generated simultaneously, the highest priority interrupt set by Interrupt Mode Register is accepted.
If there is an interrupt, Interrupt Mask Enable Flag is automatically cleared before entering the Interrupt Service
Routine. After then, no interrupt is accepted. If EI instruction is executed, interrupt mask enable bit becomes ``1``,
12.7 Key Scan Input Processing
(1) Standby Mode Release Register (SMRR)
set for correct interrupt executing, SLEEP mode and STOP
mode, the rest of executing is the same as that of external
Interrupt. Each SMRR Register bit is allowed for each port
(for Bit= ``0``, no Key Input, for Bit= ``1``, Key Input
available). At reset, SMRR becomes ``00 h``. So, there is
no Key Input source.
Key Scan Interrupt is generated by detecting low or high
Input from each Input pin (R0, R1) is one of the sources
which release standby (SLEEP, STOP) mode. Key Scan
ports are all 16bit which are controlled by Standby Mode
Release Register (SMRR0, SMRR1). Key Input is considered as Interrupt, therefore, KSCNE bit of IEHN should be
62
HYUNDAI
GMS81C50 Series
7
0
W <00DC h>
SMRR0
Internal
Key Scan
Interrupt
R00
R01
.
.
.
R07
R0 port
Selection Logic
0
7
W <00DD h>
SMRR1
R10
R11
.
.
.
R17
R0 port
Selection Logic
Figure 12-5 Key Scan Block
SMRR0 Register
7
SMRR0
KR07
KR06
KR05
SMRR1
KR03
0
KR02
KR01
KR00
KR12
KR11
KR10
SMRR1 Register
7
KR17
KR04
KR16
KR15
KR14
KR13
63
W <00DC h>
0
W <00DD h>
GMS81C50 Series
HYUNDAI
SMRR0
SMRR1
0
KR07
Key Input Selection
0
no select
1
select
0
no select
1
select
0
no select
1
select
0
no select
1
select
0
no select
1
select
0
no select
1
select
0
no select
1
select
0
no select
1
select
KR17
1
0
KR16
KR06
1
0
KR05
KR15
1
0
KR04
KR14
1
0
KR03
KR13
1
0
KR12
KR02
1
0
KR11
KR01
1
0
KR10
KR00
1
(2) Standby Release Level Control Register (SRLC)
Standby release level control register (SRLC) can select
the key scan input level ``L`` or ``H`` for standby release
by each bit pin (R0, R1). Standby release level control reg-
SRLC0 Register
7
SRLC0
KLR07
KLR06
KLR05
KLR17
KLR04
KLR03
0
KLR02
KLR01
KLR00
KLR12
KLR11
KLR10
SRLC1 Register
7
SRLC1
ister (SRLC) is write-only register and initialized as ``00
h`` in reset state.
KLR16
KLR15
KLR14
KLR13
64
W <00F6 h>
0
W <00F7 h>
HYUNDAI
GMS81C50 Series
SRLC0
SRLC1
0
KLR07
Key Input Level
0
Low
1
High
0
Low
1
High
0
Low
1
High
0
Low
1
High
0
Low
1
High
0
Low
1
High
0
Low
1
High
0
Low
1
High
KLR17
1
0
KLR16
KLR06
1
0
KLR05
KLR15
1
0
KLR04
KLR14
1
0
KLR03
KLR13
1
0
KLR12
KLR02
1
0
KLR11
KLR01
1
0
KLR10
KLR00
1
65
GMS81C50 Series
HYUNDAI
13. WATCH DOG TIMER
Watch Dog Timer (WDT) consists of 6-bit binary counter,
6-bit comparator, and Watch Dog Timer Register
(WDTR).
0
5
CLR
IFBIT
WDT0
WDT1
WDT2
WDT3
WDT4
WDTON
WDT5
To Reset circuit
6BIT COMPARATOR
IF WDT
WDTR
WDTR0
WDTR1
WDTR2
WDTR3
WDTR4
WDTR5
0
WDTCL
W <00C8 h>
6
Internal Data Bus
Figure 13-1 Block diagram of Watch Dog Timer
13.1 Control of WDT
Watch Dog Timer can be used 6-bit general Timer or specific Watch dog timer by setting
Clock Control Register
7
CKCTLR
-
bit5 (WDTON) of Clock Control Register (CKCTLR).
-
WDTON
ENPCK
BTCL
BTS2
0
BTS1
WDTON
Watch Dog Timer Function Control
0
6-bit Timer
1
Watch Dog Timer
By assigning bit6(WDTCL) of WDTR, 6-bit counter can
be cleared.
66
BTS0
W <00C7 h>
HYUNDAI
GMS81C50 Series
Watch DOG Timer Register
7
WDTR
-
WDTCL
WDTR5
WDTR4
WDTR3
WDTR2
0
WDTR1
WDTR0
W <00C8 h>
Determine Interval of IFWDT
Interval of IFWDT = Value of WDTR > Interval of IFBIT
WDTCL
Watch Dog Timer Operation
0
free-run
1
Automatically cleared, after one machine cycle
13.2 WDT Interrupt Interval
WDT Interrupt (IFWDT) interval is determined by the interrupt IFBIT interval of Basic Interval Timer and the value of WDT Register.
-Interval of IFWDT = (IFBIT interval) * (WDTR value)
*At Hardware reset time ,WDT starts automatically.
Therefore, the user must select the CKCTLR, WDTR before WDT overflow.
-Interval of IFWDT : 512 us * 1 = 512 us (MIN>)
-Reset WDTR value = 0F h,15
-65,536us * 63 = 4,128,768 us (MAX>)
-interval of WDT = 65,536 * 15 = 983040 us
(about 1second )
As IFBIT (Basic Interval Timer Interrupt Request) is used
for input clock of WDT, Input clock cycle is possible from
512 us to 65,536 us by BTS. (at fex = 4MHz)
67
GMS81C50 Series
HYUNDAI
Clock Control Register
7
CKCTLR
ENPCK
BTCL
BTS2
0
-
-
WDTON
BTS1
BTS0
BTS2
BTS1
BTS0
WDT Input clock
0
0
0
512 us
32,756 us
0
0
1
1,024 us
64,512 us
0
1
0
2,048 us
129,024 us
0
1
1
4,096 us
258,048 us
1
0
0
8,192 us
516,096 us
1
0
1
16,384 us
1,032,192 us
1
1
0
32,768 us
2,064,384 us
1
1
1
65,536 us
4,128,768 us
W <00C7 h>
Max. Interval of WDT
Output (*note1)
Device come into the reset state by WDT
N o t e : W h en W D T R R eg i st e r v al u e is 6 3 ( 3F h )
(Caution) : Do not use ``0`` for WDTR Register value.
68
HYUNDAI
GMS81C50 Series
14. STANDBY FUNCTION
To save power consumption, there is STOP modes. In this
modes, the execution of program stops.
14.1 Sleep Mode
release SLEEP mode by BITR (basic interval timer interrupt), bit10 of prescaler should be selected as B.I.T input
clock before entering SLEEP mode. ``NOP`` instruction
should be follows setting of SLEEP mode for rising precharge time of data bus line.
SLEEP mode can be entered by setting the bit of SLEEP
mode register (SLPM). In the mode, CPU clock stops but
oscillator keeps running. B.I.T and a part of peripheral
hardware execute, but prescalerís output which provide
clock to peripherals can be stopped by program. (Except,
PS10 canít stopped.) In SLEEP mode, more consuming
power can be saved by not using other peripheral hardware
except for B.I.T. By setting ENPCK (peripheral clock control bit) of CKCTLR (clock control register) to ``0``, peripheral hardware halted, and SLEEP mode is entered. To
-
-
-
-
-
NOP
: NOP instruction
0
-
-
-
SLPM0
condition
0
sleep mode release
1
sleep mode
SLPM0
Colck Control Register
7
CKCTLR
; mode register (SLPM)
SLEEP MODE CONTROL Register
7
SLPM
(ex) setting of SLEEP mode : set the bit of SLEEP
-
WDTON
ENPCK
BTCL
W <00F0 h>
0
BTS2
BTS1
ENCPK
Peripheral Clock
0
stopped
1
provided
BTS0
W <00C8 h>
14.2 STOP MODE
time of Data Bus line.
STOP mode can be entered by STOP instruction during
program. In STOP mode, oscillator is stopped to make all
clocks stop, which leads to less power consumption. All
registers and RAM data are preserved. ``NOP`` instruction
should be follows STOP instruction for rising precharge
(ex)
69
STOP
: STOP instruction execution
NOP
: NOP instruction
GMS81C50 Series
HYUNDAI
OSC.
Clock Pulse GEN
Circuit
CLR
CPU Clock
MUX
Basic Interval Timer
CLR
Prescaler
CLR
STOP
S
Q
R
S
Q
R
Control
Signal
Overflow Detection
Release Signal From Interrupt Circuit
RESET
Figure 14-1 Block Diagram of Standby Circuit
Prescaler
ENPCK
PS10
Selector
Basic Interval Timer
Peripheral
Figure 14-2 ENPCK and Basic Interval Timer Clock
70
B.I.T 7
HYUNDAI
GMS81C50 Series
14.3 STANDBY MODE RELEASE
Release of STANDBY mode is executed by RESET input
and Interrupt signal. Register value is defined when Reset.
When there is a release signal of STOP mode (Interrupt,
RESET input), the instruction execution starts after stabilization oscillation time is set by value of BTS2 ~ BTS0
and set ENPCK to ``1``.
Release Signal
SLEEP
STOP
RESET
O
O
KSCN (key input)
O
O
INT1 , INT2
O
O
B.I.T
O
X
Table 14-1 Standby Mode Register
Release Factor
RESET
KSCN
(key input)
INT1
INT2
Basic Interval Timer
(IFBIT)
Release Method
By RESET Pin = Low level, Standby mode is release and system is initialized
Standby mode is released by low input of selected pin by key scan Input
(SMRR0, SMRR1) In case of interrupt mask enable flag = ``0``,
program executes just after standby instruction,
if flag = ``1``, enters each interrupt service routine.
When external interrupt (INT1, INT2) enable flag is ``1``, standby mode is released
at the rising edge of each terminal. When Standby mode is released at interrupt.
Mask Enable flag = ``0``, program executes from the next instruction of standby
instruction. When ``1``, enters each interrupt service routine.
When B.I.T is executed only by bit10 of prescaler (PS10), SLEEP mode can be
release. Interrupt release SLEEP mode, when BIT interrupt enable flag is ``1``.
When standby mode is released at interrupt. Mask enable flag = ``0``,
program executes from the next instruction of SLEEP instruction.
When ``1``, enters each interrupt service routine.
Table 14-2 Standby Mode Release
71
GMS81C50 Series
HYUNDAI
[ SLEEP MODE ]
SLEEP command
Xin
SLEEP Mode
release by interrupt
RESET
Longer than
2 machine cycle
[ STOP MODE ]
clock
Stable
OSC. time
STOP Mode
release by interrupt
Program Setting Time by
CKCTLR
RESET
Longer than
stable OSC. Time
Figure 14-3 Release Timing of Standby Mode
14.4 RELEASE OPERATION OF STANDBY MODE
= ``1``, and jump to the relevant interrupt service routine.
After standby mode is released, the operation begins according to content of related interrupt register just before
standby mode start (Figure 14-4 )
Note: When STOP instruction is used, B.I.T should guarantee the stabilization oscillation time. Thus, just before entering STOP mode, clock of bit10 (PS10) of prescaler is
selected or peripheral hardware clock control bit (ENPCK)
to ``1``, Therefore the clock necessary for stabilization oscillation time should be input into B.I.T. otherwise, standby
mode is released by reset signal. In case of interrupt request flag and interrupt enable flag are both ``1``, standby
mode is not entered.
(1) Interrupt Enable Flag(I) of PSW = ``0``
Release by only interrupt which interrupt enable flag =
``1``, and starts to execute from next to standby instruction
(SLEEP or STOP).
(2) Interrupt Enable Flag(I) of PSW = ``1``
Released by only interrupt which each interrupt enable flag
72
HYUNDAI
GMS81C50 Series
STOP Command
Standby Mode
Interrupt Request GEN.
0
IE Flag
1
Standby Mode Release
0
PSW
IE Flag
1
Standby Next Command
Execution
Interrupt Service Routine
Figure 14-4 Standby Mode Release Flow
Internal circuit
SLEEP mode
STOP mode
Oscillator
Active
Stop
Internal CPU clock
Stop
Stop
Register
Retained
Retained
RAM
Retained
Retained
I/O port
Retained
Retained
Prescaler
Active
Retained
Basic Interval Timer
PS10 selected : Active
Others : Stop
Stop
Watch Dog Timer
Stop
Stop
Timer
Stop
Stop
Address Bus, Data Bus
Retained
Retained
Table 14-3 Operation State in Standby Mode
73
GMS81C50 Series
HYUNDAI
15. OSCILLATION CIRCUIT
pulse generator, and then enters prescaler to make peripheral hardware clock. Alternately, the oscillator may be
driven from an external source as shown is Fig. 4.2.-(b). In
the Standby (STOP) mode, oscillatiion stop, Xout state
goes to ``HIigh``, Xin state goes to ``Low``, and built-in
feed back resistor is disabled.
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Fig. 4.2-(a) shows
circuit diagrams using a crystal (or ceramic) oscillator. As
shown in the diagram, oscillation circuits can be constructed by connecting a oscillator between Xout and Xin.
Clock from oscillation circuit makes CPU clock via clock
(a) External Crystal (Ceramic) oscillator circuit
Cout
Xout
Xin
Cin
(b) External clock input circuit
Xout
Xin
External clock
Figure 15-1 Oscillator configurations
* Recommendable resonator
Frequency
4.0 MHz
Resonator Maker
Part Name
Load Capacitor
Operating Voltage
CQ
ZTA4.00MG
Cin=Cout=30pF
2.2 ~ 4.0V
TDK
FCR4.0MC5
Cin=Cout=open
2.2 ~ 4.0V
TDK
FCR4.0M5
Cin=Cout=33pF
2.2 ~ 4.0V
TDK
CCR4.0MC3
* MC type is building in load capacitior.CCR type is chip type.
74
2.2 ~ 4.0V
HYUNDAI
GMS81C50 Series
16. RESET FUNCTION
16.1 EXTERNAL RESET
The RESET pin should be held at low for at least 2machine
cycles with the power supply voltage within the operating
voltage range and must be connected 0.1uF capacitor for
stable system initialization. The RESET pin contains a
Schmitt trigger with an internal pull-up resistor.
RESET
0.1 uF Capacitor
Figure 16-1
16.2 POWER ON RESET
detection circuit.
Power On Reset circuit automatically detects the rise of
power voltage (the rising time should be within 50ms) the
power voltage reaches a certain level, RESET terminal is
maintained at °»L°» Level until a crystal ceramic oscillator
oscillates stably. After power applies and starting of oscillation, this reset state is maintained for about oscillation
cycle of 219 (about 65.5ms : at 4MHz).The execution of
built-in Power On Reset circuit is as follows :
(2) Once B.I.T Overflow detection circuit is reset. Then,
Prescaler starts to count.
(3) Prescaler output is inputted into B.I.T and PS10 of
Prescaler output is automatically selected. If overflow of
B.I.T is detected, Overflow detection circuit is set.
(4) Reset circuit generates maximum period of reset pulse
from Prescaler and B.I.T.
(1) Latch the pulse from Power On Detection Pulse Generator circuit, and reset Prescaler, B.I.T and B.I.T Overflow
Internal IC
VDD
Internal Reset
RESET
0.1uF
Power On DET
Pulse GEN.
VSS
XTAL
OSC.
CLR
PS10
Prescaler
CLR
MSB
CLR
Basic Interval
Basic Interval
Tiemr
Tiemr
Figure 16-2 Block Diagram of Power On Reset Circuit
75
GMS81C50 Series
HYUNDAI
Note: Notice ; When Power On Reset, oscillator stabilization time doesn`t include OSC. Start time.
$ 14$ 26%%1 %
??
2 %1 %%,8,6@
Figure 16-3 Oscillator stabilization diagram
RESET
INTERNAL
RESET
ADDR. BUS
SP
SP-1
INTERNAL
DATA BUS
SP-2
FFFE FFFF
FE
NEW PC
LSB
MSB
VECTOR VECTOR
Figure 16-4 Reset Timing by Diagram
16.3 Low Voltage Detection Mode
(1) Low voltage detection condition
(2) Low Voltage Detection Mode
An on board voltage comparator checks that VDD is at the
required level to ensure correct operation of the device. If
VDD is below a certain level, Low voltage detector forces
the device into low voltage detection mode.
There is no power consumption except stop current, stop
mode release function is disabled. All I/O port is configured as input mode and Data memory is retained until voltage through external capacitor is worn out. In this mode,
all port can be selected with Pull-up resistor by Mask option. If there is no information on the Mask option sheet
,the default pull up option (all port connect to pull-up resis-
76
HYUNDAI
GMS81C50 Series
tor ) is selected.
the low voltage detection mode and come into normal reset
state. It depends on user whether to execute RAM clear
routine or not.
(3) Release of Low Voltage Detection Mode
Reset signal result from new battery(normally 3V) wakes
4 * '(
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
10
20
30
40
50
60
%'(
Figure 16-5 Low Voltage vs Temperature
(4) SRAM BACK-UP after Low Voltage Detection.
77
70
GMS81C50 Series
HYUNDAI
3.0V
about hours depend on Vcc-Gnd Capacitor
MCU OPR.
Voltage
Low Voltage Detection
point
Power On Reset
( SRAM retention)
1.8V(TYP)
( 20(
Power On Reset
( SRAM unstable )
0.7V(VRET)
0V
* SRAM Data Backup
* The operation after Low voltage detection
Interrupt
: disable
User
Stop release : disable
Removes
All I/O port : input Mode
Batteries
Remout port : Low Level
OSC
: STOP
All I/O port pull-up ON (Mask Option )
SRAM Data retention
User
Replace
Batteries
Figure 16-6 Low Voltage Detection and Protection
(5) S/W flow chart example after Reset using SRAM Back-up
RESET
Stack Pointer initialize
Check the SRAM value
(RAM Pattern, Check sum..)
SRAM DATA IS VALID?
N
Clear All Ram area
Y
Use saved SRAM
value
Figure 16-7 S/W Flow Chart Example for SRAM Back-up
78
HYUNDAI
GMS81C50 Series
16.4 Low Voltage Indicator Register (LVIR)
The bit of LVIR register could be set according to the VDD
level sequentially. The VDD dection levels for Indication
are two , that is , Bit1 and Bit0 of LVIR Register. The detection level of Bit0 is higer than Bit1.
Low Voltage Indication Register (LVIR) is read only Register. It is useful to display the consumption of Batteries.
If VDD power level is below a cirtain level which is higher
than low voltage detection level ( refer to Figure 16-6 ) ,
bit
7
6
5
4
3
2
1
0
LVIR
-
-
-
-
-
-
LVIR1
LVIR0
initial value
-
-
-
-
-
-
0
0
R/W
-
-
-
-
-
-
R
R
79
<00EF h>
GMS81C50 Series
HYUNDAI
80
Appendix A. GMS800 Series Instruction
1. Instruction Map
LOW
HIGH
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
000
001
CLRC
SET1
BBS
BBS
ADC
ADC
ADC
ADC
ASL
ASL
TCALL
POP
PUSH
A.bit,rel
dp.bit,rel
#imm
dp
dp+X
!abs
A
dp
0
SETA1
.bit
BIT
dp.bit
dp
A
A
//
//
//
010
CLRG
//
//
//
011
DI
//
//
//
100
CLRV
//
//
//
101
SETC
//
//
//
110
SETG
//
//
//
111
EI
//
//
//
10000
10001
10010
10
11
12
BPL
CLR1
rel
dp.bit
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
LOW
HIGH
000
001
010
011
100
101
110
111
BVC
rel
BCC
rel
BNE
rel
BMI
rel
BVS
rel
BCS
rel
BEQ
rel
BRK
SBC
SBC
ROL
ROL
TCALL
CLRA1
COM
POP
!abs
A
dp
2
.bit
dp
X
PUSH
X
BRA
dp
SBC
dp+X
SBC
#imm
CMP
#imm
CMP
dp
CMP
dp+X
CMP
!abs
LSR
A
LSR
dp
TCALL
4
NOT1
M.bit
TST
dp
POP
Y
PUSH
Y
PCALL
Upage
OR
OR
OR
OR
ROR
ROR
TCALL
OR1
PUSH
dp
dp+X
!abs
A
dp
6
OR1B
CMPX
dp
POP
#imm
PSW
PSW
AND
AND
AND
AND
INC
INC
TCALL
AND1
CMPY
CBNE
#imm
dp
dp+X
!abs
A
dp
8
AND1B
dp
dp+X
EOR
EOR
EOR
EOR
DEC
DEC
TCALL
EOR1
DBNE
XMA
#imm
dp
dp+X
!abs
A
dp
10
EOR1B
dp
dp+X
LDA
LDA
LDA
LDA
LDY
TCALL
LDC
LDX
LDX
#imm
dp
dp+X
!abs
dp
12
LDCB
dp
dp+Y
STY
TCALL
STC
STX
STX
dp
14
M.bit
dp
dp+Y
TXA
TXSP
TSPX
rel
RET
INC
X
DEC
X
XCN
DAS
XAS
STOP
LDM
STA
STA
STA
dp,#imm
dp
dp+X
!abs
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
BBC
BBC
ADC
ADC
ADC
ADC
ASL
ASL
TCALL
ADDW
LDX
JMP
dp.bit,rel
{X}
!abs+Y
[dp+X]
[dp]+Y
!abs
dp+X
1
JMP
!abs
BIT
A.bit,rel
!abs
dp
#imm
[!abs]
SBC
SBC
ROL
ROL
TCALL
CALL
TEST
SUBW
[dp]+Y
!abs
dp+X
3
!abs
!abs
dp
LDY
#imm
JMP
!abs+Y
SBC
[dp+X]
SBC
{X}
CMP
{X}
CMP
!abs+Y
CMP
[dp+X]
CMP
[dp]+Y
LSR
!abs
LSR
dp+X
TCALL
5
MUL
TCLR1
!abs
CMPW
dp
CMPX
#imm
CALL
[dp]
CMPX
!abs
LDYA
CMPY
dp
#imm
CMPY
INCW
INC
!abs
dp
Y
TAX
OR
OR
OR
OR
ROR
ROR
TCALL
DBNE
{X}
!abs+Y
[dp+X]
[dp]+Y
!abs
dp+X
7
Y
AND
AND
AND
AND
INC
INC
TCALL
{X}
!abs+Y
[dp+X]
[dp]+Y
!abs
dp+X
9
DIV
EOR
EOR
EOR
EOR
DEC
DEC
TCALL
XMA
XMA
DECW
DEC
{X}
!abs+Y
[dp+X]
[dp]+Y
!abs
dp+X
11
{X}
dp
dp
Y
LDA
LDA
LDA
LDA
LDY
LDY
TCALL
LDA
LDX
STYA
{X}
!abs+Y
[dp+X]
[dp]+Y
!abs
dp+X
13
{X}+
!abs
dp
STA
STA
STA
STA
STY
STY
TCALL
STA
STX
CBNE
{X}
!abs+Y
[dp+X]
[dp]+Y
!abs
dp+X
15
{X}+
!abs
dp
A-1
[dp]
RETI
TAY
TYA
XAY
DAA
XYX
NOP
Appendix A. GMS800 Series Instruction
2. Alphabetic order table of instruction
NO.
MNENONIC
OP
CODE
BYTE
NO.
CYCLE
NO
OPERATION
1
ADC #imm
04
2
2
Add with carry.
2
ADC dp
05
2
3
A ← A + (M) + C
3
ADC dp + X
06
2
4
4
ADC !abs
07
3
4
5
ADC !abs+Y
15
3
5
6
ADC [dp+X]
16
2
6
7
ADC [dp]+Y
17
2
6
FLAG
NVGBHIZC
NV - - H - ZC
8
ADC {X}
14
1
3
9
ADDW dp
1D
2
5
16-bits add without carry : YA ← YA + (dp+1)(dp)
10
AND #imm
84
2
2
Logical AND
11
AND dp
85
2
3
A ← A ^ (M)
12
AND dp + X
86
2
4
13
AND !abs
87
3
4
14
AND !abs+Y
95
3
5
15
AND [dp+X]
96
2
6
16
AND [dp] + Y
97
2
6
17
AND {X}
94
1
3
18
AND1 M.bit
8B
3
4
Bit AND C-flag : C ← C ^ (M.bit)
-------C
19
AND1B M.bit
8B
3
4
Bit AND C-flag and NOT : C ← C ^ ~(M.bit)
-------C
Arithmetic shift left
NV - - H - ZC
N-----Z-
20
ASL A
08
1
2
21
ASL dp
09
2
4
22
ASL dp + X
19
2
5
23
ASL !abs
18
3
5
24
BBC A.bit,rel
y2
2
4/6
Branch if bit clear :
25
BBC dp.bit,rel
y3
3
5/7
if(bit) = 0, then PC ← PC + rel
26
BBS A.bit,rel
x2
2
4/6
Branch if bit clear :
27
BBS dp.bit,rel
x3
3
5/7
if(bit) = 1, then PC ← PC + rel
28
BCC rel
50
2
2/4
Branch if carry bit clear :
if(C) = 0, then PC ← PC + rel
29
BCS rel
D0
2
2/4
Branch if carry bit set : If (C) =1, then PC ← PC + rel
--------
30
BEQ rel
F0
2
2/4
Branch if equal : if (Z) = 1, then PC ← PC + rel
--------
31
BIT dp
0C
2
4
Bit test A with memory :
32
BIT !abs
1C
3
5
Z ← A ^ M, N ← (M7), V ← (M6)
C
7 6 5 4 3 2 1 0
← ← ← ← ← ← ← ← ← ← "0"
N - - - - - ZC
--------------MM - - - - Z -
MM - - - - Z -
33
BMI rel
90
2
2/4
Branch if munus : if (N) = 1, then PC ← PC + rel
--------
34
BNE rel
70
2
2/4
Branch if not equal : if (Z) = 0, then PC ← PC + rel
--------
35
BPL rel
10
2
2/4
Branch if not minus : if (N) = 0, then PC ← PC + rel
--------
36
BRA rel
2F
2
4
Branch always : PC ← PC + rel
--------
37
BRK
0F
1
8
Software interrupt:
B ← “1”, M(SP) ← (PCH), SP ← SP - 1,
M(s) ← (PCL), SP ← S - 1, M(SP) ← PSW,
---1-0--
SP ← SP - 1, PCL ← (0FFDEH), PCH ← (0FFDFH)
38
BVC rel
30
2
2/4
Branch if overflow bit clear :
If (V) = 0, then PC ← PC + rel
39
BVS rel
B0
2
2/4
Branch if overflow bit set :
If (V) = 1, then PC ← PC + rel
A-2
---------------
Appendix A. GMS800 Series Instruction
NO.
MNENONIC
OP
CODE
BYTE
NO.
CYCLE
NO
OPERATION
FLAG
NVGBHIZC
--------
40
CALL !abs
3B
3
8
Subroutine call
41
CALL [dp]
5F
2
8
M(SP) ← (PCH), SP ← SP-1, M(SP) ← (PCL), SP←SP-1
if !abs, PC ← abs ; if [dp], PCL ← (dp), PCH ← (dp+1)
42
CBNE dp,rel
FD
3
5/7
Compare and branch if not equal ;
43
CBNE dp + X, rel
8D
3
6/8
If A ≠ (M), then PC ← PC + rel.
44
CLR1 dp.bit
y1
2
4
Clear bit : (M.bit) ← “0”
45
CLR1A A.bit
2B
2
2
Clear A.bit : (A.bit) ← “0”
--------
46
CLRC
20
1
2
Clear C-flag : C ← “0”
-------0
47
CLRG
40
1
2
Clear G-flag : G ← “0”
--0-----
48
CLRV
80
1
2
Clear V-flag : V ← “0”
-0--0---
49
CMP #imm
44
2
2
Compare accumulator contents with memory contents
50
CMP dp
45
2
3
A - (M)
51
CMP dp + X
46
2
4
52
CMP !abs
47
3
4
53
CMP !abs + Y
55
3
5
54
CMP [dp + X]
56
2
6
55
CMP [dp] + Y
57
2
6
56
CMP {X}
54
1
3
57
CMPW dp
5D
2
4
---------------
N - - - - - ZC
Compare YA contents with memory pair contents :
N - - - - - ZC
YA - (dp+1)(dp)
58
CMPX #imm
5E
2
2
Compare X contents with memory contents
59
CMPX dp
6C
2
3
X - (M)
60
CMPX !abs
7C
3
4
61
CMPY #imm
7E
2
2
Compare Y contents with memory contents
62
CMPY dp
8C
2
3
Y - (M)
63
CMPY !abs
9C
3
4
N - - - - - ZC
N - - - - - ZC
64
COM dp
2C
2
4
1’s complement : (dp) ← ~(dp)
N-----Z-
65
DAA
DF
1
3
Decimal adjust for addition
N - - - - - ZC
66
DAS
CF
1
3
Decimal adjust for substraction
N - - - - - ZC
67
DBNE dp,rel
AC
3
5/7
Decrement and branch if not equal :
68
DBNE Y,rel
7B
2
4/6
if (M) ≠ 0, then PC ← PC + rel.
69
DEC A
A8
1
2
Decrement
70
DEC dp
A9
2
4
M←M-1
71
DEC dp + X
B9
2
5
72
DEC !abs
B8
3
5
73
DEC X
AF
1
2
74
DEC Y
BE
1
2
75
DECW dp
BD
2
6
Decrement memory pair : (dp+1)(dp) ← {(dp+1)(dp)} - 1
76
DI
60
1
3
Disable interrupts : I ← “0”
77
DIV
9B
1
12
Divide : YA/X ← Q:A, R:Y
NV - - H - Z -
78
EI
E0
1
3
Enable interrupts : I ← “1”
-----1--
--------
N-----Z-
A-3
N-----Z-----0--
Appendix A. GMS800 Series Instruction
NO.
MNENONIC
OP
CODE
BYTE
NO.
CYCLE
NO
OPERATION
FLAG
NVGBHIZC
79
EOR #imm
A4
2
2
Exclusive OR
80
EOR dp
A5
2
3
A ← A ⊕ (M)
81
EOR dp + X
A6
2
4
82
EOR !abs
A7
3
4
83
EOR !abs + Y
B5
3
5
84
EOR [ dp + X]
96
2
6
85
EOR [dp] + Y
97
2
6
86
EOR {X}
94
1
3
87
EOR1 M.bit
AB
3
5
Bit exclusive-OR C-flag : C ← C ⊕ (M.bit)
-------C
88
EOR1B M.bit
AB
3
5
Bit exclusive-OR C-flag and NOT : C ← C ⊕ ∼(M.bit)
-------C
89
INC A
88
1
2
Increment
N - - - - - ZC
90
INC dp
89
2
4
(M) ← (M) + 1
91
INC dp + X
99
2
5
92
INC !abs
98
3
5
93
INC X
8F
1
2
94
INC Y
9E
1
2
95
INCW dp
9D
2
6
Increment memory pair : (dp+1)(dp) ← {(dp+1)(dp)} + 1
96
JMP !abs
1B
3
3
Unconditional jump
97
JMP [!abs]
1F
3
5
PC ← jump address
98
JMP [dp]
3F
2
4
N-----Z-
N-----Z-
99
LDA #imm
C4
2
2
Load accumulator
100
LDA dp
C5
2
3
A ← (M)
101
LDA dp + X
C6
2
4
102
LDA !abs
C7
3
4
103
LDA !abs + Y
D5
3
5
104
LDA [dp + X]
D6
2
6
6
N-----Z--------
N-----Z-
105
LDA [dp]+Y
D7
2
106
LDA {X}
D4
1
3
107
LDA {X}+
DB
1
4
108
LDC M.bit
CB
3
4
Load C-flag : C ← (M.bit)
-------C
109
LDCB M.bit
CB
3
4
Load C-flag with NOT : C ← ~(M.bit)
-------C
110
LDM dp,#imm
E4
3
5
Load memory with immediate data : (M) ← imm
--------
111
LDX #imm
1E
2
2
Load X-register
X ← (M)
X-register auto-increment : A ← (M), X ← X + 1
112
LDX dp
CC
2
3
113
LDX dp + Y
CD
2
4
114
LDX !abs
DC
3
4
115
LDY #imm
3E
2
2
Load X-register
116
LDY dp
C9
2
3
Y ← (M)
117
LDY dp + Y
D9
2
4
4
118
LDY !abs
D8
3
119
LDYA dp
7D
2
5
Load YA : YA ← (dp+1)(dp)
120
LSR A
48
1
2
Logical shift right
121
LSR dp
49
2
4
122
LSR dp + X
59
2
5
123
LSR !abs
58
3
5
7 6 5 4 3 2 1 0
C
"0"→ → → → → → → → → →
A-4
N-----Z-
N-----Z-
N-----Z-
N - - - - - ZC
Appendix A. GMS800 Series Instruction
NO.
MNENONIC
OP
CODE
BYTE
NO.
CYCLE
NO
OPERATION
FLAG
NVGBHIZC
124
MUL
5B
1
9
Multiply : YA ← Y x A
125
NOP
FF
1
2
No operation
--------
126
NOT1 M.bit
4B
3
5
Bit complement : (M.bit) ← ~(M.bit)
--------
127
OR #imm
64
2
2
Logical OR
A ← A V (M)
128
OR dp
65
2
3
129
OR dp + X
66
2
4
130
OR !abs
67
3
4
131
OR !abs + Y
75
3
5
N-----Z-
N-----Z-
132
OR [dp +X}
76
2
6
133
OR [dp] + Y
77
2
6
134
OR {X}
74
1
3
135
OR1 M.bit
6B
3
5
Bit OR C-flag : C ← C V (M.bit)
-------C
136
OR1B M.bit
6B
3
5
Bit OR C-flag and NOT : C ← C V ~(M.bit)
-------C
137
PCALL
4F
2
6
U-page call : M(SP) ← (PCH), SP ← SP -1,
M(SP) ← (PCL), SP ← SP -1,
--------
PCL ← (upage), PCH ←"OFFH"
138
POP A
0D
1
4
Pop from stack
139
POP X
2D
1
4
SP ← SP + 1, Reg. ← M(SP)
140
POP Y
4D
1
4
141
POP PSW
6D
1
4
142
PUSH A
0E
1
4
Push to stack
M(SP) ← Reg.
143
PUSH X
2E
1
4
144
PUSH Y
4E
1
4
145
PUSH PSW
6E
1
4
146
RET
6F
1
5
(restored)
SP ← SP - 1
Return from subroutine :
SP ← SP+1, PCL ← M(SP), SP ← SP+1, PCH ← M(SP)
147
RETI
7F
1
6
--------
--------
--------
Return from interrupt :
SP ← SP+1, PSW ← M(SP), SP ← SP+1,PCL ← M(SP),
(restored)
SP ← SP+1, PCH ← M(SP)
148
ROL A
28
1
2
149
ROL dp
29
2
4
Rotate left through carry
150
ROL dp + X
39
2
5
151
ROL !abs
38
3
5
152
ROR A
68
1
2
153
ROR dp
69
2
4
154
ROR dp + X
79
2
5
155
ROR !abs
78
3
5
156
SBC #imm
24
2
2
Substract with carry
157
SBC dp
25
2
3
A ← A - (M) - ~(C)
158
SBC dp + X
26
2
4
159
SBC !abs
27
3
4
160
SBC !abs + Y
35
3
5
161
SBC [dp + X]
36
2
6
162
SBC [dp] + Y
37
2
6
163
SBC {X}
34
1
3
C
7 6 5 4 3 2 1 0
←←←←←←←←←
N - - - - - ZC
Rotate right through carry
7 6 5 4 3 2 1 0
C
→→→→→→→→→
N - - - - - ZC
NV - - HZC
A-5
Appendix A. GMS800 Series Instruction
NO.
MNENONIC
OP
CODE
BYTE
NO.
CYCLE
NO
OPERATION
FLAG
NVGBHIZC
164
SET1 dp.bit
x1
2
4
Set bit : (M.bit) ← “1”
--------
165
SETA1 A.bit
0B
2
2
Set A.bit : (A.bit) ← “1”
--------
166
SETC
A0
1
2
Set C-flag : C ← “1”
-------1
167
SETG
C0
1
2
Set G-flag : G ← “1”
--1-----
168
STA dp
E5
2
3
Store accumulator contents in memory
169
STA dp + X
E6
2
4
(M) ← A
170
STA !abs
E7
3
4
171
STA !abs + Y
F5
3
5
172
STA [dp + X]
F6
2
6
173
STA [dp] + Y
F7
2
6
174
STA {X}
F4
1
3
--------
175
STA {X}+
FB
1
4
X-register auto-increment : (M) ← A, X ← X + 1
176
STC M.bit
EB
3
6
Store C-flag : (M.bit) ← C
--------
177
STOP
00
1
3
Stop mode (halt CPU, stop oscillator)
--------
178
STX dp
EC
2
4
Store X-register contents in memory
179
STX dp + Y
ED
2
5
(M) ← X
180
STX !abs
FC
3
5
181
STY dp
E9
2
4
Store Y-register contents in memory
182
STY dp + X
F9
2
5
(M) ← Y
183
STY !abs
F8
3
5
--------
--------
184
STYA dp
DD
2
5
Store YA : (dp+1)(dp) ← YA
185
SUBW dp
3D
2
5
16-bits substract without carry : YA ← YA - (dp+1)(dp)
186
TAX
E8
1
2
Transfer accumulator contents to X-register : X ← A
N-----Z-
187
TAY
9F
1
2
Transfer accumulator contents to Y-register : Y ← A
N-----Z-
188
TCALL n
nA
1
8
-------NV - - H - ZC
Table call :
M(SP) ← (PCH), SP ← SP -1,
M(SP) ← (PCL), SP ← SP -1
--------
PCL ← (Table vector L), PCH ← (Table vector H)
189
TCLR1 !abs
5C
3
6
Test and clear bits with A :
A - (M), (M) ← (M) ^ ~(A)
190
TSET1 !abs
3C
3
6
Test and set bits with A :
A - (M), (M) ← (M) V (A)
N-----ZN-----Z-
191
TSPX
AE
1
2
Transfer stack-pointer contents to X-register : X ← SP
192
TST dp
4C
2
3
Test memory contents for negative or zero : (dp) - 00H
N-----Z-
193
TXA
C8
1
2
Transfer X-register contents to accumulator : A ← X
N-----Z-
N-----Z-
194
TXSP
8E
1
2
Transfer X-register contents to stack-pointer : SP ← X
N-----Z-
195
TYA
BF
1
2
Transfer Y-register contents to accumulator : A ← Y
N-----Z-
196
XAX
EE
1
4
Exchange X-register contents with accumulator : X fA
--------
197
XAY
DE
1
4
Exchange Y-register contents with accumulator : Y fA
--------
198
XCN
CE
1
5
Exchange nibbles within the accumulator:
A7 ~ A4 f A3 ~ A0
199
XMA dp
BC
2
5
Exchange memory contents with accumulator
200
XMA dp + X
AD
2
6
(M) f A
201
XMA {X}
BB
1
5
202
XYX
FE
1
4
Exchange X-register contents with Y-register : X f Y
A-6
N-----Z-
N-----Z--------
Appendix A. GMS800 Series Instruction
2.1 Instruction Table by Function
1. Arithmetic/Logic Operation
NO.
MNENONIC
OP
CODE
BYTE
NO.
CYCLE
NO
OPERATION
1
ADC #imm
04
2
2
Add with carry.
2
ADC dp
05
2
3
A ← A + (M) + C
3
ADC dp + X
06
2
4
4
ADC !abs
07
3
4
5
ADC !abs+Y
15
3
5
6
ADC [dp+X]
16
2
6
7
ADC [dp]+Y
17
2
6
8
ADC {X}
14
1
3
9
AND #imm
84
2
2
Logical AND
10
AND dp
85
2
3
A ← A ^ (M)
11
AND dp + X
86
2
4
12
AND !abs
87
3
4
13
AND !abs+Y
95
3
5
14
AND [dp+X]
96
2
6
15
AND [dp] + Y
97
2
6
16
AND {X}
94
1
3
17
ASL A
08
1
2
18
ASL dp
09
2
4
19
ASL dp + X
19
2
5
20
ASL !abs
18
3
5
21
CMP #imm
44
2
2
Compare accumulator contents with memory contents
22
CMP dp
45
2
3
A - (M)
23
CMP dp + X
46
2
4
24
CMP !abs
47
3
4
25
CMP !abs + Y
55
3
5
26
CMP [dp + X]
56
2
6
27
CMP [dp] + Y
57
2
6
28
CMP {X}
54
1
3
29
CMPX #imm
5E
2
2
Compare X contents with memory contents
30
CMPX dp
6C
2
3
X - (M)
31
CMPX !abs
7C
3
4
32
CMPY #imm
7E
2
2
Compare Y contents with memory contents
33
CMPY dp
8C
2
3
Y - (M)
34
CMPY !abs
9C
3
4
FLAG
NVGBHIZC
NV - - H - ZC
N-----Z-
Arithmetic shift left
C
7 6 5 4 3 2 1 0
← ← ← ← ← ← ← ← ← ← "0"
N - - - - - ZC
N - - - - - ZC
N - - - - - ZC
N - - - - - ZC
35
COM dp
2C
2
4
1’s complement : (dp) ← ~(dp)
N-----Z-
36
DAA
DF
1
3
Decimal adjust for addition
N - - - - - ZC
37
DAS
CF
1
3
Decimal adjust for substraction
N - - - - - ZC
38
DEC A
A8
1
2
Decrement
39
DEC dp
A9
2
4
M←M-1
40
DEC dp + X
B9
2
5
41
DEC !abs
B8
3
5
42
DEC X
AF
1
2
43
DEC Y
BE
1
2
44
DIV
9B
1
12
N-----Z-
Divide : YA/A ← Q:A, R:Y
A-7
NV - - H - Z -
Appendix A. GMS800 Series Instruction
NO.
MNENONIC
OP
CODE
BYTE
NO.
CYCLE
NO
OPERATION
45
EOR #imm
A4
2
2
Exclusive OR
46
EOR dp
A5
2
3
A ← A ⊕ (M)
47
EOR dp + X
A6
2
4
48
EOR !abs
A7
3
4
49
EOR !abs + Y
B5
3
5
50
EOR [ dp + X]
96
2
6
51
EOR [dp] + Y
97
2
6
52
EOR {X}
94
1
3
53
INC A
88
1
2
Increment
54
INC dp
89
2
4
(M) ← (M) + 1
55
INC dp + X
99
2
5
56
INC !abs
98
3
5
57
INC X
8F
1
2
58
INC Y
9E
1
2
59
LSR A
48
1
2
60
LSR dp
49
2
4
61
LSR dp + X
59
2
5
62
LSR !abs
58
3
5
63
MUL
5B
1
9
Multiply : YA ← Y x A
64
OR #imm
64
2
2
Logical OR
65
OR dp
65
2
3
A ← A V (M)
66
OR dp + X
66
2
4
67
OR !abs
67
3
4
68
OR !abs + Y
75
3
5
69
OR [dp +X}
76
2
6
70
OR [dp] + Y
77
2
6
71
OR {X}
74
1
3
FLAG
NVGBHIZC
N-----Z-
N - - - - - ZC
N-----Z-
Logical shift right
7 6 5 4 3 2 1 0
C
"0"→ → → → → → → → → →
N - - - - - ZC
N-----Z-
N-----Z-
72
ROL A
28
1
2
73
ROL dp
29
2
4
Rotate left through carry
74
ROL dp + X
39
2
5
75
ROL !abs
38
3
5
76
ROR A
68
1
2
77
ROR dp
69
2
4
78
ROR dp + X
79
2
5
79
ROR !abs
78
3
5
80
SBC #imm
24
2
2
Substract with carry
81
SBC dp
25
2
3
A ← A - (M) - ~(C)
82
SBC dp + X
26
2
4
83
SBC !abs
27
3
4
84
SBC !abs + Y
35
3
5
85
SBC [dp + X]
36
2
6
86
SBC [dp] + Y
37
2
6
87
SBC {X}
34
1
3
88
TST dp
4C
2
3
Test memory contents for negative or zero : (dp) - 00H
89
XCN
CE
1
5
Exchange nibbles within the accumulator:
C
7 6 5 4 3 2 1 0
←←←←←←←←←
N - - - - - ZC
Rotate right through carry
7 6 5 4 3 2 1 0
C
→→→→→→→→→
N - - - - - ZC
NV - - HZC
A7 ~ A4 f A3 ~ A0
A-8
N-----ZN-----Z-
Appendix A. GMS800 Series Instruction
2. Register / Memory Operation
NO.
MNENONIC
OP
CODE
BYTE
NO.
CYCLE
NO
OPERATION
1
LDA #imm
C4
2
2
Load accumulator
2
LDA dp
C5
2
3
A ← (M)
3
LDA dp + X
C6
2
4
4
LDA !abs
C7
3
4
5
LDA !abs + Y
D5
3
5
6
LDA [dp + X]
D6
2
6
7
LDA [dp]+Y
D7
2
6
8
LDA {X}
D4
1
3
9
LDA {X}+
DB
1
4
10
LDM dp,#imm
E4
3
5
Load memory with immediate data : (M) ← imm
11
LDX #imm
1E
2
2
Load X-register
12
LDX dp
CC
2
3
X ← (M)
13
LDX dp + Y
CD
2
4
14
LDX !abs
DC
3
4
15
LDY #imm
3E
2
2
Load X-register
16
LDY dp
C9
2
3
Y ← (M)
17
LDY dp + Y
D9
2
4
18
LDY !abs
D8
3
4
19
STA dp
E5
2
3
Store accumulator contents in memory
20
STA dp + X
E6
2
4
(M) ← A
21
STA !abs
E7
3
4
22
STA !abs + Y
F5
3
5
23
STA [dp + X]
F6
2
6
FLAG
NVGBHIZC
N-----Z-
X-register auto-increment : A ← (M), X ← X + 1
--------
N-----Z-
N-----Z-
--------
24
STA [dp] + Y
F7
2
6
25
STA {X}
F4
1
3
26
STA {X}+
FB
1
4
X-register auto-increment : (M) ← A, X ← X + 1
27
STX dp
EC
2
4
Store X-register contents in memory
28
STX dp + Y
ED
2
5
(M) ← X
29
STX !abs
FC
3
5
30
STY dp
E9
2
4
Store Y-register contents in memory
31
STY dp + X
F9
2
5
(M) ← Y
32
STY !abs
F8
3
5
33
TAX
E8
1
2
Transfer accumulator contents to X-register : X ← A
N-----Z-
34
TAY
9F
1
2
Transfer accumulator contents to Y-register : Y ← A
N-----Z-
35
TSPX
AE
1
2
Transfer stack-pointer contents to X-register : X ← SP
N-----Z-
36
TXA
C8
1
2
Transfer X-register contents to accumulator : A ← X
N-----Z-
37
TXSP
8E
1
2
Transfer X-register contents to stack-pointer : SP ← X
N-----Z-
38
TYA
BF
1
2
Transfer Y-register contents to accumulator : A ← Y
N-----Z-
39
XAX
EE
1
4
Exchange X-register contents with accumulator : X fA
--------
40
XAY
DE
1
4
Exchange Y-register contents with accumulator : Y fA
--------
41
XMA dp
BC
2
5
Exchange memory contents with accumulator
(M) f A
42
XMA dp + X
AD
2
6
43
XMA {X}
BB
1
5
44
XYX
FE
1
4
Exchange X-register contents with Y-register : X f Y
A-9
--------
--------
N-----Z--------
Appendix A. GMS800 Series Instruction
3. 16-Bit Operation
NO.
MNENONIC
OP
CODE
BYTE
NO.
CYCLE
NO
OPERATION
FLAG
NVGBHIZC
1
ADDW dp
1D
2
5
16-bits add without carry : YA ← YA + (dp+1)(dp)
NV - - H - ZC
2
CMPW dp
5D
2
4
Compare YA contents with memory pair contents :
N - - - - - ZC
YA - (dp+1)(dp)
3
DECW dp
BD
2
6
Decrement memory pair : (dp+1)(dp) ← {(dp+1)(dp)} - 1
N-----Z-
4
INCW dp
9D
2
6
Increment memory pair : (dp+1)(dp) ← {(dp+1)(dp)} + 1
N-----Z-
5
LDYA dp
7D
2
5
Load YA : YA ← (dp+1)(dp)
N-----Z-
6
STYA dp
DD
2
5
Store YA : (dp+1)(dp) ← YA
7
SUBW dp
3D
2
5
16-bits substract without carry : YA ← YA - (dp+1)(dp)
OP
CODE
BYTE
NO.
CYCLE
NO
-------NV - - H - ZC
4. Bit Manipulation
NO.
MNENONIC
OPERATION
FLAG
NVGBHIZC
1
AND1 M.bit
8B
3
4
Bit AND C-flag : C ← C ^ (M.bit)
-------C
2
AND1B M.bit
8B
3
4
Bit AND C-flag and NOT : C ← C ^ ~(M.bit)
-------C
3
BIT dp
0C
2
4
Bit test A with memory :
4
BIT !abs
1C
3
5
Z ← A ^ M, N ← (M7), V ← (M6)
MM - - - - Z -
5
CLR1 dp.bit
y1
2
4
Clear bit : (M.bit) ← “0”
6
CLR1A A.bit
2B
2
2
Clear A.bit : (A.bit) ← “0”
--------
7
CLRC
20
1
2
Clear C-flag : C ← “0”
-------0
8
CLRG
40
1
2
Clear G-flag : G ← “0”
--0-----
9
CLRV
80
1
2
Clear V-flag : V ← “0”
-0--0---
10
EOR1 M.bit
AB
3
5
Bit exclusive-OR C-flag : C ← C ⊕ (M.bit)
-------C
11
EOR1B M.bit
AB
3
5
Bit exclusive-OR C-flag and NOT : C ← C ⊕ ∼(M.bit)
-------C
12
LDC M.bit
CB
3
4
Load C-flag : C ← (M.bit)
-------C
13
LDCB M.bit
CB
3
4
Load C-flag with NOT : C ← ~(M.bit)
-------C
14
NOT1 M.bit
4B
3
5
Bit complement : (M.bit) ← ~(M.bit)
--------
15
OR1 M.bit
6B
3
5
Bit OR C-flag : C ← C V (M.bit)
-------C
-------C
--------
16
OR1B M.bit
6B
3
5
Bit OR C-flag and NOT : C ← C V ~(M.bit)
17
SET1 dp.bit
x1
2
4
Set bit : (M.bit) ← “1”
--------
18
SETA1 A.bit
0B
2
2
Set A.bit : (A.bit) ← “1”
--------
19
SETC
A0
1
2
Set C-flag : C ← “1”
-------1
20
SETG
C0
1
2
Set G-flag : G ← “1”
--1-----
21
STC M.bit
EB
3
6
Store C-flag : (M.bit) ← C
--------
22
TCLR1 !abs
5C
3
6
Test and clear bits with A :
A - (M), (M) ← (M) ^ ~(A)
23
TSET1 !abs
3C
3
6
Test and set bits with A :
A - (M), (M) ← (M) V (A)
A-10
N-----ZN-----Z-
Appendix A. GMS800 Series Instruction
5. Branch / Jump Operation
NO.
MNENONIC
OP
CODE
BYTE
NO.
CYCLE
NO
OPERATION
1
BBC A.bit,rel
y2
2
4/6
Branch if bit clear :
2
BBC dp.bit,rel
y3
3
5/7
if(bit) = 0, then PC ← PC + rel
3
BBS A.bit,rel
x2
2
4/6
Branch if bit clear :
4
BBS dp.bit,rel
x3
3
5/7
if(bit) = 1, then PC ← PC + rel
5
BCC rel
50
2
2/4
Branch if carry bit clear :
if(C) = 0, then PC ← PC + rel
FLAG
NVGBHIZC
--------------MM - - - - Z -
6
BCS rel
D0
2
2/4
Branch if carry bit set : If (C) =1, then PC ← PC + rel
7
BEQ rel
F0
2
2/4
Branch if equal : if (Z) = 1, then PC ← PC + rel
--------
8
BMI rel
90
2
2/4
Branch if munus : if (N) = 1, then PC ← PC + rel
---------------
--------
9
BNE rel
70
2
2/4
Branch if not equal : if (Z) = 0, then PC ← PC + rel
10
BPL rel
10
2
2/4
Branch if not minus : if (N) = 0, then PC ← PC + rel
--------
11
BRA rel
2F
2
4
Branch always : PC ← PC + rel
--------
12
BVC rel
30
2
2/4
Branch if overflow bit clear :
If (V) = 0, then PC ← PC + rel
13
BVS rel
B0
2
2/4
Branch if overflow bit set :
If (V) = 1, then PC ← PC + rel
14
CALL !abs
3B
3
8
Subroutine call
15
CALL [dp]
5F
2
8
M(SP) ← (PCH), SP ← SP-1, M(SP) ← (PCL), SP←SP-1
---------------
--------
if !abs, PC ← abs ; if [dp], PCL ← (dp), PCH ← (dp+1)
16
CBNE dp,rel
FD
3
5/7
Compare and branch if not equal ;
17
CBNE dp + X, rel
8D
3
6/8
If A ≠ (M), then PC ← PC + rel.
18
DBNE dp,rel
AC
3
5/7
Decrement and branch if not equal :
19
DBNE Y,rel
7B
2
4/6
if (M) ≠ 0, then PC ← PC + rel.
20
JMP !abs
1B
3
3
Unconditional jump
21
JMP [!abs]
1F
3
5
PC ← jump address
22
JMP [dp]
3F
2
4
23
PCALL
4F
2
6
---------------
--------
U-page call : M(SP) ← (PCH), SP ← SP -1,
M(SP) ← (PCL), SP ← SP -1,
--------
PCL ← (upage), PCH ←"OFFH"
24
TCALL n
nA
1
8
Table call :
M(SP) ← (PCH), SP ← SP -1,
M(SP) ← (PCL), SP ← SP -1
PCL ← (Table vector L), PCH ← (Table vector H)
A-11
--------
Appendix A. GMS800 Series Instruction
6. Control Operation & etc.
NO.
1
MNENONIC
BRK
OP
CODE
BYTE
NO.
CYCLE
NO
0F
1
8
OPERATION
FLAG
NVGBHIZC
Software interrupt:
B ← “1”, M(SP) ← (PCH), SP ← SP - 1,
M(s) ← (PCL), SP ← S - 1, M(SP) ← PSW,
---1-0--
SP ← SP - 1, PCL ← (0FFDEH), PCH ← (0FFDFH)
2
DI
60
1
3
Disable interrupts : I ← “0”
-----0--
3
EI
E0
1
3
Enable interrupts : I ← “1”
-----1--
4
NOP
FF
1
2
No operation
--------
5
POP A
0D
1
4
Pop from stack
6
POP X
2D
1
4
SP ← SP + 1, Reg. ← M(SP)
7
POP Y
4D
1
4
8
POP PSW
6D
1
4
9
PUSH A
0E
1
4
Push to stack
10
PUSH X
2E
1
4
M(SP) ← Reg.
11
PUSH Y
4E
1
4
12
PUSH PSW
6E
1
4
13
RET
6F
1
5
(restored)
SP ← SP - 1
Return from subroutine :
SP ← SP+1, PCL ← M(SP), SP ← SP+1, PCH ← M(SP)
14
RETI
7F
1
6
--------
--------
--------
Return from interrupt :
SP ← SP+1, PSW ← M(SP), SP ← SP+1,PCL ← M(SP),
(restored)
SP ← SP+1, PCH ← M(SP)
15
STOP
EF
1
3
Stop mode (halt CPU, stop oscillator)
A-12
--------
Appendix B. Programmer’s guide
1. General Circuit Diagram of GMS81C50 series
VCC
3
R02
R25 38
4
5
R03
R04
R24 37
R23 36
6
R05
R22 35
7 R06
8 R07
VCC
9
R34
10 R35
Indicator LED
11 VDD
12 R36
4MHz
13 R37
OSC
14 XOUT
15 XIN
R21 34
R20 33
R33 32
R31
29
28
R30
R17 27
R16 26
16 R10
R40
REMOUT 24
R15 23
R14 22
19 R13
Infrared LED
VSS 31
R32 30
17 R11
18 R12
vcc
Filter for Vcc-GND
noise
25
TR1
RESET 21
20 TEST
0.1uF
GND
R20
R17
R16
R15
R14
R10
R30
R12
R21
57
49
41
33 25
17
9
1
R00
122 114 106
98
90 82
74
66
58
50
42
34 26
18
10
2
R01
123 115 107
99
91 83
75
67
59
51
43
35 27
19
11
3
R02
124 116 108 100
92 84
76
68
60
52
44
36 28
20
12
4
R03
125 117 109 101
93 85
77
69
61
53
45
37 29
21
13
5
R04
126 118 110 102
94 86
78
70
62
54
46
38 30
22
14
6
R05
127 119 111 103
95 87
79
71
63
55
47
39 31
23
15
7
R06
128 120 112 104
96 88
80
72
64
56
48
40 32
24
16
8
R07
B-1
R13
R23
65
R22
R24
73
R25
89 81
R26
97
R27
121 113 105
220uF
R27 40
R26 39
0.1uF
R00
R01
GMS 81C50XX
2
1
Appendix B. Programmer’s guide
KEY MATRIX
= KEY
Figure B-1. Circuit Diagram
Note: Normally use the above 100uF capacitor for prevent power drop during pulse is transmitted. If you use the SRAM backup, use at least 220uF.
We recommend to use ALKALINE battery.
Note: Figure B-1, Circuit Description:
device : GMS81C5016
package : 40PIN PDIP
port R0x : All input port with pull-up resistor
port R1x : All output port with N-MOS Open drain
port R11 : LED Drive port
B-2
Appendix B. Programmer’s guide
2. Mask Option List Example Refer to Circuit B-1
GMS81C50 MASK OPTION LIST
LG Semicon Co., Ltd.
M/L Application Team.
Code Name : GMS81C5016 - Uxxx
1. Device & Package
GMS81C5004
GMS81C5008
GMS81C5016
28PIN : SOP
40PIN : PDIP
44PIN : PLCC
GMS81C5024
GMS81C5032
28 PIN : Skinny DIP
44PIN : MQFP
Y : Yes
- R0 PORT
Port
Y/N
Y/N*3
R01
R02
R03
R04
R05
R06
y
y
y
y
y
y
y
y
y
y
y
y
y
y
Y : Yes
- R1 PORT
Port
Y/N
Y/N*3
R11
R12
R13
R14
R15
R16
y
y
y
y
y
y
y
y
y
y
y
y
y
y
Y : Yes
R20
R21
R22
R23
R24
y
y
y
y
y
y
y
y
y
y
Port
Y/N
Y/N*3
R17
y
y
R25 *2 R26 *2 R27 *2
y
y
y
y
y
y
N : No
R30 *2 R31 *2 R32 *2 R33 *2 R34 *2 R35 *2 R36 *2 R37 *2
y
y
y
y
Y : Yes
- R4 PORT
Port
Y/N
Y/N*3
y
y
N : No
Y : Yes
- R3 PORT
R07
N : No
R10
- R2 PORT
Port
Y/N
Y/N*3
N : No
R00
y
y
y
y
y
y
y
y
y
y
y
y
N : No
R40 *2
y
y
< NOTICE >
. *1 : is not available for 28PIN & 40PIN. So, Default option is Pull-Up.
. *2 : is not available for 28PIN. So, Default Option is Pull-Up.
. *3 : is for selecting Pull-up in LVD mode.
Date
:
Company Name :
Section Name
:
Signature
:
3. Low Voltage Detection
(Means RAM retention)
Y/N
Y
rent will flow from the Pull up to GND. It cause the large
power consumption and RAM would not be retained
enough to satisfy your want.
Case2 : The case of using any I/O port for controlling PNP
TR., The TR is always turn on by the Pull up of I/O port in
LVD mode
Indicator LED
Note: Caution: When the power to the MCU would be decreased under LVD, all I/O ports are changed to input ports
with pull up resistor. In below cases, you must take care of
selecting the pull up in LVD.. You must detach the pull up
of I/O port at thease cases.
Case1 : When any I/O port is connected to GND, the cur-
R00
< Case 1 >
R00
PNP
< Case 2 >
B-3
Appendix B. Programmer’s guide
3. Key Scan
; program example ,See the Figure B-1 circuit.
ldm R1,#1111_1110b ;R10 port set to LOW
call delay_60uS
;60uS time delay routine
lda R0
;R0 port Read
To secure the key board scanning , read the input port after
minimum 60uS delay time from output port set to `Low `.
This time delay is for the port rising time depend on the input pull-up resistor .
R0 port Read timing
R10
60uS
60uS
R11
< Fig B-2 , Input with pull-up port read time method >
* Current Consumption
~ 25mA (Max 45mA). But this value is normal case. Some
special protocol can be possible to consume more larger
current.
The current consumption during the Pulse transmission depends on the external circuit and each Protocol. Normally
, if you used Fig B-1 circuit., the operation current is 15mA
B-4