PD-97534C (5962F1023502K) IRUH3301A2AK Radiation Hardended Ultra Low Dropout IRUH3301A2AP Adjustable Positive Linear Regulator +5.0VIN to VADJ @3.0A Product Summary Part Number IRUH3301A2AK IRUH3301A2AP Dropout IO VIN VOUT 0.4V 3.0A 5.0V ADJ 8-LEAD FLAT PACK Features Description The IRUH3301A2 is a space qualified, ultra low dropout linear regulator designed specifically for applications requiring high reliability, low noise and radiation hardness. The output voltage can be adjusted to a low 0.8V with a droput voltage of 400mV at the full rated current of 3.0 Amps. n Silicon On Insulator (SOI) CMOS Regulator n n n n n n n n n n n Absolute Maximum Ratings Parameter Power Dissipation @ TC = 125°C Maximum Output Current @ Maximum IC, CMOS Latch-Up Immune, Inherently Rad Hard Total Dose Capability up to 300Krads(Si) (Condition A); Tested to 500Krad (Si) ELDRS up to 100Krad(Si) (Condition D) SEU Immune up to LET = 80 MeV*cm2/mg Space Level Screened Fast Transient Response Timed Latch-Off Over-Current Protection Internal Thermal Protection Adjustable Output as low as 0.8V On/Off Control via Shutdown Pin, Power Sequencing Easily Implemented Isolated Hermetic 8-Lead Flat Pack Ensures Higher Reliability This part is also available in MO-078 Package as IRUH3301A2BK / IRUH3301A2BP Symbol Min. Max. Units PD - 25 W A Power Dissipation with no Derating Non-Operating Input Voltage IO - See Fig 4 VIN -0.3 +8.0 Operating Input Voltage VIN 2.9 6.4 GND VSHDN -0.3 -0.3 0.3 VIN + 0.3 Ground Shutdown Pin Voltage VOUT -0.3 VIN + 0.3 Operating Case Temperature Range TO -55 +140 Storage Temperature Range TS -65 +150 Maximmum Junction Temperature TJ - +150 TL RTHJC - +300 1.0 Output Pin Voltage Lead Temperature (Soldering 10sec) Pass Transistor Thermal Resistance, Junction to Case www.irf.com V °C °C/W 1 05/18/12 IRUH3301A2AK IRUH3301A2AP Electrical Characteristics c Pre-Radiation @TC = 25°C, VIN = 5.0V (Unless Otherwise Specified) Parameter Test Conditions Symbol 3.8V ≤ VIN ≤ 5.8V, 50mA ≤ IOUT ≤ 3.0A 3.8V ≤ VIN ≤ 5.8V, 50mA ≤ IOUT ≤ 3.0A, Reference Voltage (Measured @ ADJ Pin) -55°C to +125°C 3.8V ≤ VIN ≤ 5.8V, 50mA ≤ IOUT ≤ 3.0A, VOUT Post -Rad Dropout Voltage c IO = 3.0A, VOUT = 4.4V, -55°C to +125°C, Post -Rad Over-Current Latching, -55°C to +125°C, Current Limit Over-Current Time-to-Latch d Post -Rad IO > ILATCH Maximum Shutdown Temp. F= 120Hz, IO = 50mA, -55°C to +125°C d ADJ Pin Current d Ripple Rejection F= 120Hz, IO = 50mA, Post -Rad -55°C to +125°C ISOURCE = 200µA, -55°C to +125°C Minimum SHDN Pin "On" Threshold Voltage Post -Rad ISOURCE = 200µA, -55°C to +125°C Maximum SHDN Pin "Off" Threshold Voltage Post -Rad RLOAD = 36 Ohms, VSHDN = 3.3V Output Voltage at Shutdown SHDN Pin Leakage Current SHDN Pin Pull-Up Current d Power On Reset Threshold Quiescent Current d d d Min. Typ. Max. Units 0.788 0.800 0.812 0.776 0.800 0.824 0.772 0.800 0.816 V VDROP - - 0.4 V ILATCH 3.5 - - A tLATCH - 10 - ms TLATCH 125 140 - °C 65 - - 40 - - IADJUST - 1.6 - mA VSHDN - - 0.8 V VSHDN 1.2 - - V PSRR dB -55°C to +125°C, Post-Rad VSHDN = 3.3V, -55°C to +125°C,Post-Rad VOUT -0.1 - 0.1 V ISHDN -10 -98 - 10 -56 µA VSHDN = 0.4V VSHDN = 0.4V, -55°C to +125°C ISHDN -140 -98 - -30 -56 µA VT-POR - 1.7 - V VSHDN = 0.4V, Post-Rad Sweep VIN and Measure Output No Load Full Load IQ - - 15 - - 90 mA Notes: Connected as shown in Fig.1 and measured at the junction of VOUT and ADJ Pins. Under normal closed-loop operation. Guaranteed by design. Not tested in production. 2 www.irf.com IRUH3301A2AK IRUH3301A2AP Radiation Performance Characteristics Test Conditions Min Typ MIL-STD-883, Method 1019 (Condition A) Total Ionizing Dose (Gamma) Operating Bias applied during exposure Unit 300 500 c Krads (Si) 100 See d Krads (Si) Minimum Rated Load, Vin = 6.4V MIL-STD-883, Method 1019 (Condition D) Total Ionizing Dose (Gamma) (ELDRS) Operating Bias applied during exposure Minimum Rated Load, Vin = 6.4V Single Event effects Heavy Ions (LET) SEU, SEL, SEGR, SEB Operating Bias applied during exposure 2 84 MeV*cm /mg under varying operating conditions Neutron Fluence MIL-STD-883, Method 1017 1.0e 11 2 Neutrons/cm Notes: Tested to 500Krad (Si). See Fig. 5. Space Level Screening Requirements TEST/INSPECTION SCREENING LEVEL MIL-STD-883 SPACE METHOD Nondestructive Bond Pull 100% 2023 Internal Visual 100% 2017 Seal 100% 1014 Temperature Cycle 100% 1010 Constant Acceleration 100% 2001 Mechanical Shock 100% 2002 PIND 100% 2020 Pre Burn-In-Electrical 100% Burn-In 100% Final Electrical 100% Radiographic External Visual 100% 100% www.irf.com 1015 2012 2009 3 IRUH3301A2AK IRUH3301A2AP Application Information Input Voltage VIN Output Voltage VOUT R1 0.1uF and 1uF Ceramic; Two 100uF Low ESR Tantalum IRUH3301Axxx 0.1uF and 1uF Ceramic; Two 100uF Low ESR Tantalum ADJ SHDN GND Fig. 1. Typical Regulator Circuit; Note the SHDN Pin is hardwired in the “ON” position. The ADJ Pin is connected as noted in the “General Layout Rules” section. Setting the Output Voltage Choose R1 based upon the desired output voltage using the formula below. ⎛ V ⎞ R1 = ⎜ OUT − 1⎟ * 499Ω ⎝ 0.800V ⎠ Table 1 shows the closest nominal 0.1% tolerance R1 value to provide a given output voltage. Table 1- Values of R1 for a Given Output Voltage VOUT (V) Nearest R1 Value (0.1%), (Ohms) 0.9 61.9 1.0 124 1.2 249 1.5 437 1.8 619 2.5 1060 3.3 1560 Over-Current & Over-Temperature Protection The IRUH3301 series provides over-current protection by means of a timed latch function. Drive current to the internal PNP pass transistor is limited by an internal resistor (Rb in Fig. 3) between the base of the transistor and the control IC drive FET. If an over-current condition forces the voltage across this resistor to exceed 0.5V (nom), the latch feature will be triggered. The time-tolatch (tLATCH) is nominally 10ms. If the over-current condition exists for less than tLATCH , the latch will not be set. If the latch is set the drive current to the PNP pass transistor will be disabled. The latch will remain set until one of the following actions occur: 1. The SHDN Pin voltage is brought above 1.2V and then lowered below 0.8V. 2. The VIN Pin voltage is lowered below 1.7V. If the junction temperature of the regulator IC exceeds 140°C nominal, the thermal shutdown circuit will set the internal latch and disable the drive current to the PNP pass transistor as described above. After the junction temperature falls below a nominal 125°C, the latch can be reset using either of the actions described above. Under-Voltage Lock-Out The under-voltage lock-out (UVLO) function prevents operation when VIN is less than 1.7V (nominal). There is a nominal 100mV hysteresis about this point. Input Voltage Range The device control functions fully when VIN is greater than 2.9V. The output current may need to be reduced to avoid the activation of over current protection at 2.9V < VIN < 3.8V. The IRUH3301A1 is recommended for performance optimization when 2.9V < VIN < 3.8V is required. The device enters into under-voltage lock-out when VIN < 1.7V (nominal). When 1.7V (nominal) < VIN < 2.9V, VOUT will track VIN and overshoot may occur. A larger output capacitor should be used to slow down the VOUT rise rate for slow VIN ramp applications. 4 www.irf.com IRUH3301A2AK IRUH3301A2AP Shutdown (SHDN) The regulator can be shutdown by applying a voltage of >1.2V to the SHDN Pin. The regulator will restart when the SHDN Pin is pulled below the shutdown threshold of 0.8V. If the remote shutdown feature is not required, the SHDN Pin should be connected to GND. Input Capacitance Input bypass capacitors: Two (0.1µF and 1µF) ceramics and two 100µF low ESR tantalums (AVX TPS or equivalent), placed very close to the VIN Pin are required for proper operation. When the input voltage supply capacitance is more than 4 inches from the device, additional input capacitance is recommended. Larger input capacitor values will improve ripple rejection further improving the integrity of the output voltage. Output Capacitance Output bypass capacitors: Two (0.1µF and 1µF) ceramics and two 100µF low ESR tantalums (AVX TPS or equivalent) are required for loop stability. Faster transient performance can be achieved with multiple additional 1µF ceramic capacitors. Ceramic capacitors greater than 1µF in value are not recommended as they can cause stability issues. Tantalum capacitor values larger than the suggested value are recommended to improve the transient response under large load current changes. The upper capacitance value limit is governed by the delayed over-current latch function of the regulator and can be as much as 10,000µF without causing the device to latch-off during start-up. General Layout Rules Low impedance connections between the regulator output and load are essential. Solid power and ground planes are highly recommended. In those cases where the board impedances are not kept very small, oscillations can occur due to the effect of parasitic series resistance and inductance on loop bandwidth and phase margin. R1 must be directly conected to the VOUT Pin using as short a trace as possible with the connection inside the first bypass capacitor (see Fig. 2a). The trace from ADJ Pin to R1 should be as short as possible. Connect ceramic output capacitors directly across the VOUT and GND Pins with as wide a trace as design rules allow (see Fig. 2a). Avoid the use of vias for these capacitors and avoid loops. Fig.2 shows the ceramic capacitors tied directly to the regulator output. The input capacitors should be connected as close a possible to the VIN Pin. Fig. 2a. Layer 1 conductor. Fig. 2b. Layer 1 silkscreen Ground plane below layer 1 www.irf.com 5 IRUH3301A2AK IRUH3301A2AP ADJ VOUT V IN Input Undervoltage detect SHDN Thermal Shutdown Rb Shutdown & Over Current Latch Disable Error Amp + Latch Timing capacitor VREF GND Fig. 3. Simplified Schematic Circuit Maximum Output Current (A) with no derating at Maximum Dissipation 4.0 Output Current (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 100 110 120 130 140 150 160 170 Mounting Surface Temperature (’C) Fig. 4. Maximum Output Current versus Mounting Surface Temperature with no Derating at Maximum Dissipation 6 www.irf.com IRUH3301A2AK IRUH3301A2AP VOut Delta-VOut (%) 0.500% 0.250% ELDRS 0.000% TID -0.250% -0.500% 1 10 100 1000 10000 100000 Total Dose (Rad (Si)) Fig. 5. Change in Output Voltage vs. Total Ionizing Dose Radiation Exposure at Both High and Low Dose Rates PSRR (Typical) 105 95 85 PSRR (dB) 75 65 55 45 35 25 15 5 -5 0.1 1 10 100 1000 10000 Freq (KHz) Recomended Layout and Capcitors, No IRUH Iout=100mA & 1.6A, 3.3Vout, 4.8Vin Fig. 6. Typical Power Supply Ripple Rejection at 100mA and 1.6A using recommended layout and capacitors. Results above 10KHz are influenced by testing setup and layout. www.irf.com 7 IRUH3301A2AK IRUH3301A2AP Fig 7. Case Outline and Dimensions - 8-Lead Flat Pack (Lead Form Down) Pin Assignment Pin # Pin Description 1 GND 2 GND 3 4 SHUTDOWN VADJ 5 VOUT 6 VOUT 7 VIN 8 VIN Note: 1) All dimensions are in inches Warning: This Product contains BeO Fig 8. Case Outline and Dimensions - 8-Lead Flat Pack (Lead Trimmed) Pin Assignment Pin # Pin Description 1 GND 2 GND 3 4 SHUTDOWN VADJ 5 VOUT 6 VOUT 7 VIN 8 VIN Note: 1) All dimensions are in inches Warning: This Product contains BeO 8 www.irf.com IRUH3301A2AK IRUH3301A2AP Part Numbering Nomenclature IR U H3 301 A2 A K Linear Regulator U = Ultra Low Dropout Regulator Radiation Hardening H3 = 300 Krads Device indicator 301 = 3 Amp Positive Regulator Lead Form Options Blank = Lead Form Down (Fig. 7) B = Lead Form Up C = Lead Trimmed (Fig. 8) Screening Level P = Unscreened. 25°C Electrical Test Not for Qualification K = Class K per MIL-PRF-38534 Output Voltage 18 = 1.8V 25 = 2.5V 33 = 3.3V A1 = Adjustable Optimized for 3.3 V Input A2 = Adjustable Optimized for 5.0V Input Package Type A = 8 Lead Flat Pack IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 IR LEOMINSTER : 205 Crawford St., Leominster, Massachusetts 01453, USA Tel: (978) 534-5776 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice. 05/2012 www.irf.com 9