AD ADuM5410BRSZ-RL7 Quad-channel isolators with integrated dc-to-dc converter Datasheet

Quad-Channel Isolators with
Integrated DC-to-DC Converters
ADuM5410/ADuM5411/ADuM5412
Data Sheet
isoPower integrated, isolated dc-to-dc converter
Up to 150 mW output power
Quad dc to 150 Mbps signal isolation channels
24-lead SSOP package with 5.3 mm minimum creepage
High temperature operation: 105°C
High common-mode transient immunity: 100 kV/μs
Safety and regulatory approvals
UL recognition (pending)
2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A (pending)
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 565 V peak
VDD1 1
GND1 2
I/O1A 3
I/O1B 4
I/O1C 5
4-CHANNEL iCoupler CORE
ADuM5410/ADuM5411/
ADuM5412
VDD2
23
GND ISO
22
I/O2A
21
I/O2B
20
I/O2C
I/O1D 6
19
I/O2D
VE1 7
18
VE2
NIC 8
17
NIC
GND1 9
16
GND ISO
15
VSEL
14
VISO
13
GND ISO
PDIS 10
PCS
VDDP 11
GND1 12
APPLICATIONS
24
OSC
RECT
REG
NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.
RS-232 transceivers
Power supply startup bias and gate drives
Isolated sensor interfaces
Industrial PLCs
14695-001
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Figure 1.
GENERAL DESCRIPTION
The ADuM5410/ADuM5411/ADuM54121 are quad-channel
digital isolators with isoPower®, integrated, isolated dc-to-dc
converters. Based on the Analog Devices, Inc., iCoupler®
technology, the dc-to-dc converters provide regulated, isolated
power that is adjustable between 3.15 V and 5.25 V. Popular
voltage combinations and the associated power levels are shown
in Table 1.
The ADuM5410/ADuM5411/ADuM5412 eliminate the need
for a separate, isolated dc-to-dc converter in low power, isolated
designs. The iCoupler chip scale transformer technology is used for
isolated logic signals and for the magnetic components of the
dc-to-dc converters. The result is a small form factor, total
isolation solution.
The ADuM5410/ADuM5411/ADuM5412 isolators provide four
independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide for more
information).
1
Table 1. Power Levels
Input Voltage (V)
5
5
3.3
Output Voltage (V)
5
3.3
3.3
Output Power (mW)
150
100
66
Table 2. Data Input/Output Port Assignments
Ch.
I/O1A
I/O1B
I/O1C
I/O1D
I/O2A
I/O2B
I/O2C
I/O2D
Pin No.
3
4
5
6
22
21
20
19
ADuM5410
VIA
VIB
VIC
VID
VOA
VOB
VOC
VOD
ADuM5411
VIA
VIB
VIC
VOD
VOA
VOB
VOC
VID
ADuM5412
VIA
VIB
VOC
VOD
VOA
VOB
VIC
VID
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. 0
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Technical Support
www.analog.com
ADuM5410/ADuM5411/ADuM5412
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 14
General Description ......................................................................... 1
Recommended Operating Conditions .................................... 14
Functional Block Digram ................................................................ 1
Absolute Maximum Ratings ......................................................... 15
Revision History ............................................................................... 2
ESD Caution................................................................................ 15
Specifications..................................................................................... 3
Pin Configurations and Function Descriptions ......................... 16
Electrical Characteristics—5 V Primary Input Supply/5 V
Secondary Isolated Supply........................................................... 3
Truth Tables................................................................................. 19
Typical Performance Characteristics ........................................... 20
Electrical Characteristics—3.3 V Primary Input Supply/3.3 V
Secondary Isolated Supply........................................................... 5
Terminology .................................................................................... 24
Electrical Characteristics—5 V Primary Input Supply/3.3 V
Secondary Isolated Supply........................................................... 7
Applications Information .............................................................. 26
Electrical Characteristics—2.5 V Operation Digital Isolator
Channels Only .............................................................................. 9
Thermal Analysis ....................................................................... 27
Theory of Operation ...................................................................... 25
PCB Layout ................................................................................. 26
Electrical Characteristics—1.8 V Operation Digital Isolator
Channels Only ............................................................................ 11
Propagation Delay Related Parameters ................................... 27
Package Characteristics ............................................................. 13
Power Consumption .................................................................. 27
Regulatory Approvals................................................................. 13
Insulation Lifetime ..................................................................... 27
Insulation and Safety Related Specifications .......................... 13
Outline Dimensions ....................................................................... 29
EMI Considerations ................................................................... 27
Ordering Guide .......................................................................... 29
REVISION HISTORY
7/2016—Revision 0: Initial Version
Rev. 0 | Page 2 of 29
Data Sheet
ADuM5410/ADuM5411/ADuM5412
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDD1 = VDDP = VISO = 5 V, VSEL resistor network: R1 = 10 kΩ ±1%, R2 = 30.9 kΩ ± 1% between VISO
and GNDISO (see Figure 31). Minimum/maximum specifications apply over the entire recommended operation range, which is 4.5 V ≤ VDD1,
VDDP, VISO ≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS
signal levels, unless otherwise noted.
Table 3. DC-to-DC Converters Static Specifications
Parameter
DC-TO-DC CONVERTERS SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
Pulse-Width Modulation Frequency
Output Supply
Efficiency at IISO (MAX)
VDDP Supply Current
No VISO Load
Full VISO Load
Thermal Shutdown
Shutdown Temperature
Thermal Hysteresis
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
fPWM
IISO (MAX)
4.7
5.0
20
1
75
200
125
600
5.4
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
mA
%
IISO = 15 mA, R1 = 10 kΩ, R2 = 30.9 kΩ
IISO = 15 mA, VDDP = 4.5 V to 5.5 V
IISO = 3 mA to 27 mA
20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 27 mA
CBO = 0.1 µF||10 µF, IISO = 27 mA
5
30
29
IDDP (Q)
IDDP (MAX)
14
104
20
140
154
10
VISO > 4.5 V
IISO = 27 mA
mA
mA
°C
°C
Table 4. Data Channel Supply Current Specifications
Parameter
SUPPLY CURRENT
ADuM5410
ADuM5411
ADuM5412
Symbol
Min
1 Mbps
Typ Max
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
6.8
2.1
5.8
4.0
4.3
5.3
Min
25 Mbps
Typ Max
10
3.7
10.3
6.85
7.7
8.7
7.8
3.9
7.0
5.5
6.0
6.7
Min
12
5.7
10.9
8.5
9.3
10.1
100 Mbps
Typ
Max
11.8
9.2
11.4
10.3
10.3
11.0
17.4
13
15.9
14.0
14.2
14.9
Unit
Test Conditions/Comments
CL = 0 pF
mA
mA
mA
mA
mA
mA
Table 5. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
Symbol
Min
PW
6.6
tPHL, tPLH
PWD
4.8
Typ
7.2
0.5
1.5
tPSK
tPSKCD
tPSKOD
Max
150
13
3
6.1
0.5
0.5
490
70
3.0
3.0
Unit
Test Conditions/Comments
ns
Mbps
ns
ns
ps/°C
ns
Within pulse width distortion (PWD) limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Between any two units at the same temperature, voltage, and load
ns
ns
ps p-p
ps rms
Rev. 0 | Page 3 of 29
ADuM5410/ADuM5411/ADuM5412
Data Sheet
Table 6. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Input Threshold
Logic High
Symbol
Min
VIH
0.7 × VISO or 0.7 ×
VDD1
Logic Low
VIL
Output Voltage
Logic High
VOH
Logic Low
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
Quiescent Supply Current
ADuM5410
Typ
Max
Test Conditions/
Comments
V
0.3 × VISO or 0.3 ×
VDD1
VDD1 − 0.2 or VDD2 −
0.2
VDD1 − 0.5 or
VDD2 − 0.5
Unit
V
VDD1 or VDD2
V
IOx 1 = −20 µA, VIx = VIxH 2
VDD1 − 0.2 or
VDD2 − 0.2
0.0
0.0
V
IOx = −4 mA, VIx = VIxH
0.1
0.4
V
V
IOx = 20 µA, VIx = VIxL 3
IOx = 4 mA, VIx = VIxL
VDD1, VDD2, and VDDP supply
1.6
1.5
0.1
+0.01
+10
V
V
V
µA
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.2
2.0
12.0
2.0
2.2
2.72
20.0
2.92
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.6
1.9
10.0
6.0
2.46
2.62
17.0
10.0
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.6
1.6
7.2
8.4
2.46
2.46
11.5
11.5
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDDI (D)
0.01
mA/Mbps
IDDO (D)
0.01
mA/Mbps
Inputs switching, 50% duty
cycle
Inputs switching, 50% duty
cycle
VOL
UVLO
VUV+
VUV−
VUVH
II
−10
ADuM5411
ADuM5412
Dynamic Supply Current
Input
Output
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 4
tR/tF
|CMH|
75
2.5
100
ns
kV/µs
|CML|
75
100
kV/µs
10% to 90%
VIx = VDD1 or VISO, commonmode voltage (VCM) = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
IOx is the Channel x output current, where x means A, B, C, or D.
VIxH is the input side logic high.
VIxL is the input side logic low.
4
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both the rising and falling common-mode
voltage edges.
1
2
3
Rev. 0 | Page 4 of 29
Data Sheet
ADuM5410/ADuM5411/ADuM5412
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDD1 = VDDP = VISO = 3.3 V, VSEL resistor network: R1 = 10 kΩ, ±1%, R2 = 16.9 kΩ ± 1% between
VISO and GNDISO (see Figure 31). Minimum/maximum specifications apply over the entire recommended operation range, which is
3.0 V ≤ VDD1, VDDP, VISO ≤ 3.6 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF
and CMOS signal levels, unless otherwise noted.
Table 7. DC-to-DC Converter Static Specifications
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
Pulse-Width Modulation Frequency
Output Supply
Efficiency at IISO (MAX)
VDDP Supply Current
No VISO Load
Full VISO Load
Thermal Shutdown
Shutdown Temperature
Thermal Hysteresis
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
fPWM
IISO (MAX)
3.0
3.3
20
1
50
130
125
600
3.6
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
mA
%
IISO = 10 mA, R1 = 10 kΩ, R2 = 16.9 kΩ
IISO = 10 mA, VDD1 = 3.0 V to 3.6 V
IISO = 2 mA to 18 mA
20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 18 mA
CBO = 0.1 µF||10 µF, IISO = 18 mA
5
20
27
IDDP (Q)
IDDP (MAX)
14
77
20
115
3.6 V > VISO > 3 V
IISO = 18 mA
mA
mA
154
10
°C
°C
Table 8. Data Channel Supply Current Specifications
Parameter
SUPPLY CURRENT
ADuM5410
ADuM5411
ADuM5412
Symbol
Min
1 Mbps
Typ Max
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
6.6
2.0
5.65
3.9
4.3
5.0
Min
25 Mbps
Typ Max
9.8
3.7
10.1
6.65
7.7
8.4
7.4
3.5
6.65
5.2
5.6
6.2
Min
11.2
5.5
10.5
8.0
9.0
9.6
100 Mbps
Typ
Max
10.7
8.2
10.4
9.4
9.1
9.8
15.9
11.6
14.9
12.8
13
13.7
Unit
Test Conditions/Comments
CL = 0 pF
mA
mA
mA
mA
mA
mA
Table 9. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
Symbol
Min
PW
6.7
tPHL, tPLH
PWD
Typ
6.8
0.7
1.5
tPSK
tPSKCD
tPSKOD
Max
150
14
3.0
7.5
0.7
0.7
640
75
3.0
3.0
Unit
Test Conditions/Comments
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Between any two units at the same temperature, voltage, and load
ns
ns
ps p-p
ns rms
Rev. 0 | Page 5 of 29
ADuM5410/ADuM5411/ADuM5412
Data Sheet
Table 10. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Input Threshold
Logic High
Symbol
Min
VIH
0.7 × VISO or 0.7 ×
VDD1
Logic Low
VIL
Output Voltage
Logic High
VOH
Logic Low
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
Quiescent Supply Current
ADuM5410
Typ
Max
Test Conditions/
Comments
V
0.3 × VISO or 0.3 ×
VDD1
VDD1 − 0.2 or VDD2 −
0.2
VDD1 − 0.5 or
VDD2 − 0.5
Unit
V
VDD1 or VDD2
V
IOx = −20 µA, VIx = VIxH
VDD1 − 0.2 or
VDD2 − 0.2
0.0
0.0
V
IOx = −4 mA, VIx = VIxH
0.1
0.4
V
V
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VDD2, and VDDP supply
1.6
1.5
0.1
+0.01
+10
V
V
V
µA
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.2
2.0
12.0
2.0
2.12
2.68
19.6
2.8
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.5
1.8
9.8
5.7
2.36
2.52
16.7
9.7
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.6
1.6
7.2
8.4
2.4
2.4
11.2
11.2
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDDI (D)
0.01
mA/Mbps
IDDO (D)
0.01
mA/Mbps
Inputs switching, 50% duty
cycle
Inputs switching, 50% duty
cycle
VOL
UVLO
VUV+
VUV−
VUVH
II
−10
ADuM5411
ADuM5412
Dynamic Supply Current
Input
Output
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 1
1
tR/tF
|CMH|
75
2.5
100
ns
kV/µs
|CML|
75
100
kV/µs
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both the rising and falling common-mode
voltage edges.
Rev. 0 | Page 6 of 29
Data Sheet
ADuM5410/ADuM5411/ADuM5412
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDD1 = VDDP = 5.0 V, VISO = 3.3 V, VSEL resistor network: R1 = 10 kΩ ± 1%, R2 = 16.9 kΩ ±1%
between VISO and GNDISO (see Figure 31). Minimum/maximum specifications apply over the entire recommended operation range, which
is 4.5 V ≤ VDD1 = VDDP ≤ 5.5 V, 3.0 V ≤ VISO ≤ 3.6 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested
with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 11. DC-to-DC Converter Static Specifications
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
Pulse-Width Modulation Frequency
Output Supply
Efficiency at IISO (MAX)
VDDP Supply Current
No VISO Load
Full VISO Load
Thermal Shutdown
Shutdown Temperature
Thermal Hysteresis
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
fPWM
IISO (MAX)
3.0
3.3
20
1
50
130
125
600
3.6
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
mA
%
IISO = 15 mA, R1 = 10 kΩ, R2 = 16.9 kΩ
IISO = 15 mA, VDD1 = 3.0 V to 3.6 V
IISO = 3 mA to 27 mA
20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 27 mA
CBO = 0.1 µF||10 µF, IISO = 27 mA
5
30
24
IDDP (Q)
IDDP (MAX)
14
85
20
115
3.6 V > VISO > 3 V
IISO = 27 mA
mA
mA
154
10
°C
°C
Table 12. Data Channel Supply Current Specifications
Parameter
SUPPLY CURRENT
ADuM5410
ADuM5411
ADuM5412
Symbol
Min
1 Mbps
Typ Max
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
6.8
2.0
5.8
3.9
4.3
5.0
Min
25 Mbps
Typ Max
10
3.7
10.3
6.65
7.7
8.4
7.8
3.5
7.0
5.2
6.0
6.2
Min
12
5.5
10.9
8.0
9.3
9.6
100 Mbps
Typ
Max
11.8
8.2
11.4
9.4
10.3
9.8
17.4
11.6
15.9
12.8
14.2
13.7
Unit
Test Conditions/Comments
CL = 0 pF
mA
mA
mA
mA
mA
mA
Table 13. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
Symbol
Min
PW
6.7
tPHL, tPLH
PWD
Typ
6.8
0.7
1.5
tPSK
tPSKCD
tPSKOD
Max
150
14
3.0
7.5
0.7
0.7
640
75
3.0
3.0
Unit
Test Conditions/Comments
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Between any two units at the same temperature, voltage, and load
ns
ns
ps p-p
ns rms
Rev. 0 | Page 7 of 29
ADuM5410/ADuM5411/ADuM5412
Data Sheet
Table 14. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Input Threshold
Logic High
Symbol
Min
VIH
0.7 × VISO or 0.7 ×
VDD1
Logic Low
VIL
Output Voltage
Logic High
VOH
Logic Low
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
Quiescent Supply Current
ADuM5410
Typ
Max
Test Conditions/
Comments
V
0.3 × VISO or 0.3 ×
VDD1
VDD1 − 0.2 or VDD2 −
0.2
VDD1 − 0.5 or
VDD2 − 0.5
Unit
V
VDD1 or VDD2
V
IOx = −20 µA, VIx = VIxH
VDD1 − 0.2 or
VDD2 − 0.2
0.0
0.0
V
IOx = −4 mA, VIx = VIxH
0.1
0.4
V
V
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VDD2, and VDDP supply
1.6
1.5
0.1
+0.01
+10
V
V
V
µA
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.2
2.0
12.0
2.0
2.2
2.68
20.0
2.8
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.6
1.8
10.0
5.7
2.46
2.52
17.0
9.7
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.6
1.6
7.2
8.4
2.46
2.4
11.5
11.2
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDDI (D)
0.01
mA/Mbps
IDDO (D)
0.01
mA/Mbps
Inputs switching, 50% duty
cycle
Inputs switching, 50% duty
cycle
VOL
UVLO
VUV+
VUV−
VUVH
II
−10
ADuM5411
ADuM5412
Dynamic Supply Current
Input
Output
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 1
1
tR/tF
|CMH|
75
2.5
100
ns
kV/µs
|CML|
75
100
kV/µs
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both the rising and falling common-mode
voltage edges.
Rev. 0 | Page 8 of 29
Data Sheet
ADuM5410/ADuM5411/ADuM5412
ELECTRICAL CHARACTERISTICS—2.5 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire recommended
operation range: 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 15. Data Channel Supply Current Specifications
Parameter
SUPPLY CURRENT
ADuM5410
ADuM5411
ADuM5412
Symbol
Min
1 Mbps
Typ Max
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
6.5
2.0
5.6
3.8
4.3
5.0
Min
25 Mbps
Typ Max
9.8
3.6
10.0
6.55
7.7
8.4
7.3
3.3
6.4
4.8
5.4
6.1
Min
11.1
5.2
10.4
7.7
8.8
9.5
100 Mbps
Typ
Max
10.4
7.3
9.7
8.3
8.8
9.5
15.5
10.2
14.5
11.5
12.7
13.4
Unit
Test Conditions/Comments
CL = 0 pF
mA
mA
mA
mA
mA
mA
Table 16. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
Symbol
Min
PW
6.6
tPHL, tPLH
PWD
5.0
Typ
7.0
0.7
1.5
tPSK
tPSKCD
tPSKOD
Max
150
14
3
6.8
0.7
0.7
800
190
3.0
3.0
Unit
Test Conditions/Comments
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Between any two units at the same temperature, voltage, and
load
ns
ns
ps p-p
ps rms
Rev. 0 | Page 9 of 29
ADuM5410/ADuM5411/ADuM5412
Data Sheet
Table 17. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Input Threshold
Logic High
Symbol
Min
VIH
0.7 × VISO or 0.7 ×
VDD1
Logic Low
VIL
Output Voltage
Logic High
VOH
Typ
Max
Test Conditions/
Comments
V
0.3 × VISO or 0.3 ×
VDD1
V
VDD1 or VDD2
V
IOx = −20 µA, VIx = VIxH
VDD1 − 0.2 or
VDD2 − 0.2
0.0
0.0
V
IOx = −4 mA, VIx = VIxH
0.1
0.4
V
V
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VDD2, and VDDP supply
1.6
1.5
0.1
+0.01
+10
V
V
V
µA
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.2
2.0
1.2
2.0
2.0
2.64
19.6
2.76
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.46
1.75
9.7
5.67
2.32
2.47
16.6
9.67
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.6
1.6
7.2
8.4
2.32
2.32
11.2
11.2
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDDI (D)
0.01
mA/Mbps
Dynamic Output
IDDO (D)
0.01
mA/Mbps
Inputs switching, 50% duty
cycle
Inputs switching, 50% duty
cycle
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 1
tR/tF
|CMH|
75
2.5
100
ns
kV/µs
|CML|
75
100
kV/µs
Logic Low
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
Quiescent Supply Current
ADuM5410
VDD1 − 0.2 or VDD2 −
0.2
VDD1 − 0.5 or
VDD2 − 0.5
Unit
VOL
UVLO
VUV+
VUV−
VUVH
II
−10
ADuM5411
ADuM5412
Dynamic Supply Current
Dynamic Input
1
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both the rising and falling common-mode
voltage edges.
Rev. 0 | Page 10 of 29
Data Sheet
ADuM5410/ADuM5411/ADuM5412
ELECTRICAL CHARACTERISTICS—1.8 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 1.8 V. Minimum/maximum specifications apply over the entire recommended
operation range: 1.7 V ≤ VDD1 ≤ 1.9 V, 1.7 V ≤ VDD2 ≤ 1.9 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 18. Data Channel Supply Current Specifications
Parameter
SUPPLY CURRENT
ADuM5410
ADuM5411
ADuM5412
Symbol
Min
1 Mbps
Typ Max
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
6.4
1.9
5.5
3.72
4.3
4.9
Min
25 Mbps
Typ Max
9.8
3.5
9.1
6.45
7.7
8.3
7.2
3.1
6.3
4.8
5.3
6.0
Min
11
5.0
10.0
7.5
8.7
9.4
100 Mbps
Typ
Max
10.2
6.8
9.6
8.4
8.6
9.3
15.2
10
14.0
11.2
12.6
13.3
Unit
Test Conditions/Comments
CL = 0 pF
mA
mA
mA
mA
mA
mA
Table 19. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
Symbol
Min
PW
6.6
tPHL, tPLH
PWD
5.8
Typ
8.7
0.7
1.5
tPSK
tPSKCD
tPSKOD
Max
150
15
3
7.0
0.7
0.7
470
70
3.0
3.0
Unit
Test Conditions/Comments
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Between any two units at the same temperature, voltage, and
load
ns
ns
ps p-p
ps rms
Rev. 0 | Page 11 of 29
ADuM5410/ADuM5411/ADuM5412
Data Sheet
Table 20. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Input Threshold
Logic High
Logic Low
Output Voltages
Logic High
Logic Low
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
Quiescent Supply Current
ADuM5410
Symbol
Min
VIH
VIL
0.7 × VDDx
VOH
VDDx − 0.1
VDDx − 0.4
Test Conditions/
Comments
Max
Unit
0.3 × VDDx
V
V
0.1
0.4
V
V
V
V
1.6
1.5
0.1
+0.01
+10
V
V
V
µA
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.2
2.0
12.0
2.0
1.92
2.64
19.6
2.76
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.4
1.73
9.6
5.6
2.28
2.45
16.5
9.6
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.6
1.6
7.2
8.4
2.28
2.28
11.2
11.2
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDDI (D)
0.01
mA/Mbps
IDDO (D)
0.01
mA/Mbps
Inputs switching, 50% duty
cycle
Inputs switching, 50% duty
cycle
VOL
UVLO
VUV+
VUV−
VUVH
II
−10
Typ
VDDx
VDDx − 0.2
0.0
0.2
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VDD2, and VDDP supply
ADuM5411
ADuM5412
Dynamic Supply Current
Input
Output
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 1
1
tR/tF
|CMH|
75
2.5
100
ns
kV/µs
|CML|
75
100
kV/µs
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both the rising and falling common-mode
voltage edges.
Rev. 0 | Page 12 of 29
Data Sheet
ADuM5410/ADuM5411/ADuM5412
PACKAGE CHARACTERISTICS
Table 21. Thermal and Isolation Characteristics
Parameter
Resistance (Input to Output) 1
Capacitance (Input to Output)1
Input Capacitance 2
IC Junction to Ambient Thermal Resistance
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1012
2.2
4.0
50
Max
Unit
Ω
pF
pF
°C/W
Test Conditions/Comments
f = 1 MHz
Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces 3
The device is considered a 2-terminal device: Pin 1 to Pin 8 are shorted together, and Pin 9 to Pin 16 are shorted together.
Input capacitance is from any input data pin to ground.
3
See the Thermal Analysis section for thermal model definitions.
1
2
REGULATORY APPROVALS
Table 22.
UL(Pending) 1
Recognized Under 1577
Component
Recognition Program1
Single Protection,
2500 V rms
Isolation Voltage
File E214100
CSA(Pending)
Approved under CSA Component
Acceptance Notice 5A
VDE (Pending) 2
DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
CQC (Pending)
Certified under
CQC11-471543-2012
CSA 60950-1-07+A1+A2 and IEC
60950-1, second edition,
+A1+A2:
Basic insulation at 400 V rms
(565 V peak)
Basic insulation (1MOPP),
250 V rms (354 V peak)
CSA 61010-1-12 and IEC 61010-1
third edition
Basic insulation at 300 V rms
mains, 530 V rms (750 V peak)
File 205078
Reinforced Insulation 565 V peak,
VIOSM = 4 kV peak
GB4943.1-2011:
Basic insulation at 400 V rms
(565 V peak)
File 2471900-4880-0001
File (pending)
In accordance with UL 1577, each ADuM5410/ADuM5411/ADuM5412 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage
detection limit = 10 µA).
2
In accordance with DIN V VDE V 0884-10, each ADuM5410/ADuM5411/ADuM5412 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second
(partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
1
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 23. Critical Safety Related Dimensions and Material Properties
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol Value
2500
L(I01)
5.3
Minimum External Tracking (Creepage)
L(I02)
5.3
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB)
5.6
CTI
17
>400
II
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
Unit
Test Conditions/Comments
V rms
1-minute duration
mm min Measured from input terminals to output terminals,
shortest distance through air
mm min Measured from input terminals to output terminals,
shortest distance path along body
mm min Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
μm min Minimum distance through insulation
V
DIN IEC 112/VDE 0303, Part 1
Material group (DIN VDE 0110, 1/89, Table 1)
Rev. 0 | Page 13 of 29
ADuM5410/ADuM5411/ADuM5412
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
the protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval.
Table 24. VDE Characteristics
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b1
Test Conditions/Comments
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
Input to Output Test Voltage, Method a
After Environmental Tests Subgroup 1
VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
Transient overvoltage, tTR = 10 sec
1 minute withstand rating
VIOSM(TEST) = 10 kV; 1.2 µs rise time; 50 µs, 50% fall time
Maximum value allowed in the event of a failure
(see Figure 2)
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Withstand Isolation Voltage
Surge Isolation Voltage Basic
Safety Limiting Values
Case Temperature
Total Power Dissipation at 25°C
Insulation Resistance at TS
VIO = 500 V
Characteristic
Unit
VIORM
VPR
I to IV
I to IV
I to III
40/105/21
2
565
1059
V peak
V peak
VPR
Vpd(m)
848
V peak
Vpd(m)
678
V peak
VIOTM
VISO
VISOM
3535
2500
4000
V peak
V rms
V peak
TS
IS1
RS
150
2.5
>109
°C
W
Ω
RECOMMENDED OPERATING CONDITIONS
3.0
Table 25.
2.5
SAFE LIMITING POWER (W)
Symbol
Parameter
Operating Temperature 1
Supply Voltages 2
VDDP at VISO = 3.0 V to 3.6 V
VDDP at VISO = 4.5 V to 5.5 V
VDD1, VDD2
2.0
1.5
1.0
1
0.5
0
0
50
100
150
200
Min
−40
Max
+105
Unit
°C
VDDP
3.0
4.5
1.7
5.5
5.5
5.5
V
V
V
VDD1, VDD2
Operation at 105°C requires reduction of the maximum load current as
specified in Table 26.
Each voltage is relative to its respective ground.
14695-002
2
Symbol
TA
Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on
Case Temperature, per DIN EN 60747-5-2
Rev. 0 | Page 14 of 29
Data Sheet
ADuM5410/ADuM5411/ADuM5412
ABSOLUTE MAXIMUM RATINGS
Ambient temperature (TA) = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 26.
Parameter
Storage Temperature (TST)
Ambient Operating Temperature (TA)
Supply Voltages (VDD1, VDDP, VDD2, VISO)1
VISO Supply Current2
TA = −40°C to +105°C
Input Voltage (VIA, VIB, VIC, VID,VE1, VE2,
VSEL, PDIS)1, 3
Output Voltage (VOA, VOB, VOC, VOD)1, 3
Average Output Current Per Data
Output Pin4
Common-Mode Transients5
Rating
−55°C to +150°C
−40°C to +105°C
−0.5 V to +7.0 V
30 mA
−0.5 V to VDDI + 0.5 V
Table 27. Maximum Continuous Working Voltage
Supporting 50-Year Minimum Lifetime1
−0.5 V to VDDO + 0.5 V
−10 mA to +10 mA
Parameter
AC Voltage
Bipolar Waveform
−150 kV/µs to +150 kV/µs
All voltages are relative to their respective ground.
The VISO pin provides current for dc and dynamic loads on the VISO
input/output channels. This current must be included when determining the
total VISO supply current. For ambient temperatures between 85°C and
105°C, the maximum allowed current is reduced.
3
VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PCB Layout section.
4
See Figure 2 for the maximum rated current values for various temperatures.
5
Common-mode transients refers to common-mode transients across the
insulation barrier. Common-mode transients exceeding the absolute
maximum ratings may cause latch-up or permanent damage.
1
2
Unipolar Waveform
Basic Insulation
DC Voltage
Basic Insulation
1
Max
Unit
560
V peak
560
V peak
560
V peak
Applicable
Certification
All certifications,
50-year operation
Maximum continuous working voltage refers to the continuous voltage
magnitude imposed across the isolation barrier. See the Insulation Lifetime
section for more information.
ESD CAUTION
Rev. 0 | Page 15 of 29
ADuM5410/ADuM5411/ADuM5412
Data Sheet
VDD1 1
24
VDD2
GND1 2
23
GNDISO
VIA 3
22
VOA
VIB 4
21
VOB
VIC 5
20
ADuM5410
VOC
19
TOP VIEW
(Not to Scale)
VOD
18
VE2
NIC 8
17
NIC
GND1 9
16
GNDISO
PDIS 10
15
VSEL
VDDP 11
14
VISO
GND1 12
13
GNDISO
VID 6
NIC 7
NIC = NO INTERNAL CONNECTION.
LEAVE THESE PINS FLOATING.
14695-003
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. ADuM5410 Pin Configuration
Table 28. ADuM5410 Pin Function Descriptions
Pin No.
1
Mnemonic
VDD1
2, 9, 12
GND1
3
4
5
6
7, 8, 17
10
VIA
VIB
VIC
VID
NIC
PDIS
11
VDDP
13, 16, 23 GNDISO
14
15
18
VISO
VSEL
VE2
19
20
21
22
24
VOD
VOC
VOB
VOA
VDD2
Description
Power Supply for the Side 1 Logic Circuits of the Device. This pin is independent of VDDP and operates between 3.0 V
and 5.5 V.
Ground 1. Ground reference for the primary isolator. Pin 2, Pin 9, and Pin 12 are internally connected, and it is
recommended that these pins be connected to a common ground.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
No Internal Connection. Leave these pins floating.
Power Disable. When tied to any GND1 pin, the power converter is active; when a logic high voltage is applied, the
power supply enters a low power standby mode.
Primary Supply Voltage, 3.0 V to 5.5 V.
Ground Reference for VDD2 and VISO on Side 2. Pin 13, Pin 16, and Pin 23 are internally connected, and it is recommended
that these pins be connected to a common ground.
Secondary Supply Voltage Output for External Loads. Connect to VDD2 to power the isolator channels.
Output Voltage Selection.
Output Enable 2. When VE2 is high or disconnected, the VOA, VOB, VOC, and VOD outputs are enabled. When VE2 is low,
the VOA, VOB, VOC, and VOD outputs are disabled. In noisy environments, connecting VE2 to either an external logic
high or logic low is recommended.
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Power Supply for the Side 2 Logic Circuits of the Device. This pin is independent of VDDP and operates between 3.0 V
and 5.5 V.
Rev. 0 | Page 16 of 29
ADuM5410/ADuM5411/ADuM5412
VDD1 1
24
VDD2
GND1 2
23
GNDISO
VIA 3
22
VOA
VIB 4
21
VOB
VIC 5
20
VOC
19
VID
18
VE2
NIC 8
17
NIC
GND1 9
16
GNDISO
PDIS 10
15
VSEL
VDDP 11
14
VISO
GND1 12
13
GNDISO
VOD 6
VE1 7
ADuM5411
TOP VIEW
(Not to Scale)
NIC = NO INTERNAL CONNECTION.
LEAVE THESE PINS FLOATING.
14695-004
Data Sheet
Figure 4. ADuM5411 Pin Configuration
Table 29. ADuM5411 Pin Function Descriptions
Pin No.
1
Mnemonic Description
VDD1
Power Supply for the Side 1 Logic Circuits of the Device. This pin is independent of VDDP and operates between 3.0 V
and 5.5 V.
2, 9, 12
GND1
Ground 1. Ground reference for the primary isolator. Pin 2, Pin 9, and Pin 12 are internally connected, and it is recommended
that these pins be connected to a common ground.
3
VIA
Logic Input A.
4
VIB
Logic Input B.
5
VIC
Logic Input C.
6
VOD
Logic Output D.
7
VE1
Output Enable 1. When VE1 is high or disconnected, the VOD output is enabled. When VE1 is low, the VOD output is
disabled. In noisy environments, connecting VE1 to either an external logic high or logic low is recommended.
8, 17
NIC
No Internal Connection. Leave these pins floating.
10
PDIS
Power Disable. When tied to any GND1 pin, the power converter is active; when a logic high voltage is applied, the
power supply enters a low power standby mode.
11
VDDP
Primary Supply Voltage, 3.0 V to 5.5 V.
13, 16, 23 GNDISO
Ground Reference for VDD2 and VISO on Side 2. Pin 13, Pin 16, and Pin 23 are internally connected, and it is recommended that
these pins be connected to a common ground.
14
VISO
Secondary Supply Voltage Output for External Loads. Connect to VDD2 to power the isolator channels.
15
VSEL
Output Voltage Selection.
18
VE2
Output Enable 2. When VE2 is high or disconnected, the VOA, VOB, and VOC outputs are enabled. When VE2 is low, the VOA,
VOB, and VOC outputs are disabled. In noisy environments, connecting VE2 to either an external logic high or logic low is
recommended.
19
VID
Logic Input D.
20
VOC
Logic Output C.
21
VOB
Logic Output B.
22
VOA
Logic Output A.
24
VDD2
Power Supply for the Side 2 Logic Circuits of the Device. This pin is independent of VDDP and operates between 3.0 V
and 5.5 V.
Rev. 0 | Page 17 of 29
Data Sheet
VDD1 1
24
VDD2
GND1 2
23
GNDISO
VIA 3
22
VOA
VIB 4
21
VOB
VOC 5
20
VIC
19
VID
18
VE2
NIC 8
17
NIC
GND1 9
16
GNDISO
PDIS 10
15
VSEL
VDDP 11
14
VISO
GND1 12
13
GNDISO
VOD 6
VE1 7
ADuM5412
TOP VIEW
(Not to Scale)
NIC = NO INTERNAL CONNECTION.
LEAVE THESE PINS FLOATING.
14695-005
ADuM5410/ADuM5411/ADuM5412
Figure 5. ADuM5412 Pin Configuration
Table 30. ADuM5412 Pin Function Descriptions
Pin No.
1
Mnemonic
VDD1
2, 9, 12
GND1
3
4
5
6
7
VIA
VIB
VOC
VOD
VE1
8, 17
10
NIC
PDIS
11
VDDP
13, 16, 23 GNDISO
14
15
18
VISO
VSEL
VE2
19
20
21
22
24
VID
VIC
VOB
VOA
VDD2
Description
Power Supply for the Side 1 Logic Circuits of the Device. This pin is independent of VDDP and operates between 3.0 V
and 5.5 V.
Ground 1. Ground reference for the primary isolator. Pin 2, Pin 9, and Pin 12 are internally connected, and it is
recommended that these pins be connected to a common ground.
Logic Input A.
Logic Input B.
Logic Output C.
Logic Output D.
Output Enable 1. When VE1 is high or disconnected, the VOC and VOD outputs are enabled. When VE1 is low, the VOC
and VOD outputs are disabled. In noisy environments, connecting VE1 to either an external logic high or logic low is
recommended.
No Internal Connection. Leave these pins floating.
Power Disable. When tied to any GND1 pin, the power converter is active; when a logic high voltage is applied, the
power supply enters a low power standby mode.
Primary Supply Voltage, 3.0 V to 5.5 V.
Ground Reference for VDD2 and VISO on Side 2. Pin 13, Pin 16, and Pin 23 are internally connected, and it is recommended
that these pins be connected to a common ground.
Secondary Supply Voltage Output for External Loads. Connect to VDD2 to power the isolator channels.
Output Voltage Selection.
Output Enable 2. When VE2 is high or disconnected, the VOA and VOB outputs are enabled. When VE2 is low, the VOA
and VOB outputs are disabled. In noisy environments, connecting VE2 to either an external logic high or logic low is
recommended.
Logic Input D.
Logic Input C.
Logic Output B.
Logic Output A.
Power Supply for the Side 2 Logic Circuits of the Device. This pin is independent of VDDP and operates between 3.0 V
and 5.5 V.
Rev. 0 | Page 18 of 29
Data Sheet
ADuM5410/ADuM5411/ADuM5412
TRUTH TABLES
Table 31. Truth Table (Positive Logic)
VDDP (V)
5
5
3.3
3.3
5
5
3.3
3.3
VSEL Input
R1 = 10 kΩ, R2 = 30.9 kΩ
R1 = 10 kΩ, R2 = 30.9 kΩ
R1 = 10 kΩ, R2 = 16.9 kΩ
R1 = 10 kΩ, R2 = 16.9 kΩ
R1 = 10 kΩ, R2 = 16.9 kΩ
R1 = 10 kΩ, R2 = 16.9 kΩ
R1 = 10 kΩ, R2 = 30.9 kΩ
R1 = 10 kΩ, R2 = 30.9 kΩ
PDIS Input Logic
Low
High
Low
High
Low
High
Low
High
VISO Output (V)
5
0
3.3
0
3.3
0
5
0
Notes
This configuration is not recommended
Table 32. Data Section Truth Table (Positive Logic)
VDDI State 1
Powered
Powered
Don’t care
Unpowered
Unpowered
1
VIx Input1
High
Low
Don’t care
Low
High
VDDO State1
Powered
Powered
Unpowered
Powered
Powered
VOx Output1
High
Low
High-Z
Low
Indeterminate
Notes
Normal operation, data is high
Normal operation, data is low
Output is off
Output default low
If a high level is applied to an input when no supply is present, the
input can parasitically power the input side, causing unpredictable
operation
VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively. VIx and VOx refer to the input and output signals of a given
channel (Channel A, Channel B, Channel C, or Channel D).
Rev. 0 | Page 19 of 29
ADuM5410/ADuM5411/ADuM5412
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.8
0.25
0.20
0.15
0.10
0.45
0.40
1.6
0.35
1.4
0.30
1.0
0.25
0.8
0.20
0.6
0.15
0.4
0.05
0
0.02
0.04
LOAD CURRENT (A)
0.06
0.08
0.10
0.2
0
3.0
14695-006
0
VDD1 = VDDP = 5V/VDD2 = 5V
VDD1 = VDDP = 5V/VDD2 = 3.3V
VDD1 = VDDP = 3.3V/VDD2 = 3.3V
3.5
4.0
4.5
VDD1 (V)
5.0
5.5
0
6.0
Figure 9. Short-Circuit Input Current (IDDP ) and Power Dissipation vs. VDD1 Supply
Voltage
VDD1 = VDDP = 5V/VDD2 = 5V
VDD1 = VDDP = 5V/VDD2 = 3.3V
VDD1 = VDDP = 3.3V/VDD2 = 3.3V
14695-007
(1ms/DIV)
Figure 10. VISO Transient Load Response, 5 V Output,
10% to 90% Load Step
Figure 7. Total Power Dissipation vs. Output Supply Current, IISO, with Data
Channels Idle
Figure 8. Isolated IISO as a Function of External Load, No Dynamic Current
Draw at 5 V/5 V, 5 V/3.3 V, and 3.3 V/3.3 V
Rev. 0 | Page 20 of 29
(1ms/DIV)
Figure 11. Transient Load Response, 3 V Output,
10% to 90% Load Step
14695-011
14695-008
VISO (100mV/DIV)
VDD1 = VDDP = 5V/VDD2 = 5V
VDD1 = VDDP = 5V/VDD2 = 3.3V
VDD1 = VDDP = 3.3V/VDD2 = 3.3V
14695-010
VISO (100mV/DIV)
Figure 6. Power Supply Efficiency at 5 V/5 V, 5 V/3.3 V, and 3.3 V/3.3 V
0.05
14695-009
POWER DISSIPATION (W)
0.30
0.50
IDDP
POWER DISSIPATION
IDDP (A)
2.0
0.35
ADuM5410/ADuM5411/ADuM5412
14695-015
(1ms/DIV)
14695-012
MINIMUM INPUT VOLTAGE (V)
VISO (100mV/DIV)
Data Sheet
OUTPUT VOLTAGE (V)
Figure 12. Transient Load Response, 5 V Input, 3.3 V Output,
10% to 90% Load Step
Figure 15. Relationship Between Output Voltage and Required Input Voltage,
Under Load, to Maintain >80% Duty Factor in the PWM
4.970
500
450
POWER DISSIPATION (mW)
4.965
VISO (V)
4.960
4.955
4.950
VDD1 = VDDP = 5V/VDD2 = 5V
VDD1 = VDDP = 5V/VDD2 = 3.3V
400
350
300
250
200
4.945
TIME (µs)
100
–40
14695-013
4.940
Figure 13. Output Voltage Ripple at 90% Load, VISO = 5 V
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
100
120
14695-016
150
Figure 16. Power Dissipation vs. Ambient Temperature with a 30 mA Load
3.280
500
450
POWER DISSIPATION (mW)
3.276
3.274
3.272
VDD1 = 5V/VDD2 = 5V
VDD1 = 3.3V/VDD2 = 3.3V
VDDP = 5V/VDD2 = 3.3V
400
350
300
250
200
3.270
TIME (µs)
Figure 14. Output Voltage Ripple at 90% Load, VISO = 3.3 V
100
–40
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
100
120
14695-017
150
14695-014
VISO (V)
2.278
Figure 17. Power Dissipation vs. Ambient Temperature with a 20 mA Load
Rev. 0 | Page 21 of 29
ADuM5410/ADuM5411/ADuM5412
Data Sheet
16
10
9
14
IDD1 SUPPLY CURRENT (mA)
7
6
5
4
5V
3
3.3V
2
5V
10
3.3V
8
6
4
2
1
0
0
20
40
60
80
100
120
140
160
DATA RATE (Mbps)
14695-018
0
12
0
20
40
60
80
100
120
140
160
DATA RATE (Mbps)
14695-021
SUPPLY CURRENT (mA)
8
Figure 21. ADuM5410 VDD1 Supply Current (IDD1) vs. Data Rate for 5 V and 3.3 V
Operation
Figure 18. Supply Current per Input Channel vs. Data Rate
for 5 V and 3.3 V Operation
10
16
9
14
IDD2 SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
8
7
6
5
4
3
5V
2
12
10
5V
8
3.3V
6
4
3.3V
0
20
40
60
80
100
120
140
160
DATA RATE (Mbps)
0
14695-019
Figure 19. Supply Current per Output Channel vs. Data Rate for 5 V and 3.3 V
Operation (No Output Load)
40
60
80
100
120
140
160
Figure 22. ADuM5410 VDD2 Supply Current (IDD2) vs. Data Rate for 5 V and 3.3 V
Operation
16
9
14
IDD1 SUPPLY CURRENT (mA)
8
SUPPLY CURRENT (mA)
20
DATA RATE (Mbps)
10
7
6
5V
5
3.3V
4
3
2
12
5V
10
3.3V
8
6
4
2
1
0
20
40
60
80
100
DATA RATE (Mbps)
120
140
160
0
14695-020
0
0
Figure 20. Supply Current per Output Channel vs. Data Rate for 5 V and 3.3 V
Operation (15 pF Output Load)
0
20
40
60
80
100
DATA RATE (Mbps)
120
140
160
14695-023
0
14695-022
2
1
Figure 23. ADuM5411 VDD1 Supply Current (IDD1) vs. Data Rate for 5 V and 3.3 V
Operation
Rev. 0 | Page 22 of 29
ADuM5410/ADuM5411/ADuM5412
16
14
14
12
PROPAGATION DELAY, tPLH (ns)
12
5V
10
3.3V
8
6
4
8
5V
3.3V
6
4
2
2
0
20
40
60
120
100
80
140
160
DATA RATE (Mbps)
0
–40
14695-024
0
10
Figure 24. ADuM5411 VDD2 Supply Current (IDD2) vs. Data Rate for 5 V and
3.3 V Operation
0
–20
20
60
40
80
100
120
140
TEMPERATURE (°C)
14695-026
IDD2 SUPPLY CURRENT (mA)
Data Sheet
Figure 27. Propagation Delay, tPLH vs. Temperature for 5 V and 3.3 V Operation
14
PROPAGATION DELAY, tPHL (ns)
IDD1 SUPPLY CURRENT (mA)
12
5V
3.3V
10
8
5V
3.3V
6
4
20
40
60
80
100
120
140
160
DATA RATE (Mbps)
Figure 25. ADuM5412 VDD1 Supply Current (IDD1) vs. Data Rate for 5 V and
3.3 V Operation
0
–40
IDD2 SUPPLY CURRENT (mA)
12
5V
10
3.3V
6
4
2
40
60
80
100
DATA RATE (Mbps)
120
140
160
14695-025
0
20
20
40
60
80
100
120
140
Figure 28. Propagation Delay, tPHL vs. Temperature for 5 V and 3.3 V Operation
14
0
0
TEMPERATURE (°C)
16
8
–20
14695-027
0
14695-0124
2
Figure 26. ADuM5412 VDD2 Supply Current (IDD2) vs. Data Rate for 5 V and
3.3 V Operation
Rev. 0 | Page 23 of 29
ADuM5410/ADuM5411/ADuM5412
Data Sheet
TERMINOLOGY
IDD1 (Q)
IDD1 (Q) is the minimum operating current drawn at the VDD1 pin
when there is no external load at VISO and the input/output pins
are operating below 2 Mbps, requiring no additional dynamic
supply current. IDD1 (Q) reflects the minimum current operating
condition.
IDD1 (D)
IDD1 (D) is the typical input supply current with all channels
simultaneously driven at a maximum data rate of 33 Mbps
with full capacitive load representing the maximum dynamic
load conditions. Treat resistive loads on the outputs separately
from the dynamic load.
IDD1 (MAX)
IDD1 (MAX) is the input current under full dynamic and VISO load
conditions.
ISO (LOAD)
ISO (LOAD) is the current available to load.
Propagation Delay, tPHL
tPHL propagation delay is measured from the 50% level of the
falling edge of the VIx signal to the 50% level of the falling edge
of the VOx signal.
Propagation Delay, tPLH
tPLH propagation delay is measured from the 50% level of the rising
edge of the VIx signal to the 50% level of the rising edge of the
VOx signal.
Propagation Delay Skew, tPSK
tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH
that is measured between units at the same operating temperature,
supply voltages, and output load within the recommended
operating conditions.
Channel to Channel Matching, tPSKCD/tPSKOD
Channel to channel matching is the absolute value of the
difference in propagation delays between the two channels
when operated with identical loads.
Minimum Pulse Width
The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed.
Maximum Data Rate
The maximum data rate is the fastest data rate at which the
specified pulse width distortion is guaranteed.
Rev. 0 | Page 24 of 29
Data Sheet
ADuM5410/ADuM5411/ADuM5412
THEORY OF OPERATION
The dc-to-dc converter section of the ADuM5410/ADuM5411/
ADuM5412 works on principles that are common to most
modern power supplies. It has a split controller architecture with
isolated PWM feedback. VDDP power is supplied to an oscillating
circuit that switches current into a chip-scale air core transformer.
Power transferred to the secondary side is rectified and regulated to
a value between 3.15 V and 5.25 V, depending on the setpoint
supplied by an external voltage divider (see Equation 1). The
secondary (VISO) side controller regulates the output by creating a
PWM control signal that is sent to the primary (VDDP) side by a
dedicated iCoupler data channel. The PWM modulates the
oscillator circuit to control the power being sent to the secondary
side. Feedback allows for significantly higher power and efficiency.
(R1 R2)
(1)
R1
where:
R1 is a resistor between VSEL and GNDISO.
R2 is a resistor between VSEL and VISO.
Because the output voltage can be adjusted continuously,
there are an infinite number of operating conditions. This
data sheet addresses three discrete operating conditions in the
Specifications section. Many other combinations of input and
output voltage are possible; Figure 15 shows the supported
voltage combinations at room temperature. Figure 15 was
generated by fixing the VISO load and decreasing the input
voltage until the PWM was at 80% duty cycle. Each of the
figures represents the minimum input voltage that is required
for operation under this criterion. For example, if the application requires 30 mA of output current at 5 V, the minimum
input voltage at VDDP is 4.25 V. Figure 15 also illustrates why the
VDDP = 3.3 V input and VISO = 5 V configuration is not
recommended. Even at 10 mA of output current, the PWM
Typically, the ADuM5410/ADuM5411/ADuM5412 dissipate
about 17% more power between room temperature and maximum temperature; therefore, the 20% PWM margin covers
temperature variations.
The ADuM5410/ADuM5411/ADuM5412 implement
undervoltage lockout (UVLO) with hysteresis on the primary
and secondary side input/output pins as well as the VDDP power
input. This feature ensures that the converters do not go into
oscillation due to noisy input power or slow power-on ramp rates.
The digital isolator channels use a high frequency carrier to
transmit data across the isolation barrier using iCoupler chip
scale transformer coils separated by layers of polyimide isolation.
Using an on/off keying (OOK) technique and the differential
architecture shown in Figure 29, the digital isolator channels have
very low propagation delay and high speed. Internal regulators and
input/output design techniques allow logic and supply voltages over
a wide range from 1.7 V to 5.5 V, offering voltage translation of
1.8 V, 2.5 V, 3.3 V, and 5 V logic. The architecture is designed for
high common-mode transient immunity and high immunity to
electrical noise and magnetic interference. Radiated emissions
are minimized with a spread spectrum OOK carrier and
other techniques.
Figure 29 shows the waveforms of the digital isolator channels
that have the condition of the fail-safe output state equal to low,
where the carrier waveform is off when the input state is low. If
the input side is off or not operating, the low fail-safe output state
sets the output to low.
REGULATOR
REGULATOR
TRANSMITTER
RECEIVER
VIN
VOUT
GND1
GND2
Figure 29. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State
Rev. 0 | Page 25 of 29
14695-028
VISO  1.225 V
cannot maintain less than 80% duty factor, leaving no margin to
support load or temperature variations.
ADuM5410/ADuM5411/ADuM5412
Data Sheet
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM5410/ADuM5411/ADuM5412 digital isolators with
0.15 W isoPower integrated dc-to-dc converters require no
external interface circuitry for the logic interfaces. Power supply
bypassing is required at the input and output supply pins (see
Figure 32). Note that low ESR bypass capacitors of 0.01 μF to
0.1 μF value are required between the VDD1 pin and GND1 pin,
and between the VDD2 pin and GNDISO pin, as close to the chip
pads as possible, for proper operation of the data channels. The
isoPower inputs require several passive components to bypass
the power effectively, as well as set the output voltage and bypass
the core voltage regulator (see Figure 30 through Figure 32).
10µF
+
0.1µF
GND1
10
11
12
Figure 30. VDDP Bias and Bypass Components
14
13
VSEL
FB1
VISO
GNDISO
R2
30kΩ
VISO OUT
0.1µF
10µF
FB2
R1
10kΩ
ISO GND
VDD1
14695-030
15
Table 33. Surface-Mount Ferrite Beads Example
Manufacturer
Taiyo Yuden
Murata Electronics
GND1
Figure 31. VISO Bias and Bypass Components
The power supply section of the ADuM5410/ADuM5411/
ADuM5412 uses a 125 MHz oscillator frequency to efficiently
pass power through its chip-scale transformers. Bypass capacitors
are required for several operating frequencies. Noise suppression
requires a low inductance, high frequency capacitor; ripple
suppression and proper regulation require a large value capacitor.
These capacitors are most conveniently connected between the
VDDP pin and GND1 pin, and between the VISO pin and GNDISO pin.
To suppress noise and reduce ripple, a parallel combination of at
least two capacitors is required. The recommended capacitor values
are 0.1 μF and 10 μF for VDD1. The smaller capacitor must have a
low ESR; for example, use of a ceramic capacitor is advised. Note
that the total lead length between the ends of the low ESR
capacitor and the input power supply pin must not exceed 2 mm.
Installing the bypass capacitor with traces more than 2 mm in
length may result in data corruption.
Part No.
BKH1005LM182-T
BLM15HD182SN1
0.1µF
0.1µF
VDD2
GNDISO
VIA
VOA
VIB
VOB
VIC/VOC
VOC/VIC
ADuM5410/
ADuM5411/
ADuM5412
VID/VOD
VE1/NIC
VOD/VID
VE2
NIC
NIC
GND1
GNDISO
PDIS
VSEL
VDDP
VISO
GND1
10µF 0.1µF
0.1µF FERRITES 10µF
GNDISO
SMT 100pF SAFETY CAPACITOR
NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.
Figure 32. Recommended PCB Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur equally affects all pins on a given component
side. Failure to ensure these steps can cause voltage differentials
between pins, exceeding the absolute maximum ratings
specified in Table 26, thereby leading to latch-up and/or
permanent damage.
Rev. 0 | Page 26 of 29
14695-031
VDDP
14695-029
PDIS
To reduce the level of electromagnetic radiation, the impedance
to high frequency currents between the VISO and GNDISO pins and
the PCB trace connections can be increased. Using this method
of EMI suppression controls the radiating signal at its source by
placing surface-mount ferrite beads in series with the VISO and
GNDISO pins, as seen in Figure 32. The impedance of the ferrite
bead is chosen to be about 2 kΩ between the 100 MHz and 1 GHz
frequency range, to reduce the emissions at the 125 MHz primary
switching frequency and the 250 MHz secondary side rectifying
frequency and harmonics. See Table 33 for examples of appropriate
surface-mount ferrite beads. For additional reduction in emissions,
PCB stitching capacitance can be implemented with a high voltage
SMT safety capacitor. For optimal performance, it is important
that the capacitor is connected directly between GND1 (Pin 12)
and GNDISO (Pin 13), as shown in Figure 32.This capacitor is a
SMT Size 1812, has a 3 kV voltage rating, and is manufactured
by TDK Corporation (C4532C0G3F101K160KA).
Data Sheet
ADuM5410/ADuM5411/ADuM5412
THERMAL ANALYSIS
The ADuM5410/ADuM5411/ADuM5412 consist of four internal
die attached to a split lead frame with two die attach pads. For the
purposes of thermal analysis, the die is treated as a thermal unit,
with the highest junction temperature reflected in the θJA value
from Table 21. The value of θJA is based on measurements taken
with the devices mounted on a JEDEC standard, 4-layer board
with fine width traces and still air. Under normal operating
conditions, the ADuM5410/ADuM5411/ADuM5412 can
operate at full load across the full temperature range without
derating the output current.
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component (see Figure 33).
The propagation delay to a logic low output may differ from the
propagation delay to a logic high.
INPUT (VIx)
50%
OUTPUT (VOx)
tPHL
14695-032
tPLH
50%
Figure 33. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the input signal timing is preserved.
Channel to channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM5410/ADuM5411/ADuM5412 component.
Treat the converter as a standalone supply to be utilized at the
discretion of the designer.
The VDD1 or VDD2 supply current at a given channel of the
ADuM5410/ADuM5411/ADuM5412 isolator is a function of
the supply voltage, the data rate of the channel, and the output
load of the channel.
To calculate the total VDD1 and VDD2 supply current, the supply
currents for each input and output channel corresponding to
VDD1 and VDD2 are calculated and totaled. Figure 18 and
Figure 19 show per channel supply currents as a function of
data rate for an unloaded output condition. Figure 20 shows the
per channel supply current as a function of data rate for a 15 pF
output condition. Figure 21 through Figure 26 show the total
VDD1 and VDD2 supply current as a function of data rate for
ADuM5410/ADuM5411/ADuM5412 channel configurations.
INSULATION LIFETIME
All insulation structures eventually break down when subjected to
voltage stress over a sufficiently long period. The rate of insulation
degradation is dependent on the characteristics of the voltage
waveform applied across the insulation as well as on the materials
and material interfaces.
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
Surface Tracking
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM5410/
ADuM5411/ADuM5412 components operating under the
same conditions.
EMI CONSIDERATIONS
The dc-to-dc converter section of the ADuM5410/ADuM5411/
ADuM5412 components must, of necessity, operate at a very high
frequency to allow efficient power transfer through the small
transformers, which creates high frequency currents that can
propagate in circuit board ground and power planes, causing
edge and dipole radiation. Grounded enclosures are recommended
for applications that use these devices. If grounded enclosures are
not possible, follow good RF design practices in the layout of
the PCB. Follow the layout techniques described in the PCB
Layout section. See the AN-0971 Application Note for the most
current PCB layout recommendations for the ADuM5410/
ADuM5411/ADuM5412.
POWER CONSUMPTION
The VDDP power supply input only provides power to the converter.
Power for the data channels is provided through VDD1 and VDD2.
These power supplies can be connected to VDDP and VISO if desired,
or the supplies can receive power from an independent source.
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components that allows the components to be
categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and, therefore, can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in
each system level standard and is based on the total rms voltage
across the isolation, pollution degree, and material group. The
material group and creepage for the digital isolator channels are
presented in Table 23.
Insulation Wear Out
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. The working voltage applicable
to tracking is specified in most standards.
Rev. 0 | Page 27 of 29
Data Sheet
The ratings in certification documents are usually based on
60 Hz sinusoidal stress because this reflects isolation from line
voltage. However, many practical applications have combinations
of 60 Hz ac and dc across the barrier as shown in Equation 1.
Because only the ac portion of the stress causes wear out, the
equation can be rearranged to solve for the ac rms voltage, as is
shown in Equation 2. For insulation wear out with the polyimide
materials used in these products, the ac rms voltage determines
the product lifetime.
VRMS 
VAC RMS2
VDC2
VACRMS  VRMS2 VDC2
(2)
VPEAK
VRMS
VDC
TIME
Figure 34. Critical Voltage Example
The working voltage across the barrier from Equation 1 is
VRMS  VAC RMS2  VDC2
VRMS  240 2  400 2
(1)
or
VAC RMS
14695-033
Testing and modeling show that the primary driver of longterm degradation is displacement current in the polyimide
insulation causing incremental damage. The stress on the insulation can be broken down into broad categories, such as dc stress,
which causes very little wear out because there is no displacement
current, and an ac component time varying voltage stress, which
causes wear out.
ISOLATION VOLTAGE
ADuM5410/ADuM5411/ADuM5412
VRMS = 466 V
This VRMS value is the working voltage used together with the
material group and pollution degree when looking up the creepage
required by a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
where:
VAC RMS is the time varying portion of the working voltage.
VRMS is the total rms working voltage.
VDC is the dc offset of the working voltage.
VAC RMS  VRMS2 VDC2
Calculation and Use of Parameters Example
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation is 240 V ac rms and a 400 V dc bus voltage is present
on the other side of the isolation barrier. The isolator material is
polyimide. To establish the critical voltages in determining the
creepage, clearance and lifetime of a device, see Figure 34 and
the following equations.
VAC RMS  4662  4002
VAC RMS = 240 V rms
In this case, the ac rms voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform is
not sinusoidal. The value is compared to the limits for working
voltage in Table 27 for the expected lifetime, which is less than a
60 Hz sine wave, and it is well within the limit for a 50-year
service life.
Note that the dc working voltage limit is set by the creepage of
the package as specified in IEC 60664-1. This value can differ
for specific system level standards.
Rev. 0 | Page 28 of 29
Data Sheet
ADuM5410/ADuM5411/ADuM5412
OUTLINE DIMENSIONS
8.50
8.20
7.90
13
24
5.60
5.30
5.00
1
8.20
7.80
7.40
12
0.65 BSC
0.38
0.22
SEATING
PLANE
8°
4°
0°
0.95
0.75
0.55
060106-A
0.05 MIN
COPLANARITY
0.10
0.25
0.09
1.85
1.75
1.65
2.00 MAX
COMPLIANT TO JEDEC STANDARDS MO-150-AG
Figure 35. 24-Lead Shrink Small Outline Package [SSOP]
(RS-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADuM5410BRSZ
ADuM5410BRSZ-RL7
ADuM5411BRSZ
ADuM5411BRSZ-RL7
ADuM5412BRSZ
ADuM5412BRSZ-RL7
EVAL-ADuM5411EBZ
EVAL-ADuM5411UEBZ
Number
of Inputs,
VDD1 Side
4
4
3
3
2
2
Number
of Inputs,
VISO Side
0
0
1
1
2
2
Maximum
Data Rate
(Mbps)
150
150
150
150
150
150
Maximum
Propagation
Delay, 5 V (ns)
13
13
13
13
13
13
Z = RoHS Compliant Part.
The EVAL-ADuM5411EBZ is packaged with the ADuM5411BRSZ installed.
3
The EVAL-ADuM5411UEBZ is packaged without an ADuM5411 installed.
1
2
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14695-0-7/16(0)
Rev. 0 | Page 29 of 29
Maximum
Pulse Width
Distortion (ns)
3
3
3
3
3
3
Temperature
Range (°C)
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
Package
Description
24-Lead SSOP
24-Lead SSOP
24-Lead SSOP
24-Lead SSOP
24-Lead SSOP
24-Lead SSOP
Evaluation Board 2
Evaluation Board 3
Package
Option
RS-24
RS-24
RS-24
RS-24
RS-24
RS-24